2 * Copyright (c) 2006-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
35 #include "efx_check.h"
36 #include "efx_phy_ids.h"
42 #define EFX_STATIC_ASSERT(_cond) \
43 ((void)sizeof(char[(_cond) ? 1 : -1]))
45 #define EFX_ARRAY_SIZE(_array) \
46 (sizeof(_array) / sizeof((_array)[0]))
48 #define EFX_FIELD_OFFSET(_type, _field) \
49 ((size_t) &(((_type *)0)->_field))
53 typedef __success(return == 0) int efx_rc_t;
58 typedef enum efx_family_e {
60 EFX_FAMILY_FALCON, /* Obsolete and not supported */
62 EFX_FAMILY_HUNTINGTON,
67 extern __checkReturn efx_rc_t
71 __out efx_family_t *efp);
74 #define EFX_PCI_VENID_SFC 0x1924
76 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
78 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
79 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
80 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
82 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
83 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
84 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
86 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
87 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
89 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
90 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
91 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
100 EFX_ERR_BUFID_DC_OOB,
113 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
114 extern __checkReturn uint32_t
116 __in uint32_t crc_init,
117 __in_ecount(length) uint8_t const *input,
121 /* Type prototypes */
123 typedef struct efx_rxq_s efx_rxq_t;
127 typedef struct efx_nic_s efx_nic_t;
129 extern __checkReturn efx_rc_t
131 __in efx_family_t family,
132 __in efsys_identifier_t *esip,
133 __in efsys_bar_t *esbp,
134 __in efsys_lock_t *eslp,
135 __deref_out efx_nic_t **enpp);
137 extern __checkReturn efx_rc_t
139 __in efx_nic_t *enp);
141 extern __checkReturn efx_rc_t
143 __in efx_nic_t *enp);
145 extern __checkReturn efx_rc_t
147 __in efx_nic_t *enp);
151 __in efx_nic_t *enp);
155 __in efx_nic_t *enp);
159 __in efx_nic_t *enp);
161 #define EFX_PCIE_LINK_SPEED_GEN1 1
162 #define EFX_PCIE_LINK_SPEED_GEN2 2
163 #define EFX_PCIE_LINK_SPEED_GEN3 3
165 typedef enum efx_pcie_link_performance_e {
166 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
167 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
168 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
169 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
170 } efx_pcie_link_performance_t;
172 extern __checkReturn efx_rc_t
173 efx_nic_calculate_pcie_link_bandwidth(
174 __in uint32_t pcie_link_width,
175 __in uint32_t pcie_link_gen,
176 __out uint32_t *bandwidth_mbpsp);
178 extern __checkReturn efx_rc_t
179 efx_nic_check_pcie_link_speed(
181 __in uint32_t pcie_link_width,
182 __in uint32_t pcie_link_gen,
183 __out efx_pcie_link_performance_t *resultp);
187 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
189 typedef enum efx_mcdi_exception_e {
190 EFX_MCDI_EXCEPTION_MC_REBOOT,
191 EFX_MCDI_EXCEPTION_MC_BADASSERT,
192 } efx_mcdi_exception_t;
194 #if EFSYS_OPT_MCDI_LOGGING
195 typedef enum efx_log_msg_e {
197 EFX_LOG_MCDI_REQUEST,
198 EFX_LOG_MCDI_RESPONSE,
200 #endif /* EFSYS_OPT_MCDI_LOGGING */
202 typedef struct efx_mcdi_transport_s {
204 efsys_mem_t *emt_dma_mem;
205 void (*emt_execute)(void *, efx_mcdi_req_t *);
206 void (*emt_ev_cpl)(void *);
207 void (*emt_exception)(void *, efx_mcdi_exception_t);
208 #if EFSYS_OPT_MCDI_LOGGING
209 void (*emt_logger)(void *, efx_log_msg_t,
210 void *, size_t, void *, size_t);
211 #endif /* EFSYS_OPT_MCDI_LOGGING */
212 } efx_mcdi_transport_t;
214 extern __checkReturn efx_rc_t
217 __in const efx_mcdi_transport_t *mtp);
219 extern __checkReturn efx_rc_t
221 __in efx_nic_t *enp);
225 __in efx_nic_t *enp);
228 efx_mcdi_get_timeout(
230 __in efx_mcdi_req_t *emrp,
231 __out uint32_t *usec_timeoutp);
234 efx_mcdi_request_start(
236 __in efx_mcdi_req_t *emrp,
237 __in boolean_t ev_cpl);
239 extern __checkReturn boolean_t
240 efx_mcdi_request_poll(
241 __in efx_nic_t *enp);
243 extern __checkReturn boolean_t
244 efx_mcdi_request_abort(
245 __in efx_nic_t *enp);
249 __in efx_nic_t *enp);
251 #endif /* EFSYS_OPT_MCDI */
255 #define EFX_NINTR_SIENA 1024
257 typedef enum efx_intr_type_e {
258 EFX_INTR_INVALID = 0,
264 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
266 extern __checkReturn efx_rc_t
269 __in efx_intr_type_t type,
270 __in efsys_mem_t *esmp);
274 __in efx_nic_t *enp);
278 __in efx_nic_t *enp);
281 efx_intr_disable_unlocked(
282 __in efx_nic_t *enp);
284 #define EFX_INTR_NEVQS 32
286 extern __checkReturn efx_rc_t
289 __in unsigned int level);
292 efx_intr_status_line(
294 __out boolean_t *fatalp,
295 __out uint32_t *maskp);
298 efx_intr_status_message(
300 __in unsigned int message,
301 __out boolean_t *fatalp);
305 __in efx_nic_t *enp);
309 __in efx_nic_t *enp);
313 typedef enum efx_link_mode_e {
314 EFX_LINK_UNKNOWN = 0,
327 #define EFX_MAC_ADDR_LEN 6
329 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
331 #define EFX_MAC_MULTICAST_LIST_MAX 256
333 #define EFX_MAC_SDU_MAX 9202
335 #define EFX_MAC_PDU_ADJUSTMENT \
339 + /* bug16011 */ 16) \
341 #define EFX_MAC_PDU(_sdu) \
342 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
345 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
346 * the SDU rounded up slightly.
348 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
350 #define EFX_MAC_PDU_MIN 60
351 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
353 extern __checkReturn efx_rc_t
358 extern __checkReturn efx_rc_t
363 extern __checkReturn efx_rc_t
368 extern __checkReturn efx_rc_t
371 __in boolean_t all_unicst,
372 __in boolean_t mulcst,
373 __in boolean_t all_mulcst,
374 __in boolean_t brdcst);
376 extern __checkReturn efx_rc_t
377 efx_mac_multicast_list_set(
379 __in_ecount(6*count) uint8_t const *addrs,
382 extern __checkReturn efx_rc_t
383 efx_mac_filter_default_rxq_set(
386 __in boolean_t using_rss);
389 efx_mac_filter_default_rxq_clear(
390 __in efx_nic_t *enp);
392 extern __checkReturn efx_rc_t
395 __in boolean_t enabled);
397 extern __checkReturn efx_rc_t
400 __out boolean_t *mac_upp);
402 #define EFX_FCNTL_RESPOND 0x00000001
403 #define EFX_FCNTL_GENERATE 0x00000002
405 extern __checkReturn efx_rc_t
408 __in unsigned int fcntl,
409 __in boolean_t autoneg);
414 __out unsigned int *fcntl_wantedp,
415 __out unsigned int *fcntl_linkp);
420 typedef enum efx_mon_type_e {
432 __in efx_nic_t *enp);
434 #endif /* EFSYS_OPT_NAMES */
436 extern __checkReturn efx_rc_t
438 __in efx_nic_t *enp);
442 __in efx_nic_t *enp);
446 extern __checkReturn efx_rc_t
448 __in efx_nic_t *enp);
450 extern __checkReturn efx_rc_t
452 __in efx_nic_t *enp);
454 extern __checkReturn efx_rc_t
457 __out_opt efx_link_mode_t *link_modep);
461 __in efx_nic_t *enp);
463 typedef enum efx_phy_cap_type_e {
464 EFX_PHY_CAP_INVALID = 0,
471 EFX_PHY_CAP_10000FDX,
475 EFX_PHY_CAP_40000FDX,
477 } efx_phy_cap_type_t;
480 #define EFX_PHY_CAP_CURRENT 0x00000000
481 #define EFX_PHY_CAP_DEFAULT 0x00000001
482 #define EFX_PHY_CAP_PERM 0x00000002
488 __out uint32_t *maskp);
490 extern __checkReturn efx_rc_t
498 __out uint32_t *maskp);
500 extern __checkReturn efx_rc_t
503 __out uint32_t *ouip);
505 typedef enum efx_phy_media_type_e {
506 EFX_PHY_MEDIA_INVALID = 0,
511 EFX_PHY_MEDIA_SFP_PLUS,
512 EFX_PHY_MEDIA_BASE_T,
513 EFX_PHY_MEDIA_QSFP_PLUS,
515 } efx_phy_media_type_t;
517 /* Get the type of medium currently used. If the board has ports for
518 * modules, a module is present, and we recognise the media type of
519 * the module, then this will be the media type of the module.
520 * Otherwise it will be the media type of the port.
523 efx_phy_media_type_get(
525 __out efx_phy_media_type_t *typep);
528 efx_phy_module_get_info(
530 __in uint8_t dev_addr,
533 __out_bcount(len) uint8_t *data);
536 #define EFX_FEATURE_IPV6 0x00000001
537 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
538 #define EFX_FEATURE_LINK_EVENTS 0x00000004
539 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
540 #define EFX_FEATURE_MCDI 0x00000020
541 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
542 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
543 #define EFX_FEATURE_TURBO 0x00000100
544 #define EFX_FEATURE_MCDI_DMA 0x00000200
545 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
546 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
547 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
548 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
549 #define EFX_FEATURE_PACKED_STREAM 0x00004000
551 typedef struct efx_nic_cfg_s {
552 uint32_t enc_board_type;
553 uint32_t enc_phy_type;
555 char enc_phy_name[21];
557 char enc_phy_revision[21];
558 efx_mon_type_t enc_mon_type;
559 unsigned int enc_features;
560 uint8_t enc_mac_addr[6];
561 uint8_t enc_port; /* PHY port number */
562 uint32_t enc_intr_vec_base;
563 uint32_t enc_intr_limit;
564 uint32_t enc_evq_limit;
565 uint32_t enc_txq_limit;
566 uint32_t enc_rxq_limit;
567 uint32_t enc_txq_max_ndescs;
568 uint32_t enc_buftbl_limit;
569 uint32_t enc_piobuf_limit;
570 uint32_t enc_piobuf_size;
571 uint32_t enc_piobuf_min_alloc_size;
572 uint32_t enc_evq_timer_quantum_ns;
573 uint32_t enc_evq_timer_max_us;
574 uint32_t enc_clk_mult;
575 uint32_t enc_rx_prefix_size;
576 uint32_t enc_rx_buf_align_start;
577 uint32_t enc_rx_buf_align_end;
579 uint8_t enc_mcdi_mdio_channel;
580 #endif /* EFSYS_OPT_MCDI */
581 boolean_t enc_bug26807_workaround;
582 boolean_t enc_bug35388_workaround;
583 boolean_t enc_bug41750_workaround;
584 boolean_t enc_bug61265_workaround;
585 boolean_t enc_rx_batching_enabled;
586 /* Maximum number of descriptors completed in an rx event. */
587 uint32_t enc_rx_batch_max;
588 /* Number of rx descriptors the hardware requires for a push. */
589 uint32_t enc_rx_push_align;
591 * Maximum number of bytes into the packet the TCP header can start for
592 * the hardware to apply TSO packet edits.
594 uint32_t enc_tx_tso_tcp_header_offset_limit;
595 boolean_t enc_fw_assisted_tso_enabled;
596 boolean_t enc_fw_assisted_tso_v2_enabled;
597 /* Number of TSO contexts on the NIC (FATSOv2) */
598 uint32_t enc_fw_assisted_tso_v2_n_contexts;
599 boolean_t enc_hw_tx_insert_vlan_enabled;
600 /* Number of PFs on the NIC */
601 uint32_t enc_hw_pf_count;
602 /* Datapath firmware vadapter/vport/vswitch support */
603 boolean_t enc_datapath_cap_evb;
604 boolean_t enc_rx_disable_scatter_supported;
605 boolean_t enc_allow_set_mac_with_installed_filters;
606 boolean_t enc_enhanced_set_mac_supported;
607 boolean_t enc_init_evq_v2_supported;
608 boolean_t enc_rx_packed_stream_supported;
609 boolean_t enc_rx_var_packed_stream_supported;
610 boolean_t enc_pm_and_rxdp_counters;
611 boolean_t enc_mac_stats_40g_tx_size_bins;
612 /* External port identifier */
613 uint8_t enc_external_port;
614 uint32_t enc_mcdi_max_payload_length;
615 /* VPD may be per-PF or global */
616 boolean_t enc_vpd_is_global;
617 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
618 uint32_t enc_required_pcie_bandwidth_mbps;
619 uint32_t enc_max_pcie_link_gen;
620 /* Firmware verifies integrity of NVRAM updates */
621 uint32_t enc_fw_verified_nvram_update_required;
624 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
625 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
627 #define EFX_PCI_FUNCTION(_encp) \
628 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
630 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
632 extern const efx_nic_cfg_t *
634 __in efx_nic_t *enp);
636 /* Driver resource limits (minimum required/maximum usable). */
637 typedef struct efx_drv_limits_s {
638 uint32_t edl_min_evq_count;
639 uint32_t edl_max_evq_count;
641 uint32_t edl_min_rxq_count;
642 uint32_t edl_max_rxq_count;
644 uint32_t edl_min_txq_count;
645 uint32_t edl_max_txq_count;
647 /* PIO blocks (sub-allocated from piobuf) */
648 uint32_t edl_min_pio_alloc_size;
649 uint32_t edl_max_pio_alloc_count;
652 extern __checkReturn efx_rc_t
653 efx_nic_set_drv_limits(
654 __inout efx_nic_t *enp,
655 __in efx_drv_limits_t *edlp);
657 typedef enum efx_nic_region_e {
658 EFX_REGION_VI, /* Memory BAR UC mapping */
659 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
662 extern __checkReturn efx_rc_t
663 efx_nic_get_bar_region(
665 __in efx_nic_region_t region,
666 __out uint32_t *offsetp,
667 __out size_t *sizep);
669 extern __checkReturn efx_rc_t
672 __out uint32_t *evq_countp,
673 __out uint32_t *rxq_countp,
674 __out uint32_t *txq_countp);
679 extern __checkReturn efx_rc_t
680 efx_sram_buf_tbl_set(
683 __in efsys_mem_t *esmp,
687 efx_sram_buf_tbl_clear(
692 #define EFX_BUF_TBL_SIZE 0x20000
694 #define EFX_BUF_SIZE 4096
698 typedef struct efx_evq_s efx_evq_t;
700 extern __checkReturn efx_rc_t
702 __in efx_nic_t *enp);
706 __in efx_nic_t *enp);
708 #define EFX_EVQ_MAXNEVS 32768
709 #define EFX_EVQ_MINNEVS 512
711 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
712 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
714 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
715 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
716 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
717 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
719 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
720 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
721 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
723 extern __checkReturn efx_rc_t
726 __in unsigned int index,
727 __in efsys_mem_t *esmp,
732 __deref_out efx_evq_t **eepp);
739 typedef __checkReturn boolean_t
740 (*efx_initialized_ev_t)(
743 #define EFX_PKT_UNICAST 0x0004
744 #define EFX_PKT_START 0x0008
746 #define EFX_PKT_VLAN_TAGGED 0x0010
747 #define EFX_CKSUM_TCPUDP 0x0020
748 #define EFX_CKSUM_IPV4 0x0040
749 #define EFX_PKT_CONT 0x0080
751 #define EFX_CHECK_VLAN 0x0100
752 #define EFX_PKT_TCP 0x0200
753 #define EFX_PKT_UDP 0x0400
754 #define EFX_PKT_IPV4 0x0800
756 #define EFX_PKT_IPV6 0x1000
757 #define EFX_PKT_PREFIX_LEN 0x2000
758 #define EFX_ADDR_MISMATCH 0x4000
759 #define EFX_DISCARD 0x8000
762 * The following flags are used only for packed stream
763 * mode. The values for the flags are reused to fit into 16 bit,
764 * since EFX_PKT_START and EFX_PKT_CONT are never used in
767 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
768 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
771 #define EFX_EV_RX_NLABELS 32
772 #define EFX_EV_TX_NLABELS 32
774 typedef __checkReturn boolean_t
780 __in uint16_t flags);
782 typedef __checkReturn boolean_t
788 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
789 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
790 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
791 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
792 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
793 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
794 #define EFX_EXCEPTION_RX_ERROR 0x00000007
795 #define EFX_EXCEPTION_TX_ERROR 0x00000008
796 #define EFX_EXCEPTION_EV_ERROR 0x00000009
798 typedef __checkReturn boolean_t
799 (*efx_exception_ev_t)(
804 typedef __checkReturn boolean_t
805 (*efx_rxq_flush_done_ev_t)(
807 __in uint32_t rxq_index);
809 typedef __checkReturn boolean_t
810 (*efx_rxq_flush_failed_ev_t)(
812 __in uint32_t rxq_index);
814 typedef __checkReturn boolean_t
815 (*efx_txq_flush_done_ev_t)(
817 __in uint32_t txq_index);
819 typedef __checkReturn boolean_t
820 (*efx_software_ev_t)(
822 __in uint16_t magic);
824 typedef __checkReturn boolean_t
829 #define EFX_SRAM_CLEAR 0
830 #define EFX_SRAM_UPDATE 1
831 #define EFX_SRAM_ILLEGAL_CLEAR 2
833 typedef __checkReturn boolean_t
836 __in uint32_t label);
838 typedef __checkReturn boolean_t
841 __in uint32_t label);
843 typedef __checkReturn boolean_t
844 (*efx_link_change_ev_t)(
846 __in efx_link_mode_t link_mode);
848 typedef struct efx_ev_callbacks_s {
849 efx_initialized_ev_t eec_initialized;
852 efx_exception_ev_t eec_exception;
853 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
854 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
855 efx_txq_flush_done_ev_t eec_txq_flush_done;
856 efx_software_ev_t eec_software;
857 efx_sram_ev_t eec_sram;
858 efx_wake_up_ev_t eec_wake_up;
859 efx_timer_ev_t eec_timer;
860 efx_link_change_ev_t eec_link_change;
861 } efx_ev_callbacks_t;
863 extern __checkReturn boolean_t
866 __in unsigned int count);
871 __inout unsigned int *countp,
872 __in const efx_ev_callbacks_t *eecp,
875 extern __checkReturn efx_rc_t
876 efx_ev_usecs_to_ticks(
878 __in unsigned int usecs,
879 __out unsigned int *ticksp);
881 extern __checkReturn efx_rc_t
884 __in unsigned int us);
886 extern __checkReturn efx_rc_t
889 __in unsigned int count);
893 __in efx_evq_t *eep);
897 extern __checkReturn efx_rc_t
899 __inout efx_nic_t *enp);
903 __in efx_nic_t *enp);
905 extern __checkReturn efx_rc_t
906 efx_pseudo_hdr_pkt_length_get(
908 __in uint8_t *buffer,
909 __out uint16_t *pkt_lengthp);
911 #define EFX_RXQ_MAXNDESCS 4096
912 #define EFX_RXQ_MINNDESCS 512
914 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
915 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
916 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
917 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
919 typedef enum efx_rxq_type_e {
920 EFX_RXQ_TYPE_DEFAULT,
921 EFX_RXQ_TYPE_SCATTER,
922 EFX_RXQ_TYPE_PACKED_STREAM_1M,
923 EFX_RXQ_TYPE_PACKED_STREAM_512K,
924 EFX_RXQ_TYPE_PACKED_STREAM_256K,
925 EFX_RXQ_TYPE_PACKED_STREAM_128K,
926 EFX_RXQ_TYPE_PACKED_STREAM_64K,
930 extern __checkReturn efx_rc_t
933 __in unsigned int index,
934 __in unsigned int label,
935 __in efx_rxq_type_t type,
936 __in efsys_mem_t *esmp,
940 __deref_out efx_rxq_t **erpp);
942 typedef struct efx_buffer_s {
943 efsys_dma_addr_t eb_addr;
948 typedef struct efx_desc_s {
955 __in_ecount(n) efsys_dma_addr_t *addrp,
958 __in unsigned int completed,
959 __in unsigned int added);
964 __in unsigned int added,
965 __inout unsigned int *pushedp);
967 extern __checkReturn efx_rc_t
969 __in efx_rxq_t *erp);
973 __in efx_rxq_t *erp);
977 __in efx_rxq_t *erp);
981 typedef struct efx_txq_s efx_txq_t;
983 extern __checkReturn efx_rc_t
985 __in efx_nic_t *enp);
989 __in efx_nic_t *enp);
991 #define EFX_TXQ_MINNDESCS 512
993 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
994 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
995 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
996 #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
998 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
1000 #define EFX_TXQ_CKSUM_IPV4 0x0001
1001 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
1002 #define EFX_TXQ_FATSOV2 0x0004
1004 extern __checkReturn efx_rc_t
1006 __in efx_nic_t *enp,
1007 __in unsigned int index,
1008 __in unsigned int label,
1009 __in efsys_mem_t *esmp,
1012 __in uint16_t flags,
1013 __in efx_evq_t *eep,
1014 __deref_out efx_txq_t **etpp,
1015 __out unsigned int *addedp);
1017 extern __checkReturn efx_rc_t
1019 __in efx_txq_t *etp,
1020 __in_ecount(n) efx_buffer_t *eb,
1021 __in unsigned int n,
1022 __in unsigned int completed,
1023 __inout unsigned int *addedp);
1025 extern __checkReturn efx_rc_t
1027 __in efx_txq_t *etp,
1028 __in unsigned int ns);
1032 __in efx_txq_t *etp,
1033 __in unsigned int added,
1034 __in unsigned int pushed);
1036 extern __checkReturn efx_rc_t
1038 __in efx_txq_t *etp);
1042 __in efx_txq_t *etp);
1044 extern __checkReturn efx_rc_t
1046 __in efx_txq_t *etp);
1049 efx_tx_qpio_disable(
1050 __in efx_txq_t *etp);
1052 extern __checkReturn efx_rc_t
1054 __in efx_txq_t *etp,
1055 __in_ecount(buf_length) uint8_t *buffer,
1056 __in size_t buf_length,
1057 __in size_t pio_buf_offset);
1059 extern __checkReturn efx_rc_t
1061 __in efx_txq_t *etp,
1062 __in size_t pkt_length,
1063 __in unsigned int completed,
1064 __inout unsigned int *addedp);
1066 extern __checkReturn efx_rc_t
1068 __in efx_txq_t *etp,
1069 __in_ecount(n) efx_desc_t *ed,
1070 __in unsigned int n,
1071 __in unsigned int completed,
1072 __inout unsigned int *addedp);
1075 efx_tx_qdesc_dma_create(
1076 __in efx_txq_t *etp,
1077 __in efsys_dma_addr_t addr,
1080 __out efx_desc_t *edp);
1083 efx_tx_qdesc_tso_create(
1084 __in efx_txq_t *etp,
1085 __in uint16_t ipv4_id,
1086 __in uint32_t tcp_seq,
1087 __in uint8_t tcp_flags,
1088 __out efx_desc_t *edp);
1090 /* Number of FATSOv2 option descriptors */
1091 #define EFX_TX_FATSOV2_OPT_NDESCS 2
1093 /* Maximum number of DMA segments per TSO packet (not superframe) */
1094 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
1097 efx_tx_qdesc_tso2_create(
1098 __in efx_txq_t *etp,
1099 __in uint16_t ipv4_id,
1100 __in uint32_t tcp_seq,
1101 __in uint16_t tcp_mss,
1102 __out_ecount(count) efx_desc_t *edp,
1106 efx_tx_qdesc_vlantci_create(
1107 __in efx_txq_t *etp,
1109 __out efx_desc_t *edp);
1113 __in efx_txq_t *etp);
1118 #if EFSYS_OPT_FILTER
1120 #define EFX_ETHER_TYPE_IPV4 0x0800
1121 #define EFX_ETHER_TYPE_IPV6 0x86DD
1123 #define EFX_IPPROTO_TCP 6
1124 #define EFX_IPPROTO_UDP 17
1126 /* Use RSS to spread across multiple queues */
1127 #define EFX_FILTER_FLAG_RX_RSS 0x01
1128 /* Enable RX scatter */
1129 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
1131 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
1132 * May only be set by the filter implementation for each type.
1133 * A removal request will restore the automatic filter in its place.
1135 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
1136 /* Filter is for RX */
1137 #define EFX_FILTER_FLAG_RX 0x08
1138 /* Filter is for TX */
1139 #define EFX_FILTER_FLAG_TX 0x10
1141 typedef unsigned int efx_filter_flags_t;
1143 typedef enum efx_filter_match_flags_e {
1144 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host
1146 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host
1148 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */
1149 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */
1150 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */
1151 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */
1152 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */
1153 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */
1154 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */
1155 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport
1157 EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400, /* Match by local MAC address
1158 * I/G bit. Used for RX default
1159 * unicast and multicast/
1160 * broadcast filters. */
1161 } efx_filter_match_flags_t;
1163 typedef enum efx_filter_priority_s {
1164 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
1165 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
1166 * address list or hardware
1167 * requirements. This may only be used
1168 * by the filter implementation for
1170 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
1171 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
1172 * client (e.g. SR-IOV, HyperV VMQ etc.)
1174 } efx_filter_priority_t;
1177 * FIXME: All these fields are assumed to be in little-endian byte order.
1178 * It may be better for some to be big-endian. See bug42804.
1181 typedef struct efx_filter_spec_s {
1182 uint32_t efs_match_flags:12;
1183 uint32_t efs_priority:2;
1184 uint32_t efs_flags:6;
1185 uint32_t efs_dmaq_id:12;
1186 uint32_t efs_rss_context;
1187 uint16_t efs_outer_vid;
1188 uint16_t efs_inner_vid;
1189 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
1190 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
1191 uint16_t efs_ether_type;
1192 uint8_t efs_ip_proto;
1193 uint16_t efs_loc_port;
1194 uint16_t efs_rem_port;
1195 efx_oword_t efs_rem_host;
1196 efx_oword_t efs_loc_host;
1197 } efx_filter_spec_t;
1200 /* Default values for use in filter specifications */
1201 #define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff
1202 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
1203 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
1205 extern __checkReturn efx_rc_t
1207 __in efx_nic_t *enp);
1211 __in efx_nic_t *enp);
1213 extern __checkReturn efx_rc_t
1215 __in efx_nic_t *enp,
1216 __inout efx_filter_spec_t *spec);
1218 extern __checkReturn efx_rc_t
1220 __in efx_nic_t *enp,
1221 __inout efx_filter_spec_t *spec);
1223 extern __checkReturn efx_rc_t
1225 __in efx_nic_t *enp);
1227 extern __checkReturn efx_rc_t
1228 efx_filter_supported_filters(
1229 __in efx_nic_t *enp,
1230 __out uint32_t *list,
1231 __out size_t *length);
1234 efx_filter_spec_init_rx(
1235 __out efx_filter_spec_t *spec,
1236 __in efx_filter_priority_t priority,
1237 __in efx_filter_flags_t flags,
1238 __in efx_rxq_t *erp);
1241 efx_filter_spec_init_tx(
1242 __out efx_filter_spec_t *spec,
1243 __in efx_txq_t *etp);
1245 extern __checkReturn efx_rc_t
1246 efx_filter_spec_set_ipv4_local(
1247 __inout efx_filter_spec_t *spec,
1250 __in uint16_t port);
1252 extern __checkReturn efx_rc_t
1253 efx_filter_spec_set_ipv4_full(
1254 __inout efx_filter_spec_t *spec,
1256 __in uint32_t lhost,
1257 __in uint16_t lport,
1258 __in uint32_t rhost,
1259 __in uint16_t rport);
1261 extern __checkReturn efx_rc_t
1262 efx_filter_spec_set_eth_local(
1263 __inout efx_filter_spec_t *spec,
1265 __in const uint8_t *addr);
1267 extern __checkReturn efx_rc_t
1268 efx_filter_spec_set_uc_def(
1269 __inout efx_filter_spec_t *spec);
1271 extern __checkReturn efx_rc_t
1272 efx_filter_spec_set_mc_def(
1273 __inout efx_filter_spec_t *spec);
1275 #endif /* EFSYS_OPT_FILTER */
1279 extern __checkReturn uint32_t
1281 __in_ecount(count) uint32_t const *input,
1283 __in uint32_t init);
1285 extern __checkReturn uint32_t
1287 __in_ecount(length) uint8_t const *input,
1289 __in uint32_t init);
1297 #endif /* _SYS_EFX_H */