drivers/net/sfc/base/efx_ev.c

   1 /*
   2  * Copyright (c) 2007-2016 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  */
  30
  31 #include "efx.h"
  32 #include "efx_impl.h"
  33
  34 #if EFSYS_OPT_QSTATS
  35 #define EFX_EV_QSTAT_INCR(_eep, _stat)                                  \
  36         do {                                                            \
  37                 (_eep)->ee_stat[_stat]++;                               \
  38         _NOTE(CONSTANTCONDITION)                                        \
  39         } while (B_FALSE)
  40 #else
  41 #define EFX_EV_QSTAT_INCR(_eep, _stat)
  42 #endif
  43
  44 #define EFX_EV_PRESENT(_qword)                                          \
  45         (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff &&        \
  46         EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
  47
  48
  49
  50 #if EFSYS_OPT_SIENA
  51
  52 static  __checkReturn   efx_rc_t
  53 siena_ev_init(
  54         __in            efx_nic_t *enp);
  55
  56 static                  void
  57 siena_ev_fini(
  58         __in            efx_nic_t *enp);
  59
  60 static  __checkReturn   efx_rc_t
  61 siena_ev_qcreate(
  62         __in            efx_nic_t *enp,
  63         __in            unsigned int index,
  64         __in            efsys_mem_t *esmp,
  65         __in            size_t n,
  66         __in            uint32_t id,
  67         __in            uint32_t us,
  68         __in            uint32_t flags,
  69         __in            efx_evq_t *eep);
  70
  71 static                  void
  72 siena_ev_qdestroy(
  73         __in            efx_evq_t *eep);
  74
  75 static  __checkReturn   efx_rc_t
  76 siena_ev_qprime(
  77         __in            efx_evq_t *eep,
  78         __in            unsigned int count);
  79
  80 static                  void
  81 siena_ev_qpost(
  82         __in    efx_evq_t *eep,
  83         __in    uint16_t data);
  84
  85 static  __checkReturn   efx_rc_t
  86 siena_ev_qmoderate(
  87         __in            efx_evq_t *eep,
  88         __in            unsigned int us);
  89
  90 #if EFSYS_OPT_QSTATS
  91 static                  void
  92 siena_ev_qstats_update(
  93         __in                            efx_evq_t *eep,
  94         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat);
  95
  96 #endif
  97
  98 #endif /* EFSYS_OPT_SIENA */
  99
 100 #if EFSYS_OPT_SIENA
 101 static const efx_ev_ops_t       __efx_ev_siena_ops = {
 102         siena_ev_init,                          /* eevo_init */
 103         siena_ev_fini,                          /* eevo_fini */
 104         siena_ev_qcreate,                       /* eevo_qcreate */
 105         siena_ev_qdestroy,                      /* eevo_qdestroy */
 106         siena_ev_qprime,                        /* eevo_qprime */
 107         siena_ev_qpost,                         /* eevo_qpost */
 108         siena_ev_qmoderate,                     /* eevo_qmoderate */
 109 #if EFSYS_OPT_QSTATS
 110         siena_ev_qstats_update,                 /* eevo_qstats_update */
 111 #endif
 112 };
 113 #endif /* EFSYS_OPT_SIENA */
 114
 115 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 116 static const efx_ev_ops_t       __efx_ev_ef10_ops = {
 117         ef10_ev_init,                           /* eevo_init */
 118         ef10_ev_fini,                           /* eevo_fini */
 119         ef10_ev_qcreate,                        /* eevo_qcreate */
 120         ef10_ev_qdestroy,                       /* eevo_qdestroy */
 121         ef10_ev_qprime,                         /* eevo_qprime */
 122         ef10_ev_qpost,                          /* eevo_qpost */
 123         ef10_ev_qmoderate,                      /* eevo_qmoderate */
 124 #if EFSYS_OPT_QSTATS
 125         ef10_ev_qstats_update,                  /* eevo_qstats_update */
 126 #endif
 127 };
 128 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 129
 130
 131         __checkReturn   efx_rc_t
 132 efx_ev_init(
 133         __in            efx_nic_t *enp)
 134 {
 135         const efx_ev_ops_t *eevop;
 136         efx_rc_t rc;
 137
 138         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 139         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
 140
 141         if (enp->en_mod_flags & EFX_MOD_EV) {
 142                 rc = EINVAL;
 143                 goto fail1;
 144         }
 145
 146         switch (enp->en_family) {
 147 #if EFSYS_OPT_SIENA
 148         case EFX_FAMILY_SIENA:
 149                 eevop = &__efx_ev_siena_ops;
 150                 break;
 151 #endif /* EFSYS_OPT_SIENA */
 152
 153 #if EFSYS_OPT_HUNTINGTON
 154         case EFX_FAMILY_HUNTINGTON:
 155                 eevop = &__efx_ev_ef10_ops;
 156                 break;
 157 #endif /* EFSYS_OPT_HUNTINGTON */
 158
 159 #if EFSYS_OPT_MEDFORD
 160         case EFX_FAMILY_MEDFORD:
 161                 eevop = &__efx_ev_ef10_ops;
 162                 break;
 163 #endif /* EFSYS_OPT_MEDFORD */
 164
 165         default:
 166                 EFSYS_ASSERT(0);
 167                 rc = ENOTSUP;
 168                 goto fail1;
 169         }
 170
 171         EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
 172
 173         if ((rc = eevop->eevo_init(enp)) != 0)
 174                 goto fail2;
 175
 176         enp->en_eevop = eevop;
 177         enp->en_mod_flags |= EFX_MOD_EV;
 178         return (0);
 179
 180 fail2:
 181         EFSYS_PROBE(fail2);
 182
 183 fail1:
 184         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 185
 186         enp->en_eevop = NULL;
 187         enp->en_mod_flags &= ~EFX_MOD_EV;
 188         return (rc);
 189 }
 190
 191                 void
 192 efx_ev_fini(
 193         __in    efx_nic_t *enp)
 194 {
 195         const efx_ev_ops_t *eevop = enp->en_eevop;
 196
 197         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 198         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
 199         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
 200         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 201         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 202         EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
 203
 204         eevop->eevo_fini(enp);
 205
 206         enp->en_eevop = NULL;
 207         enp->en_mod_flags &= ~EFX_MOD_EV;
 208 }
 209
 210
 211         __checkReturn   efx_rc_t
 212 efx_ev_qcreate(
 213         __in            efx_nic_t *enp,
 214         __in            unsigned int index,
 215         __in            efsys_mem_t *esmp,
 216         __in            size_t n,
 217         __in            uint32_t id,
 218         __in            uint32_t us,
 219         __in            uint32_t flags,
 220         __deref_out     efx_evq_t **eepp)
 221 {
 222         const efx_ev_ops_t *eevop = enp->en_eevop;
 223         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 224         efx_evq_t *eep;
 225         efx_rc_t rc;
 226
 227         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 228         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
 229
 230         EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit);
 231
 232         switch (flags & EFX_EVQ_FLAGS_NOTIFY_MASK) {
 233         case EFX_EVQ_FLAGS_NOTIFY_INTERRUPT:
 234                 break;
 235         case EFX_EVQ_FLAGS_NOTIFY_DISABLED:
 236                 if (us != 0) {
 237                         rc = EINVAL;
 238                         goto fail1;
 239                 }
 240                 break;
 241         default:
 242                 rc = EINVAL;
 243                 goto fail2;
 244         }
 245
 246         /* Allocate an EVQ object */
 247         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
 248         if (eep == NULL) {
 249                 rc = ENOMEM;
 250                 goto fail3;
 251         }
 252
 253         eep->ee_magic = EFX_EVQ_MAGIC;
 254         eep->ee_enp = enp;
 255         eep->ee_index = index;
 256         eep->ee_mask = n - 1;
 257         eep->ee_flags = flags;
 258         eep->ee_esmp = esmp;
 259
 260         /*
 261          * Set outputs before the queue is created because interrupts may be
 262          * raised for events immediately after the queue is created, before the
 263          * function call below returns. See bug58606.
 264          *
 265          * The eepp pointer passed in by the client must therefore point to data
 266          * shared with the client's event processing context.
 267          */
 268         enp->en_ev_qcount++;
 269         *eepp = eep;
 270
 271         if ((rc = eevop->eevo_qcreate(enp, index, esmp, n, id, us, flags,
 272             eep)) != 0)
 273                 goto fail4;
 274
 275         return (0);
 276
 277 fail4:
 278         EFSYS_PROBE(fail4);
 279
 280         *eepp = NULL;
 281         enp->en_ev_qcount--;
 282         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
 283 fail3:
 284         EFSYS_PROBE(fail3);
 285 fail2:
 286         EFSYS_PROBE(fail2);
 287 fail1:
 288         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 289         return (rc);
 290 }
 291
 292                 void
 293 efx_ev_qdestroy(
 294         __in    efx_evq_t *eep)
 295 {
 296         efx_nic_t *enp = eep->ee_enp;
 297         const efx_ev_ops_t *eevop = enp->en_eevop;
 298
 299         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 300
 301         EFSYS_ASSERT(enp->en_ev_qcount != 0);
 302         --enp->en_ev_qcount;
 303
 304         eevop->eevo_qdestroy(eep);
 305
 306         /* Free the EVQ object */
 307         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
 308 }
 309
 310         __checkReturn   efx_rc_t
 311 efx_ev_qprime(
 312         __in            efx_evq_t *eep,
 313         __in            unsigned int count)
 314 {
 315         efx_nic_t *enp = eep->ee_enp;
 316         const efx_ev_ops_t *eevop = enp->en_eevop;
 317         efx_rc_t rc;
 318
 319         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 320
 321         if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
 322                 rc = EINVAL;
 323                 goto fail1;
 324         }
 325
 326         if ((rc = eevop->eevo_qprime(eep, count)) != 0)
 327                 goto fail2;
 328
 329         return (0);
 330
 331 fail2:
 332         EFSYS_PROBE(fail2);
 333 fail1:
 334         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 335         return (rc);
 336 }
 337
 338         __checkReturn   boolean_t
 339 efx_ev_qpending(
 340         __in            efx_evq_t *eep,
 341         __in            unsigned int count)
 342 {
 343         size_t offset;
 344         efx_qword_t qword;
 345
 346         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 347
 348         offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 349         EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
 350
 351         return (EFX_EV_PRESENT(qword));
 352 }
 353
 354 #if EFSYS_OPT_EV_PREFETCH
 355
 356                         void
 357 efx_ev_qprefetch(
 358         __in            efx_evq_t *eep,
 359         __in            unsigned int count)
 360 {
 361         unsigned int offset;
 362
 363         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 364
 365         offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 366         EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
 367 }
 368
 369 #endif  /* EFSYS_OPT_EV_PREFETCH */
 370
 371 #define EFX_EV_BATCH    8
 372
 373                         void
 374 efx_ev_qpoll(
 375         __in            efx_evq_t *eep,
 376         __inout         unsigned int *countp,
 377         __in            const efx_ev_callbacks_t *eecp,
 378         __in_opt        void *arg)
 379 {
 380         efx_qword_t ev[EFX_EV_BATCH];
 381         unsigned int batch;
 382         unsigned int total;
 383         unsigned int count;
 384         unsigned int index;
 385         size_t offset;
 386
 387         /* Ensure events codes match for EF10 (Huntington/Medford) and Siena */
 388         EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);
 389         EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);
 390
 391         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);
 392         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);
 393         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);
 394         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==
 395             FSE_AZ_EV_CODE_DRV_GEN_EV);
 396 #if EFSYS_OPT_MCDI
 397         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==
 398             FSE_AZ_EV_CODE_MCDI_EVRESPONSE);
 399 #endif
 400
 401         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 402         EFSYS_ASSERT(countp != NULL);
 403         EFSYS_ASSERT(eecp != NULL);
 404
 405         count = *countp;
 406         do {
 407                 /* Read up until the end of the batch period */
 408                 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));
 409                 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 410                 for (total = 0; total < batch; ++total) {
 411                         EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
 412
 413                         if (!EFX_EV_PRESENT(ev[total]))
 414                                 break;
 415
 416                         EFSYS_PROBE3(event, unsigned int, eep->ee_index,
 417                             uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
 418                             uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
 419
 420                         offset += sizeof (efx_qword_t);
 421                 }
 422
 423 #if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1)
 424                 /*
 425                  * Prefetch the next batch when we get within PREFETCH_PERIOD
 426                  * of a completed batch. If the batch is smaller, then prefetch
 427                  * immediately.
 428                  */
 429                 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD)
 430                         EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
 431 #endif  /* EFSYS_OPT_EV_PREFETCH */
 432
 433                 /* Process the batch of events */
 434                 for (index = 0; index < total; ++index) {
 435                         boolean_t should_abort;
 436                         uint32_t code;
 437
 438 #if EFSYS_OPT_EV_PREFETCH
 439                         /* Prefetch if we've now reached the batch period */
 440                         if (total == batch &&
 441                             index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) {
 442                                 offset = (count + batch) & eep->ee_mask;
 443                                 offset *= sizeof (efx_qword_t);
 444
 445                                 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
 446                         }
 447 #endif  /* EFSYS_OPT_EV_PREFETCH */
 448
 449                         EFX_EV_QSTAT_INCR(eep, EV_ALL);
 450
 451                         code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
 452                         switch (code) {
 453                         case FSE_AZ_EV_CODE_RX_EV:
 454                                 should_abort = eep->ee_rx(eep,
 455                                     &(ev[index]), eecp, arg);
 456                                 break;
 457                         case FSE_AZ_EV_CODE_TX_EV:
 458                                 should_abort = eep->ee_tx(eep,
 459                                     &(ev[index]), eecp, arg);
 460                                 break;
 461                         case FSE_AZ_EV_CODE_DRIVER_EV:
 462                                 should_abort = eep->ee_driver(eep,
 463                                     &(ev[index]), eecp, arg);
 464                                 break;
 465                         case FSE_AZ_EV_CODE_DRV_GEN_EV:
 466                                 should_abort = eep->ee_drv_gen(eep,
 467                                     &(ev[index]), eecp, arg);
 468                                 break;
 469 #if EFSYS_OPT_MCDI
 470                         case FSE_AZ_EV_CODE_MCDI_EVRESPONSE:
 471                                 should_abort = eep->ee_mcdi(eep,
 472                                     &(ev[index]), eecp, arg);
 473                                 break;
 474 #endif
 475                         case FSE_AZ_EV_CODE_GLOBAL_EV:
 476                                 if (eep->ee_global) {
 477                                         should_abort = eep->ee_global(eep,
 478                                             &(ev[index]), eecp, arg);
 479                                         break;
 480                                 }
 481                                 /* else fallthrough */
 482                         default:
 483                                 EFSYS_PROBE3(bad_event,
 484                                     unsigned int, eep->ee_index,
 485                                     uint32_t,
 486                                     EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),
 487                                     uint32_t,
 488                                     EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));
 489
 490                                 EFSYS_ASSERT(eecp->eec_exception != NULL);
 491                                 (void) eecp->eec_exception(arg,
 492                                         EFX_EXCEPTION_EV_ERROR, code);
 493                                 should_abort = B_TRUE;
 494                         }
 495                         if (should_abort) {
 496                                 /* Ignore subsequent events */
 497                                 total = index + 1;
 498                                 break;
 499                         }
 500                 }
 501
 502                 /*
 503                  * Now that the hardware has most likely moved onto dma'ing
 504                  * into the next cache line, clear the processed events. Take
 505                  * care to only clear out events that we've processed
 506                  */
 507                 EFX_SET_QWORD(ev[0]);
 508                 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 509                 for (index = 0; index < total; ++index) {
 510                         EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));
 511                         offset += sizeof (efx_qword_t);
 512                 }
 513
 514                 count += total;
 515
 516         } while (total == batch);
 517
 518         *countp = count;
 519 }
 520
 521                         void
 522 efx_ev_qpost(
 523         __in    efx_evq_t *eep,
 524         __in    uint16_t data)
 525 {
 526         efx_nic_t *enp = eep->ee_enp;
 527         const efx_ev_ops_t *eevop = enp->en_eevop;
 528
 529         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 530
 531         EFSYS_ASSERT(eevop != NULL &&
 532             eevop->eevo_qpost != NULL);
 533
 534         eevop->eevo_qpost(eep, data);
 535 }
 536
 537         __checkReturn   efx_rc_t
 538 efx_ev_usecs_to_ticks(
 539         __in            efx_nic_t *enp,
 540         __in            unsigned int us,
 541         __out           unsigned int *ticksp)
 542 {
 543         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 544         unsigned int ticks;
 545
 546         /* Convert microseconds to a timer tick count */
 547         if (us == 0)
 548                 ticks = 0;
 549         else if (us * 1000 < encp->enc_evq_timer_quantum_ns)
 550                 ticks = 1;      /* Never round down to zero */
 551         else
 552                 ticks = us * 1000 / encp->enc_evq_timer_quantum_ns;
 553
 554         *ticksp = ticks;
 555         return (0);
 556 }
 557
 558         __checkReturn   efx_rc_t
 559 efx_ev_qmoderate(
 560         __in            efx_evq_t *eep,
 561         __in            unsigned int us)
 562 {
 563         efx_nic_t *enp = eep->ee_enp;
 564         const efx_ev_ops_t *eevop = enp->en_eevop;
 565         efx_rc_t rc;
 566
 567         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 568
 569         if ((eep->ee_flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
 570             EFX_EVQ_FLAGS_NOTIFY_DISABLED) {
 571                 rc = EINVAL;
 572                 goto fail1;
 573         }
 574
 575         if ((rc = eevop->eevo_qmoderate(eep, us)) != 0)
 576                 goto fail2;
 577
 578         return (0);
 579
 580 fail2:
 581         EFSYS_PROBE(fail2);
 582 fail1:
 583         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 584         return (rc);
 585 }
 586
 587 #if EFSYS_OPT_QSTATS
 588                                         void
 589 efx_ev_qstats_update(
 590         __in                            efx_evq_t *eep,
 591         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat)
 592
 593 {       efx_nic_t *enp = eep->ee_enp;
 594         const efx_ev_ops_t *eevop = enp->en_eevop;
 595
 596         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 597
 598         eevop->eevo_qstats_update(eep, stat);
 599 }
 600
 601 #endif  /* EFSYS_OPT_QSTATS */
 602
 603 #if EFSYS_OPT_SIENA
 604
 605 static  __checkReturn   efx_rc_t
 606 siena_ev_init(
 607         __in            efx_nic_t *enp)
 608 {
 609         efx_oword_t oword;
 610
 611         /*
 612          * Program the event queue for receive and transmit queue
 613          * flush events.
 614          */
 615         EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword);
 616         EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
 617         EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
 618
 619         return (0);
 620
 621 }
 622
 623 static  __checkReturn   boolean_t
 624 siena_ev_rx_not_ok(
 625         __in            efx_evq_t *eep,
 626         __in            efx_qword_t *eqp,
 627         __in            uint32_t label,
 628         __in            uint32_t id,
 629         __inout         uint16_t *flagsp)
 630 {
 631         boolean_t ignore = B_FALSE;
 632
 633         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) {
 634                 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC);
 635                 EFSYS_PROBE(tobe_disc);
 636                 /*
 637                  * Assume this is a unicast address mismatch, unless below
 638                  * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or
 639                  * EV_RX_PAUSE_FRM_ERR is set.
 640                  */
 641                 (*flagsp) |= EFX_ADDR_MISMATCH;
 642         }
 643
 644         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) {
 645                 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id);
 646                 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
 647                 (*flagsp) |= EFX_DISCARD;
 648
 649 #if EFSYS_OPT_RX_SCATTER
 650                 /*
 651                  * Lookout for payload queue ran dry errors and ignore them.
 652                  *
 653                  * Sadly for the header/data split cases, the descriptor
 654                  * pointer in this event refers to the header queue and
 655                  * therefore cannot be easily detected as duplicate.
 656                  * So we drop these and rely on the receive processing seeing
 657                  * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard
 658                  * the partially received packet.
 659                  */
 660                 if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) &&
 661                     (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) &&
 662                     (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0))
 663                         ignore = B_TRUE;
 664 #endif  /* EFSYS_OPT_RX_SCATTER */
 665         }
 666
 667         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) {
 668                 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
 669                 EFSYS_PROBE(crc_err);
 670                 (*flagsp) &= ~EFX_ADDR_MISMATCH;
 671                 (*flagsp) |= EFX_DISCARD;
 672         }
 673
 674         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) {
 675                 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR);
 676                 EFSYS_PROBE(pause_frm_err);
 677                 (*flagsp) &= ~EFX_ADDR_MISMATCH;
 678                 (*flagsp) |= EFX_DISCARD;
 679         }
 680
 681         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) {
 682                 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR);
 683                 EFSYS_PROBE(owner_id_err);
 684                 (*flagsp) |= EFX_DISCARD;
 685         }
 686
 687         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) {
 688                 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
 689                 EFSYS_PROBE(ipv4_err);
 690                 (*flagsp) &= ~EFX_CKSUM_IPV4;
 691         }
 692
 693         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) {
 694                 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
 695                 EFSYS_PROBE(udp_chk_err);
 696                 (*flagsp) &= ~EFX_CKSUM_TCPUDP;
 697         }
 698
 699         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) {
 700                 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR);
 701
 702                 /*
 703                  * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This
 704                  * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error
 705                  * condition.
 706                  */
 707                 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP);
 708         }
 709
 710         return (ignore);
 711 }
 712
 713 static  __checkReturn   boolean_t
 714 siena_ev_rx(
 715         __in            efx_evq_t *eep,
 716         __in            efx_qword_t *eqp,
 717         __in            const efx_ev_callbacks_t *eecp,
 718         __in_opt        void *arg)
 719 {
 720         uint32_t id;
 721         uint32_t size;
 722         uint32_t label;
 723         boolean_t ok;
 724 #if EFSYS_OPT_RX_SCATTER
 725         boolean_t sop;
 726         boolean_t jumbo_cont;
 727 #endif  /* EFSYS_OPT_RX_SCATTER */
 728         uint32_t hdr_type;
 729         boolean_t is_v6;
 730         uint16_t flags;
 731         boolean_t ignore;
 732         boolean_t should_abort;
 733
 734         EFX_EV_QSTAT_INCR(eep, EV_RX);
 735
 736         /* Basic packet information */
 737         id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR);
 738         size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT);
 739         label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL);
 740         ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0);
 741
 742 #if EFSYS_OPT_RX_SCATTER
 743         sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0);
 744         jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0);
 745 #endif  /* EFSYS_OPT_RX_SCATTER */
 746
 747         hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE);
 748
 749         is_v6 = (EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0);
 750
 751         /*
 752          * If packet is marked as OK and packet type is TCP/IP or
 753          * UDP/IP or other IP, then we can rely on the hardware checksums.
 754          */
 755         switch (hdr_type) {
 756         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
 757                 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP;
 758                 if (is_v6) {
 759                         EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
 760                         flags |= EFX_PKT_IPV6;
 761                 } else {
 762                         EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
 763                         flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
 764                 }
 765                 break;
 766
 767         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
 768                 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP;
 769                 if (is_v6) {
 770                         EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
 771                         flags |= EFX_PKT_IPV6;
 772                 } else {
 773                         EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
 774                         flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
 775                 }
 776                 break;
 777
 778         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
 779                 if (is_v6) {
 780                         EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
 781                         flags = EFX_PKT_IPV6;
 782                 } else {
 783                         EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
 784                         flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
 785                 }
 786                 break;
 787
 788         case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
 789                 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
 790                 flags = 0;
 791                 break;
 792
 793         default:
 794                 EFSYS_ASSERT(B_FALSE);
 795                 flags = 0;
 796                 break;
 797         }
 798
 799 #if EFSYS_OPT_RX_SCATTER
 800         /* Report scatter and header/lookahead split buffer flags */
 801         if (sop)
 802                 flags |= EFX_PKT_START;
 803         if (jumbo_cont)
 804                 flags |= EFX_PKT_CONT;
 805 #endif  /* EFSYS_OPT_RX_SCATTER */
 806
 807         /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
 808         if (!ok) {
 809                 ignore = siena_ev_rx_not_ok(eep, eqp, label, id, &flags);
 810                 if (ignore) {
 811                         EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
 812                             uint32_t, size, uint16_t, flags);
 813
 814                         return (B_FALSE);
 815                 }
 816         }
 817
 818         /* If we're not discarding the packet then it is ok */
 819         if (~flags & EFX_DISCARD)
 820                 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
 821
 822         /* Detect multicast packets that didn't match the filter */
 823         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) {
 824                 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT);
 825
 826                 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) {
 827                         EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH);
 828                 } else {
 829                         EFSYS_PROBE(mcast_mismatch);
 830                         flags |= EFX_ADDR_MISMATCH;
 831                 }
 832         } else {
 833                 flags |= EFX_PKT_UNICAST;
 834         }
 835
 836         /*
 837          * The packet parser in Siena can abort parsing packets under
 838          * certain error conditions, setting the PKT_NOT_PARSED bit
 839          * (which clears PKT_OK). If this is set, then don't trust
 840          * the PKT_TYPE field.
 841          */
 842         if (!ok) {
 843                 uint32_t parse_err;
 844
 845                 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED);
 846                 if (parse_err != 0)
 847                         flags |= EFX_CHECK_VLAN;
 848         }
 849
 850         if (~flags & EFX_CHECK_VLAN) {
 851                 uint32_t pkt_type;
 852
 853                 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE);
 854                 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN)
 855                         flags |= EFX_PKT_VLAN_TAGGED;
 856         }
 857
 858         EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
 859             uint32_t, size, uint16_t, flags);
 860
 861         EFSYS_ASSERT(eecp->eec_rx != NULL);
 862         should_abort = eecp->eec_rx(arg, label, id, size, flags);
 863
 864         return (should_abort);
 865 }
 866
 867 static  __checkReturn   boolean_t
 868 siena_ev_tx(
 869         __in            efx_evq_t *eep,
 870         __in            efx_qword_t *eqp,
 871         __in            const efx_ev_callbacks_t *eecp,
 872         __in_opt        void *arg)
 873 {
 874         uint32_t id;
 875         uint32_t label;
 876         boolean_t should_abort;
 877
 878         EFX_EV_QSTAT_INCR(eep, EV_TX);
 879
 880         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 &&
 881             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
 882             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
 883             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
 884
 885                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
 886                 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);
 887
 888                 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
 889
 890                 EFSYS_ASSERT(eecp->eec_tx != NULL);
 891                 should_abort = eecp->eec_tx(arg, label, id);
 892
 893                 return (should_abort);
 894         }
 895
 896         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0)
 897                 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
 898                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
 899                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
 900
 901         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0)
 902                 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR);
 903
 904         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0)
 905                 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG);
 906
 907         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0)
 908                 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL);
 909
 910         EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED);
 911         return (B_FALSE);
 912 }
 913
 914 static  __checkReturn   boolean_t
 915 siena_ev_global(
 916         __in            efx_evq_t *eep,
 917         __in            efx_qword_t *eqp,
 918         __in            const efx_ev_callbacks_t *eecp,
 919         __in_opt        void *arg)
 920 {
 921         _NOTE(ARGUNUSED(eqp, eecp, arg))
 922
 923         EFX_EV_QSTAT_INCR(eep, EV_GLOBAL);
 924
 925         return (B_FALSE);
 926 }
 927
 928 static  __checkReturn   boolean_t
 929 siena_ev_driver(
 930         __in            efx_evq_t *eep,
 931         __in            efx_qword_t *eqp,
 932         __in            const efx_ev_callbacks_t *eecp,
 933         __in_opt        void *arg)
 934 {
 935         boolean_t should_abort;
 936
 937         EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
 938         should_abort = B_FALSE;
 939
 940         switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) {
 941         case FSE_AZ_TX_DESCQ_FLS_DONE_EV: {
 942                 uint32_t txq_index;
 943
 944                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
 945
 946                 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
 947
 948                 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
 949
 950                 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
 951                 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
 952
 953                 break;
 954         }
 955         case FSE_AZ_RX_DESCQ_FLS_DONE_EV: {
 956                 uint32_t rxq_index;
 957                 uint32_t failed;
 958
 959                 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
 960                 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
 961
 962                 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
 963                 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL);
 964
 965                 if (failed) {
 966                         EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED);
 967
 968                         EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
 969
 970                         should_abort = eecp->eec_rxq_flush_failed(arg,
 971                                                                     rxq_index);
 972                 } else {
 973                         EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
 974
 975                         EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
 976
 977                         should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
 978                 }
 979
 980                 break;
 981         }
 982         case FSE_AZ_EVQ_INIT_DONE_EV:
 983                 EFSYS_ASSERT(eecp->eec_initialized != NULL);
 984                 should_abort = eecp->eec_initialized(arg);
 985
 986                 break;
 987
 988         case FSE_AZ_EVQ_NOT_EN_EV:
 989                 EFSYS_PROBE(evq_not_en);
 990                 break;
 991
 992         case FSE_AZ_SRM_UPD_DONE_EV: {
 993                 uint32_t code;
 994
 995                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE);
 996
 997                 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
 998
 999                 EFSYS_ASSERT(eecp->eec_sram != NULL);
1000                 should_abort = eecp->eec_sram(arg, code);
1001
1002                 break;
1003         }
1004         case FSE_AZ_WAKE_UP_EV: {
1005                 uint32_t id;
1006
1007                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
1008
1009                 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
1010                 should_abort = eecp->eec_wake_up(arg, id);
1011
1012                 break;
1013         }
1014         case FSE_AZ_TX_PKT_NON_TCP_UDP:
1015                 EFSYS_PROBE(tx_pkt_non_tcp_udp);
1016                 break;
1017
1018         case FSE_AZ_TIMER_EV: {
1019                 uint32_t id;
1020
1021                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
1022
1023                 EFSYS_ASSERT(eecp->eec_timer != NULL);
1024                 should_abort = eecp->eec_timer(arg, id);
1025
1026                 break;
1027         }
1028         case FSE_AZ_RX_DSC_ERROR_EV:
1029                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR);
1030
1031                 EFSYS_PROBE(rx_dsc_error);
1032
1033                 EFSYS_ASSERT(eecp->eec_exception != NULL);
1034                 should_abort = eecp->eec_exception(arg,
1035                         EFX_EXCEPTION_RX_DSC_ERROR, 0);
1036
1037                 break;
1038
1039         case FSE_AZ_TX_DSC_ERROR_EV:
1040                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR);
1041
1042                 EFSYS_PROBE(tx_dsc_error);
1043
1044                 EFSYS_ASSERT(eecp->eec_exception != NULL);
1045                 should_abort = eecp->eec_exception(arg,
1046                         EFX_EXCEPTION_TX_DSC_ERROR, 0);
1047
1048                 break;
1049
1050         default:
1051                 break;
1052         }
1053
1054         return (should_abort);
1055 }
1056
1057 static  __checkReturn   boolean_t
1058 siena_ev_drv_gen(
1059         __in            efx_evq_t *eep,
1060         __in            efx_qword_t *eqp,
1061         __in            const efx_ev_callbacks_t *eecp,
1062         __in_opt        void *arg)
1063 {
1064         uint32_t data;
1065         boolean_t should_abort;
1066
1067         EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
1068
1069         data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0);
1070         if (data >= ((uint32_t)1 << 16)) {
1071                 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1072                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1073                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1074                 return (B_TRUE);
1075         }
1076
1077         EFSYS_ASSERT(eecp->eec_software != NULL);
1078         should_abort = eecp->eec_software(arg, (uint16_t)data);
1079
1080         return (should_abort);
1081 }
1082
1083 #if EFSYS_OPT_MCDI
1084
1085 static  __checkReturn   boolean_t
1086 siena_ev_mcdi(
1087         __in            efx_evq_t *eep,
1088         __in            efx_qword_t *eqp,
1089         __in            const efx_ev_callbacks_t *eecp,
1090         __in_opt        void *arg)
1091 {
1092         efx_nic_t *enp = eep->ee_enp;
1093         unsigned int code;
1094         boolean_t should_abort = B_FALSE;
1095
1096         EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
1097
1098         if (enp->en_family != EFX_FAMILY_SIENA)
1099                 goto out;
1100
1101         EFSYS_ASSERT(eecp->eec_link_change != NULL);
1102         EFSYS_ASSERT(eecp->eec_exception != NULL);
1103
1104         EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
1105
1106         code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
1107         switch (code) {
1108         case MCDI_EVENT_CODE_BADSSERT:
1109                 efx_mcdi_ev_death(enp, EINTR);
1110                 break;
1111
1112         case MCDI_EVENT_CODE_CMDDONE:
1113                 efx_mcdi_ev_cpl(enp,
1114                     MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
1115                     MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
1116                     MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
1117                 break;
1118
1119         case MCDI_EVENT_CODE_LINKCHANGE: {
1120                 efx_link_mode_t link_mode;
1121
1122                 siena_phy_link_ev(enp, eqp, &link_mode);
1123                 should_abort = eecp->eec_link_change(arg, link_mode);
1124                 break;
1125         }
1126         case MCDI_EVENT_CODE_SENSOREVT: {
1127                 should_abort = B_FALSE;
1128                 break;
1129         }
1130         case MCDI_EVENT_CODE_SCHEDERR:
1131                 /* Informational only */
1132                 break;
1133
1134         case MCDI_EVENT_CODE_REBOOT:
1135                 efx_mcdi_ev_death(enp, EIO);
1136                 break;
1137
1138         case MCDI_EVENT_CODE_MAC_STATS_DMA:
1139 #if EFSYS_OPT_MAC_STATS
1140                 if (eecp->eec_mac_stats != NULL) {
1141                         eecp->eec_mac_stats(arg,
1142                             MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1143                 }
1144 #endif
1145                 break;
1146
1147         case MCDI_EVENT_CODE_FWALERT: {
1148                 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1149
1150                 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1151                         should_abort = eecp->eec_exception(arg,
1152                                 EFX_EXCEPTION_FWALERT_SRAM,
1153                                 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1154                 else
1155                         should_abort = eecp->eec_exception(arg,
1156                                 EFX_EXCEPTION_UNKNOWN_FWALERT,
1157                                 MCDI_EV_FIELD(eqp, DATA));
1158                 break;
1159         }
1160
1161         default:
1162                 EFSYS_PROBE1(mc_pcol_error, int, code);
1163                 break;
1164         }
1165
1166 out:
1167         return (should_abort);
1168 }
1169
1170 #endif  /* EFSYS_OPT_MCDI */
1171
1172 static  __checkReturn   efx_rc_t
1173 siena_ev_qprime(
1174         __in            efx_evq_t *eep,
1175         __in            unsigned int count)
1176 {
1177         efx_nic_t *enp = eep->ee_enp;
1178         uint32_t rptr;
1179         efx_dword_t dword;
1180
1181         rptr = count & eep->ee_mask;
1182
1183         EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr);
1184
1185         EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index,
1186                             &dword, B_FALSE);
1187
1188         return (0);
1189 }
1190
1191 static          void
1192 siena_ev_qpost(
1193         __in    efx_evq_t *eep,
1194         __in    uint16_t data)
1195 {
1196         efx_nic_t *enp = eep->ee_enp;
1197         efx_qword_t ev;
1198         efx_oword_t oword;
1199
1200         EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
1201             FSF_AZ_EV_DATA_DW0, (uint32_t)data);
1202
1203         EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index,
1204             EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0),
1205             EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1));
1206
1207         EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
1208 }
1209
1210 static  __checkReturn   efx_rc_t
1211 siena_ev_qmoderate(
1212         __in            efx_evq_t *eep,
1213         __in            unsigned int us)
1214 {
1215         efx_nic_t *enp = eep->ee_enp;
1216         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1217         unsigned int locked;
1218         efx_dword_t dword;
1219         efx_rc_t rc;
1220
1221         if (us > encp->enc_evq_timer_max_us) {
1222                 rc = EINVAL;
1223                 goto fail1;
1224         }
1225
1226         /* If the value is zero then disable the timer */
1227         if (us == 0) {
1228                 EFX_POPULATE_DWORD_2(dword,
1229                     FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS,
1230                     FRF_CZ_TC_TIMER_VAL, 0);
1231         } else {
1232                 unsigned int ticks;
1233
1234                 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
1235                         goto fail2;
1236
1237                 EFSYS_ASSERT(ticks > 0);
1238                 EFX_POPULATE_DWORD_2(dword,
1239                     FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF,
1240                     FRF_CZ_TC_TIMER_VAL, ticks - 1);
1241         }
1242
1243         locked = (eep->ee_index == 0) ? 1 : 0;
1244
1245         EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0,
1246             eep->ee_index, &dword, locked);
1247
1248         return (0);
1249
1250 fail2:
1251         EFSYS_PROBE(fail2);
1252 fail1:
1253         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1254
1255         return (rc);
1256 }
1257
1258 static  __checkReturn   efx_rc_t
1259 siena_ev_qcreate(
1260         __in            efx_nic_t *enp,
1261         __in            unsigned int index,
1262         __in            efsys_mem_t *esmp,
1263         __in            size_t n,
1264         __in            uint32_t id,
1265         __in            uint32_t us,
1266         __in            uint32_t flags,
1267         __in            efx_evq_t *eep)
1268 {
1269         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1270         uint32_t size;
1271         efx_oword_t oword;
1272         efx_rc_t rc;
1273         boolean_t notify_mode;
1274
1275         _NOTE(ARGUNUSED(esmp))
1276
1277         EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
1278         EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
1279
1280         if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) {
1281                 rc = EINVAL;
1282                 goto fail1;
1283         }
1284         if (index >= encp->enc_evq_limit) {
1285                 rc = EINVAL;
1286                 goto fail2;
1287         }
1288         for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS);
1289             size++)
1290                 if ((1 << size) == (int)(n / EFX_EVQ_MINNEVS))
1291                         break;
1292         if (id + (1 << size) >= encp->enc_buftbl_limit) {
1293                 rc = EINVAL;
1294                 goto fail4;
1295         }
1296
1297         /* Set up the handler table */
1298         eep->ee_rx      = siena_ev_rx;
1299         eep->ee_tx      = siena_ev_tx;
1300         eep->ee_driver  = siena_ev_driver;
1301         eep->ee_global  = siena_ev_global;
1302         eep->ee_drv_gen = siena_ev_drv_gen;
1303 #if EFSYS_OPT_MCDI
1304         eep->ee_mcdi    = siena_ev_mcdi;
1305 #endif  /* EFSYS_OPT_MCDI */
1306
1307         notify_mode = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) !=
1308             EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
1309
1310         /* Set up the new event queue */
1311         EFX_POPULATE_OWORD_3(oword, FRF_CZ_TIMER_Q_EN, 1,
1312             FRF_CZ_HOST_NOTIFY_MODE, notify_mode,
1313             FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1314         EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE);
1315
1316         EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size,
1317             FRF_AZ_EVQ_BUF_BASE_ID, id);
1318
1319         EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE);
1320
1321         /* Set initial interrupt moderation */
1322         siena_ev_qmoderate(eep, us);
1323
1324         return (0);
1325
1326 fail4:
1327         EFSYS_PROBE(fail4);
1328 fail2:
1329         EFSYS_PROBE(fail2);
1330 fail1:
1331         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1332
1333         return (rc);
1334 }
1335
1336 #endif /* EFSYS_OPT_SIENA */
1337
1338 #if EFSYS_OPT_QSTATS
1339 #if EFSYS_OPT_NAMES
1340 /* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock c0f3bc5083b40532 */
1341 static const char * const __efx_ev_qstat_name[] = {
1342         "all",
1343         "rx",
1344         "rx_ok",
1345         "rx_frm_trunc",
1346         "rx_tobe_disc",
1347         "rx_pause_frm_err",
1348         "rx_buf_owner_id_err",
1349         "rx_ipv4_hdr_chksum_err",
1350         "rx_tcp_udp_chksum_err",
1351         "rx_eth_crc_err",
1352         "rx_ip_frag_err",
1353         "rx_mcast_pkt",
1354         "rx_mcast_hash_match",
1355         "rx_tcp_ipv4",
1356         "rx_tcp_ipv6",
1357         "rx_udp_ipv4",
1358         "rx_udp_ipv6",
1359         "rx_other_ipv4",
1360         "rx_other_ipv6",
1361         "rx_non_ip",
1362         "rx_batch",
1363         "tx",
1364         "tx_wq_ff_full",
1365         "tx_pkt_err",
1366         "tx_pkt_too_big",
1367         "tx_unexpected",
1368         "global",
1369         "global_mnt",
1370         "driver",
1371         "driver_srm_upd_done",
1372         "driver_tx_descq_fls_done",
1373         "driver_rx_descq_fls_done",
1374         "driver_rx_descq_fls_failed",
1375         "driver_rx_dsc_error",
1376         "driver_tx_dsc_error",
1377         "drv_gen",
1378         "mcdi_response",
1379 };
1380 /* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */
1381
1382                 const char *
1383 efx_ev_qstat_name(
1384         __in    efx_nic_t *enp,
1385         __in    unsigned int id)
1386 {
1387         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1388         EFSYS_ASSERT3U(id, <, EV_NQSTATS);
1389
1390         return (__efx_ev_qstat_name[id]);
1391 }
1392 #endif  /* EFSYS_OPT_NAMES */
1393 #endif  /* EFSYS_OPT_QSTATS */
1394
1395 #if EFSYS_OPT_SIENA
1396
1397 #if EFSYS_OPT_QSTATS
1398 static                                  void
1399 siena_ev_qstats_update(
1400         __in                            efx_evq_t *eep,
1401         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat)
1402 {
1403         unsigned int id;
1404
1405         for (id = 0; id < EV_NQSTATS; id++) {
1406                 efsys_stat_t *essp = &stat[id];
1407
1408                 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
1409                 eep->ee_stat[id] = 0;
1410         }
1411 }
1412 #endif  /* EFSYS_OPT_QSTATS */
1413
1414 static          void
1415 siena_ev_qdestroy(
1416         __in    efx_evq_t *eep)
1417 {
1418         efx_nic_t *enp = eep->ee_enp;
1419         efx_oword_t oword;
1420
1421         /* Purge event queue */
1422         EFX_ZERO_OWORD(oword);
1423
1424         EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL,
1425             eep->ee_index, &oword, B_TRUE);
1426
1427         EFX_ZERO_OWORD(oword);
1428         EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, eep->ee_index, &oword, B_TRUE);
1429 }
1430
1431 static          void
1432 siena_ev_fini(
1433         __in    efx_nic_t *enp)
1434 {
1435         _NOTE(ARGUNUSED(enp))
1436 }
1437
1438 #endif /* EFSYS_OPT_SIENA */