drivers/net/sfc/base/efx_impl.h

   1 /*
   2  * Copyright (c) 2007-2016 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  */
  30
  31 #ifndef _SYS_EFX_IMPL_H
  32 #define _SYS_EFX_IMPL_H
  33
  34 #include "efx.h"
  35 #include "efx_regs.h"
  36 #include "efx_regs_ef10.h"
  37
  38 /* FIXME: Add definition for driver generated software events */
  39 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  40 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  41 #endif
  42
  43
  44 #if EFSYS_OPT_SIENA
  45 #include "siena_impl.h"
  46 #endif  /* EFSYS_OPT_SIENA */
  47
  48 #if EFSYS_OPT_HUNTINGTON
  49 #include "hunt_impl.h"
  50 #endif  /* EFSYS_OPT_HUNTINGTON */
  51
  52 #if EFSYS_OPT_MEDFORD
  53 #include "medford_impl.h"
  54 #endif  /* EFSYS_OPT_MEDFORD */
  55
  56 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
  57 #include "ef10_impl.h"
  58 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
  59
  60 #ifdef  __cplusplus
  61 extern "C" {
  62 #endif
  63
  64 #define EFX_MOD_MCDI            0x00000001
  65 #define EFX_MOD_PROBE           0x00000002
  66 #define EFX_MOD_NVRAM           0x00000004
  67 #define EFX_MOD_VPD             0x00000008
  68 #define EFX_MOD_NIC             0x00000010
  69 #define EFX_MOD_INTR            0x00000020
  70 #define EFX_MOD_EV              0x00000040
  71 #define EFX_MOD_RX              0x00000080
  72 #define EFX_MOD_TX              0x00000100
  73 #define EFX_MOD_PORT            0x00000200
  74 #define EFX_MOD_MON             0x00000400
  75 #define EFX_MOD_FILTER          0x00001000
  76 #define EFX_MOD_LIC             0x00002000
  77
  78 #define EFX_RESET_PHY           0x00000001
  79 #define EFX_RESET_RXQ_ERR       0x00000002
  80 #define EFX_RESET_TXQ_ERR       0x00000004
  81
  82 typedef enum efx_mac_type_e {
  83         EFX_MAC_INVALID = 0,
  84         EFX_MAC_SIENA,
  85         EFX_MAC_HUNTINGTON,
  86         EFX_MAC_MEDFORD,
  87         EFX_MAC_NTYPES
  88 } efx_mac_type_t;
  89
  90 typedef struct efx_ev_ops_s {
  91         efx_rc_t        (*eevo_init)(efx_nic_t *);
  92         void            (*eevo_fini)(efx_nic_t *);
  93         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  94                                           efsys_mem_t *, size_t, uint32_t,
  95                                           uint32_t, uint32_t, efx_evq_t *);
  96         void            (*eevo_qdestroy)(efx_evq_t *);
  97         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  98         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  99         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
 100 #if EFSYS_OPT_QSTATS
 101         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
 102 #endif
 103 } efx_ev_ops_t;
 104
 105 typedef struct efx_tx_ops_s {
 106         efx_rc_t        (*etxo_init)(efx_nic_t *);
 107         void            (*etxo_fini)(efx_nic_t *);
 108         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 109                                         unsigned int, unsigned int,
 110                                         efsys_mem_t *, size_t,
 111                                         uint32_t, uint16_t,
 112                                         efx_evq_t *, efx_txq_t *,
 113                                         unsigned int *);
 114         void            (*etxo_qdestroy)(efx_txq_t *);
 115         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 116                                       unsigned int, unsigned int,
 117                                       unsigned int *);
 118         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 119         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 120         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 121         void            (*etxo_qenable)(efx_txq_t *);
 122         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 123         void            (*etxo_qpio_disable)(efx_txq_t *);
 124         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 125                                            size_t);
 126         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 127                                            unsigned int *);
 128         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 129                                       unsigned int, unsigned int,
 130                                       unsigned int *);
 131         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 132                                                 size_t, boolean_t,
 133                                                 efx_desc_t *);
 134         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 135                                                 uint32_t, uint8_t,
 136                                                 efx_desc_t *);
 137         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 138                                                 uint32_t, uint16_t,
 139                                                 efx_desc_t *, int);
 140         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 141                                                 efx_desc_t *);
 142 #if EFSYS_OPT_QSTATS
 143         void            (*etxo_qstats_update)(efx_txq_t *,
 144                                               efsys_stat_t *);
 145 #endif
 146 } efx_tx_ops_t;
 147
 148 typedef struct efx_rx_ops_s {
 149         efx_rc_t        (*erxo_init)(efx_nic_t *);
 150         void            (*erxo_fini)(efx_nic_t *);
 151 #if EFSYS_OPT_RX_SCATTER
 152         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 153 #endif
 154 #if EFSYS_OPT_RX_SCALE
 155         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
 156                                                efx_rx_hash_type_t, boolean_t);
 157         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
 158         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
 159                                               size_t);
 160         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 161                                             uint8_t *);
 162 #endif /* EFSYS_OPT_RX_SCALE */
 163         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 164                                               uint16_t *);
 165         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 166                                       unsigned int, unsigned int,
 167                                       unsigned int);
 168         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 169         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 170         void            (*erxo_qenable)(efx_rxq_t *);
 171         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 172                                         unsigned int, efx_rxq_type_t,
 173                                         efsys_mem_t *, size_t, uint32_t,
 174                                         efx_evq_t *, efx_rxq_t *);
 175         void            (*erxo_qdestroy)(efx_rxq_t *);
 176 } efx_rx_ops_t;
 177
 178 typedef struct efx_mac_ops_s {
 179         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 180         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 181         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 182         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 183         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 184         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 185         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 186         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 187                                                       efx_rxq_t *, boolean_t);
 188         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 189 #if EFSYS_OPT_LOOPBACK
 190         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 191                                             efx_loopback_type_t);
 192 #endif  /* EFSYS_OPT_LOOPBACK */
 193 #if EFSYS_OPT_MAC_STATS
 194         efx_rc_t        (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
 195         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 196         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 197                                               uint16_t, boolean_t);
 198         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 199                                             efsys_stat_t *, uint32_t *);
 200 #endif  /* EFSYS_OPT_MAC_STATS */
 201 } efx_mac_ops_t;
 202
 203 typedef struct efx_phy_ops_s {
 204         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 205         efx_rc_t        (*epo_reset)(efx_nic_t *);
 206         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 207         efx_rc_t        (*epo_verify)(efx_nic_t *);
 208         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 209 #if EFSYS_OPT_PHY_STATS
 210         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 211                                             uint32_t *);
 212 #endif  /* EFSYS_OPT_PHY_STATS */
 213 #if EFSYS_OPT_BIST
 214         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 215         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 216         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 217                                          efx_bist_result_t *, uint32_t *,
 218                                          unsigned long *, size_t);
 219         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 220 #endif  /* EFSYS_OPT_BIST */
 221 } efx_phy_ops_t;
 222
 223 #if EFSYS_OPT_FILTER
 224 typedef struct efx_filter_ops_s {
 225         efx_rc_t        (*efo_init)(efx_nic_t *);
 226         void            (*efo_fini)(efx_nic_t *);
 227         efx_rc_t        (*efo_restore)(efx_nic_t *);
 228         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 229                                    boolean_t may_replace);
 230         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 231         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
 232         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 233                                    boolean_t, boolean_t, boolean_t,
 234                                    uint8_t const *, uint32_t);
 235 } efx_filter_ops_t;
 236
 237 extern  __checkReturn   efx_rc_t
 238 efx_filter_reconfigure(
 239         __in                            efx_nic_t *enp,
 240         __in_ecount(6)                  uint8_t const *mac_addr,
 241         __in                            boolean_t all_unicst,
 242         __in                            boolean_t mulcst,
 243         __in                            boolean_t all_mulcst,
 244         __in                            boolean_t brdcst,
 245         __in_ecount(6*count)            uint8_t const *addrs,
 246         __in                            uint32_t count);
 247
 248 #endif /* EFSYS_OPT_FILTER */
 249
 250
 251 typedef struct efx_port_s {
 252         efx_mac_type_t          ep_mac_type;
 253         uint32_t                ep_phy_type;
 254         uint8_t                 ep_port;
 255         uint32_t                ep_mac_pdu;
 256         uint8_t                 ep_mac_addr[6];
 257         efx_link_mode_t         ep_link_mode;
 258         boolean_t               ep_all_unicst;
 259         boolean_t               ep_mulcst;
 260         boolean_t               ep_all_mulcst;
 261         boolean_t               ep_brdcst;
 262         unsigned int            ep_fcntl;
 263         boolean_t               ep_fcntl_autoneg;
 264         efx_oword_t             ep_multicst_hash[2];
 265         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 266                                                     EFX_MAC_MULTICAST_LIST_MAX];
 267         uint32_t                ep_mulcst_addr_count;
 268 #if EFSYS_OPT_LOOPBACK
 269         efx_loopback_type_t     ep_loopback_type;
 270         efx_link_mode_t         ep_loopback_link_mode;
 271 #endif  /* EFSYS_OPT_LOOPBACK */
 272 #if EFSYS_OPT_PHY_FLAGS
 273         uint32_t                ep_phy_flags;
 274 #endif  /* EFSYS_OPT_PHY_FLAGS */
 275 #if EFSYS_OPT_PHY_LED_CONTROL
 276         efx_phy_led_mode_t      ep_phy_led_mode;
 277 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 278         efx_phy_media_type_t    ep_fixed_port_type;
 279         efx_phy_media_type_t    ep_module_type;
 280         uint32_t                ep_adv_cap_mask;
 281         uint32_t                ep_lp_cap_mask;
 282         uint32_t                ep_default_adv_cap_mask;
 283         uint32_t                ep_phy_cap_mask;
 284         boolean_t               ep_mac_drain;
 285         boolean_t               ep_mac_stats_pending;
 286 #if EFSYS_OPT_BIST
 287         efx_bist_type_t         ep_current_bist;
 288 #endif
 289         const efx_mac_ops_t     *ep_emop;
 290         const efx_phy_ops_t     *ep_epop;
 291 } efx_port_t;
 292
 293 typedef struct efx_mon_ops_s {
 294 } efx_mon_ops_t;
 295
 296 typedef struct efx_mon_s {
 297         efx_mon_type_t          em_type;
 298         const efx_mon_ops_t     *em_emop;
 299 } efx_mon_t;
 300
 301 typedef struct efx_intr_ops_s {
 302         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 303         void            (*eio_enable)(efx_nic_t *);
 304         void            (*eio_disable)(efx_nic_t *);
 305         void            (*eio_disable_unlocked)(efx_nic_t *);
 306         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 307         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 308         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 309                                  boolean_t *);
 310         void            (*eio_fatal)(efx_nic_t *);
 311         void            (*eio_fini)(efx_nic_t *);
 312 } efx_intr_ops_t;
 313
 314 typedef struct efx_intr_s {
 315         const efx_intr_ops_t    *ei_eiop;
 316         efsys_mem_t             *ei_esmp;
 317         efx_intr_type_t         ei_type;
 318         unsigned int            ei_level;
 319 } efx_intr_t;
 320
 321 typedef struct efx_nic_ops_s {
 322         efx_rc_t        (*eno_probe)(efx_nic_t *);
 323         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 324         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 325         efx_rc_t        (*eno_reset)(efx_nic_t *);
 326         efx_rc_t        (*eno_init)(efx_nic_t *);
 327         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 328         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 329                                         uint32_t *, size_t *);
 330 #if EFSYS_OPT_DIAG
 331         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 332 #endif  /* EFSYS_OPT_DIAG */
 333         void            (*eno_fini)(efx_nic_t *);
 334         void            (*eno_unprobe)(efx_nic_t *);
 335 } efx_nic_ops_t;
 336
 337 #ifndef EFX_TXQ_LIMIT_TARGET
 338 #define EFX_TXQ_LIMIT_TARGET 259
 339 #endif
 340 #ifndef EFX_RXQ_LIMIT_TARGET
 341 #define EFX_RXQ_LIMIT_TARGET 512
 342 #endif
 343 #ifndef EFX_TXQ_DC_SIZE
 344 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
 345 #endif
 346 #ifndef EFX_RXQ_DC_SIZE
 347 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
 348 #endif
 349
 350 #if EFSYS_OPT_FILTER
 351
 352 #if EFSYS_OPT_SIENA
 353
 354 typedef struct siena_filter_spec_s {
 355         uint8_t         sfs_type;
 356         uint32_t        sfs_flags;
 357         uint32_t        sfs_dmaq_id;
 358         uint32_t        sfs_dword[3];
 359 } siena_filter_spec_t;
 360
 361 typedef enum siena_filter_type_e {
 362         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 363         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 364         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 365         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 366         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 367         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 368
 369         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 370         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 371         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 372         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 373         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 374         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 375
 376         EFX_SIENA_FILTER_NTYPES
 377 } siena_filter_type_t;
 378
 379 typedef enum siena_filter_tbl_id_e {
 380         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 381         EFX_SIENA_FILTER_TBL_RX_MAC,
 382         EFX_SIENA_FILTER_TBL_TX_IP,
 383         EFX_SIENA_FILTER_TBL_TX_MAC,
 384         EFX_SIENA_FILTER_NTBLS
 385 } siena_filter_tbl_id_t;
 386
 387 typedef struct siena_filter_tbl_s {
 388         int                     sft_size;       /* number of entries */
 389         int                     sft_used;       /* active count */
 390         uint32_t                *sft_bitmap;    /* active bitmap */
 391         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 392 } siena_filter_tbl_t;
 393
 394 typedef struct siena_filter_s {
 395         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 396         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 397 } siena_filter_t;
 398
 399 #endif  /* EFSYS_OPT_SIENA */
 400
 401 typedef struct efx_filter_s {
 402 #if EFSYS_OPT_SIENA
 403         siena_filter_t          *ef_siena_filter;
 404 #endif /* EFSYS_OPT_SIENA */
 405 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 406         ef10_filter_table_t     *ef_ef10_filter_table;
 407 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 408 } efx_filter_t;
 409
 410 #if EFSYS_OPT_SIENA
 411
 412 extern                  void
 413 siena_filter_tbl_clear(
 414         __in            efx_nic_t *enp,
 415         __in            siena_filter_tbl_id_t tbl);
 416
 417 #endif  /* EFSYS_OPT_SIENA */
 418
 419 #endif  /* EFSYS_OPT_FILTER */
 420
 421 #if EFSYS_OPT_MCDI
 422
 423 typedef struct efx_mcdi_ops_s {
 424         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 425         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 426                                         void *, size_t);
 427         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 428         boolean_t       (*emco_poll_response)(efx_nic_t *);
 429         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 430         void            (*emco_fini)(efx_nic_t *);
 431         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 432                                             efx_mcdi_feature_id_t, boolean_t *);
 433         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 434                                             uint32_t *);
 435 } efx_mcdi_ops_t;
 436
 437 typedef struct efx_mcdi_s {
 438         const efx_mcdi_ops_t            *em_emcop;
 439         const efx_mcdi_transport_t      *em_emtp;
 440         efx_mcdi_iface_t                em_emip;
 441 } efx_mcdi_t;
 442
 443 #endif /* EFSYS_OPT_MCDI */
 444
 445 typedef struct efx_drv_cfg_s {
 446         uint32_t                edc_min_vi_count;
 447         uint32_t                edc_max_vi_count;
 448
 449         uint32_t                edc_max_piobuf_count;
 450         uint32_t                edc_pio_alloc_size;
 451 } efx_drv_cfg_t;
 452
 453 struct efx_nic_s {
 454         uint32_t                en_magic;
 455         efx_family_t            en_family;
 456         uint32_t                en_features;
 457         efsys_identifier_t      *en_esip;
 458         efsys_lock_t            *en_eslp;
 459         efsys_bar_t             *en_esbp;
 460         unsigned int            en_mod_flags;
 461         unsigned int            en_reset_flags;
 462         efx_nic_cfg_t           en_nic_cfg;
 463         efx_drv_cfg_t           en_drv_cfg;
 464         efx_port_t              en_port;
 465         efx_mon_t               en_mon;
 466         efx_intr_t              en_intr;
 467         uint32_t                en_ev_qcount;
 468         uint32_t                en_rx_qcount;
 469         uint32_t                en_tx_qcount;
 470         const efx_nic_ops_t     *en_enop;
 471         const efx_ev_ops_t      *en_eevop;
 472         const efx_tx_ops_t      *en_etxop;
 473         const efx_rx_ops_t      *en_erxop;
 474 #if EFSYS_OPT_FILTER
 475         efx_filter_t            en_filter;
 476         const efx_filter_ops_t  *en_efop;
 477 #endif  /* EFSYS_OPT_FILTER */
 478 #if EFSYS_OPT_MCDI
 479         efx_mcdi_t              en_mcdi;
 480 #endif  /* EFSYS_OPT_MCDI */
 481 #if EFSYS_OPT_RX_SCALE
 482         efx_rx_hash_support_t   en_hash_support;
 483         efx_rx_scale_support_t  en_rss_support;
 484         uint32_t                en_rss_context;
 485 #endif  /* EFSYS_OPT_RX_SCALE */
 486         uint32_t                en_vport_id;
 487         union {
 488 #if EFSYS_OPT_SIENA
 489                 struct {
 490                         int                     enu_unused;
 491                 } siena;
 492 #endif  /* EFSYS_OPT_SIENA */
 493                 int     enu_unused;
 494         } en_u;
 495 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
 496         union en_arch {
 497                 struct {
 498                         int                     ena_vi_base;
 499                         int                     ena_vi_count;
 500                         int                     ena_vi_shift;
 501                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 502                         uint32_t                ena_piobuf_count;
 503                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 504                         uint32_t                ena_pio_write_vi_base;
 505                         /* Memory BAR mapping regions */
 506                         uint32_t                ena_uc_mem_map_offset;
 507                         size_t                  ena_uc_mem_map_size;
 508                         uint32_t                ena_wc_mem_map_offset;
 509                         size_t                  ena_wc_mem_map_size;
 510                 } ef10;
 511         } en_arch;
 512 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
 513 };
 514
 515
 516 #define EFX_NIC_MAGIC   0x02121996
 517
 518 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 519     const efx_ev_callbacks_t *, void *);
 520
 521 typedef struct efx_evq_rxq_state_s {
 522         unsigned int                    eers_rx_read_ptr;
 523         unsigned int                    eers_rx_mask;
 524 } efx_evq_rxq_state_t;
 525
 526 struct efx_evq_s {
 527         uint32_t                        ee_magic;
 528         efx_nic_t                       *ee_enp;
 529         unsigned int                    ee_index;
 530         unsigned int                    ee_mask;
 531         efsys_mem_t                     *ee_esmp;
 532 #if EFSYS_OPT_QSTATS
 533         uint32_t                        ee_stat[EV_NQSTATS];
 534 #endif  /* EFSYS_OPT_QSTATS */
 535
 536         efx_ev_handler_t                ee_rx;
 537         efx_ev_handler_t                ee_tx;
 538         efx_ev_handler_t                ee_driver;
 539         efx_ev_handler_t                ee_global;
 540         efx_ev_handler_t                ee_drv_gen;
 541 #if EFSYS_OPT_MCDI
 542         efx_ev_handler_t                ee_mcdi;
 543 #endif  /* EFSYS_OPT_MCDI */
 544
 545         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 546
 547         uint32_t                        ee_flags;
 548 };
 549
 550 #define EFX_EVQ_MAGIC   0x08081997
 551
 552 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 553
 554 struct efx_rxq_s {
 555         uint32_t                        er_magic;
 556         efx_nic_t                       *er_enp;
 557         efx_evq_t                       *er_eep;
 558         unsigned int                    er_index;
 559         unsigned int                    er_label;
 560         unsigned int                    er_mask;
 561         efsys_mem_t                     *er_esmp;
 562 };
 563
 564 #define EFX_RXQ_MAGIC   0x15022005
 565
 566 struct efx_txq_s {
 567         uint32_t                        et_magic;
 568         efx_nic_t                       *et_enp;
 569         unsigned int                    et_index;
 570         unsigned int                    et_mask;
 571         efsys_mem_t                     *et_esmp;
 572 #if EFSYS_OPT_HUNTINGTON
 573         uint32_t                        et_pio_bufnum;
 574         uint32_t                        et_pio_blknum;
 575         uint32_t                        et_pio_write_offset;
 576         uint32_t                        et_pio_offset;
 577         size_t                          et_pio_size;
 578 #endif
 579 #if EFSYS_OPT_QSTATS
 580         uint32_t                        et_stat[TX_NQSTATS];
 581 #endif  /* EFSYS_OPT_QSTATS */
 582 };
 583
 584 #define EFX_TXQ_MAGIC   0x05092005
 585
 586 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 587         do {                                                            \
 588                 (_dst)[0] = (_src)[0];                                  \
 589                 (_dst)[1] = (_src)[1];                                  \
 590                 (_dst)[2] = (_src)[2];                                  \
 591                 (_dst)[3] = (_src)[3];                                  \
 592                 (_dst)[4] = (_src)[4];                                  \
 593                 (_dst)[5] = (_src)[5];                                  \
 594         _NOTE(CONSTANTCONDITION)                                        \
 595         } while (B_FALSE)
 596
 597 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 598         do {                                                            \
 599                 uint16_t *_d = (uint16_t *)(_dst);                      \
 600                 _d[0] = 0xffff;                                         \
 601                 _d[1] = 0xffff;                                         \
 602                 _d[2] = 0xffff;                                         \
 603         _NOTE(CONSTANTCONDITION)                                        \
 604         } while (B_FALSE)
 605
 606 #if EFSYS_OPT_CHECK_REG
 607 #define EFX_CHECK_REG(_enp, _reg)                                       \
 608         do {                                                            \
 609                 const char *name = #_reg;                               \
 610                 char min = name[4];                                     \
 611                 char max = name[5];                                     \
 612                 char rev;                                               \
 613                                                                         \
 614                 switch ((_enp)->en_family) {                            \
 615                 case EFX_FAMILY_SIENA:                                  \
 616                         rev = 'C';                                      \
 617                         break;                                          \
 618                                                                         \
 619                 case EFX_FAMILY_HUNTINGTON:                             \
 620                         rev = 'D';                                      \
 621                         break;                                          \
 622                                                                         \
 623                 case EFX_FAMILY_MEDFORD:                                \
 624                         rev = 'E';                                      \
 625                         break;                                          \
 626                                                                         \
 627                 default:                                                \
 628                         rev = '?';                                      \
 629                         break;                                          \
 630                 }                                                       \
 631                                                                         \
 632                 EFSYS_ASSERT3S(rev, >=, min);                           \
 633                 EFSYS_ASSERT3S(rev, <=, max);                           \
 634                                                                         \
 635         _NOTE(CONSTANTCONDITION)                                        \
 636         } while (B_FALSE)
 637 #else
 638 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 639         _NOTE(CONSTANTCONDITION)                                        \
 640         } while (B_FALSE)
 641 #endif
 642
 643 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 644         do {                                                            \
 645                 EFX_CHECK_REG((_enp), (_reg));                          \
 646                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 647                     (_edp), (_lock));                                   \
 648                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 649                     uint32_t, _reg ## _OFST,                            \
 650                     uint32_t, (_edp)->ed_u32[0]);                       \
 651         _NOTE(CONSTANTCONDITION)                                        \
 652         } while (B_FALSE)
 653
 654 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 655         do {                                                            \
 656                 EFX_CHECK_REG((_enp), (_reg));                          \
 657                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 658                     uint32_t, _reg ## _OFST,                            \
 659                     uint32_t, (_edp)->ed_u32[0]);                       \
 660                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 661                     (_edp), (_lock));                                   \
 662         _NOTE(CONSTANTCONDITION)                                        \
 663         } while (B_FALSE)
 664
 665 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 666         do {                                                            \
 667                 EFX_CHECK_REG((_enp), (_reg));                          \
 668                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 669                     (_eqp));                                            \
 670                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 671                     uint32_t, _reg ## _OFST,                            \
 672                     uint32_t, (_eqp)->eq_u32[1],                        \
 673                     uint32_t, (_eqp)->eq_u32[0]);                       \
 674         _NOTE(CONSTANTCONDITION)                                        \
 675         } while (B_FALSE)
 676
 677 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 678         do {                                                            \
 679                 EFX_CHECK_REG((_enp), (_reg));                          \
 680                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 681                     uint32_t, _reg ## _OFST,                            \
 682                     uint32_t, (_eqp)->eq_u32[1],                        \
 683                     uint32_t, (_eqp)->eq_u32[0]);                       \
 684                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 685                     (_eqp));                                            \
 686         _NOTE(CONSTANTCONDITION)                                        \
 687         } while (B_FALSE)
 688
 689 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 690         do {                                                            \
 691                 EFX_CHECK_REG((_enp), (_reg));                          \
 692                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 693                     (_eop), B_TRUE);                                    \
 694                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 695                     uint32_t, _reg ## _OFST,                            \
 696                     uint32_t, (_eop)->eo_u32[3],                        \
 697                     uint32_t, (_eop)->eo_u32[2],                        \
 698                     uint32_t, (_eop)->eo_u32[1],                        \
 699                     uint32_t, (_eop)->eo_u32[0]);                       \
 700         _NOTE(CONSTANTCONDITION)                                        \
 701         } while (B_FALSE)
 702
 703 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 704         do {                                                            \
 705                 EFX_CHECK_REG((_enp), (_reg));                          \
 706                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 707                     uint32_t, _reg ## _OFST,                            \
 708                     uint32_t, (_eop)->eo_u32[3],                        \
 709                     uint32_t, (_eop)->eo_u32[2],                        \
 710                     uint32_t, (_eop)->eo_u32[1],                        \
 711                     uint32_t, (_eop)->eo_u32[0]);                       \
 712                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 713                     (_eop), B_TRUE);                                    \
 714         _NOTE(CONSTANTCONDITION)                                        \
 715         } while (B_FALSE)
 716
 717 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 718         do {                                                            \
 719                 EFX_CHECK_REG((_enp), (_reg));                          \
 720                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 721                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 722                     (_edp), (_lock));                                   \
 723                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 724                     uint32_t, (_index),                                 \
 725                     uint32_t, _reg ## _OFST,                            \
 726                     uint32_t, (_edp)->ed_u32[0]);                       \
 727         _NOTE(CONSTANTCONDITION)                                        \
 728         } while (B_FALSE)
 729
 730 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
 731         do {                                                            \
 732                 EFX_CHECK_REG((_enp), (_reg));                          \
 733                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 734                     uint32_t, (_index),                                 \
 735                     uint32_t, _reg ## _OFST,                            \
 736                     uint32_t, (_edp)->ed_u32[0]);                       \
 737                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 738                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 739                     (_edp), (_lock));                                   \
 740         _NOTE(CONSTANTCONDITION)                                        \
 741         } while (B_FALSE)
 742
 743 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)            \
 744         do {                                                            \
 745                 EFX_CHECK_REG((_enp), (_reg));                          \
 746                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 747                     uint32_t, (_index),                                 \
 748                     uint32_t, _reg ## _OFST,                            \
 749                     uint32_t, (_edp)->ed_u32[0]);                       \
 750                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 751                     (_reg ## _OFST +                                    \
 752                     (2 * sizeof (efx_dword_t)) +                        \
 753                     ((_index) * _reg ## _STEP)),                        \
 754                     (_edp), (_lock));                                   \
 755         _NOTE(CONSTANTCONDITION)                                        \
 756         } while (B_FALSE)
 757
 758 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
 759         do {                                                            \
 760                 EFX_CHECK_REG((_enp), (_reg));                          \
 761                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 762                     uint32_t, (_index),                                 \
 763                     uint32_t, _reg ## _OFST,                            \
 764                     uint32_t, (_edp)->ed_u32[0]);                       \
 765                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 766                     (_reg ## _OFST +                                    \
 767                     (3 * sizeof (efx_dword_t)) +                        \
 768                     ((_index) * _reg ## _STEP)),                        \
 769                     (_edp), (_lock));                                   \
 770         _NOTE(CONSTANTCONDITION)                                        \
 771         } while (B_FALSE)
 772
 773 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
 774         do {                                                            \
 775                 EFX_CHECK_REG((_enp), (_reg));                          \
 776                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
 777                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 778                     (_eqp));                                            \
 779                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
 780                     uint32_t, (_index),                                 \
 781                     uint32_t, _reg ## _OFST,                            \
 782                     uint32_t, (_eqp)->eq_u32[1],                        \
 783                     uint32_t, (_eqp)->eq_u32[0]);                       \
 784         _NOTE(CONSTANTCONDITION)                                        \
 785         } while (B_FALSE)
 786
 787 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
 788         do {                                                            \
 789                 EFX_CHECK_REG((_enp), (_reg));                          \
 790                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
 791                     uint32_t, (_index),                                 \
 792                     uint32_t, _reg ## _OFST,                            \
 793                     uint32_t, (_eqp)->eq_u32[1],                        \
 794                     uint32_t, (_eqp)->eq_u32[0]);                       \
 795                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
 796                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 797                     (_eqp));                                            \
 798         _NOTE(CONSTANTCONDITION)                                        \
 799         } while (B_FALSE)
 800
 801 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
 802         do {                                                            \
 803                 EFX_CHECK_REG((_enp), (_reg));                          \
 804                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
 805                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 806                     (_eop), (_lock));                                   \
 807                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
 808                     uint32_t, (_index),                                 \
 809                     uint32_t, _reg ## _OFST,                            \
 810                     uint32_t, (_eop)->eo_u32[3],                        \
 811                     uint32_t, (_eop)->eo_u32[2],                        \
 812                     uint32_t, (_eop)->eo_u32[1],                        \
 813                     uint32_t, (_eop)->eo_u32[0]);                       \
 814         _NOTE(CONSTANTCONDITION)                                        \
 815         } while (B_FALSE)
 816
 817 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
 818         do {                                                            \
 819                 EFX_CHECK_REG((_enp), (_reg));                          \
 820                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
 821                     uint32_t, (_index),                                 \
 822                     uint32_t, _reg ## _OFST,                            \
 823                     uint32_t, (_eop)->eo_u32[3],                        \
 824                     uint32_t, (_eop)->eo_u32[2],                        \
 825                     uint32_t, (_eop)->eo_u32[1],                        \
 826                     uint32_t, (_eop)->eo_u32[0]);                       \
 827                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
 828                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 829                     (_eop), (_lock));                                   \
 830         _NOTE(CONSTANTCONDITION)                                        \
 831         } while (B_FALSE)
 832
 833 /*
 834  * Allow drivers to perform optimised 128-bit doorbell writes.
 835  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
 836  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
 837  * the need for locking in the host, and are the only ones known to be safe to
 838  * use 128-bites write with.
 839  */
 840 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)           \
 841         do {                                                            \
 842                 EFX_CHECK_REG((_enp), (_reg));                          \
 843                 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,               \
 844                     const char *,                                       \
 845                     #_reg,                                              \
 846                     uint32_t, (_index),                                 \
 847                     uint32_t, _reg ## _OFST,                            \
 848                     uint32_t, (_eop)->eo_u32[3],                        \
 849                     uint32_t, (_eop)->eo_u32[2],                        \
 850                     uint32_t, (_eop)->eo_u32[1],                        \
 851                     uint32_t, (_eop)->eo_u32[0]);                       \
 852                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
 853                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 854                     (_eop));                                            \
 855         _NOTE(CONSTANTCONDITION)                                        \
 856         } while (B_FALSE)
 857
 858 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
 859         do {                                                            \
 860                 unsigned int _new = (_wptr);                            \
 861                 unsigned int _old = (_owptr);                           \
 862                                                                         \
 863                 if ((_new) >= (_old))                                   \
 864                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
 865                             (_old) * sizeof (efx_desc_t),               \
 866                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
 867                 else                                                    \
 868                         /*                                              \
 869                          * It is cheaper to sync entire map than sync   \
 870                          * two parts especially when offset/size are    \
 871                          * ignored and entire map is synced in any case.\
 872                          */                                             \
 873                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
 874                             0,                                          \
 875                             (_entries) * sizeof (efx_desc_t));          \
 876         _NOTE(CONSTANTCONDITION)                                        \
 877         } while (B_FALSE)
 878
 879 extern  __checkReturn   efx_rc_t
 880 efx_nic_biu_test(
 881         __in            efx_nic_t *enp);
 882
 883 extern  __checkReturn   efx_rc_t
 884 efx_mac_select(
 885         __in            efx_nic_t *enp);
 886
 887 extern  void
 888 efx_mac_multicast_hash_compute(
 889         __in_ecount(6*count)            uint8_t const *addrs,
 890         __in                            int count,
 891         __out                           efx_oword_t *hash_low,
 892         __out                           efx_oword_t *hash_high);
 893
 894 extern  __checkReturn   efx_rc_t
 895 efx_phy_probe(
 896         __in            efx_nic_t *enp);
 897
 898 extern                  void
 899 efx_phy_unprobe(
 900         __in            efx_nic_t *enp);
 901
 902 #if EFSYS_OPT_DIAG
 903
 904 extern  efx_sram_pattern_fn_t   __efx_sram_pattern_fns[];
 905
 906 typedef struct efx_register_set_s {
 907         unsigned int            address;
 908         unsigned int            step;
 909         unsigned int            rows;
 910         efx_oword_t             mask;
 911 } efx_register_set_t;
 912
 913 extern  __checkReturn   efx_rc_t
 914 efx_nic_test_registers(
 915         __in            efx_nic_t *enp,
 916         __in            efx_register_set_t *rsp,
 917         __in            size_t count);
 918
 919 extern  __checkReturn   efx_rc_t
 920 efx_nic_test_tables(
 921         __in            efx_nic_t *enp,
 922         __in            efx_register_set_t *rsp,
 923         __in            efx_pattern_type_t pattern,
 924         __in            size_t count);
 925
 926 #endif  /* EFSYS_OPT_DIAG */
 927
 928 #if EFSYS_OPT_MCDI
 929
 930 extern  __checkReturn           efx_rc_t
 931 efx_mcdi_set_workaround(
 932         __in                    efx_nic_t *enp,
 933         __in                    uint32_t type,
 934         __in                    boolean_t enabled,
 935         __out_opt               uint32_t *flagsp);
 936
 937 extern  __checkReturn           efx_rc_t
 938 efx_mcdi_get_workarounds(
 939         __in                    efx_nic_t *enp,
 940         __out_opt               uint32_t *implementedp,
 941         __out_opt               uint32_t *enabledp);
 942
 943 #endif /* EFSYS_OPT_MCDI */
 944
 945 #if EFSYS_OPT_MAC_STATS
 946
 947 /*
 948  * Closed range of stats (i.e. the first and the last are included).
 949  * The last must be greater or equal (if the range is one item only) to
 950  * the first.
 951  */
 952 struct efx_mac_stats_range {
 953         efx_mac_stat_t          first;
 954         efx_mac_stat_t          last;
 955 };
 956
 957 extern                                  efx_rc_t
 958 efx_mac_stats_mask_add_ranges(
 959         __inout_bcount(mask_size)       uint32_t *maskp,
 960         __in                            size_t mask_size,
 961         __in_ecount(rng_count)          const struct efx_mac_stats_range *rngp,
 962         __in                            unsigned int rng_count);
 963
 964 #endif  /* EFSYS_OPT_MAC_STATS */
 965
 966 #ifdef  __cplusplus
 967 }
 968 #endif
 969
 970 #endif  /* _SYS_EFX_IMPL_H */