drivers/net/sfc/base/efx_impl.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2007-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  */
   6
   7 #ifndef _SYS_EFX_IMPL_H
   8 #define _SYS_EFX_IMPL_H
   9
  10 #include "efx.h"
  11 #include "efx_regs.h"
  12 #include "efx_regs_ef10.h"
  13 #if EFSYS_OPT_MCDI
  14 #include "efx_mcdi.h"
  15 #endif  /* EFSYS_OPT_MCDI */
  16
  17 /* FIXME: Add definition for driver generated software events */
  18 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  19 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  20 #endif
  21
  22
  23 #if EFSYS_OPT_SIENA
  24 #include "siena_impl.h"
  25 #endif  /* EFSYS_OPT_SIENA */
  26
  27 #if EFSYS_OPT_HUNTINGTON
  28 #include "hunt_impl.h"
  29 #endif  /* EFSYS_OPT_HUNTINGTON */
  30
  31 #if EFSYS_OPT_MEDFORD
  32 #include "medford_impl.h"
  33 #endif  /* EFSYS_OPT_MEDFORD */
  34
  35 #if EFSYS_OPT_MEDFORD2
  36 #include "medford2_impl.h"
  37 #endif  /* EFSYS_OPT_MEDFORD2 */
  38
  39 #if EFX_OPTS_EF10()
  40 #include "ef10_impl.h"
  41 #endif  /* EFX_OPTS_EF10() */
  42
  43 #ifdef  __cplusplus
  44 extern "C" {
  45 #endif
  46
  47 #define EFX_MOD_MCDI            0x00000001
  48 #define EFX_MOD_PROBE           0x00000002
  49 #define EFX_MOD_NVRAM           0x00000004
  50 #define EFX_MOD_VPD             0x00000008
  51 #define EFX_MOD_NIC             0x00000010
  52 #define EFX_MOD_INTR            0x00000020
  53 #define EFX_MOD_EV              0x00000040
  54 #define EFX_MOD_RX              0x00000080
  55 #define EFX_MOD_TX              0x00000100
  56 #define EFX_MOD_PORT            0x00000200
  57 #define EFX_MOD_MON             0x00000400
  58 #define EFX_MOD_FILTER          0x00001000
  59 #define EFX_MOD_LIC             0x00002000
  60 #define EFX_MOD_TUNNEL          0x00004000
  61 #define EFX_MOD_EVB             0x00008000
  62 #define EFX_MOD_PROXY           0x00010000
  63
  64 #define EFX_RESET_PHY           0x00000001
  65 #define EFX_RESET_RXQ_ERR       0x00000002
  66 #define EFX_RESET_TXQ_ERR       0x00000004
  67 #define EFX_RESET_HW_UNAVAIL    0x00000008
  68
  69 typedef enum efx_mac_type_e {
  70         EFX_MAC_INVALID = 0,
  71         EFX_MAC_SIENA,
  72         EFX_MAC_HUNTINGTON,
  73         EFX_MAC_MEDFORD,
  74         EFX_MAC_MEDFORD2,
  75         EFX_MAC_NTYPES
  76 } efx_mac_type_t;
  77
  78 typedef struct efx_ev_ops_s {
  79         efx_rc_t        (*eevo_init)(efx_nic_t *);
  80         void            (*eevo_fini)(efx_nic_t *);
  81         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  82                                           efsys_mem_t *, size_t, uint32_t,
  83                                           uint32_t, uint32_t, efx_evq_t *);
  84         void            (*eevo_qdestroy)(efx_evq_t *);
  85         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  86         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  87         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
  88 #if EFSYS_OPT_QSTATS
  89         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
  90 #endif
  91 } efx_ev_ops_t;
  92
  93 typedef struct efx_tx_ops_s {
  94         efx_rc_t        (*etxo_init)(efx_nic_t *);
  95         void            (*etxo_fini)(efx_nic_t *);
  96         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
  97                                         unsigned int, unsigned int,
  98                                         efsys_mem_t *, size_t,
  99                                         uint32_t, uint16_t,
 100                                         efx_evq_t *, efx_txq_t *,
 101                                         unsigned int *);
 102         void            (*etxo_qdestroy)(efx_txq_t *);
 103         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 104                                       unsigned int, unsigned int,
 105                                       unsigned int *);
 106         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 107         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 108         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 109         void            (*etxo_qenable)(efx_txq_t *);
 110         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 111         void            (*etxo_qpio_disable)(efx_txq_t *);
 112         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 113                                            size_t);
 114         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 115                                            unsigned int *);
 116         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 117                                       unsigned int, unsigned int,
 118                                       unsigned int *);
 119         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 120                                                 size_t, boolean_t,
 121                                                 efx_desc_t *);
 122         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 123                                                 uint32_t, uint8_t,
 124                                                 efx_desc_t *);
 125         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 126                                                 uint16_t, uint32_t, uint16_t,
 127                                                 efx_desc_t *, int);
 128         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 129                                                 efx_desc_t *);
 130         void            (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t,
 131                                                 efx_desc_t *);
 132 #if EFSYS_OPT_QSTATS
 133         void            (*etxo_qstats_update)(efx_txq_t *,
 134                                               efsys_stat_t *);
 135 #endif
 136 } efx_tx_ops_t;
 137
 138 typedef union efx_rxq_type_data_u {
 139         struct {
 140                 size_t          ed_buf_size;
 141         } ertd_default;
 142 #if EFSYS_OPT_RX_PACKED_STREAM
 143         struct {
 144                 uint32_t        eps_buf_size;
 145         } ertd_packed_stream;
 146 #endif
 147 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
 148         struct {
 149                 uint32_t        eessb_bufs_per_desc;
 150                 uint32_t        eessb_max_dma_len;
 151                 uint32_t        eessb_buf_stride;
 152                 uint32_t        eessb_hol_block_timeout;
 153         } ertd_es_super_buffer;
 154 #endif
 155 } efx_rxq_type_data_t;
 156
 157 typedef struct efx_rx_ops_s {
 158         efx_rc_t        (*erxo_init)(efx_nic_t *);
 159         void            (*erxo_fini)(efx_nic_t *);
 160 #if EFSYS_OPT_RX_SCATTER
 161         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 162 #endif
 163 #if EFSYS_OPT_RX_SCALE
 164         efx_rc_t        (*erxo_scale_context_alloc)(efx_nic_t *,
 165                                                     efx_rx_scale_context_type_t,
 166                                                     uint32_t, uint32_t *);
 167         efx_rc_t        (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
 168         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
 169                                                efx_rx_hash_alg_t,
 170                                                efx_rx_hash_type_t, boolean_t);
 171         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
 172                                               uint8_t *, size_t);
 173         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
 174                                               unsigned int *, size_t);
 175         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 176                                             uint8_t *);
 177 #endif /* EFSYS_OPT_RX_SCALE */
 178         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 179                                               uint16_t *);
 180         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 181                                       unsigned int, unsigned int,
 182                                       unsigned int);
 183         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 184 #if EFSYS_OPT_RX_PACKED_STREAM
 185         void            (*erxo_qpush_ps_credits)(efx_rxq_t *);
 186         uint8_t *       (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
 187                                                 uint32_t, uint32_t,
 188                                                 uint16_t *, uint32_t *, uint32_t *);
 189 #endif
 190         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 191         void            (*erxo_qenable)(efx_rxq_t *);
 192         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 193                                         unsigned int, efx_rxq_type_t,
 194                                         const efx_rxq_type_data_t *,
 195                                         efsys_mem_t *, size_t, uint32_t,
 196                                         unsigned int,
 197                                         efx_evq_t *, efx_rxq_t *);
 198         void            (*erxo_qdestroy)(efx_rxq_t *);
 199 } efx_rx_ops_t;
 200
 201 typedef struct efx_mac_ops_s {
 202         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 203         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 204         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 205         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 206         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 207         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 208         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 209         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 210                                                       efx_rxq_t *, boolean_t);
 211         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 212 #if EFSYS_OPT_LOOPBACK
 213         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 214                                             efx_loopback_type_t);
 215 #endif  /* EFSYS_OPT_LOOPBACK */
 216 #if EFSYS_OPT_MAC_STATS
 217         efx_rc_t        (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
 218         efx_rc_t        (*emo_stats_clear)(efx_nic_t *);
 219         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 220         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 221                                               uint16_t, boolean_t);
 222         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 223                                             efsys_stat_t *, uint32_t *);
 224 #endif  /* EFSYS_OPT_MAC_STATS */
 225 } efx_mac_ops_t;
 226
 227 typedef struct efx_phy_ops_s {
 228         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 229         efx_rc_t        (*epo_reset)(efx_nic_t *);
 230         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 231         efx_rc_t        (*epo_verify)(efx_nic_t *);
 232         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 233         efx_rc_t        (*epo_link_state_get)(efx_nic_t *, efx_phy_link_state_t *);
 234 #if EFSYS_OPT_PHY_STATS
 235         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 236                                             uint32_t *);
 237 #endif  /* EFSYS_OPT_PHY_STATS */
 238 #if EFSYS_OPT_BIST
 239         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 240         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 241         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 242                                          efx_bist_result_t *, uint32_t *,
 243                                          unsigned long *, size_t);
 244         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 245 #endif  /* EFSYS_OPT_BIST */
 246 } efx_phy_ops_t;
 247
 248 #if EFSYS_OPT_FILTER
 249 typedef struct efx_filter_ops_s {
 250         efx_rc_t        (*efo_init)(efx_nic_t *);
 251         void            (*efo_fini)(efx_nic_t *);
 252         efx_rc_t        (*efo_restore)(efx_nic_t *);
 253         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 254                                    boolean_t may_replace);
 255         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 256         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *,
 257                                    size_t, size_t *);
 258         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 259                                    boolean_t, boolean_t, boolean_t,
 260                                    uint8_t const *, uint32_t);
 261 } efx_filter_ops_t;
 262
 263 extern  __checkReturn   efx_rc_t
 264 efx_filter_reconfigure(
 265         __in                            efx_nic_t *enp,
 266         __in_ecount(6)                  uint8_t const *mac_addr,
 267         __in                            boolean_t all_unicst,
 268         __in                            boolean_t mulcst,
 269         __in                            boolean_t all_mulcst,
 270         __in                            boolean_t brdcst,
 271         __in_ecount(6*count)            uint8_t const *addrs,
 272         __in                            uint32_t count);
 273
 274 #endif /* EFSYS_OPT_FILTER */
 275
 276 #if EFSYS_OPT_TUNNEL
 277 typedef struct efx_tunnel_ops_s {
 278         boolean_t       (*eto_udp_encap_supported)(efx_nic_t *);
 279         efx_rc_t        (*eto_reconfigure)(efx_nic_t *);
 280 } efx_tunnel_ops_t;
 281 #endif /* EFSYS_OPT_TUNNEL */
 282
 283 typedef struct efx_port_s {
 284         efx_mac_type_t          ep_mac_type;
 285         uint32_t                ep_phy_type;
 286         uint8_t                 ep_port;
 287         uint32_t                ep_mac_pdu;
 288         uint8_t                 ep_mac_addr[6];
 289         efx_link_mode_t         ep_link_mode;
 290         boolean_t               ep_all_unicst;
 291         boolean_t               ep_mulcst;
 292         boolean_t               ep_all_mulcst;
 293         boolean_t               ep_brdcst;
 294         unsigned int            ep_fcntl;
 295         boolean_t               ep_fcntl_autoneg;
 296         efx_oword_t             ep_multicst_hash[2];
 297         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 298                                                     EFX_MAC_MULTICAST_LIST_MAX];
 299         uint32_t                ep_mulcst_addr_count;
 300 #if EFSYS_OPT_LOOPBACK
 301         efx_loopback_type_t     ep_loopback_type;
 302         efx_link_mode_t         ep_loopback_link_mode;
 303 #endif  /* EFSYS_OPT_LOOPBACK */
 304 #if EFSYS_OPT_PHY_FLAGS
 305         uint32_t                ep_phy_flags;
 306 #endif  /* EFSYS_OPT_PHY_FLAGS */
 307 #if EFSYS_OPT_PHY_LED_CONTROL
 308         efx_phy_led_mode_t      ep_phy_led_mode;
 309 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 310         efx_phy_media_type_t    ep_fixed_port_type;
 311         efx_phy_media_type_t    ep_module_type;
 312         uint32_t                ep_adv_cap_mask;
 313         uint32_t                ep_lp_cap_mask;
 314         uint32_t                ep_default_adv_cap_mask;
 315         uint32_t                ep_phy_cap_mask;
 316         boolean_t               ep_mac_drain;
 317 #if EFSYS_OPT_BIST
 318         efx_bist_type_t         ep_current_bist;
 319 #endif
 320         const efx_mac_ops_t     *ep_emop;
 321         const efx_phy_ops_t     *ep_epop;
 322 } efx_port_t;
 323
 324 typedef struct efx_mon_ops_s {
 325 #if EFSYS_OPT_MON_STATS
 326         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 327                                             efx_mon_stat_value_t *);
 328         efx_rc_t        (*emo_limits_update)(efx_nic_t *,
 329                                              efx_mon_stat_limits_t *);
 330 #endif  /* EFSYS_OPT_MON_STATS */
 331 } efx_mon_ops_t;
 332
 333 typedef struct efx_mon_s {
 334         efx_mon_type_t          em_type;
 335         const efx_mon_ops_t     *em_emop;
 336 } efx_mon_t;
 337
 338 typedef struct efx_intr_ops_s {
 339         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 340         void            (*eio_enable)(efx_nic_t *);
 341         void            (*eio_disable)(efx_nic_t *);
 342         void            (*eio_disable_unlocked)(efx_nic_t *);
 343         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 344         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 345         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 346                                  boolean_t *);
 347         void            (*eio_fatal)(efx_nic_t *);
 348         void            (*eio_fini)(efx_nic_t *);
 349 } efx_intr_ops_t;
 350
 351 typedef struct efx_intr_s {
 352         const efx_intr_ops_t    *ei_eiop;
 353         efsys_mem_t             *ei_esmp;
 354         efx_intr_type_t         ei_type;
 355         unsigned int            ei_level;
 356 } efx_intr_t;
 357
 358 typedef struct efx_nic_ops_s {
 359         efx_rc_t        (*eno_probe)(efx_nic_t *);
 360         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 361         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 362         efx_rc_t        (*eno_reset)(efx_nic_t *);
 363         efx_rc_t        (*eno_init)(efx_nic_t *);
 364         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 365         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 366                                         uint32_t *, size_t *);
 367         boolean_t       (*eno_hw_unavailable)(efx_nic_t *);
 368         void            (*eno_set_hw_unavailable)(efx_nic_t *);
 369 #if EFSYS_OPT_DIAG
 370         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 371 #endif  /* EFSYS_OPT_DIAG */
 372         void            (*eno_fini)(efx_nic_t *);
 373         void            (*eno_unprobe)(efx_nic_t *);
 374 } efx_nic_ops_t;
 375
 376 #ifndef EFX_TXQ_LIMIT_TARGET
 377 #define EFX_TXQ_LIMIT_TARGET 259
 378 #endif
 379 #ifndef EFX_RXQ_LIMIT_TARGET
 380 #define EFX_RXQ_LIMIT_TARGET 512
 381 #endif
 382
 383
 384 #if EFSYS_OPT_FILTER
 385
 386 #if EFSYS_OPT_SIENA
 387
 388 typedef struct siena_filter_spec_s {
 389         uint8_t         sfs_type;
 390         uint32_t        sfs_flags;
 391         uint32_t        sfs_dmaq_id;
 392         uint32_t        sfs_dword[3];
 393 } siena_filter_spec_t;
 394
 395 typedef enum siena_filter_type_e {
 396         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 397         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 398         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 399         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 400         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 401         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 402
 403         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 404         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 405         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 406         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 407         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 408         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 409
 410         EFX_SIENA_FILTER_NTYPES
 411 } siena_filter_type_t;
 412
 413 typedef enum siena_filter_tbl_id_e {
 414         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 415         EFX_SIENA_FILTER_TBL_RX_MAC,
 416         EFX_SIENA_FILTER_TBL_TX_IP,
 417         EFX_SIENA_FILTER_TBL_TX_MAC,
 418         EFX_SIENA_FILTER_NTBLS
 419 } siena_filter_tbl_id_t;
 420
 421 typedef struct siena_filter_tbl_s {
 422         int                     sft_size;       /* number of entries */
 423         int                     sft_used;       /* active count */
 424         uint32_t                *sft_bitmap;    /* active bitmap */
 425         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 426 } siena_filter_tbl_t;
 427
 428 typedef struct siena_filter_s {
 429         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 430         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 431 } siena_filter_t;
 432
 433 #endif  /* EFSYS_OPT_SIENA */
 434
 435 typedef struct efx_filter_s {
 436 #if EFSYS_OPT_SIENA
 437         siena_filter_t          *ef_siena_filter;
 438 #endif /* EFSYS_OPT_SIENA */
 439 #if EFX_OPTS_EF10()
 440         ef10_filter_table_t     *ef_ef10_filter_table;
 441 #endif /* EFX_OPTS_EF10() */
 442 } efx_filter_t;
 443
 444 #if EFSYS_OPT_SIENA
 445
 446 extern                  void
 447 siena_filter_tbl_clear(
 448         __in            efx_nic_t *enp,
 449         __in            siena_filter_tbl_id_t tbl);
 450
 451 #endif  /* EFSYS_OPT_SIENA */
 452
 453 #endif  /* EFSYS_OPT_FILTER */
 454
 455 #if EFSYS_OPT_MCDI
 456
 457 #define EFX_TUNNEL_MAXNENTRIES  (16)
 458
 459 #if EFSYS_OPT_TUNNEL
 460
 461 typedef struct efx_tunnel_udp_entry_s {
 462         uint16_t                        etue_port; /* host/cpu-endian */
 463         uint16_t                        etue_protocol;
 464 } efx_tunnel_udp_entry_t;
 465
 466 typedef struct efx_tunnel_cfg_s {
 467         efx_tunnel_udp_entry_t  etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
 468         unsigned int            etc_udp_entries_num;
 469 } efx_tunnel_cfg_t;
 470
 471 #endif /* EFSYS_OPT_TUNNEL */
 472
 473 typedef struct efx_mcdi_ops_s {
 474         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 475         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 476                                         void *, size_t);
 477         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 478         boolean_t       (*emco_poll_response)(efx_nic_t *);
 479         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 480         void            (*emco_fini)(efx_nic_t *);
 481         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 482                                             efx_mcdi_feature_id_t, boolean_t *);
 483         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 484                                             uint32_t *);
 485 } efx_mcdi_ops_t;
 486
 487 typedef struct efx_mcdi_s {
 488         const efx_mcdi_ops_t            *em_emcop;
 489         const efx_mcdi_transport_t      *em_emtp;
 490         efx_mcdi_iface_t                em_emip;
 491 } efx_mcdi_t;
 492
 493 #endif /* EFSYS_OPT_MCDI */
 494
 495 #if EFSYS_OPT_NVRAM
 496
 497 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
 498 #define EFX_NVRAM_PARTN_INVALID         (0xffffffffu)
 499
 500 typedef struct efx_nvram_ops_s {
 501 #if EFSYS_OPT_DIAG
 502         efx_rc_t        (*envo_test)(efx_nic_t *);
 503 #endif  /* EFSYS_OPT_DIAG */
 504         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 505                                             uint32_t *);
 506         efx_rc_t        (*envo_partn_info)(efx_nic_t *, uint32_t,
 507                                             efx_nvram_info_t *);
 508         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 509         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 510                                             unsigned int, caddr_t, size_t);
 511         efx_rc_t        (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
 512                                             unsigned int, caddr_t, size_t);
 513         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 514                                             unsigned int, size_t);
 515         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 516                                             unsigned int, caddr_t, size_t);
 517         efx_rc_t        (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
 518                                             uint32_t *);
 519         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 520                                             uint32_t *, uint16_t *);
 521         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 522                                             uint16_t *);
 523         efx_rc_t        (*envo_buffer_validate)(uint32_t,
 524                                             caddr_t, size_t);
 525 } efx_nvram_ops_t;
 526 #endif /* EFSYS_OPT_NVRAM */
 527
 528 #if EFSYS_OPT_VPD
 529 typedef struct efx_vpd_ops_s {
 530         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 531         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 532         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 533         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 534         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 535         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 536                                         efx_vpd_value_t *);
 537         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 538                                         efx_vpd_value_t *);
 539         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 540                                         efx_vpd_value_t *, unsigned int *);
 541         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 542         void            (*evpdo_fini)(efx_nic_t *);
 543 } efx_vpd_ops_t;
 544 #endif  /* EFSYS_OPT_VPD */
 545
 546 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 547
 548         __checkReturn           efx_rc_t
 549 efx_mcdi_nvram_partitions(
 550         __in                    efx_nic_t *enp,
 551         __out_bcount(size)      caddr_t data,
 552         __in                    size_t size,
 553         __out                   unsigned int *npartnp);
 554
 555         __checkReturn           efx_rc_t
 556 efx_mcdi_nvram_metadata(
 557         __in                    efx_nic_t *enp,
 558         __in                    uint32_t partn,
 559         __out                   uint32_t *subtypep,
 560         __out_ecount(4)         uint16_t version[4],
 561         __out_bcount_opt(size)  char *descp,
 562         __in                    size_t size);
 563
 564         __checkReturn           efx_rc_t
 565 efx_mcdi_nvram_info(
 566         __in                    efx_nic_t *enp,
 567         __in                    uint32_t partn,
 568         __out                   efx_nvram_info_t *eni);
 569
 570         __checkReturn           efx_rc_t
 571 efx_mcdi_nvram_update_start(
 572         __in                    efx_nic_t *enp,
 573         __in                    uint32_t partn);
 574
 575         __checkReturn           efx_rc_t
 576 efx_mcdi_nvram_read(
 577         __in                    efx_nic_t *enp,
 578         __in                    uint32_t partn,
 579         __in                    uint32_t offset,
 580         __out_bcount(size)      caddr_t data,
 581         __in                    size_t size,
 582         __in                    uint32_t mode);
 583
 584         __checkReturn           efx_rc_t
 585 efx_mcdi_nvram_erase(
 586         __in                    efx_nic_t *enp,
 587         __in                    uint32_t partn,
 588         __in                    uint32_t offset,
 589         __in                    size_t size);
 590
 591         __checkReturn           efx_rc_t
 592 efx_mcdi_nvram_write(
 593         __in                    efx_nic_t *enp,
 594         __in                    uint32_t partn,
 595         __in                    uint32_t offset,
 596         __in_bcount(size)       caddr_t data,
 597         __in                    size_t size);
 598
 599 #define EFX_NVRAM_UPDATE_FLAGS_BACKGROUND       0x00000001
 600 #define EFX_NVRAM_UPDATE_FLAGS_POLL             0x00000002
 601
 602         __checkReturn           efx_rc_t
 603 efx_mcdi_nvram_update_finish(
 604         __in                    efx_nic_t *enp,
 605         __in                    uint32_t partn,
 606         __in                    boolean_t reboot,
 607         __in                    uint32_t flags,
 608         __out_opt               uint32_t *verify_resultp);
 609
 610 #if EFSYS_OPT_DIAG
 611
 612         __checkReturn           efx_rc_t
 613 efx_mcdi_nvram_test(
 614         __in                    efx_nic_t *enp,
 615         __in                    uint32_t partn);
 616
 617 #endif  /* EFSYS_OPT_DIAG */
 618
 619 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 620
 621 #if EFSYS_OPT_LICENSING
 622
 623 typedef struct efx_lic_ops_s {
 624         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 625         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 626         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 627         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 628                                       size_t *, uint8_t *);
 629         efx_rc_t        (*elo_find_start)
 630                                 (efx_nic_t *, caddr_t, size_t, uint32_t *);
 631         efx_rc_t        (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
 632                                 uint32_t, uint32_t *);
 633         boolean_t       (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
 634                                 uint32_t, uint32_t *, uint32_t *);
 635         boolean_t       (*elo_validate_key)(efx_nic_t *,
 636                                 caddr_t, uint32_t);
 637         efx_rc_t        (*elo_read_key)(efx_nic_t *,
 638                                 caddr_t, size_t, uint32_t, uint32_t,
 639                                 caddr_t, size_t, uint32_t *);
 640         efx_rc_t        (*elo_write_key)(efx_nic_t *,
 641                                 caddr_t, size_t, uint32_t,
 642                                 caddr_t, uint32_t, uint32_t *);
 643         efx_rc_t        (*elo_delete_key)(efx_nic_t *,
 644                                 caddr_t, size_t, uint32_t,
 645                                 uint32_t, uint32_t, uint32_t *);
 646         efx_rc_t        (*elo_create_partition)(efx_nic_t *,
 647                                 caddr_t, size_t);
 648         efx_rc_t        (*elo_finish_partition)(efx_nic_t *,
 649                                 caddr_t, size_t);
 650 } efx_lic_ops_t;
 651
 652 #endif
 653
 654 #if EFSYS_OPT_EVB
 655
 656 struct efx_vswitch_s {
 657         efx_nic_t               *ev_enp;
 658         efx_vswitch_id_t        ev_vswitch_id;
 659         uint32_t                ev_num_vports;
 660         /*
 661          * Vport configuration array: index 0 to store PF configuration
 662          * and next ev_num_vports-1 entries hold VFs configuration.
 663          */
 664         efx_vport_config_t      *ev_evcp;
 665 };
 666
 667 typedef struct efx_evb_ops_s {
 668         efx_rc_t        (*eeo_init)(efx_nic_t *);
 669         void            (*eeo_fini)(efx_nic_t *);
 670         efx_rc_t        (*eeo_vswitch_alloc)(efx_nic_t *, efx_vswitch_id_t *);
 671         efx_rc_t        (*eeo_vswitch_free)(efx_nic_t *, efx_vswitch_id_t);
 672         efx_rc_t        (*eeo_vport_alloc)(efx_nic_t *, efx_vswitch_id_t,
 673                                                 efx_vport_type_t, uint16_t,
 674                                                 boolean_t, efx_vport_id_t *);
 675         efx_rc_t        (*eeo_vport_free)(efx_nic_t *, efx_vswitch_id_t,
 676                                                 efx_vport_id_t);
 677         efx_rc_t        (*eeo_vport_mac_addr_add)(efx_nic_t *, efx_vswitch_id_t,
 678                                                 efx_vport_id_t, uint8_t *);
 679         efx_rc_t        (*eeo_vport_mac_addr_del)(efx_nic_t *, efx_vswitch_id_t,
 680                                                 efx_vport_id_t, uint8_t *);
 681         efx_rc_t        (*eeo_vadaptor_alloc)(efx_nic_t *, efx_vswitch_id_t,
 682                                                 efx_vport_id_t);
 683         efx_rc_t        (*eeo_vadaptor_free)(efx_nic_t *, efx_vswitch_id_t,
 684                                                 efx_vport_id_t);
 685         efx_rc_t        (*eeo_vport_assign)(efx_nic_t *, efx_vswitch_id_t,
 686                                                 efx_vport_id_t, uint32_t);
 687         efx_rc_t        (*eeo_vport_reconfigure)(efx_nic_t *, efx_vswitch_id_t,
 688                                                         efx_vport_id_t,
 689                                                         uint16_t *, uint8_t *,
 690                                                         boolean_t *);
 691         efx_rc_t        (*eeo_vport_stats)(efx_nic_t *, efx_vswitch_id_t,
 692                                                 efx_vport_id_t, efsys_mem_t *);
 693 } efx_evb_ops_t;
 694
 695 extern __checkReturn    boolean_t
 696 efx_is_zero_eth_addr(
 697         __in_bcount(EFX_MAC_ADDR_LEN)   const uint8_t *addrp);
 698
 699 #endif /* EFSYS_OPT_EVB */
 700
 701 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
 702
 703 #define EFX_PROXY_CONFIGURE_MAGIC       0xAB2015EF
 704
 705
 706 typedef struct efx_proxy_ops_s {
 707         efx_rc_t        (*epo_init)(efx_nic_t *);
 708         void            (*epo_fini)(efx_nic_t *);
 709         efx_rc_t        (*epo_mc_config)(efx_nic_t *, efsys_mem_t *,
 710                                         efsys_mem_t *, efsys_mem_t *,
 711                                         uint32_t, uint32_t *, size_t);
 712         efx_rc_t        (*epo_disable)(efx_nic_t *);
 713         efx_rc_t        (*epo_privilege_modify)(efx_nic_t *, uint32_t, uint32_t,
 714                                         uint32_t, uint32_t, uint32_t);
 715         efx_rc_t        (*epo_set_privilege_mask)(efx_nic_t *, uint32_t,
 716                                         uint32_t, uint32_t);
 717         efx_rc_t        (*epo_complete_request)(efx_nic_t *, uint32_t,
 718                                         uint32_t, uint32_t);
 719         efx_rc_t        (*epo_exec_cmd)(efx_nic_t *, efx_proxy_cmd_params_t *);
 720 } efx_proxy_ops_t;
 721
 722 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
 723
 724 #define EFX_DRV_VER_MAX         20
 725
 726 typedef struct efx_drv_cfg_s {
 727         uint32_t                edc_min_vi_count;
 728         uint32_t                edc_max_vi_count;
 729
 730         uint32_t                edc_max_piobuf_count;
 731         uint32_t                edc_pio_alloc_size;
 732 } efx_drv_cfg_t;
 733
 734 struct efx_nic_s {
 735         uint32_t                en_magic;
 736         efx_family_t            en_family;
 737         uint32_t                en_features;
 738         efsys_identifier_t      *en_esip;
 739         efsys_lock_t            *en_eslp;
 740         efsys_bar_t             *en_esbp;
 741         unsigned int            en_mod_flags;
 742         unsigned int            en_reset_flags;
 743         efx_nic_cfg_t           en_nic_cfg;
 744         efx_drv_cfg_t           en_drv_cfg;
 745         efx_port_t              en_port;
 746         efx_mon_t               en_mon;
 747         efx_intr_t              en_intr;
 748         uint32_t                en_ev_qcount;
 749         uint32_t                en_rx_qcount;
 750         uint32_t                en_tx_qcount;
 751         const efx_nic_ops_t     *en_enop;
 752         const efx_ev_ops_t      *en_eevop;
 753         const efx_tx_ops_t      *en_etxop;
 754         const efx_rx_ops_t      *en_erxop;
 755         efx_fw_variant_t        efv;
 756         char                    en_drv_version[EFX_DRV_VER_MAX];
 757 #if EFSYS_OPT_FILTER
 758         efx_filter_t            en_filter;
 759         const efx_filter_ops_t  *en_efop;
 760 #endif  /* EFSYS_OPT_FILTER */
 761 #if EFSYS_OPT_TUNNEL
 762         efx_tunnel_cfg_t        en_tunnel_cfg;
 763         const efx_tunnel_ops_t  *en_etop;
 764 #endif /* EFSYS_OPT_TUNNEL */
 765 #if EFSYS_OPT_MCDI
 766         efx_mcdi_t              en_mcdi;
 767 #endif  /* EFSYS_OPT_MCDI */
 768 #if EFSYS_OPT_NVRAM
 769         uint32_t                en_nvram_partn_locked;
 770         const efx_nvram_ops_t   *en_envop;
 771 #endif  /* EFSYS_OPT_NVRAM */
 772 #if EFSYS_OPT_VPD
 773         const efx_vpd_ops_t     *en_evpdop;
 774 #endif  /* EFSYS_OPT_VPD */
 775 #if EFSYS_OPT_RX_SCALE
 776         efx_rx_hash_support_t           en_hash_support;
 777         efx_rx_scale_context_type_t     en_rss_context_type;
 778         uint32_t                        en_rss_context;
 779 #endif  /* EFSYS_OPT_RX_SCALE */
 780         uint32_t                en_vport_id;
 781 #if EFSYS_OPT_LICENSING
 782         const efx_lic_ops_t     *en_elop;
 783         boolean_t               en_licensing_supported;
 784 #endif
 785         union {
 786 #if EFSYS_OPT_SIENA
 787                 struct {
 788 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 789                         unsigned int            enu_partn_mask;
 790 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 791 #if EFSYS_OPT_VPD
 792                         caddr_t                 enu_svpd;
 793                         size_t                  enu_svpd_length;
 794 #endif  /* EFSYS_OPT_VPD */
 795                         int                     enu_unused;
 796                 } siena;
 797 #endif  /* EFSYS_OPT_SIENA */
 798                 int     enu_unused;
 799         } en_u;
 800 #if EFX_OPTS_EF10()
 801         union en_arch {
 802                 struct {
 803                         int                     ena_vi_base;
 804                         int                     ena_vi_count;
 805                         int                     ena_vi_shift;
 806 #if EFSYS_OPT_VPD
 807                         caddr_t                 ena_svpd;
 808                         size_t                  ena_svpd_length;
 809 #endif  /* EFSYS_OPT_VPD */
 810                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 811                         uint32_t                ena_piobuf_count;
 812                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 813                         uint32_t                ena_pio_write_vi_base;
 814                         /* Memory BAR mapping regions */
 815                         uint32_t                ena_uc_mem_map_offset;
 816                         size_t                  ena_uc_mem_map_size;
 817                         uint32_t                ena_wc_mem_map_offset;
 818                         size_t                  ena_wc_mem_map_size;
 819                 } ef10;
 820         } en_arch;
 821 #endif  /* EFX_OPTS_EF10() */
 822 #if EFSYS_OPT_EVB
 823         const efx_evb_ops_t     *en_eeop;
 824         struct efx_vswitch_s    *en_vswitchp;
 825 #endif  /* EFSYS_OPT_EVB */
 826 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
 827         const efx_proxy_ops_t   *en_epop;
 828 #endif  /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
 829 };
 830
 831 #define EFX_FAMILY_IS_EF10(_enp) \
 832         ((_enp)->en_family == EFX_FAMILY_MEDFORD2 || \
 833          (_enp)->en_family == EFX_FAMILY_MEDFORD || \
 834          (_enp)->en_family == EFX_FAMILY_HUNTINGTON)
 835
 836
 837 #define EFX_NIC_MAGIC   0x02121996
 838
 839 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 840     const efx_ev_callbacks_t *, void *);
 841
 842 typedef struct efx_evq_rxq_state_s {
 843         unsigned int                    eers_rx_read_ptr;
 844         unsigned int                    eers_rx_mask;
 845 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
 846         unsigned int                    eers_rx_stream_npackets;
 847         boolean_t                       eers_rx_packed_stream;
 848 #endif
 849 #if EFSYS_OPT_RX_PACKED_STREAM
 850         unsigned int                    eers_rx_packed_stream_credits;
 851 #endif
 852 } efx_evq_rxq_state_t;
 853
 854 struct efx_evq_s {
 855         uint32_t                        ee_magic;
 856         uint32_t                        ee_flags;
 857         efx_nic_t                       *ee_enp;
 858         unsigned int                    ee_index;
 859         unsigned int                    ee_mask;
 860         efsys_mem_t                     *ee_esmp;
 861 #if EFSYS_OPT_QSTATS
 862         uint32_t                        ee_stat[EV_NQSTATS];
 863 #endif  /* EFSYS_OPT_QSTATS */
 864
 865         efx_ev_handler_t                ee_rx;
 866         efx_ev_handler_t                ee_tx;
 867         efx_ev_handler_t                ee_driver;
 868         efx_ev_handler_t                ee_global;
 869         efx_ev_handler_t                ee_drv_gen;
 870 #if EFSYS_OPT_MCDI
 871         efx_ev_handler_t                ee_mcdi;
 872 #endif  /* EFSYS_OPT_MCDI */
 873
 874         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 875 };
 876
 877 #define EFX_EVQ_MAGIC   0x08081997
 878
 879 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 880
 881 #if EFSYS_OPT_QSTATS
 882 #define EFX_EV_QSTAT_INCR(_eep, _stat)                                  \
 883         do {                                                            \
 884                 (_eep)->ee_stat[_stat]++;                               \
 885         _NOTE(CONSTANTCONDITION)                                        \
 886         } while (B_FALSE)
 887 #else
 888 #define EFX_EV_QSTAT_INCR(_eep, _stat)
 889 #endif
 890
 891 struct efx_rxq_s {
 892         uint32_t                        er_magic;
 893         efx_nic_t                       *er_enp;
 894         efx_evq_t                       *er_eep;
 895         unsigned int                    er_index;
 896         unsigned int                    er_label;
 897         unsigned int                    er_mask;
 898         size_t                          er_buf_size;
 899         efsys_mem_t                     *er_esmp;
 900         efx_evq_rxq_state_t             *er_ev_qstate;
 901 };
 902
 903 #define EFX_RXQ_MAGIC   0x15022005
 904
 905 struct efx_txq_s {
 906         uint32_t                        et_magic;
 907         efx_nic_t                       *et_enp;
 908         unsigned int                    et_index;
 909         unsigned int                    et_mask;
 910         efsys_mem_t                     *et_esmp;
 911 #if EFSYS_OPT_HUNTINGTON
 912         uint32_t                        et_pio_bufnum;
 913         uint32_t                        et_pio_blknum;
 914         uint32_t                        et_pio_write_offset;
 915         uint32_t                        et_pio_offset;
 916         size_t                          et_pio_size;
 917 #endif
 918 #if EFSYS_OPT_QSTATS
 919         uint32_t                        et_stat[TX_NQSTATS];
 920 #endif  /* EFSYS_OPT_QSTATS */
 921 };
 922
 923 #define EFX_TXQ_MAGIC   0x05092005
 924
 925 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 926         do {                                                            \
 927                 (_dst)[0] = (_src)[0];                                  \
 928                 (_dst)[1] = (_src)[1];                                  \
 929                 (_dst)[2] = (_src)[2];                                  \
 930                 (_dst)[3] = (_src)[3];                                  \
 931                 (_dst)[4] = (_src)[4];                                  \
 932                 (_dst)[5] = (_src)[5];                                  \
 933         _NOTE(CONSTANTCONDITION)                                        \
 934         } while (B_FALSE)
 935
 936 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 937         do {                                                            \
 938                 uint16_t *_d = (uint16_t *)(_dst);                      \
 939                 _d[0] = 0xffff;                                         \
 940                 _d[1] = 0xffff;                                         \
 941                 _d[2] = 0xffff;                                         \
 942         _NOTE(CONSTANTCONDITION)                                        \
 943         } while (B_FALSE)
 944
 945 #if EFSYS_OPT_CHECK_REG
 946 #define EFX_CHECK_REG(_enp, _reg)                                       \
 947         do {                                                            \
 948                 const char *name = #_reg;                               \
 949                 char min = name[4];                                     \
 950                 char max = name[5];                                     \
 951                 char rev;                                               \
 952                                                                         \
 953                 switch ((_enp)->en_family) {                            \
 954                 case EFX_FAMILY_SIENA:                                  \
 955                         rev = 'C';                                      \
 956                         break;                                          \
 957                                                                         \
 958                 case EFX_FAMILY_HUNTINGTON:                             \
 959                         rev = 'D';                                      \
 960                         break;                                          \
 961                                                                         \
 962                 case EFX_FAMILY_MEDFORD:                                \
 963                         rev = 'E';                                      \
 964                         break;                                          \
 965                                                                         \
 966                 case EFX_FAMILY_MEDFORD2:                               \
 967                         rev = 'F';                                      \
 968                         break;                                          \
 969                                                                         \
 970                 default:                                                \
 971                         rev = '?';                                      \
 972                         break;                                          \
 973                 }                                                       \
 974                                                                         \
 975                 EFSYS_ASSERT3S(rev, >=, min);                           \
 976                 EFSYS_ASSERT3S(rev, <=, max);                           \
 977                                                                         \
 978         _NOTE(CONSTANTCONDITION)                                        \
 979         } while (B_FALSE)
 980 #else
 981 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 982         _NOTE(CONSTANTCONDITION)                                        \
 983         } while (B_FALSE)
 984 #endif
 985
 986 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 987         do {                                                            \
 988                 EFX_CHECK_REG((_enp), (_reg));                          \
 989                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 990                     (_edp), (_lock));                                   \
 991                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 992                     uint32_t, _reg ## _OFST,                            \
 993                     uint32_t, (_edp)->ed_u32[0]);                       \
 994         _NOTE(CONSTANTCONDITION)                                        \
 995         } while (B_FALSE)
 996
 997 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 998         do {                                                            \
 999                 EFX_CHECK_REG((_enp), (_reg));                          \
1000                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
1001                     uint32_t, _reg ## _OFST,                            \
1002                     uint32_t, (_edp)->ed_u32[0]);                       \
1003                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
1004                     (_edp), (_lock));                                   \
1005         _NOTE(CONSTANTCONDITION)                                        \
1006         } while (B_FALSE)
1007
1008 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
1009         do {                                                            \
1010                 EFX_CHECK_REG((_enp), (_reg));                          \
1011                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
1012                     (_eqp));                                            \
1013                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
1014                     uint32_t, _reg ## _OFST,                            \
1015                     uint32_t, (_eqp)->eq_u32[1],                        \
1016                     uint32_t, (_eqp)->eq_u32[0]);                       \
1017         _NOTE(CONSTANTCONDITION)                                        \
1018         } while (B_FALSE)
1019
1020 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
1021         do {                                                            \
1022                 EFX_CHECK_REG((_enp), (_reg));                          \
1023                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
1024                     uint32_t, _reg ## _OFST,                            \
1025                     uint32_t, (_eqp)->eq_u32[1],                        \
1026                     uint32_t, (_eqp)->eq_u32[0]);                       \
1027                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
1028                     (_eqp));                                            \
1029         _NOTE(CONSTANTCONDITION)                                        \
1030         } while (B_FALSE)
1031
1032 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
1033         do {                                                            \
1034                 EFX_CHECK_REG((_enp), (_reg));                          \
1035                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
1036                     (_eop), B_TRUE);                                    \
1037                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
1038                     uint32_t, _reg ## _OFST,                            \
1039                     uint32_t, (_eop)->eo_u32[3],                        \
1040                     uint32_t, (_eop)->eo_u32[2],                        \
1041                     uint32_t, (_eop)->eo_u32[1],                        \
1042                     uint32_t, (_eop)->eo_u32[0]);                       \
1043         _NOTE(CONSTANTCONDITION)                                        \
1044         } while (B_FALSE)
1045
1046 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
1047         do {                                                            \
1048                 EFX_CHECK_REG((_enp), (_reg));                          \
1049                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
1050                     uint32_t, _reg ## _OFST,                            \
1051                     uint32_t, (_eop)->eo_u32[3],                        \
1052                     uint32_t, (_eop)->eo_u32[2],                        \
1053                     uint32_t, (_eop)->eo_u32[1],                        \
1054                     uint32_t, (_eop)->eo_u32[0]);                       \
1055                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
1056                     (_eop), B_TRUE);                                    \
1057         _NOTE(CONSTANTCONDITION)                                        \
1058         } while (B_FALSE)
1059
1060 /*
1061  * Accessors for memory BAR non-VI tables.
1062  *
1063  * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers,
1064  * to ensure the correct runtime VI window size is used on Medford2.
1065  *
1066  * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers.
1067  */
1068
1069 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
1070         do {                                                            \
1071                 EFX_CHECK_REG((_enp), (_reg));                          \
1072                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
1073                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1074                     (_edp), (_lock));                                   \
1075                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
1076                     uint32_t, (_index),                                 \
1077                     uint32_t, _reg ## _OFST,                            \
1078                     uint32_t, (_edp)->ed_u32[0]);                       \
1079         _NOTE(CONSTANTCONDITION)                                        \
1080         } while (B_FALSE)
1081
1082 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
1083         do {                                                            \
1084                 EFX_CHECK_REG((_enp), (_reg));                          \
1085                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
1086                     uint32_t, (_index),                                 \
1087                     uint32_t, _reg ## _OFST,                            \
1088                     uint32_t, (_edp)->ed_u32[0]);                       \
1089                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1090                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1091                     (_edp), (_lock));                                   \
1092         _NOTE(CONSTANTCONDITION)                                        \
1093         } while (B_FALSE)
1094
1095 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
1096         do {                                                            \
1097                 EFX_CHECK_REG((_enp), (_reg));                          \
1098                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
1099                     uint32_t, (_index),                                 \
1100                     uint32_t, _reg ## _OFST,                            \
1101                     uint32_t, (_edp)->ed_u32[0]);                       \
1102                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1103                     (_reg ## _OFST +                                    \
1104                     (3 * sizeof (efx_dword_t)) +                        \
1105                     ((_index) * _reg ## _STEP)),                        \
1106                     (_edp), (_lock));                                   \
1107         _NOTE(CONSTANTCONDITION)                                        \
1108         } while (B_FALSE)
1109
1110 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
1111         do {                                                            \
1112                 EFX_CHECK_REG((_enp), (_reg));                          \
1113                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
1114                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1115                     (_eqp));                                            \
1116                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
1117                     uint32_t, (_index),                                 \
1118                     uint32_t, _reg ## _OFST,                            \
1119                     uint32_t, (_eqp)->eq_u32[1],                        \
1120                     uint32_t, (_eqp)->eq_u32[0]);                       \
1121         _NOTE(CONSTANTCONDITION)                                        \
1122         } while (B_FALSE)
1123
1124 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
1125         do {                                                            \
1126                 EFX_CHECK_REG((_enp), (_reg));                          \
1127                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
1128                     uint32_t, (_index),                                 \
1129                     uint32_t, _reg ## _OFST,                            \
1130                     uint32_t, (_eqp)->eq_u32[1],                        \
1131                     uint32_t, (_eqp)->eq_u32[0]);                       \
1132                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
1133                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1134                     (_eqp));                                            \
1135         _NOTE(CONSTANTCONDITION)                                        \
1136         } while (B_FALSE)
1137
1138 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
1139         do {                                                            \
1140                 EFX_CHECK_REG((_enp), (_reg));                          \
1141                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
1142                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1143                     (_eop), (_lock));                                   \
1144                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
1145                     uint32_t, (_index),                                 \
1146                     uint32_t, _reg ## _OFST,                            \
1147                     uint32_t, (_eop)->eo_u32[3],                        \
1148                     uint32_t, (_eop)->eo_u32[2],                        \
1149                     uint32_t, (_eop)->eo_u32[1],                        \
1150                     uint32_t, (_eop)->eo_u32[0]);                       \
1151         _NOTE(CONSTANTCONDITION)                                        \
1152         } while (B_FALSE)
1153
1154 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
1155         do {                                                            \
1156                 EFX_CHECK_REG((_enp), (_reg));                          \
1157                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
1158                     uint32_t, (_index),                                 \
1159                     uint32_t, _reg ## _OFST,                            \
1160                     uint32_t, (_eop)->eo_u32[3],                        \
1161                     uint32_t, (_eop)->eo_u32[2],                        \
1162                     uint32_t, (_eop)->eo_u32[1],                        \
1163                     uint32_t, (_eop)->eo_u32[0]);                       \
1164                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
1165                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1166                     (_eop), (_lock));                                   \
1167         _NOTE(CONSTANTCONDITION)                                        \
1168         } while (B_FALSE)
1169
1170 /*
1171  * Accessors for memory BAR per-VI registers.
1172  *
1173  * The VI window size is 8KB for Medford and all earlier controllers.
1174  * For Medford2, the VI window size can be 8KB, 16KB or 64KB.
1175  */
1176
1177 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock)               \
1178         do {                                                            \
1179                 EFX_CHECK_REG((_enp), (_reg));                          \
1180                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
1181                     ((_reg ## _OFST) +                                  \
1182                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1183                     (_edp), (_lock));                                   \
1184                 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg,     \
1185                     uint32_t, (_index),                                 \
1186                     uint32_t, _reg ## _OFST,                            \
1187                     uint32_t, (_edp)->ed_u32[0]);                       \
1188         _NOTE(CONSTANTCONDITION)                                        \
1189         } while (B_FALSE)
1190
1191 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock)              \
1192         do {                                                            \
1193                 EFX_CHECK_REG((_enp), (_reg));                          \
1194                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1195                     uint32_t, (_index),                                 \
1196                     uint32_t, _reg ## _OFST,                            \
1197                     uint32_t, (_edp)->ed_u32[0]);                       \
1198                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1199                     ((_reg ## _OFST) +                                  \
1200                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1201                     (_edp), (_lock));                                   \
1202         _NOTE(CONSTANTCONDITION)                                        \
1203         } while (B_FALSE)
1204
1205 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock)             \
1206         do {                                                            \
1207                 EFX_CHECK_REG((_enp), (_reg));                          \
1208                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1209                     uint32_t, (_index),                                 \
1210                     uint32_t, _reg ## _OFST,                            \
1211                     uint32_t, (_edp)->ed_u32[0]);                       \
1212                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1213                     ((_reg ## _OFST) +                                  \
1214                     (2 * sizeof (efx_dword_t)) +                        \
1215                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1216                     (_edp), (_lock));                                   \
1217         _NOTE(CONSTANTCONDITION)                                        \
1218         } while (B_FALSE)
1219
1220 /*
1221  * Allow drivers to perform optimised 128-bit VI doorbell writes.
1222  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1223  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1224  * the need for locking in the host, and are the only ones known to be safe to
1225  * use 128-bites write with.
1226  */
1227 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop)            \
1228         do {                                                            \
1229                 EFX_CHECK_REG((_enp), (_reg));                          \
1230                 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo,                \
1231                     const char *, #_reg,                                \
1232                     uint32_t, (_index),                                 \
1233                     uint32_t, _reg ## _OFST,                            \
1234                     uint32_t, (_eop)->eo_u32[3],                        \
1235                     uint32_t, (_eop)->eo_u32[2],                        \
1236                     uint32_t, (_eop)->eo_u32[1],                        \
1237                     uint32_t, (_eop)->eo_u32[0]);                       \
1238                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1239                     (_reg ## _OFST +                                    \
1240                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1241                     (_eop));                                            \
1242         _NOTE(CONSTANTCONDITION)                                        \
1243         } while (B_FALSE)
1244
1245 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1246         do {                                                            \
1247                 unsigned int _new = (_wptr);                            \
1248                 unsigned int _old = (_owptr);                           \
1249                                                                         \
1250                 if ((_new) >= (_old))                                   \
1251                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1252                             (_old) * sizeof (efx_desc_t),               \
1253                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1254                 else                                                    \
1255                         /*                                              \
1256                          * It is cheaper to sync entire map than sync   \
1257                          * two parts especially when offset/size are    \
1258                          * ignored and entire map is synced in any case.\
1259                          */                                             \
1260                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1261                             0,                                          \
1262                             (_entries) * sizeof (efx_desc_t));          \
1263         _NOTE(CONSTANTCONDITION)                                        \
1264         } while (B_FALSE)
1265
1266 extern  __checkReturn   efx_rc_t
1267 efx_mac_select(
1268         __in            efx_nic_t *enp);
1269
1270 extern  void
1271 efx_mac_multicast_hash_compute(
1272         __in_ecount(6*count)            uint8_t const *addrs,
1273         __in                            int count,
1274         __out                           efx_oword_t *hash_low,
1275         __out                           efx_oword_t *hash_high);
1276
1277 extern  __checkReturn   efx_rc_t
1278 efx_phy_probe(
1279         __in            efx_nic_t *enp);
1280
1281 extern                  void
1282 efx_phy_unprobe(
1283         __in            efx_nic_t *enp);
1284
1285 #if EFSYS_OPT_VPD
1286
1287 /* VPD utility functions */
1288
1289 extern  __checkReturn           efx_rc_t
1290 efx_vpd_hunk_length(
1291         __in_bcount(size)       caddr_t data,
1292         __in                    size_t size,
1293         __out                   size_t *lengthp);
1294
1295 extern  __checkReturn           efx_rc_t
1296 efx_vpd_hunk_verify(
1297         __in_bcount(size)       caddr_t data,
1298         __in                    size_t size,
1299         __out_opt               boolean_t *cksummedp);
1300
1301 extern  __checkReturn           efx_rc_t
1302 efx_vpd_hunk_reinit(
1303         __in_bcount(size)       caddr_t data,
1304         __in                    size_t size,
1305         __in                    boolean_t wantpid);
1306
1307 extern  __checkReturn           efx_rc_t
1308 efx_vpd_hunk_get(
1309         __in_bcount(size)       caddr_t data,
1310         __in                    size_t size,
1311         __in                    efx_vpd_tag_t tag,
1312         __in                    efx_vpd_keyword_t keyword,
1313         __out                   unsigned int *payloadp,
1314         __out                   uint8_t *paylenp);
1315
1316 extern  __checkReturn                   efx_rc_t
1317 efx_vpd_hunk_next(
1318         __in_bcount(size)               caddr_t data,
1319         __in                            size_t size,
1320         __out                           efx_vpd_tag_t *tagp,
1321         __out                           efx_vpd_keyword_t *keyword,
1322         __out_opt                       unsigned int *payloadp,
1323         __out_opt                       uint8_t *paylenp,
1324         __inout                         unsigned int *contp);
1325
1326 extern  __checkReturn           efx_rc_t
1327 efx_vpd_hunk_set(
1328         __in_bcount(size)       caddr_t data,
1329         __in                    size_t size,
1330         __in                    efx_vpd_value_t *evvp);
1331
1332 #endif  /* EFSYS_OPT_VPD */
1333
1334 #if EFSYS_OPT_MCDI
1335
1336 extern  __checkReturn           efx_rc_t
1337 efx_mcdi_set_workaround(
1338         __in                    efx_nic_t *enp,
1339         __in                    uint32_t type,
1340         __in                    boolean_t enabled,
1341         __out_opt               uint32_t *flagsp);
1342
1343 extern  __checkReturn           efx_rc_t
1344 efx_mcdi_get_workarounds(
1345         __in                    efx_nic_t *enp,
1346         __out_opt               uint32_t *implementedp,
1347         __out_opt               uint32_t *enabledp);
1348
1349 #endif /* EFSYS_OPT_MCDI */
1350
1351 #if EFSYS_OPT_MAC_STATS
1352
1353 /*
1354  * Closed range of stats (i.e. the first and the last are included).
1355  * The last must be greater or equal (if the range is one item only) to
1356  * the first.
1357  */
1358 struct efx_mac_stats_range {
1359         efx_mac_stat_t          first;
1360         efx_mac_stat_t          last;
1361 };
1362
1363 typedef enum efx_stats_action_e {
1364         EFX_STATS_CLEAR,
1365         EFX_STATS_UPLOAD,
1366         EFX_STATS_ENABLE_NOEVENTS,
1367         EFX_STATS_ENABLE_EVENTS,
1368         EFX_STATS_DISABLE,
1369 } efx_stats_action_t;
1370
1371 extern                                  efx_rc_t
1372 efx_mac_stats_mask_add_ranges(
1373         __inout_bcount(mask_size)       uint32_t *maskp,
1374         __in                            size_t mask_size,
1375         __in_ecount(rng_count)          const struct efx_mac_stats_range *rngp,
1376         __in                            unsigned int rng_count);
1377
1378 extern  __checkReturn   efx_rc_t
1379 efx_mcdi_mac_stats(
1380         __in            efx_nic_t *enp,
1381         __in            uint32_t vport_id,
1382         __in_opt        efsys_mem_t *esmp,
1383         __in            efx_stats_action_t action,
1384         __in            uint16_t period_ms);
1385
1386 #endif  /* EFSYS_OPT_MAC_STATS */
1387
1388 #ifdef  __cplusplus
1389 }
1390 #endif
1391
1392 #endif  /* _SYS_EFX_IMPL_H */