drivers/net/sfc/base/efx_impl.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2007-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  */
   6
   7 #ifndef _SYS_EFX_IMPL_H
   8 #define _SYS_EFX_IMPL_H
   9
  10 #include "efx.h"
  11 #include "efx_regs.h"
  12 #include "efx_regs_ef10.h"
  13 #if EFSYS_OPT_MCDI
  14 #include "efx_mcdi.h"
  15 #endif  /* EFSYS_OPT_MCDI */
  16
  17 /* FIXME: Add definition for driver generated software events */
  18 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  19 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  20 #endif
  21
  22
  23 #if EFSYS_OPT_SIENA
  24 #include "siena_impl.h"
  25 #endif  /* EFSYS_OPT_SIENA */
  26
  27 #if EFSYS_OPT_HUNTINGTON
  28 #include "hunt_impl.h"
  29 #endif  /* EFSYS_OPT_HUNTINGTON */
  30
  31 #if EFSYS_OPT_MEDFORD
  32 #include "medford_impl.h"
  33 #endif  /* EFSYS_OPT_MEDFORD */
  34
  35 #if EFSYS_OPT_MEDFORD2
  36 #include "medford2_impl.h"
  37 #endif  /* EFSYS_OPT_MEDFORD2 */
  38
  39 #if EFX_OPTS_EF10()
  40 #include "ef10_impl.h"
  41 #endif  /* EFX_OPTS_EF10() */
  42
  43 #ifdef  __cplusplus
  44 extern "C" {
  45 #endif
  46
  47 #define EFX_MOD_MCDI            0x00000001
  48 #define EFX_MOD_PROBE           0x00000002
  49 #define EFX_MOD_NVRAM           0x00000004
  50 #define EFX_MOD_VPD             0x00000008
  51 #define EFX_MOD_NIC             0x00000010
  52 #define EFX_MOD_INTR            0x00000020
  53 #define EFX_MOD_EV              0x00000040
  54 #define EFX_MOD_RX              0x00000080
  55 #define EFX_MOD_TX              0x00000100
  56 #define EFX_MOD_PORT            0x00000200
  57 #define EFX_MOD_MON             0x00000400
  58 #define EFX_MOD_FILTER          0x00001000
  59 #define EFX_MOD_LIC             0x00002000
  60 #define EFX_MOD_TUNNEL          0x00004000
  61 #define EFX_MOD_EVB             0x00008000
  62 #define EFX_MOD_PROXY           0x00010000
  63
  64 #define EFX_RESET_PHY           0x00000001
  65 #define EFX_RESET_RXQ_ERR       0x00000002
  66 #define EFX_RESET_TXQ_ERR       0x00000004
  67 #define EFX_RESET_HW_UNAVAIL    0x00000008
  68
  69 typedef enum efx_mac_type_e {
  70         EFX_MAC_INVALID = 0,
  71         EFX_MAC_SIENA,
  72         EFX_MAC_HUNTINGTON,
  73         EFX_MAC_MEDFORD,
  74         EFX_MAC_MEDFORD2,
  75         EFX_MAC_NTYPES
  76 } efx_mac_type_t;
  77
  78 typedef struct efx_ev_ops_s {
  79         efx_rc_t        (*eevo_init)(efx_nic_t *);
  80         void            (*eevo_fini)(efx_nic_t *);
  81         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  82                                           efsys_mem_t *, size_t, uint32_t,
  83                                           uint32_t, uint32_t, efx_evq_t *);
  84         void            (*eevo_qdestroy)(efx_evq_t *);
  85         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  86         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  87         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
  88 #if EFSYS_OPT_QSTATS
  89         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
  90 #endif
  91 } efx_ev_ops_t;
  92
  93 typedef struct efx_tx_ops_s {
  94         efx_rc_t        (*etxo_init)(efx_nic_t *);
  95         void            (*etxo_fini)(efx_nic_t *);
  96         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
  97                                         unsigned int, unsigned int,
  98                                         efsys_mem_t *, size_t,
  99                                         uint32_t, uint16_t,
 100                                         efx_evq_t *, efx_txq_t *,
 101                                         unsigned int *);
 102         void            (*etxo_qdestroy)(efx_txq_t *);
 103         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 104                                       unsigned int, unsigned int,
 105                                       unsigned int *);
 106         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 107         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 108         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 109         void            (*etxo_qenable)(efx_txq_t *);
 110         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 111         void            (*etxo_qpio_disable)(efx_txq_t *);
 112         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 113                                            size_t);
 114         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 115                                            unsigned int *);
 116         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 117                                       unsigned int, unsigned int,
 118                                       unsigned int *);
 119         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 120                                                 size_t, boolean_t,
 121                                                 efx_desc_t *);
 122         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 123                                                 uint32_t, uint8_t,
 124                                                 efx_desc_t *);
 125         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 126                                                 uint16_t, uint32_t, uint16_t,
 127                                                 efx_desc_t *, int);
 128         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 129                                                 efx_desc_t *);
 130         void            (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t,
 131                                                 efx_desc_t *);
 132 #if EFSYS_OPT_QSTATS
 133         void            (*etxo_qstats_update)(efx_txq_t *,
 134                                               efsys_stat_t *);
 135 #endif
 136 } efx_tx_ops_t;
 137
 138 typedef union efx_rxq_type_data_u {
 139         struct {
 140                 size_t          ed_buf_size;
 141         } ertd_default;
 142 #if EFSYS_OPT_RX_PACKED_STREAM
 143         struct {
 144                 uint32_t        eps_buf_size;
 145         } ertd_packed_stream;
 146 #endif
 147 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
 148         struct {
 149                 uint32_t        eessb_bufs_per_desc;
 150                 uint32_t        eessb_max_dma_len;
 151                 uint32_t        eessb_buf_stride;
 152                 uint32_t        eessb_hol_block_timeout;
 153         } ertd_es_super_buffer;
 154 #endif
 155 } efx_rxq_type_data_t;
 156
 157 typedef struct efx_rx_ops_s {
 158         efx_rc_t        (*erxo_init)(efx_nic_t *);
 159         void            (*erxo_fini)(efx_nic_t *);
 160 #if EFSYS_OPT_RX_SCATTER
 161         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 162 #endif
 163 #if EFSYS_OPT_RX_SCALE
 164         efx_rc_t        (*erxo_scale_context_alloc)(efx_nic_t *,
 165                                                     efx_rx_scale_context_type_t,
 166                                                     uint32_t, uint32_t *);
 167         efx_rc_t        (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
 168         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
 169                                                efx_rx_hash_alg_t,
 170                                                efx_rx_hash_type_t, boolean_t);
 171         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
 172                                               uint8_t *, size_t);
 173         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
 174                                               unsigned int *, size_t);
 175         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 176                                             uint8_t *);
 177 #endif /* EFSYS_OPT_RX_SCALE */
 178         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 179                                               uint16_t *);
 180         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 181                                       unsigned int, unsigned int,
 182                                       unsigned int);
 183         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 184 #if EFSYS_OPT_RX_PACKED_STREAM
 185         void            (*erxo_qpush_ps_credits)(efx_rxq_t *);
 186         uint8_t *       (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
 187                                                 uint32_t, uint32_t,
 188                                                 uint16_t *, uint32_t *, uint32_t *);
 189 #endif
 190         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 191         void            (*erxo_qenable)(efx_rxq_t *);
 192         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 193                                         unsigned int, efx_rxq_type_t,
 194                                         const efx_rxq_type_data_t *,
 195                                         efsys_mem_t *, size_t, uint32_t,
 196                                         unsigned int,
 197                                         efx_evq_t *, efx_rxq_t *);
 198         void            (*erxo_qdestroy)(efx_rxq_t *);
 199 } efx_rx_ops_t;
 200
 201 typedef struct efx_mac_ops_s {
 202         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 203         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 204         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 205         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 206         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 207         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 208         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 209         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 210                                                       efx_rxq_t *, boolean_t);
 211         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 212 #if EFSYS_OPT_LOOPBACK
 213         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 214                                             efx_loopback_type_t);
 215 #endif  /* EFSYS_OPT_LOOPBACK */
 216 #if EFSYS_OPT_MAC_STATS
 217         efx_rc_t        (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
 218         efx_rc_t        (*emo_stats_clear)(efx_nic_t *);
 219         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 220         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 221                                               uint16_t, boolean_t);
 222         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 223                                             efsys_stat_t *, uint32_t *);
 224 #endif  /* EFSYS_OPT_MAC_STATS */
 225 } efx_mac_ops_t;
 226
 227 typedef struct efx_phy_ops_s {
 228         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 229         efx_rc_t        (*epo_reset)(efx_nic_t *);
 230         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 231         efx_rc_t        (*epo_verify)(efx_nic_t *);
 232         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 233         efx_rc_t        (*epo_link_state_get)(efx_nic_t *, efx_phy_link_state_t *);
 234 #if EFSYS_OPT_PHY_STATS
 235         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 236                                             uint32_t *);
 237 #endif  /* EFSYS_OPT_PHY_STATS */
 238 #if EFSYS_OPT_BIST
 239         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 240         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 241         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 242                                          efx_bist_result_t *, uint32_t *,
 243                                          unsigned long *, size_t);
 244         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 245 #endif  /* EFSYS_OPT_BIST */
 246 } efx_phy_ops_t;
 247
 248 #if EFSYS_OPT_FILTER
 249 typedef struct efx_filter_ops_s {
 250         efx_rc_t        (*efo_init)(efx_nic_t *);
 251         void            (*efo_fini)(efx_nic_t *);
 252         efx_rc_t        (*efo_restore)(efx_nic_t *);
 253         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 254                                    boolean_t may_replace);
 255         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 256         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *,
 257                                    size_t, size_t *);
 258         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 259                                    boolean_t, boolean_t, boolean_t,
 260                                    uint8_t const *, uint32_t);
 261 } efx_filter_ops_t;
 262
 263 extern  __checkReturn   efx_rc_t
 264 efx_filter_reconfigure(
 265         __in                            efx_nic_t *enp,
 266         __in_ecount(6)                  uint8_t const *mac_addr,
 267         __in                            boolean_t all_unicst,
 268         __in                            boolean_t mulcst,
 269         __in                            boolean_t all_mulcst,
 270         __in                            boolean_t brdcst,
 271         __in_ecount(6*count)            uint8_t const *addrs,
 272         __in                            uint32_t count);
 273
 274 #endif /* EFSYS_OPT_FILTER */
 275
 276 #if EFSYS_OPT_TUNNEL
 277 typedef struct efx_tunnel_ops_s {
 278         boolean_t       (*eto_udp_encap_supported)(efx_nic_t *);
 279         efx_rc_t        (*eto_reconfigure)(efx_nic_t *);
 280 } efx_tunnel_ops_t;
 281 #endif /* EFSYS_OPT_TUNNEL */
 282
 283 typedef struct efx_port_s {
 284         efx_mac_type_t          ep_mac_type;
 285         uint32_t                ep_phy_type;
 286         uint8_t                 ep_port;
 287         uint32_t                ep_mac_pdu;
 288         uint8_t                 ep_mac_addr[6];
 289         efx_link_mode_t         ep_link_mode;
 290         boolean_t               ep_all_unicst;
 291         boolean_t               ep_mulcst;
 292         boolean_t               ep_all_mulcst;
 293         boolean_t               ep_brdcst;
 294         unsigned int            ep_fcntl;
 295         boolean_t               ep_fcntl_autoneg;
 296         efx_oword_t             ep_multicst_hash[2];
 297         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 298                                                     EFX_MAC_MULTICAST_LIST_MAX];
 299         uint32_t                ep_mulcst_addr_count;
 300 #if EFSYS_OPT_LOOPBACK
 301         efx_loopback_type_t     ep_loopback_type;
 302         efx_link_mode_t         ep_loopback_link_mode;
 303 #endif  /* EFSYS_OPT_LOOPBACK */
 304 #if EFSYS_OPT_PHY_FLAGS
 305         uint32_t                ep_phy_flags;
 306 #endif  /* EFSYS_OPT_PHY_FLAGS */
 307 #if EFSYS_OPT_PHY_LED_CONTROL
 308         efx_phy_led_mode_t      ep_phy_led_mode;
 309 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 310         efx_phy_media_type_t    ep_fixed_port_type;
 311         efx_phy_media_type_t    ep_module_type;
 312         uint32_t                ep_adv_cap_mask;
 313         uint32_t                ep_lp_cap_mask;
 314         uint32_t                ep_default_adv_cap_mask;
 315         uint32_t                ep_phy_cap_mask;
 316         boolean_t               ep_mac_drain;
 317 #if EFSYS_OPT_BIST
 318         efx_bist_type_t         ep_current_bist;
 319 #endif
 320         const efx_mac_ops_t     *ep_emop;
 321         const efx_phy_ops_t     *ep_epop;
 322 } efx_port_t;
 323
 324 typedef struct efx_mon_ops_s {
 325 #if EFSYS_OPT_MON_STATS
 326         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 327                                             efx_mon_stat_value_t *);
 328         efx_rc_t        (*emo_limits_update)(efx_nic_t *,
 329                                              efx_mon_stat_limits_t *);
 330 #endif  /* EFSYS_OPT_MON_STATS */
 331 } efx_mon_ops_t;
 332
 333 typedef struct efx_mon_s {
 334         efx_mon_type_t          em_type;
 335         const efx_mon_ops_t     *em_emop;
 336 } efx_mon_t;
 337
 338 typedef struct efx_intr_ops_s {
 339         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 340         void            (*eio_enable)(efx_nic_t *);
 341         void            (*eio_disable)(efx_nic_t *);
 342         void            (*eio_disable_unlocked)(efx_nic_t *);
 343         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 344         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 345         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 346                                  boolean_t *);
 347         void            (*eio_fatal)(efx_nic_t *);
 348         void            (*eio_fini)(efx_nic_t *);
 349 } efx_intr_ops_t;
 350
 351 typedef struct efx_intr_s {
 352         const efx_intr_ops_t    *ei_eiop;
 353         efsys_mem_t             *ei_esmp;
 354         efx_intr_type_t         ei_type;
 355         unsigned int            ei_level;
 356 } efx_intr_t;
 357
 358 typedef struct efx_nic_ops_s {
 359         efx_rc_t        (*eno_probe)(efx_nic_t *);
 360         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 361         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 362         efx_rc_t        (*eno_reset)(efx_nic_t *);
 363         efx_rc_t        (*eno_init)(efx_nic_t *);
 364         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 365         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 366                                         uint32_t *, size_t *);
 367         boolean_t       (*eno_hw_unavailable)(efx_nic_t *);
 368         void            (*eno_set_hw_unavailable)(efx_nic_t *);
 369 #if EFSYS_OPT_DIAG
 370         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 371 #endif  /* EFSYS_OPT_DIAG */
 372         void            (*eno_fini)(efx_nic_t *);
 373         void            (*eno_unprobe)(efx_nic_t *);
 374 } efx_nic_ops_t;
 375
 376 #ifndef EFX_TXQ_LIMIT_TARGET
 377 #define EFX_TXQ_LIMIT_TARGET 259
 378 #endif
 379 #ifndef EFX_RXQ_LIMIT_TARGET
 380 #define EFX_RXQ_LIMIT_TARGET 512
 381 #endif
 382
 383
 384 #if EFSYS_OPT_FILTER
 385
 386 #if EFSYS_OPT_SIENA
 387
 388 typedef struct siena_filter_spec_s {
 389         uint8_t         sfs_type;
 390         uint32_t        sfs_flags;
 391         uint32_t        sfs_dmaq_id;
 392         uint32_t        sfs_dword[3];
 393 } siena_filter_spec_t;
 394
 395 typedef enum siena_filter_type_e {
 396         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 397         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 398         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 399         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 400         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 401         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 402
 403         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 404         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 405         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 406         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 407         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 408         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 409
 410         EFX_SIENA_FILTER_NTYPES
 411 } siena_filter_type_t;
 412
 413 typedef enum siena_filter_tbl_id_e {
 414         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 415         EFX_SIENA_FILTER_TBL_RX_MAC,
 416         EFX_SIENA_FILTER_TBL_TX_IP,
 417         EFX_SIENA_FILTER_TBL_TX_MAC,
 418         EFX_SIENA_FILTER_NTBLS
 419 } siena_filter_tbl_id_t;
 420
 421 typedef struct siena_filter_tbl_s {
 422         int                     sft_size;       /* number of entries */
 423         int                     sft_used;       /* active count */
 424         uint32_t                *sft_bitmap;    /* active bitmap */
 425         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 426 } siena_filter_tbl_t;
 427
 428 typedef struct siena_filter_s {
 429         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 430         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 431 } siena_filter_t;
 432
 433 #endif  /* EFSYS_OPT_SIENA */
 434
 435 typedef struct efx_filter_s {
 436 #if EFSYS_OPT_SIENA
 437         siena_filter_t          *ef_siena_filter;
 438 #endif /* EFSYS_OPT_SIENA */
 439 #if EFX_OPTS_EF10()
 440         ef10_filter_table_t     *ef_ef10_filter_table;
 441 #endif /* EFX_OPTS_EF10() */
 442 } efx_filter_t;
 443
 444 #if EFSYS_OPT_SIENA
 445
 446 extern                  void
 447 siena_filter_tbl_clear(
 448         __in            efx_nic_t *enp,
 449         __in            siena_filter_tbl_id_t tbl);
 450
 451 #endif  /* EFSYS_OPT_SIENA */
 452
 453 #endif  /* EFSYS_OPT_FILTER */
 454
 455 #if EFSYS_OPT_MCDI
 456
 457 #define EFX_TUNNEL_MAXNENTRIES  (16)
 458
 459 #if EFSYS_OPT_TUNNEL
 460
 461 typedef struct efx_tunnel_udp_entry_s {
 462         uint16_t                        etue_port; /* host/cpu-endian */
 463         uint16_t                        etue_protocol;
 464 } efx_tunnel_udp_entry_t;
 465
 466 typedef struct efx_tunnel_cfg_s {
 467         efx_tunnel_udp_entry_t  etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
 468         unsigned int            etc_udp_entries_num;
 469 } efx_tunnel_cfg_t;
 470
 471 #endif /* EFSYS_OPT_TUNNEL */
 472
 473 typedef struct efx_mcdi_ops_s {
 474         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 475         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 476                                         void *, size_t);
 477         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 478         boolean_t       (*emco_poll_response)(efx_nic_t *);
 479         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 480         void            (*emco_fini)(efx_nic_t *);
 481         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 482                                             efx_mcdi_feature_id_t, boolean_t *);
 483         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 484                                             uint32_t *);
 485 } efx_mcdi_ops_t;
 486
 487 typedef struct efx_mcdi_s {
 488         const efx_mcdi_ops_t            *em_emcop;
 489         const efx_mcdi_transport_t      *em_emtp;
 490         efx_mcdi_iface_t                em_emip;
 491 } efx_mcdi_t;
 492
 493 #endif /* EFSYS_OPT_MCDI */
 494
 495 #if EFSYS_OPT_NVRAM
 496
 497 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
 498 #define EFX_NVRAM_PARTN_INVALID         (0xffffffffu)
 499
 500 typedef struct efx_nvram_ops_s {
 501 #if EFSYS_OPT_DIAG
 502         efx_rc_t        (*envo_test)(efx_nic_t *);
 503 #endif  /* EFSYS_OPT_DIAG */
 504         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 505                                             uint32_t *);
 506         efx_rc_t        (*envo_partn_info)(efx_nic_t *, uint32_t,
 507                                             efx_nvram_info_t *);
 508         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 509         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 510                                             unsigned int, caddr_t, size_t);
 511         efx_rc_t        (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
 512                                             unsigned int, caddr_t, size_t);
 513         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 514                                             unsigned int, size_t);
 515         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 516                                             unsigned int, caddr_t, size_t);
 517         efx_rc_t        (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
 518                                             uint32_t *);
 519         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 520                                             uint32_t *, uint16_t *);
 521         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 522                                             uint16_t *);
 523         efx_rc_t        (*envo_buffer_validate)(uint32_t,
 524                                             caddr_t, size_t);
 525 } efx_nvram_ops_t;
 526 #endif /* EFSYS_OPT_NVRAM */
 527
 528 #if EFSYS_OPT_VPD
 529 typedef struct efx_vpd_ops_s {
 530         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 531         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 532         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 533         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 534         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 535         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 536                                         efx_vpd_value_t *);
 537         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 538                                         efx_vpd_value_t *);
 539         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 540                                         efx_vpd_value_t *, unsigned int *);
 541         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 542         void            (*evpdo_fini)(efx_nic_t *);
 543 } efx_vpd_ops_t;
 544 #endif  /* EFSYS_OPT_VPD */
 545
 546 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 547
 548         __checkReturn           efx_rc_t
 549 efx_mcdi_nvram_partitions(
 550         __in                    efx_nic_t *enp,
 551         __out_bcount(size)      caddr_t data,
 552         __in                    size_t size,
 553         __out                   unsigned int *npartnp);
 554
 555         __checkReturn           efx_rc_t
 556 efx_mcdi_nvram_metadata(
 557         __in                    efx_nic_t *enp,
 558         __in                    uint32_t partn,
 559         __out                   uint32_t *subtypep,
 560         __out_ecount(4)         uint16_t version[4],
 561         __out_bcount_opt(size)  char *descp,
 562         __in                    size_t size);
 563
 564         __checkReturn           efx_rc_t
 565 efx_mcdi_nvram_info(
 566         __in                    efx_nic_t *enp,
 567         __in                    uint32_t partn,
 568         __out                   efx_nvram_info_t *eni);
 569
 570         __checkReturn           efx_rc_t
 571 efx_mcdi_nvram_update_start(
 572         __in                    efx_nic_t *enp,
 573         __in                    uint32_t partn);
 574
 575         __checkReturn           efx_rc_t
 576 efx_mcdi_nvram_read(
 577         __in                    efx_nic_t *enp,
 578         __in                    uint32_t partn,
 579         __in                    uint32_t offset,
 580         __out_bcount(size)      caddr_t data,
 581         __in                    size_t size,
 582         __in                    uint32_t mode);
 583
 584         __checkReturn           efx_rc_t
 585 efx_mcdi_nvram_erase(
 586         __in                    efx_nic_t *enp,
 587         __in                    uint32_t partn,
 588         __in                    uint32_t offset,
 589         __in                    size_t size);
 590
 591         __checkReturn           efx_rc_t
 592 efx_mcdi_nvram_write(
 593         __in                    efx_nic_t *enp,
 594         __in                    uint32_t partn,
 595         __in                    uint32_t offset,
 596         __in_bcount(size)       caddr_t data,
 597         __in                    size_t size);
 598
 599 #define EFX_NVRAM_UPDATE_FLAGS_BACKGROUND       0x00000001
 600 #define EFX_NVRAM_UPDATE_FLAGS_POLL             0x00000002
 601
 602         __checkReturn           efx_rc_t
 603 efx_mcdi_nvram_update_finish(
 604         __in                    efx_nic_t *enp,
 605         __in                    uint32_t partn,
 606         __in                    boolean_t reboot,
 607         __in                    uint32_t flags,
 608         __out_opt               uint32_t *verify_resultp);
 609
 610 #if EFSYS_OPT_DIAG
 611
 612         __checkReturn           efx_rc_t
 613 efx_mcdi_nvram_test(
 614         __in                    efx_nic_t *enp,
 615         __in                    uint32_t partn);
 616
 617 #endif  /* EFSYS_OPT_DIAG */
 618
 619 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 620
 621 #if EFSYS_OPT_LICENSING
 622
 623 typedef struct efx_lic_ops_s {
 624         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 625         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 626         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 627         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 628                                       size_t *, uint8_t *);
 629         efx_rc_t        (*elo_find_start)
 630                                 (efx_nic_t *, caddr_t, size_t, uint32_t *);
 631         efx_rc_t        (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
 632                                 uint32_t, uint32_t *);
 633         boolean_t       (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
 634                                 uint32_t, uint32_t *, uint32_t *);
 635         boolean_t       (*elo_validate_key)(efx_nic_t *,
 636                                 caddr_t, uint32_t);
 637         efx_rc_t        (*elo_read_key)(efx_nic_t *,
 638                                 caddr_t, size_t, uint32_t, uint32_t,
 639                                 caddr_t, size_t, uint32_t *);
 640         efx_rc_t        (*elo_write_key)(efx_nic_t *,
 641                                 caddr_t, size_t, uint32_t,
 642                                 caddr_t, uint32_t, uint32_t *);
 643         efx_rc_t        (*elo_delete_key)(efx_nic_t *,
 644                                 caddr_t, size_t, uint32_t,
 645                                 uint32_t, uint32_t, uint32_t *);
 646         efx_rc_t        (*elo_create_partition)(efx_nic_t *,
 647                                 caddr_t, size_t);
 648         efx_rc_t        (*elo_finish_partition)(efx_nic_t *,
 649                                 caddr_t, size_t);
 650 } efx_lic_ops_t;
 651
 652 #endif
 653
 654 #if EFSYS_OPT_EVB
 655
 656 struct efx_vswitch_s {
 657         efx_nic_t               *ev_enp;
 658         efx_vswitch_id_t        ev_vswitch_id;
 659         uint32_t                ev_num_vports;
 660         /*
 661          * Vport configuration array: index 0 to store PF configuration
 662          * and next ev_num_vports-1 entries hold VFs configuration.
 663          */
 664         efx_vport_config_t      *ev_evcp;
 665 };
 666
 667 typedef struct efx_evb_ops_s {
 668         efx_rc_t        (*eeo_init)(efx_nic_t *);
 669         void            (*eeo_fini)(efx_nic_t *);
 670         efx_rc_t        (*eeo_vswitch_alloc)(efx_nic_t *, efx_vswitch_id_t *);
 671         efx_rc_t        (*eeo_vswitch_free)(efx_nic_t *, efx_vswitch_id_t);
 672         efx_rc_t        (*eeo_vport_alloc)(efx_nic_t *, efx_vswitch_id_t,
 673                                                 efx_vport_type_t, uint16_t,
 674                                                 boolean_t, efx_vport_id_t *);
 675         efx_rc_t        (*eeo_vport_free)(efx_nic_t *, efx_vswitch_id_t,
 676                                                 efx_vport_id_t);
 677         efx_rc_t        (*eeo_vport_mac_addr_add)(efx_nic_t *, efx_vswitch_id_t,
 678                                                 efx_vport_id_t, uint8_t *);
 679         efx_rc_t        (*eeo_vport_mac_addr_del)(efx_nic_t *, efx_vswitch_id_t,
 680                                                 efx_vport_id_t, uint8_t *);
 681         efx_rc_t        (*eeo_vadaptor_alloc)(efx_nic_t *, efx_vswitch_id_t,
 682                                                 efx_vport_id_t);
 683         efx_rc_t        (*eeo_vadaptor_free)(efx_nic_t *, efx_vswitch_id_t,
 684                                                 efx_vport_id_t);
 685         efx_rc_t        (*eeo_vport_assign)(efx_nic_t *, efx_vswitch_id_t,
 686                                                 efx_vport_id_t, uint32_t);
 687 } efx_evb_ops_t;
 688
 689 extern __checkReturn    boolean_t
 690 efx_is_zero_eth_addr(
 691         __in_bcount(EFX_MAC_ADDR_LEN)   const uint8_t *addrp);
 692
 693 #endif /* EFSYS_OPT_EVB */
 694
 695 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
 696
 697 #define EFX_PROXY_CONFIGURE_MAGIC       0xAB2015EF
 698
 699
 700 typedef struct efx_proxy_ops_s {
 701         efx_rc_t        (*epo_init)(efx_nic_t *);
 702         void            (*epo_fini)(efx_nic_t *);
 703         efx_rc_t        (*epo_mc_config)(efx_nic_t *, efsys_mem_t *,
 704                                         efsys_mem_t *, efsys_mem_t *,
 705                                         uint32_t, uint32_t *, size_t);
 706         efx_rc_t        (*epo_disable)(efx_nic_t *);
 707         efx_rc_t        (*epo_privilege_modify)(efx_nic_t *, uint32_t, uint32_t,
 708                                         uint32_t, uint32_t, uint32_t);
 709 } efx_proxy_ops_t;
 710
 711 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
 712
 713 #define EFX_DRV_VER_MAX         20
 714
 715 typedef struct efx_drv_cfg_s {
 716         uint32_t                edc_min_vi_count;
 717         uint32_t                edc_max_vi_count;
 718
 719         uint32_t                edc_max_piobuf_count;
 720         uint32_t                edc_pio_alloc_size;
 721 } efx_drv_cfg_t;
 722
 723 struct efx_nic_s {
 724         uint32_t                en_magic;
 725         efx_family_t            en_family;
 726         uint32_t                en_features;
 727         efsys_identifier_t      *en_esip;
 728         efsys_lock_t            *en_eslp;
 729         efsys_bar_t             *en_esbp;
 730         unsigned int            en_mod_flags;
 731         unsigned int            en_reset_flags;
 732         efx_nic_cfg_t           en_nic_cfg;
 733         efx_drv_cfg_t           en_drv_cfg;
 734         efx_port_t              en_port;
 735         efx_mon_t               en_mon;
 736         efx_intr_t              en_intr;
 737         uint32_t                en_ev_qcount;
 738         uint32_t                en_rx_qcount;
 739         uint32_t                en_tx_qcount;
 740         const efx_nic_ops_t     *en_enop;
 741         const efx_ev_ops_t      *en_eevop;
 742         const efx_tx_ops_t      *en_etxop;
 743         const efx_rx_ops_t      *en_erxop;
 744         efx_fw_variant_t        efv;
 745         char                    en_drv_version[EFX_DRV_VER_MAX];
 746 #if EFSYS_OPT_FILTER
 747         efx_filter_t            en_filter;
 748         const efx_filter_ops_t  *en_efop;
 749 #endif  /* EFSYS_OPT_FILTER */
 750 #if EFSYS_OPT_TUNNEL
 751         efx_tunnel_cfg_t        en_tunnel_cfg;
 752         const efx_tunnel_ops_t  *en_etop;
 753 #endif /* EFSYS_OPT_TUNNEL */
 754 #if EFSYS_OPT_MCDI
 755         efx_mcdi_t              en_mcdi;
 756 #endif  /* EFSYS_OPT_MCDI */
 757 #if EFSYS_OPT_NVRAM
 758         uint32_t                en_nvram_partn_locked;
 759         const efx_nvram_ops_t   *en_envop;
 760 #endif  /* EFSYS_OPT_NVRAM */
 761 #if EFSYS_OPT_VPD
 762         const efx_vpd_ops_t     *en_evpdop;
 763 #endif  /* EFSYS_OPT_VPD */
 764 #if EFSYS_OPT_RX_SCALE
 765         efx_rx_hash_support_t           en_hash_support;
 766         efx_rx_scale_context_type_t     en_rss_context_type;
 767         uint32_t                        en_rss_context;
 768 #endif  /* EFSYS_OPT_RX_SCALE */
 769         uint32_t                en_vport_id;
 770 #if EFSYS_OPT_LICENSING
 771         const efx_lic_ops_t     *en_elop;
 772         boolean_t               en_licensing_supported;
 773 #endif
 774         union {
 775 #if EFSYS_OPT_SIENA
 776                 struct {
 777 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 778                         unsigned int            enu_partn_mask;
 779 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 780 #if EFSYS_OPT_VPD
 781                         caddr_t                 enu_svpd;
 782                         size_t                  enu_svpd_length;
 783 #endif  /* EFSYS_OPT_VPD */
 784                         int                     enu_unused;
 785                 } siena;
 786 #endif  /* EFSYS_OPT_SIENA */
 787                 int     enu_unused;
 788         } en_u;
 789 #if EFX_OPTS_EF10()
 790         union en_arch {
 791                 struct {
 792                         int                     ena_vi_base;
 793                         int                     ena_vi_count;
 794                         int                     ena_vi_shift;
 795 #if EFSYS_OPT_VPD
 796                         caddr_t                 ena_svpd;
 797                         size_t                  ena_svpd_length;
 798 #endif  /* EFSYS_OPT_VPD */
 799                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 800                         uint32_t                ena_piobuf_count;
 801                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 802                         uint32_t                ena_pio_write_vi_base;
 803                         /* Memory BAR mapping regions */
 804                         uint32_t                ena_uc_mem_map_offset;
 805                         size_t                  ena_uc_mem_map_size;
 806                         uint32_t                ena_wc_mem_map_offset;
 807                         size_t                  ena_wc_mem_map_size;
 808                 } ef10;
 809         } en_arch;
 810 #endif  /* EFX_OPTS_EF10() */
 811 #if EFSYS_OPT_EVB
 812         const efx_evb_ops_t     *en_eeop;
 813         struct efx_vswitch_s    *en_vswitchp;
 814 #endif  /* EFSYS_OPT_EVB */
 815 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
 816         const efx_proxy_ops_t   *en_epop;
 817 #endif  /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
 818 };
 819
 820 #define EFX_FAMILY_IS_EF10(_enp) \
 821         ((_enp)->en_family == EFX_FAMILY_MEDFORD2 || \
 822          (_enp)->en_family == EFX_FAMILY_MEDFORD || \
 823          (_enp)->en_family == EFX_FAMILY_HUNTINGTON)
 824
 825
 826 #define EFX_NIC_MAGIC   0x02121996
 827
 828 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 829     const efx_ev_callbacks_t *, void *);
 830
 831 typedef struct efx_evq_rxq_state_s {
 832         unsigned int                    eers_rx_read_ptr;
 833         unsigned int                    eers_rx_mask;
 834 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
 835         unsigned int                    eers_rx_stream_npackets;
 836         boolean_t                       eers_rx_packed_stream;
 837 #endif
 838 #if EFSYS_OPT_RX_PACKED_STREAM
 839         unsigned int                    eers_rx_packed_stream_credits;
 840 #endif
 841 } efx_evq_rxq_state_t;
 842
 843 struct efx_evq_s {
 844         uint32_t                        ee_magic;
 845         uint32_t                        ee_flags;
 846         efx_nic_t                       *ee_enp;
 847         unsigned int                    ee_index;
 848         unsigned int                    ee_mask;
 849         efsys_mem_t                     *ee_esmp;
 850 #if EFSYS_OPT_QSTATS
 851         uint32_t                        ee_stat[EV_NQSTATS];
 852 #endif  /* EFSYS_OPT_QSTATS */
 853
 854         efx_ev_handler_t                ee_rx;
 855         efx_ev_handler_t                ee_tx;
 856         efx_ev_handler_t                ee_driver;
 857         efx_ev_handler_t                ee_global;
 858         efx_ev_handler_t                ee_drv_gen;
 859 #if EFSYS_OPT_MCDI
 860         efx_ev_handler_t                ee_mcdi;
 861 #endif  /* EFSYS_OPT_MCDI */
 862
 863         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 864 };
 865
 866 #define EFX_EVQ_MAGIC   0x08081997
 867
 868 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 869
 870 #if EFSYS_OPT_QSTATS
 871 #define EFX_EV_QSTAT_INCR(_eep, _stat)                                  \
 872         do {                                                            \
 873                 (_eep)->ee_stat[_stat]++;                               \
 874         _NOTE(CONSTANTCONDITION)                                        \
 875         } while (B_FALSE)
 876 #else
 877 #define EFX_EV_QSTAT_INCR(_eep, _stat)
 878 #endif
 879
 880 struct efx_rxq_s {
 881         uint32_t                        er_magic;
 882         efx_nic_t                       *er_enp;
 883         efx_evq_t                       *er_eep;
 884         unsigned int                    er_index;
 885         unsigned int                    er_label;
 886         unsigned int                    er_mask;
 887         size_t                          er_buf_size;
 888         efsys_mem_t                     *er_esmp;
 889         efx_evq_rxq_state_t             *er_ev_qstate;
 890 };
 891
 892 #define EFX_RXQ_MAGIC   0x15022005
 893
 894 struct efx_txq_s {
 895         uint32_t                        et_magic;
 896         efx_nic_t                       *et_enp;
 897         unsigned int                    et_index;
 898         unsigned int                    et_mask;
 899         efsys_mem_t                     *et_esmp;
 900 #if EFSYS_OPT_HUNTINGTON
 901         uint32_t                        et_pio_bufnum;
 902         uint32_t                        et_pio_blknum;
 903         uint32_t                        et_pio_write_offset;
 904         uint32_t                        et_pio_offset;
 905         size_t                          et_pio_size;
 906 #endif
 907 #if EFSYS_OPT_QSTATS
 908         uint32_t                        et_stat[TX_NQSTATS];
 909 #endif  /* EFSYS_OPT_QSTATS */
 910 };
 911
 912 #define EFX_TXQ_MAGIC   0x05092005
 913
 914 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 915         do {                                                            \
 916                 (_dst)[0] = (_src)[0];                                  \
 917                 (_dst)[1] = (_src)[1];                                  \
 918                 (_dst)[2] = (_src)[2];                                  \
 919                 (_dst)[3] = (_src)[3];                                  \
 920                 (_dst)[4] = (_src)[4];                                  \
 921                 (_dst)[5] = (_src)[5];                                  \
 922         _NOTE(CONSTANTCONDITION)                                        \
 923         } while (B_FALSE)
 924
 925 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 926         do {                                                            \
 927                 uint16_t *_d = (uint16_t *)(_dst);                      \
 928                 _d[0] = 0xffff;                                         \
 929                 _d[1] = 0xffff;                                         \
 930                 _d[2] = 0xffff;                                         \
 931         _NOTE(CONSTANTCONDITION)                                        \
 932         } while (B_FALSE)
 933
 934 #if EFSYS_OPT_CHECK_REG
 935 #define EFX_CHECK_REG(_enp, _reg)                                       \
 936         do {                                                            \
 937                 const char *name = #_reg;                               \
 938                 char min = name[4];                                     \
 939                 char max = name[5];                                     \
 940                 char rev;                                               \
 941                                                                         \
 942                 switch ((_enp)->en_family) {                            \
 943                 case EFX_FAMILY_SIENA:                                  \
 944                         rev = 'C';                                      \
 945                         break;                                          \
 946                                                                         \
 947                 case EFX_FAMILY_HUNTINGTON:                             \
 948                         rev = 'D';                                      \
 949                         break;                                          \
 950                                                                         \
 951                 case EFX_FAMILY_MEDFORD:                                \
 952                         rev = 'E';                                      \
 953                         break;                                          \
 954                                                                         \
 955                 case EFX_FAMILY_MEDFORD2:                               \
 956                         rev = 'F';                                      \
 957                         break;                                          \
 958                                                                         \
 959                 default:                                                \
 960                         rev = '?';                                      \
 961                         break;                                          \
 962                 }                                                       \
 963                                                                         \
 964                 EFSYS_ASSERT3S(rev, >=, min);                           \
 965                 EFSYS_ASSERT3S(rev, <=, max);                           \
 966                                                                         \
 967         _NOTE(CONSTANTCONDITION)                                        \
 968         } while (B_FALSE)
 969 #else
 970 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 971         _NOTE(CONSTANTCONDITION)                                        \
 972         } while (B_FALSE)
 973 #endif
 974
 975 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 976         do {                                                            \
 977                 EFX_CHECK_REG((_enp), (_reg));                          \
 978                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 979                     (_edp), (_lock));                                   \
 980                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 981                     uint32_t, _reg ## _OFST,                            \
 982                     uint32_t, (_edp)->ed_u32[0]);                       \
 983         _NOTE(CONSTANTCONDITION)                                        \
 984         } while (B_FALSE)
 985
 986 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 987         do {                                                            \
 988                 EFX_CHECK_REG((_enp), (_reg));                          \
 989                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 990                     uint32_t, _reg ## _OFST,                            \
 991                     uint32_t, (_edp)->ed_u32[0]);                       \
 992                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 993                     (_edp), (_lock));                                   \
 994         _NOTE(CONSTANTCONDITION)                                        \
 995         } while (B_FALSE)
 996
 997 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 998         do {                                                            \
 999                 EFX_CHECK_REG((_enp), (_reg));                          \
1000                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
1001                     (_eqp));                                            \
1002                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
1003                     uint32_t, _reg ## _OFST,                            \
1004                     uint32_t, (_eqp)->eq_u32[1],                        \
1005                     uint32_t, (_eqp)->eq_u32[0]);                       \
1006         _NOTE(CONSTANTCONDITION)                                        \
1007         } while (B_FALSE)
1008
1009 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
1010         do {                                                            \
1011                 EFX_CHECK_REG((_enp), (_reg));                          \
1012                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
1013                     uint32_t, _reg ## _OFST,                            \
1014                     uint32_t, (_eqp)->eq_u32[1],                        \
1015                     uint32_t, (_eqp)->eq_u32[0]);                       \
1016                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
1017                     (_eqp));                                            \
1018         _NOTE(CONSTANTCONDITION)                                        \
1019         } while (B_FALSE)
1020
1021 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
1022         do {                                                            \
1023                 EFX_CHECK_REG((_enp), (_reg));                          \
1024                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
1025                     (_eop), B_TRUE);                                    \
1026                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
1027                     uint32_t, _reg ## _OFST,                            \
1028                     uint32_t, (_eop)->eo_u32[3],                        \
1029                     uint32_t, (_eop)->eo_u32[2],                        \
1030                     uint32_t, (_eop)->eo_u32[1],                        \
1031                     uint32_t, (_eop)->eo_u32[0]);                       \
1032         _NOTE(CONSTANTCONDITION)                                        \
1033         } while (B_FALSE)
1034
1035 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
1036         do {                                                            \
1037                 EFX_CHECK_REG((_enp), (_reg));                          \
1038                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
1039                     uint32_t, _reg ## _OFST,                            \
1040                     uint32_t, (_eop)->eo_u32[3],                        \
1041                     uint32_t, (_eop)->eo_u32[2],                        \
1042                     uint32_t, (_eop)->eo_u32[1],                        \
1043                     uint32_t, (_eop)->eo_u32[0]);                       \
1044                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
1045                     (_eop), B_TRUE);                                    \
1046         _NOTE(CONSTANTCONDITION)                                        \
1047         } while (B_FALSE)
1048
1049 /*
1050  * Accessors for memory BAR non-VI tables.
1051  *
1052  * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers,
1053  * to ensure the correct runtime VI window size is used on Medford2.
1054  *
1055  * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers.
1056  */
1057
1058 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
1059         do {                                                            \
1060                 EFX_CHECK_REG((_enp), (_reg));                          \
1061                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
1062                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1063                     (_edp), (_lock));                                   \
1064                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
1065                     uint32_t, (_index),                                 \
1066                     uint32_t, _reg ## _OFST,                            \
1067                     uint32_t, (_edp)->ed_u32[0]);                       \
1068         _NOTE(CONSTANTCONDITION)                                        \
1069         } while (B_FALSE)
1070
1071 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
1072         do {                                                            \
1073                 EFX_CHECK_REG((_enp), (_reg));                          \
1074                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
1075                     uint32_t, (_index),                                 \
1076                     uint32_t, _reg ## _OFST,                            \
1077                     uint32_t, (_edp)->ed_u32[0]);                       \
1078                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1079                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1080                     (_edp), (_lock));                                   \
1081         _NOTE(CONSTANTCONDITION)                                        \
1082         } while (B_FALSE)
1083
1084 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
1085         do {                                                            \
1086                 EFX_CHECK_REG((_enp), (_reg));                          \
1087                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
1088                     uint32_t, (_index),                                 \
1089                     uint32_t, _reg ## _OFST,                            \
1090                     uint32_t, (_edp)->ed_u32[0]);                       \
1091                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1092                     (_reg ## _OFST +                                    \
1093                     (3 * sizeof (efx_dword_t)) +                        \
1094                     ((_index) * _reg ## _STEP)),                        \
1095                     (_edp), (_lock));                                   \
1096         _NOTE(CONSTANTCONDITION)                                        \
1097         } while (B_FALSE)
1098
1099 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
1100         do {                                                            \
1101                 EFX_CHECK_REG((_enp), (_reg));                          \
1102                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
1103                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1104                     (_eqp));                                            \
1105                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
1106                     uint32_t, (_index),                                 \
1107                     uint32_t, _reg ## _OFST,                            \
1108                     uint32_t, (_eqp)->eq_u32[1],                        \
1109                     uint32_t, (_eqp)->eq_u32[0]);                       \
1110         _NOTE(CONSTANTCONDITION)                                        \
1111         } while (B_FALSE)
1112
1113 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
1114         do {                                                            \
1115                 EFX_CHECK_REG((_enp), (_reg));                          \
1116                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
1117                     uint32_t, (_index),                                 \
1118                     uint32_t, _reg ## _OFST,                            \
1119                     uint32_t, (_eqp)->eq_u32[1],                        \
1120                     uint32_t, (_eqp)->eq_u32[0]);                       \
1121                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
1122                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1123                     (_eqp));                                            \
1124         _NOTE(CONSTANTCONDITION)                                        \
1125         } while (B_FALSE)
1126
1127 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
1128         do {                                                            \
1129                 EFX_CHECK_REG((_enp), (_reg));                          \
1130                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
1131                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1132                     (_eop), (_lock));                                   \
1133                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
1134                     uint32_t, (_index),                                 \
1135                     uint32_t, _reg ## _OFST,                            \
1136                     uint32_t, (_eop)->eo_u32[3],                        \
1137                     uint32_t, (_eop)->eo_u32[2],                        \
1138                     uint32_t, (_eop)->eo_u32[1],                        \
1139                     uint32_t, (_eop)->eo_u32[0]);                       \
1140         _NOTE(CONSTANTCONDITION)                                        \
1141         } while (B_FALSE)
1142
1143 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
1144         do {                                                            \
1145                 EFX_CHECK_REG((_enp), (_reg));                          \
1146                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
1147                     uint32_t, (_index),                                 \
1148                     uint32_t, _reg ## _OFST,                            \
1149                     uint32_t, (_eop)->eo_u32[3],                        \
1150                     uint32_t, (_eop)->eo_u32[2],                        \
1151                     uint32_t, (_eop)->eo_u32[1],                        \
1152                     uint32_t, (_eop)->eo_u32[0]);                       \
1153                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
1154                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1155                     (_eop), (_lock));                                   \
1156         _NOTE(CONSTANTCONDITION)                                        \
1157         } while (B_FALSE)
1158
1159 /*
1160  * Accessors for memory BAR per-VI registers.
1161  *
1162  * The VI window size is 8KB for Medford and all earlier controllers.
1163  * For Medford2, the VI window size can be 8KB, 16KB or 64KB.
1164  */
1165
1166 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock)               \
1167         do {                                                            \
1168                 EFX_CHECK_REG((_enp), (_reg));                          \
1169                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
1170                     ((_reg ## _OFST) +                                  \
1171                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1172                     (_edp), (_lock));                                   \
1173                 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg,     \
1174                     uint32_t, (_index),                                 \
1175                     uint32_t, _reg ## _OFST,                            \
1176                     uint32_t, (_edp)->ed_u32[0]);                       \
1177         _NOTE(CONSTANTCONDITION)                                        \
1178         } while (B_FALSE)
1179
1180 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock)              \
1181         do {                                                            \
1182                 EFX_CHECK_REG((_enp), (_reg));                          \
1183                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1184                     uint32_t, (_index),                                 \
1185                     uint32_t, _reg ## _OFST,                            \
1186                     uint32_t, (_edp)->ed_u32[0]);                       \
1187                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1188                     ((_reg ## _OFST) +                                  \
1189                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1190                     (_edp), (_lock));                                   \
1191         _NOTE(CONSTANTCONDITION)                                        \
1192         } while (B_FALSE)
1193
1194 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock)             \
1195         do {                                                            \
1196                 EFX_CHECK_REG((_enp), (_reg));                          \
1197                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1198                     uint32_t, (_index),                                 \
1199                     uint32_t, _reg ## _OFST,                            \
1200                     uint32_t, (_edp)->ed_u32[0]);                       \
1201                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1202                     ((_reg ## _OFST) +                                  \
1203                     (2 * sizeof (efx_dword_t)) +                        \
1204                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1205                     (_edp), (_lock));                                   \
1206         _NOTE(CONSTANTCONDITION)                                        \
1207         } while (B_FALSE)
1208
1209 /*
1210  * Allow drivers to perform optimised 128-bit VI doorbell writes.
1211  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1212  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1213  * the need for locking in the host, and are the only ones known to be safe to
1214  * use 128-bites write with.
1215  */
1216 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop)            \
1217         do {                                                            \
1218                 EFX_CHECK_REG((_enp), (_reg));                          \
1219                 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo,                \
1220                     const char *, #_reg,                                \
1221                     uint32_t, (_index),                                 \
1222                     uint32_t, _reg ## _OFST,                            \
1223                     uint32_t, (_eop)->eo_u32[3],                        \
1224                     uint32_t, (_eop)->eo_u32[2],                        \
1225                     uint32_t, (_eop)->eo_u32[1],                        \
1226                     uint32_t, (_eop)->eo_u32[0]);                       \
1227                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1228                     (_reg ## _OFST +                                    \
1229                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1230                     (_eop));                                            \
1231         _NOTE(CONSTANTCONDITION)                                        \
1232         } while (B_FALSE)
1233
1234 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1235         do {                                                            \
1236                 unsigned int _new = (_wptr);                            \
1237                 unsigned int _old = (_owptr);                           \
1238                                                                         \
1239                 if ((_new) >= (_old))                                   \
1240                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1241                             (_old) * sizeof (efx_desc_t),               \
1242                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1243                 else                                                    \
1244                         /*                                              \
1245                          * It is cheaper to sync entire map than sync   \
1246                          * two parts especially when offset/size are    \
1247                          * ignored and entire map is synced in any case.\
1248                          */                                             \
1249                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1250                             0,                                          \
1251                             (_entries) * sizeof (efx_desc_t));          \
1252         _NOTE(CONSTANTCONDITION)                                        \
1253         } while (B_FALSE)
1254
1255 extern  __checkReturn   efx_rc_t
1256 efx_mac_select(
1257         __in            efx_nic_t *enp);
1258
1259 extern  void
1260 efx_mac_multicast_hash_compute(
1261         __in_ecount(6*count)            uint8_t const *addrs,
1262         __in                            int count,
1263         __out                           efx_oword_t *hash_low,
1264         __out                           efx_oword_t *hash_high);
1265
1266 extern  __checkReturn   efx_rc_t
1267 efx_phy_probe(
1268         __in            efx_nic_t *enp);
1269
1270 extern                  void
1271 efx_phy_unprobe(
1272         __in            efx_nic_t *enp);
1273
1274 #if EFSYS_OPT_VPD
1275
1276 /* VPD utility functions */
1277
1278 extern  __checkReturn           efx_rc_t
1279 efx_vpd_hunk_length(
1280         __in_bcount(size)       caddr_t data,
1281         __in                    size_t size,
1282         __out                   size_t *lengthp);
1283
1284 extern  __checkReturn           efx_rc_t
1285 efx_vpd_hunk_verify(
1286         __in_bcount(size)       caddr_t data,
1287         __in                    size_t size,
1288         __out_opt               boolean_t *cksummedp);
1289
1290 extern  __checkReturn           efx_rc_t
1291 efx_vpd_hunk_reinit(
1292         __in_bcount(size)       caddr_t data,
1293         __in                    size_t size,
1294         __in                    boolean_t wantpid);
1295
1296 extern  __checkReturn           efx_rc_t
1297 efx_vpd_hunk_get(
1298         __in_bcount(size)       caddr_t data,
1299         __in                    size_t size,
1300         __in                    efx_vpd_tag_t tag,
1301         __in                    efx_vpd_keyword_t keyword,
1302         __out                   unsigned int *payloadp,
1303         __out                   uint8_t *paylenp);
1304
1305 extern  __checkReturn                   efx_rc_t
1306 efx_vpd_hunk_next(
1307         __in_bcount(size)               caddr_t data,
1308         __in                            size_t size,
1309         __out                           efx_vpd_tag_t *tagp,
1310         __out                           efx_vpd_keyword_t *keyword,
1311         __out_opt                       unsigned int *payloadp,
1312         __out_opt                       uint8_t *paylenp,
1313         __inout                         unsigned int *contp);
1314
1315 extern  __checkReturn           efx_rc_t
1316 efx_vpd_hunk_set(
1317         __in_bcount(size)       caddr_t data,
1318         __in                    size_t size,
1319         __in                    efx_vpd_value_t *evvp);
1320
1321 #endif  /* EFSYS_OPT_VPD */
1322
1323 #if EFSYS_OPT_MCDI
1324
1325 extern  __checkReturn           efx_rc_t
1326 efx_mcdi_set_workaround(
1327         __in                    efx_nic_t *enp,
1328         __in                    uint32_t type,
1329         __in                    boolean_t enabled,
1330         __out_opt               uint32_t *flagsp);
1331
1332 extern  __checkReturn           efx_rc_t
1333 efx_mcdi_get_workarounds(
1334         __in                    efx_nic_t *enp,
1335         __out_opt               uint32_t *implementedp,
1336         __out_opt               uint32_t *enabledp);
1337
1338 #endif /* EFSYS_OPT_MCDI */
1339
1340 #if EFSYS_OPT_MAC_STATS
1341
1342 /*
1343  * Closed range of stats (i.e. the first and the last are included).
1344  * The last must be greater or equal (if the range is one item only) to
1345  * the first.
1346  */
1347 struct efx_mac_stats_range {
1348         efx_mac_stat_t          first;
1349         efx_mac_stat_t          last;
1350 };
1351
1352 extern                                  efx_rc_t
1353 efx_mac_stats_mask_add_ranges(
1354         __inout_bcount(mask_size)       uint32_t *maskp,
1355         __in                            size_t mask_size,
1356         __in_ecount(rng_count)          const struct efx_mac_stats_range *rngp,
1357         __in                            unsigned int rng_count);
1358
1359 #endif  /* EFSYS_OPT_MAC_STATS */
1360
1361 #ifdef  __cplusplus
1362 }
1363 #endif
1364
1365 #endif  /* _SYS_EFX_IMPL_H */