drivers/net/sfc/base/efx_impl.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2007-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  */
   6
   7 #ifndef _SYS_EFX_IMPL_H
   8 #define _SYS_EFX_IMPL_H
   9
  10 #include "efx.h"
  11 #include "efx_regs.h"
  12 #include "efx_regs_ef10.h"
  13 #if EFSYS_OPT_MCDI
  14 #include "efx_mcdi.h"
  15 #endif  /* EFSYS_OPT_MCDI */
  16
  17 /* FIXME: Add definition for driver generated software events */
  18 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  19 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  20 #endif
  21
  22
  23 #if EFSYS_OPT_SIENA
  24 #include "siena_impl.h"
  25 #endif  /* EFSYS_OPT_SIENA */
  26
  27 #if EFSYS_OPT_HUNTINGTON
  28 #include "hunt_impl.h"
  29 #endif  /* EFSYS_OPT_HUNTINGTON */
  30
  31 #if EFSYS_OPT_MEDFORD
  32 #include "medford_impl.h"
  33 #endif  /* EFSYS_OPT_MEDFORD */
  34
  35 #if EFSYS_OPT_MEDFORD2
  36 #include "medford2_impl.h"
  37 #endif  /* EFSYS_OPT_MEDFORD2 */
  38
  39 #if EFX_OPTS_EF10()
  40 #include "ef10_impl.h"
  41 #endif  /* EFX_OPTS_EF10() */
  42
  43 #ifdef  __cplusplus
  44 extern "C" {
  45 #endif
  46
  47 #define EFX_MOD_MCDI            0x00000001
  48 #define EFX_MOD_PROBE           0x00000002
  49 #define EFX_MOD_NVRAM           0x00000004
  50 #define EFX_MOD_VPD             0x00000008
  51 #define EFX_MOD_NIC             0x00000010
  52 #define EFX_MOD_INTR            0x00000020
  53 #define EFX_MOD_EV              0x00000040
  54 #define EFX_MOD_RX              0x00000080
  55 #define EFX_MOD_TX              0x00000100
  56 #define EFX_MOD_PORT            0x00000200
  57 #define EFX_MOD_MON             0x00000400
  58 #define EFX_MOD_FILTER          0x00001000
  59 #define EFX_MOD_LIC             0x00002000
  60 #define EFX_MOD_TUNNEL          0x00004000
  61 #define EFX_MOD_EVB             0x00008000
  62 #define EFX_MOD_PROXY           0x00010000
  63
  64 #define EFX_RESET_PHY           0x00000001
  65 #define EFX_RESET_RXQ_ERR       0x00000002
  66 #define EFX_RESET_TXQ_ERR       0x00000004
  67 #define EFX_RESET_HW_UNAVAIL    0x00000008
  68
  69 typedef enum efx_mac_type_e {
  70         EFX_MAC_INVALID = 0,
  71         EFX_MAC_SIENA,
  72         EFX_MAC_HUNTINGTON,
  73         EFX_MAC_MEDFORD,
  74         EFX_MAC_MEDFORD2,
  75         EFX_MAC_NTYPES
  76 } efx_mac_type_t;
  77
  78 typedef struct efx_ev_ops_s {
  79         efx_rc_t        (*eevo_init)(efx_nic_t *);
  80         void            (*eevo_fini)(efx_nic_t *);
  81         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  82                                           efsys_mem_t *, size_t, uint32_t,
  83                                           uint32_t, uint32_t, efx_evq_t *);
  84         void            (*eevo_qdestroy)(efx_evq_t *);
  85         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  86         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  87         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
  88 #if EFSYS_OPT_QSTATS
  89         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
  90 #endif
  91 } efx_ev_ops_t;
  92
  93 typedef struct efx_tx_ops_s {
  94         efx_rc_t        (*etxo_init)(efx_nic_t *);
  95         void            (*etxo_fini)(efx_nic_t *);
  96         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
  97                                         unsigned int, unsigned int,
  98                                         efsys_mem_t *, size_t,
  99                                         uint32_t, uint16_t,
 100                                         efx_evq_t *, efx_txq_t *,
 101                                         unsigned int *);
 102         void            (*etxo_qdestroy)(efx_txq_t *);
 103         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 104                                       unsigned int, unsigned int,
 105                                       unsigned int *);
 106         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 107         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 108         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 109         void            (*etxo_qenable)(efx_txq_t *);
 110         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 111         void            (*etxo_qpio_disable)(efx_txq_t *);
 112         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 113                                            size_t);
 114         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 115                                            unsigned int *);
 116         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 117                                       unsigned int, unsigned int,
 118                                       unsigned int *);
 119         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 120                                                 size_t, boolean_t,
 121                                                 efx_desc_t *);
 122         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 123                                                 uint32_t, uint8_t,
 124                                                 efx_desc_t *);
 125         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 126                                                 uint16_t, uint32_t, uint16_t,
 127                                                 efx_desc_t *, int);
 128         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 129                                                 efx_desc_t *);
 130         void            (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t,
 131                                                 efx_desc_t *);
 132 #if EFSYS_OPT_QSTATS
 133         void            (*etxo_qstats_update)(efx_txq_t *,
 134                                               efsys_stat_t *);
 135 #endif
 136 } efx_tx_ops_t;
 137
 138 typedef union efx_rxq_type_data_u {
 139         struct {
 140                 size_t          ed_buf_size;
 141         } ertd_default;
 142 #if EFSYS_OPT_RX_PACKED_STREAM
 143         struct {
 144                 uint32_t        eps_buf_size;
 145         } ertd_packed_stream;
 146 #endif
 147 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
 148         struct {
 149                 uint32_t        eessb_bufs_per_desc;
 150                 uint32_t        eessb_max_dma_len;
 151                 uint32_t        eessb_buf_stride;
 152                 uint32_t        eessb_hol_block_timeout;
 153         } ertd_es_super_buffer;
 154 #endif
 155 } efx_rxq_type_data_t;
 156
 157 typedef struct efx_rx_ops_s {
 158         efx_rc_t        (*erxo_init)(efx_nic_t *);
 159         void            (*erxo_fini)(efx_nic_t *);
 160 #if EFSYS_OPT_RX_SCATTER
 161         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 162 #endif
 163 #if EFSYS_OPT_RX_SCALE
 164         efx_rc_t        (*erxo_scale_context_alloc)(efx_nic_t *,
 165                                                     efx_rx_scale_context_type_t,
 166                                                     uint32_t, uint32_t *);
 167         efx_rc_t        (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
 168         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
 169                                                efx_rx_hash_alg_t,
 170                                                efx_rx_hash_type_t, boolean_t);
 171         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
 172                                               uint8_t *, size_t);
 173         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
 174                                               unsigned int *, size_t);
 175         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 176                                             uint8_t *);
 177 #endif /* EFSYS_OPT_RX_SCALE */
 178         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 179                                               uint16_t *);
 180         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 181                                       unsigned int, unsigned int,
 182                                       unsigned int);
 183         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 184 #if EFSYS_OPT_RX_PACKED_STREAM
 185         void            (*erxo_qpush_ps_credits)(efx_rxq_t *);
 186         uint8_t *       (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
 187                                                 uint32_t, uint32_t,
 188                                                 uint16_t *, uint32_t *, uint32_t *);
 189 #endif
 190         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 191         void            (*erxo_qenable)(efx_rxq_t *);
 192         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 193                                         unsigned int, efx_rxq_type_t,
 194                                         const efx_rxq_type_data_t *,
 195                                         efsys_mem_t *, size_t, uint32_t,
 196                                         unsigned int,
 197                                         efx_evq_t *, efx_rxq_t *);
 198         void            (*erxo_qdestroy)(efx_rxq_t *);
 199 } efx_rx_ops_t;
 200
 201 typedef struct efx_mac_ops_s {
 202         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 203         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 204         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 205         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 206         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 207         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 208         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 209         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 210                                                       efx_rxq_t *, boolean_t);
 211         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 212 #if EFSYS_OPT_LOOPBACK
 213         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 214                                             efx_loopback_type_t);
 215 #endif  /* EFSYS_OPT_LOOPBACK */
 216 #if EFSYS_OPT_MAC_STATS
 217         efx_rc_t        (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
 218         efx_rc_t        (*emo_stats_clear)(efx_nic_t *);
 219         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 220         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 221                                               uint16_t, boolean_t);
 222         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 223                                             efsys_stat_t *, uint32_t *);
 224 #endif  /* EFSYS_OPT_MAC_STATS */
 225 } efx_mac_ops_t;
 226
 227 typedef struct efx_phy_ops_s {
 228         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 229         efx_rc_t        (*epo_reset)(efx_nic_t *);
 230         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 231         efx_rc_t        (*epo_verify)(efx_nic_t *);
 232         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 233         efx_rc_t        (*epo_link_state_get)(efx_nic_t *, efx_phy_link_state_t *);
 234 #if EFSYS_OPT_PHY_STATS
 235         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 236                                             uint32_t *);
 237 #endif  /* EFSYS_OPT_PHY_STATS */
 238 #if EFSYS_OPT_BIST
 239         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 240         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 241         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 242                                          efx_bist_result_t *, uint32_t *,
 243                                          unsigned long *, size_t);
 244         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 245 #endif  /* EFSYS_OPT_BIST */
 246 } efx_phy_ops_t;
 247
 248 #if EFSYS_OPT_FILTER
 249
 250 /*
 251  * Policy for replacing existing filter when inserting a new one.
 252  * Note that all policies allow for storing the new lower priority
 253  * filters as overridden by existing higher priority ones. It is needed
 254  * to restore the lower priority filters on higher priority ones removal.
 255  */
 256 typedef enum efx_filter_replacement_policy_e {
 257         /* Cannot replace existing filter */
 258         EFX_FILTER_REPLACEMENT_NEVER,
 259         /* Higher priority filters can replace lower priotiry ones */
 260         EFX_FILTER_REPLACEMENT_HIGHER_PRIORITY,
 261         /*
 262          * Higher priority filters can replace lower priority ones and
 263          * equal priority filters can replace each other.
 264          */
 265         EFX_FILTER_REPLACEMENT_HIGHER_OR_EQUAL_PRIORITY,
 266 } efx_filter_replacement_policy_t;
 267
 268 typedef struct efx_filter_ops_s {
 269         efx_rc_t        (*efo_init)(efx_nic_t *);
 270         void            (*efo_fini)(efx_nic_t *);
 271         efx_rc_t        (*efo_restore)(efx_nic_t *);
 272         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 273                                    efx_filter_replacement_policy_t policy);
 274         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 275         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *,
 276                                    size_t, size_t *);
 277         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 278                                    boolean_t, boolean_t, boolean_t,
 279                                    uint8_t const *, uint32_t);
 280 } efx_filter_ops_t;
 281
 282 extern  __checkReturn   efx_rc_t
 283 efx_filter_reconfigure(
 284         __in                            efx_nic_t *enp,
 285         __in_ecount(6)                  uint8_t const *mac_addr,
 286         __in                            boolean_t all_unicst,
 287         __in                            boolean_t mulcst,
 288         __in                            boolean_t all_mulcst,
 289         __in                            boolean_t brdcst,
 290         __in_ecount(6*count)            uint8_t const *addrs,
 291         __in                            uint32_t count);
 292
 293 #endif /* EFSYS_OPT_FILTER */
 294
 295 #if EFSYS_OPT_TUNNEL
 296 typedef struct efx_tunnel_ops_s {
 297         boolean_t       (*eto_udp_encap_supported)(efx_nic_t *);
 298         efx_rc_t        (*eto_reconfigure)(efx_nic_t *);
 299 } efx_tunnel_ops_t;
 300 #endif /* EFSYS_OPT_TUNNEL */
 301
 302 typedef struct efx_port_s {
 303         efx_mac_type_t          ep_mac_type;
 304         uint32_t                ep_phy_type;
 305         uint8_t                 ep_port;
 306         uint32_t                ep_mac_pdu;
 307         uint8_t                 ep_mac_addr[6];
 308         efx_link_mode_t         ep_link_mode;
 309         boolean_t               ep_all_unicst;
 310         boolean_t               ep_mulcst;
 311         boolean_t               ep_all_mulcst;
 312         boolean_t               ep_brdcst;
 313         unsigned int            ep_fcntl;
 314         boolean_t               ep_fcntl_autoneg;
 315         efx_oword_t             ep_multicst_hash[2];
 316         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 317                                                     EFX_MAC_MULTICAST_LIST_MAX];
 318         uint32_t                ep_mulcst_addr_count;
 319 #if EFSYS_OPT_LOOPBACK
 320         efx_loopback_type_t     ep_loopback_type;
 321         efx_link_mode_t         ep_loopback_link_mode;
 322 #endif  /* EFSYS_OPT_LOOPBACK */
 323 #if EFSYS_OPT_PHY_FLAGS
 324         uint32_t                ep_phy_flags;
 325 #endif  /* EFSYS_OPT_PHY_FLAGS */
 326 #if EFSYS_OPT_PHY_LED_CONTROL
 327         efx_phy_led_mode_t      ep_phy_led_mode;
 328 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 329         efx_phy_media_type_t    ep_fixed_port_type;
 330         efx_phy_media_type_t    ep_module_type;
 331         uint32_t                ep_adv_cap_mask;
 332         uint32_t                ep_lp_cap_mask;
 333         uint32_t                ep_default_adv_cap_mask;
 334         uint32_t                ep_phy_cap_mask;
 335         boolean_t               ep_mac_drain;
 336 #if EFSYS_OPT_BIST
 337         efx_bist_type_t         ep_current_bist;
 338 #endif
 339         const efx_mac_ops_t     *ep_emop;
 340         const efx_phy_ops_t     *ep_epop;
 341 } efx_port_t;
 342
 343 typedef struct efx_mon_ops_s {
 344 #if EFSYS_OPT_MON_STATS
 345         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 346                                             efx_mon_stat_value_t *);
 347         efx_rc_t        (*emo_limits_update)(efx_nic_t *,
 348                                              efx_mon_stat_limits_t *);
 349 #endif  /* EFSYS_OPT_MON_STATS */
 350 } efx_mon_ops_t;
 351
 352 typedef struct efx_mon_s {
 353         efx_mon_type_t          em_type;
 354         const efx_mon_ops_t     *em_emop;
 355 } efx_mon_t;
 356
 357 typedef struct efx_intr_ops_s {
 358         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 359         void            (*eio_enable)(efx_nic_t *);
 360         void            (*eio_disable)(efx_nic_t *);
 361         void            (*eio_disable_unlocked)(efx_nic_t *);
 362         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 363         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 364         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 365                                  boolean_t *);
 366         void            (*eio_fatal)(efx_nic_t *);
 367         void            (*eio_fini)(efx_nic_t *);
 368 } efx_intr_ops_t;
 369
 370 typedef struct efx_intr_s {
 371         const efx_intr_ops_t    *ei_eiop;
 372         efsys_mem_t             *ei_esmp;
 373         efx_intr_type_t         ei_type;
 374         unsigned int            ei_level;
 375 } efx_intr_t;
 376
 377 typedef struct efx_nic_ops_s {
 378         efx_rc_t        (*eno_probe)(efx_nic_t *);
 379         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 380         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 381         efx_rc_t        (*eno_reset)(efx_nic_t *);
 382         efx_rc_t        (*eno_init)(efx_nic_t *);
 383         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 384         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 385                                         uint32_t *, size_t *);
 386         boolean_t       (*eno_hw_unavailable)(efx_nic_t *);
 387         void            (*eno_set_hw_unavailable)(efx_nic_t *);
 388 #if EFSYS_OPT_DIAG
 389         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 390 #endif  /* EFSYS_OPT_DIAG */
 391         void            (*eno_fini)(efx_nic_t *);
 392         void            (*eno_unprobe)(efx_nic_t *);
 393 } efx_nic_ops_t;
 394
 395 #ifndef EFX_TXQ_LIMIT_TARGET
 396 #define EFX_TXQ_LIMIT_TARGET 259
 397 #endif
 398 #ifndef EFX_RXQ_LIMIT_TARGET
 399 #define EFX_RXQ_LIMIT_TARGET 512
 400 #endif
 401
 402
 403 #if EFSYS_OPT_FILTER
 404
 405 #if EFSYS_OPT_SIENA
 406
 407 typedef struct siena_filter_spec_s {
 408         uint8_t         sfs_type;
 409         uint32_t        sfs_flags;
 410         uint32_t        sfs_dmaq_id;
 411         uint32_t        sfs_dword[3];
 412 } siena_filter_spec_t;
 413
 414 typedef enum siena_filter_type_e {
 415         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 416         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 417         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 418         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 419         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 420         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 421
 422         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 423         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 424         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 425         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 426         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 427         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 428
 429         EFX_SIENA_FILTER_NTYPES
 430 } siena_filter_type_t;
 431
 432 typedef enum siena_filter_tbl_id_e {
 433         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 434         EFX_SIENA_FILTER_TBL_RX_MAC,
 435         EFX_SIENA_FILTER_TBL_TX_IP,
 436         EFX_SIENA_FILTER_TBL_TX_MAC,
 437         EFX_SIENA_FILTER_NTBLS
 438 } siena_filter_tbl_id_t;
 439
 440 typedef struct siena_filter_tbl_s {
 441         int                     sft_size;       /* number of entries */
 442         int                     sft_used;       /* active count */
 443         uint32_t                *sft_bitmap;    /* active bitmap */
 444         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 445 } siena_filter_tbl_t;
 446
 447 typedef struct siena_filter_s {
 448         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 449         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 450 } siena_filter_t;
 451
 452 #endif  /* EFSYS_OPT_SIENA */
 453
 454 typedef struct efx_filter_s {
 455 #if EFSYS_OPT_SIENA
 456         siena_filter_t          *ef_siena_filter;
 457 #endif /* EFSYS_OPT_SIENA */
 458 #if EFX_OPTS_EF10()
 459         ef10_filter_table_t     *ef_ef10_filter_table;
 460 #endif /* EFX_OPTS_EF10() */
 461 } efx_filter_t;
 462
 463 #if EFSYS_OPT_SIENA
 464
 465 extern                  void
 466 siena_filter_tbl_clear(
 467         __in            efx_nic_t *enp,
 468         __in            siena_filter_tbl_id_t tbl);
 469
 470 #endif  /* EFSYS_OPT_SIENA */
 471
 472 #endif  /* EFSYS_OPT_FILTER */
 473
 474 #if EFSYS_OPT_MCDI
 475
 476 #define EFX_TUNNEL_MAXNENTRIES  (16)
 477
 478 #if EFSYS_OPT_TUNNEL
 479
 480 typedef struct efx_tunnel_udp_entry_s {
 481         uint16_t                        etue_port; /* host/cpu-endian */
 482         uint16_t                        etue_protocol;
 483 } efx_tunnel_udp_entry_t;
 484
 485 typedef struct efx_tunnel_cfg_s {
 486         efx_tunnel_udp_entry_t  etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
 487         unsigned int            etc_udp_entries_num;
 488 } efx_tunnel_cfg_t;
 489
 490 #endif /* EFSYS_OPT_TUNNEL */
 491
 492 typedef struct efx_mcdi_ops_s {
 493         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 494         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 495                                         void *, size_t);
 496         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 497         boolean_t       (*emco_poll_response)(efx_nic_t *);
 498         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 499         void            (*emco_fini)(efx_nic_t *);
 500         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 501                                             efx_mcdi_feature_id_t, boolean_t *);
 502         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 503                                             uint32_t *);
 504 } efx_mcdi_ops_t;
 505
 506 typedef struct efx_mcdi_s {
 507         const efx_mcdi_ops_t            *em_emcop;
 508         const efx_mcdi_transport_t      *em_emtp;
 509         efx_mcdi_iface_t                em_emip;
 510 } efx_mcdi_t;
 511
 512 #endif /* EFSYS_OPT_MCDI */
 513
 514 #if EFSYS_OPT_NVRAM
 515
 516 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
 517 #define EFX_NVRAM_PARTN_INVALID         (0xffffffffu)
 518
 519 typedef struct efx_nvram_ops_s {
 520 #if EFSYS_OPT_DIAG
 521         efx_rc_t        (*envo_test)(efx_nic_t *);
 522 #endif  /* EFSYS_OPT_DIAG */
 523         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 524                                             uint32_t *);
 525         efx_rc_t        (*envo_partn_info)(efx_nic_t *, uint32_t,
 526                                             efx_nvram_info_t *);
 527         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 528         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 529                                             unsigned int, caddr_t, size_t);
 530         efx_rc_t        (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
 531                                             unsigned int, caddr_t, size_t);
 532         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 533                                             unsigned int, size_t);
 534         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 535                                             unsigned int, caddr_t, size_t);
 536         efx_rc_t        (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
 537                                             uint32_t *);
 538         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 539                                             uint32_t *, uint16_t *);
 540         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 541                                             uint16_t *);
 542         efx_rc_t        (*envo_buffer_validate)(uint32_t,
 543                                             caddr_t, size_t);
 544 } efx_nvram_ops_t;
 545 #endif /* EFSYS_OPT_NVRAM */
 546
 547 #if EFSYS_OPT_VPD
 548 typedef struct efx_vpd_ops_s {
 549         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 550         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 551         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 552         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 553         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 554         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 555                                         efx_vpd_value_t *);
 556         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 557                                         efx_vpd_value_t *);
 558         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 559                                         efx_vpd_value_t *, unsigned int *);
 560         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 561         void            (*evpdo_fini)(efx_nic_t *);
 562 } efx_vpd_ops_t;
 563 #endif  /* EFSYS_OPT_VPD */
 564
 565 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 566
 567         __checkReturn           efx_rc_t
 568 efx_mcdi_nvram_partitions(
 569         __in                    efx_nic_t *enp,
 570         __out_bcount(size)      caddr_t data,
 571         __in                    size_t size,
 572         __out                   unsigned int *npartnp);
 573
 574         __checkReturn           efx_rc_t
 575 efx_mcdi_nvram_metadata(
 576         __in                    efx_nic_t *enp,
 577         __in                    uint32_t partn,
 578         __out                   uint32_t *subtypep,
 579         __out_ecount(4)         uint16_t version[4],
 580         __out_bcount_opt(size)  char *descp,
 581         __in                    size_t size);
 582
 583         __checkReturn           efx_rc_t
 584 efx_mcdi_nvram_info(
 585         __in                    efx_nic_t *enp,
 586         __in                    uint32_t partn,
 587         __out                   efx_nvram_info_t *eni);
 588
 589         __checkReturn           efx_rc_t
 590 efx_mcdi_nvram_update_start(
 591         __in                    efx_nic_t *enp,
 592         __in                    uint32_t partn);
 593
 594         __checkReturn           efx_rc_t
 595 efx_mcdi_nvram_read(
 596         __in                    efx_nic_t *enp,
 597         __in                    uint32_t partn,
 598         __in                    uint32_t offset,
 599         __out_bcount(size)      caddr_t data,
 600         __in                    size_t size,
 601         __in                    uint32_t mode);
 602
 603         __checkReturn           efx_rc_t
 604 efx_mcdi_nvram_erase(
 605         __in                    efx_nic_t *enp,
 606         __in                    uint32_t partn,
 607         __in                    uint32_t offset,
 608         __in                    size_t size);
 609
 610         __checkReturn           efx_rc_t
 611 efx_mcdi_nvram_write(
 612         __in                    efx_nic_t *enp,
 613         __in                    uint32_t partn,
 614         __in                    uint32_t offset,
 615         __in_bcount(size)       caddr_t data,
 616         __in                    size_t size);
 617
 618 #define EFX_NVRAM_UPDATE_FLAGS_BACKGROUND       0x00000001
 619 #define EFX_NVRAM_UPDATE_FLAGS_POLL             0x00000002
 620
 621         __checkReturn           efx_rc_t
 622 efx_mcdi_nvram_update_finish(
 623         __in                    efx_nic_t *enp,
 624         __in                    uint32_t partn,
 625         __in                    boolean_t reboot,
 626         __in                    uint32_t flags,
 627         __out_opt               uint32_t *verify_resultp);
 628
 629 #if EFSYS_OPT_DIAG
 630
 631         __checkReturn           efx_rc_t
 632 efx_mcdi_nvram_test(
 633         __in                    efx_nic_t *enp,
 634         __in                    uint32_t partn);
 635
 636 #endif  /* EFSYS_OPT_DIAG */
 637
 638 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 639
 640 #if EFSYS_OPT_LICENSING
 641
 642 typedef struct efx_lic_ops_s {
 643         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 644         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 645         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 646         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 647                                       size_t *, uint8_t *);
 648         efx_rc_t        (*elo_find_start)
 649                                 (efx_nic_t *, caddr_t, size_t, uint32_t *);
 650         efx_rc_t        (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
 651                                 uint32_t, uint32_t *);
 652         boolean_t       (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
 653                                 uint32_t, uint32_t *, uint32_t *);
 654         boolean_t       (*elo_validate_key)(efx_nic_t *,
 655                                 caddr_t, uint32_t);
 656         efx_rc_t        (*elo_read_key)(efx_nic_t *,
 657                                 caddr_t, size_t, uint32_t, uint32_t,
 658                                 caddr_t, size_t, uint32_t *);
 659         efx_rc_t        (*elo_write_key)(efx_nic_t *,
 660                                 caddr_t, size_t, uint32_t,
 661                                 caddr_t, uint32_t, uint32_t *);
 662         efx_rc_t        (*elo_delete_key)(efx_nic_t *,
 663                                 caddr_t, size_t, uint32_t,
 664                                 uint32_t, uint32_t, uint32_t *);
 665         efx_rc_t        (*elo_create_partition)(efx_nic_t *,
 666                                 caddr_t, size_t);
 667         efx_rc_t        (*elo_finish_partition)(efx_nic_t *,
 668                                 caddr_t, size_t);
 669 } efx_lic_ops_t;
 670
 671 #endif
 672
 673 #if EFSYS_OPT_EVB
 674
 675 struct efx_vswitch_s {
 676         efx_nic_t               *ev_enp;
 677         efx_vswitch_id_t        ev_vswitch_id;
 678         uint32_t                ev_num_vports;
 679         /*
 680          * Vport configuration array: index 0 to store PF configuration
 681          * and next ev_num_vports-1 entries hold VFs configuration.
 682          */
 683         efx_vport_config_t      *ev_evcp;
 684 };
 685
 686 typedef struct efx_evb_ops_s {
 687         efx_rc_t        (*eeo_init)(efx_nic_t *);
 688         void            (*eeo_fini)(efx_nic_t *);
 689         efx_rc_t        (*eeo_vswitch_alloc)(efx_nic_t *, efx_vswitch_id_t *);
 690         efx_rc_t        (*eeo_vswitch_free)(efx_nic_t *, efx_vswitch_id_t);
 691         efx_rc_t        (*eeo_vport_alloc)(efx_nic_t *, efx_vswitch_id_t,
 692                                                 efx_vport_type_t, uint16_t,
 693                                                 boolean_t, efx_vport_id_t *);
 694         efx_rc_t        (*eeo_vport_free)(efx_nic_t *, efx_vswitch_id_t,
 695                                                 efx_vport_id_t);
 696         efx_rc_t        (*eeo_vport_mac_addr_add)(efx_nic_t *, efx_vswitch_id_t,
 697                                                 efx_vport_id_t, uint8_t *);
 698         efx_rc_t        (*eeo_vport_mac_addr_del)(efx_nic_t *, efx_vswitch_id_t,
 699                                                 efx_vport_id_t, uint8_t *);
 700         efx_rc_t        (*eeo_vadaptor_alloc)(efx_nic_t *, efx_vswitch_id_t,
 701                                                 efx_vport_id_t);
 702         efx_rc_t        (*eeo_vadaptor_free)(efx_nic_t *, efx_vswitch_id_t,
 703                                                 efx_vport_id_t);
 704         efx_rc_t        (*eeo_vport_assign)(efx_nic_t *, efx_vswitch_id_t,
 705                                                 efx_vport_id_t, uint32_t);
 706         efx_rc_t        (*eeo_vport_reconfigure)(efx_nic_t *, efx_vswitch_id_t,
 707                                                         efx_vport_id_t,
 708                                                         uint16_t *, uint8_t *,
 709                                                         boolean_t *);
 710         efx_rc_t        (*eeo_vport_stats)(efx_nic_t *, efx_vswitch_id_t,
 711                                                 efx_vport_id_t, efsys_mem_t *);
 712 } efx_evb_ops_t;
 713
 714 extern __checkReturn    boolean_t
 715 efx_is_zero_eth_addr(
 716         __in_bcount(EFX_MAC_ADDR_LEN)   const uint8_t *addrp);
 717
 718 #endif /* EFSYS_OPT_EVB */
 719
 720 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
 721
 722 #define EFX_PROXY_CONFIGURE_MAGIC       0xAB2015EF
 723
 724
 725 typedef struct efx_proxy_ops_s {
 726         efx_rc_t        (*epo_init)(efx_nic_t *);
 727         void            (*epo_fini)(efx_nic_t *);
 728         efx_rc_t        (*epo_mc_config)(efx_nic_t *, efsys_mem_t *,
 729                                         efsys_mem_t *, efsys_mem_t *,
 730                                         uint32_t, uint32_t *, size_t);
 731         efx_rc_t        (*epo_disable)(efx_nic_t *);
 732         efx_rc_t        (*epo_privilege_modify)(efx_nic_t *, uint32_t, uint32_t,
 733                                         uint32_t, uint32_t, uint32_t);
 734         efx_rc_t        (*epo_set_privilege_mask)(efx_nic_t *, uint32_t,
 735                                         uint32_t, uint32_t);
 736         efx_rc_t        (*epo_complete_request)(efx_nic_t *, uint32_t,
 737                                         uint32_t, uint32_t);
 738         efx_rc_t        (*epo_exec_cmd)(efx_nic_t *, efx_proxy_cmd_params_t *);
 739         efx_rc_t        (*epo_get_privilege_mask)(efx_nic_t *, uint32_t,
 740                                         uint32_t, uint32_t *);
 741 } efx_proxy_ops_t;
 742
 743 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
 744
 745 #define EFX_DRV_VER_MAX         20
 746
 747 typedef struct efx_drv_cfg_s {
 748         uint32_t                edc_min_vi_count;
 749         uint32_t                edc_max_vi_count;
 750
 751         uint32_t                edc_max_piobuf_count;
 752         uint32_t                edc_pio_alloc_size;
 753 } efx_drv_cfg_t;
 754
 755 struct efx_nic_s {
 756         uint32_t                en_magic;
 757         efx_family_t            en_family;
 758         uint32_t                en_features;
 759         efsys_identifier_t      *en_esip;
 760         efsys_lock_t            *en_eslp;
 761         efsys_bar_t             *en_esbp;
 762         unsigned int            en_mod_flags;
 763         unsigned int            en_reset_flags;
 764         efx_nic_cfg_t           en_nic_cfg;
 765         efx_drv_cfg_t           en_drv_cfg;
 766         efx_port_t              en_port;
 767         efx_mon_t               en_mon;
 768         efx_intr_t              en_intr;
 769         uint32_t                en_ev_qcount;
 770         uint32_t                en_rx_qcount;
 771         uint32_t                en_tx_qcount;
 772         const efx_nic_ops_t     *en_enop;
 773         const efx_ev_ops_t      *en_eevop;
 774         const efx_tx_ops_t      *en_etxop;
 775         const efx_rx_ops_t      *en_erxop;
 776         efx_fw_variant_t        efv;
 777         char                    en_drv_version[EFX_DRV_VER_MAX];
 778 #if EFSYS_OPT_FILTER
 779         efx_filter_t            en_filter;
 780         const efx_filter_ops_t  *en_efop;
 781 #endif  /* EFSYS_OPT_FILTER */
 782 #if EFSYS_OPT_TUNNEL
 783         efx_tunnel_cfg_t        en_tunnel_cfg;
 784         const efx_tunnel_ops_t  *en_etop;
 785 #endif /* EFSYS_OPT_TUNNEL */
 786 #if EFSYS_OPT_MCDI
 787         efx_mcdi_t              en_mcdi;
 788 #endif  /* EFSYS_OPT_MCDI */
 789 #if EFSYS_OPT_NVRAM
 790         uint32_t                en_nvram_partn_locked;
 791         const efx_nvram_ops_t   *en_envop;
 792 #endif  /* EFSYS_OPT_NVRAM */
 793 #if EFSYS_OPT_VPD
 794         const efx_vpd_ops_t     *en_evpdop;
 795 #endif  /* EFSYS_OPT_VPD */
 796 #if EFSYS_OPT_RX_SCALE
 797         efx_rx_hash_support_t           en_hash_support;
 798         efx_rx_scale_context_type_t     en_rss_context_type;
 799         uint32_t                        en_rss_context;
 800 #endif  /* EFSYS_OPT_RX_SCALE */
 801         uint32_t                en_vport_id;
 802 #if EFSYS_OPT_LICENSING
 803         const efx_lic_ops_t     *en_elop;
 804         boolean_t               en_licensing_supported;
 805 #endif
 806         union {
 807 #if EFSYS_OPT_SIENA
 808                 struct {
 809 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 810                         unsigned int            enu_partn_mask;
 811 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 812 #if EFSYS_OPT_VPD
 813                         caddr_t                 enu_svpd;
 814                         size_t                  enu_svpd_length;
 815 #endif  /* EFSYS_OPT_VPD */
 816                         int                     enu_unused;
 817                 } siena;
 818 #endif  /* EFSYS_OPT_SIENA */
 819                 int     enu_unused;
 820         } en_u;
 821 #if EFX_OPTS_EF10()
 822         union en_arch {
 823                 struct {
 824                         int                     ena_vi_base;
 825                         int                     ena_vi_count;
 826                         int                     ena_vi_shift;
 827 #if EFSYS_OPT_VPD
 828                         caddr_t                 ena_svpd;
 829                         size_t                  ena_svpd_length;
 830 #endif  /* EFSYS_OPT_VPD */
 831                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 832                         uint32_t                ena_piobuf_count;
 833                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 834                         uint32_t                ena_pio_write_vi_base;
 835                         /* Memory BAR mapping regions */
 836                         uint32_t                ena_uc_mem_map_offset;
 837                         size_t                  ena_uc_mem_map_size;
 838                         uint32_t                ena_wc_mem_map_offset;
 839                         size_t                  ena_wc_mem_map_size;
 840                 } ef10;
 841         } en_arch;
 842 #endif  /* EFX_OPTS_EF10() */
 843 #if EFSYS_OPT_EVB
 844         const efx_evb_ops_t     *en_eeop;
 845         struct efx_vswitch_s    *en_vswitchp;
 846 #endif  /* EFSYS_OPT_EVB */
 847 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
 848         const efx_proxy_ops_t   *en_epop;
 849 #endif  /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
 850 };
 851
 852 #define EFX_FAMILY_IS_EF10(_enp) \
 853         ((_enp)->en_family == EFX_FAMILY_MEDFORD2 || \
 854          (_enp)->en_family == EFX_FAMILY_MEDFORD || \
 855          (_enp)->en_family == EFX_FAMILY_HUNTINGTON)
 856
 857
 858 #define EFX_NIC_MAGIC   0x02121996
 859
 860 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 861     const efx_ev_callbacks_t *, void *);
 862
 863 typedef struct efx_evq_rxq_state_s {
 864         unsigned int                    eers_rx_read_ptr;
 865         unsigned int                    eers_rx_mask;
 866 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
 867         unsigned int                    eers_rx_stream_npackets;
 868         boolean_t                       eers_rx_packed_stream;
 869 #endif
 870 #if EFSYS_OPT_RX_PACKED_STREAM
 871         unsigned int                    eers_rx_packed_stream_credits;
 872 #endif
 873 } efx_evq_rxq_state_t;
 874
 875 struct efx_evq_s {
 876         uint32_t                        ee_magic;
 877         uint32_t                        ee_flags;
 878         efx_nic_t                       *ee_enp;
 879         unsigned int                    ee_index;
 880         unsigned int                    ee_mask;
 881         efsys_mem_t                     *ee_esmp;
 882 #if EFSYS_OPT_QSTATS
 883         uint32_t                        ee_stat[EV_NQSTATS];
 884 #endif  /* EFSYS_OPT_QSTATS */
 885
 886         efx_ev_handler_t                ee_rx;
 887         efx_ev_handler_t                ee_tx;
 888         efx_ev_handler_t                ee_driver;
 889         efx_ev_handler_t                ee_global;
 890         efx_ev_handler_t                ee_drv_gen;
 891 #if EFSYS_OPT_MCDI
 892         efx_ev_handler_t                ee_mcdi;
 893 #endif  /* EFSYS_OPT_MCDI */
 894
 895         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 896 };
 897
 898 #define EFX_EVQ_MAGIC   0x08081997
 899
 900 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 901
 902 #if EFSYS_OPT_QSTATS
 903 #define EFX_EV_QSTAT_INCR(_eep, _stat)                                  \
 904         do {                                                            \
 905                 (_eep)->ee_stat[_stat]++;                               \
 906         _NOTE(CONSTANTCONDITION)                                        \
 907         } while (B_FALSE)
 908 #else
 909 #define EFX_EV_QSTAT_INCR(_eep, _stat)
 910 #endif
 911
 912 struct efx_rxq_s {
 913         uint32_t                        er_magic;
 914         efx_nic_t                       *er_enp;
 915         efx_evq_t                       *er_eep;
 916         unsigned int                    er_index;
 917         unsigned int                    er_label;
 918         unsigned int                    er_mask;
 919         size_t                          er_buf_size;
 920         efsys_mem_t                     *er_esmp;
 921         efx_evq_rxq_state_t             *er_ev_qstate;
 922 };
 923
 924 #define EFX_RXQ_MAGIC   0x15022005
 925
 926 struct efx_txq_s {
 927         uint32_t                        et_magic;
 928         efx_nic_t                       *et_enp;
 929         unsigned int                    et_index;
 930         unsigned int                    et_mask;
 931         efsys_mem_t                     *et_esmp;
 932 #if EFSYS_OPT_HUNTINGTON
 933         uint32_t                        et_pio_bufnum;
 934         uint32_t                        et_pio_blknum;
 935         uint32_t                        et_pio_write_offset;
 936         uint32_t                        et_pio_offset;
 937         size_t                          et_pio_size;
 938 #endif
 939 #if EFSYS_OPT_QSTATS
 940         uint32_t                        et_stat[TX_NQSTATS];
 941 #endif  /* EFSYS_OPT_QSTATS */
 942 };
 943
 944 #define EFX_TXQ_MAGIC   0x05092005
 945
 946 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 947         do {                                                            \
 948                 (_dst)[0] = (_src)[0];                                  \
 949                 (_dst)[1] = (_src)[1];                                  \
 950                 (_dst)[2] = (_src)[2];                                  \
 951                 (_dst)[3] = (_src)[3];                                  \
 952                 (_dst)[4] = (_src)[4];                                  \
 953                 (_dst)[5] = (_src)[5];                                  \
 954         _NOTE(CONSTANTCONDITION)                                        \
 955         } while (B_FALSE)
 956
 957 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 958         do {                                                            \
 959                 uint16_t *_d = (uint16_t *)(_dst);                      \
 960                 _d[0] = 0xffff;                                         \
 961                 _d[1] = 0xffff;                                         \
 962                 _d[2] = 0xffff;                                         \
 963         _NOTE(CONSTANTCONDITION)                                        \
 964         } while (B_FALSE)
 965
 966 #if EFSYS_OPT_CHECK_REG
 967 #define EFX_CHECK_REG(_enp, _reg)                                       \
 968         do {                                                            \
 969                 const char *name = #_reg;                               \
 970                 char min = name[4];                                     \
 971                 char max = name[5];                                     \
 972                 char rev;                                               \
 973                                                                         \
 974                 switch ((_enp)->en_family) {                            \
 975                 case EFX_FAMILY_SIENA:                                  \
 976                         rev = 'C';                                      \
 977                         break;                                          \
 978                                                                         \
 979                 case EFX_FAMILY_HUNTINGTON:                             \
 980                         rev = 'D';                                      \
 981                         break;                                          \
 982                                                                         \
 983                 case EFX_FAMILY_MEDFORD:                                \
 984                         rev = 'E';                                      \
 985                         break;                                          \
 986                                                                         \
 987                 case EFX_FAMILY_MEDFORD2:                               \
 988                         rev = 'F';                                      \
 989                         break;                                          \
 990                                                                         \
 991                 default:                                                \
 992                         rev = '?';                                      \
 993                         break;                                          \
 994                 }                                                       \
 995                                                                         \
 996                 EFSYS_ASSERT3S(rev, >=, min);                           \
 997                 EFSYS_ASSERT3S(rev, <=, max);                           \
 998                                                                         \
 999         _NOTE(CONSTANTCONDITION)                                        \
1000         } while (B_FALSE)
1001 #else
1002 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
1003         _NOTE(CONSTANTCONDITION)                                        \
1004         } while (B_FALSE)
1005 #endif
1006
1007 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
1008         do {                                                            \
1009                 EFX_CHECK_REG((_enp), (_reg));                          \
1010                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
1011                     (_edp), (_lock));                                   \
1012                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
1013                     uint32_t, _reg ## _OFST,                            \
1014                     uint32_t, (_edp)->ed_u32[0]);                       \
1015         _NOTE(CONSTANTCONDITION)                                        \
1016         } while (B_FALSE)
1017
1018 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
1019         do {                                                            \
1020                 EFX_CHECK_REG((_enp), (_reg));                          \
1021                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
1022                     uint32_t, _reg ## _OFST,                            \
1023                     uint32_t, (_edp)->ed_u32[0]);                       \
1024                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
1025                     (_edp), (_lock));                                   \
1026         _NOTE(CONSTANTCONDITION)                                        \
1027         } while (B_FALSE)
1028
1029 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
1030         do {                                                            \
1031                 EFX_CHECK_REG((_enp), (_reg));                          \
1032                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
1033                     (_eqp));                                            \
1034                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
1035                     uint32_t, _reg ## _OFST,                            \
1036                     uint32_t, (_eqp)->eq_u32[1],                        \
1037                     uint32_t, (_eqp)->eq_u32[0]);                       \
1038         _NOTE(CONSTANTCONDITION)                                        \
1039         } while (B_FALSE)
1040
1041 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
1042         do {                                                            \
1043                 EFX_CHECK_REG((_enp), (_reg));                          \
1044                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
1045                     uint32_t, _reg ## _OFST,                            \
1046                     uint32_t, (_eqp)->eq_u32[1],                        \
1047                     uint32_t, (_eqp)->eq_u32[0]);                       \
1048                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
1049                     (_eqp));                                            \
1050         _NOTE(CONSTANTCONDITION)                                        \
1051         } while (B_FALSE)
1052
1053 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
1054         do {                                                            \
1055                 EFX_CHECK_REG((_enp), (_reg));                          \
1056                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
1057                     (_eop), B_TRUE);                                    \
1058                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
1059                     uint32_t, _reg ## _OFST,                            \
1060                     uint32_t, (_eop)->eo_u32[3],                        \
1061                     uint32_t, (_eop)->eo_u32[2],                        \
1062                     uint32_t, (_eop)->eo_u32[1],                        \
1063                     uint32_t, (_eop)->eo_u32[0]);                       \
1064         _NOTE(CONSTANTCONDITION)                                        \
1065         } while (B_FALSE)
1066
1067 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
1068         do {                                                            \
1069                 EFX_CHECK_REG((_enp), (_reg));                          \
1070                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
1071                     uint32_t, _reg ## _OFST,                            \
1072                     uint32_t, (_eop)->eo_u32[3],                        \
1073                     uint32_t, (_eop)->eo_u32[2],                        \
1074                     uint32_t, (_eop)->eo_u32[1],                        \
1075                     uint32_t, (_eop)->eo_u32[0]);                       \
1076                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
1077                     (_eop), B_TRUE);                                    \
1078         _NOTE(CONSTANTCONDITION)                                        \
1079         } while (B_FALSE)
1080
1081 /*
1082  * Accessors for memory BAR non-VI tables.
1083  *
1084  * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers,
1085  * to ensure the correct runtime VI window size is used on Medford2.
1086  *
1087  * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers.
1088  */
1089
1090 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
1091         do {                                                            \
1092                 EFX_CHECK_REG((_enp), (_reg));                          \
1093                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
1094                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1095                     (_edp), (_lock));                                   \
1096                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
1097                     uint32_t, (_index),                                 \
1098                     uint32_t, _reg ## _OFST,                            \
1099                     uint32_t, (_edp)->ed_u32[0]);                       \
1100         _NOTE(CONSTANTCONDITION)                                        \
1101         } while (B_FALSE)
1102
1103 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
1104         do {                                                            \
1105                 EFX_CHECK_REG((_enp), (_reg));                          \
1106                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
1107                     uint32_t, (_index),                                 \
1108                     uint32_t, _reg ## _OFST,                            \
1109                     uint32_t, (_edp)->ed_u32[0]);                       \
1110                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1111                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1112                     (_edp), (_lock));                                   \
1113         _NOTE(CONSTANTCONDITION)                                        \
1114         } while (B_FALSE)
1115
1116 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
1117         do {                                                            \
1118                 EFX_CHECK_REG((_enp), (_reg));                          \
1119                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
1120                     uint32_t, (_index),                                 \
1121                     uint32_t, _reg ## _OFST,                            \
1122                     uint32_t, (_edp)->ed_u32[0]);                       \
1123                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1124                     (_reg ## _OFST +                                    \
1125                     (3 * sizeof (efx_dword_t)) +                        \
1126                     ((_index) * _reg ## _STEP)),                        \
1127                     (_edp), (_lock));                                   \
1128         _NOTE(CONSTANTCONDITION)                                        \
1129         } while (B_FALSE)
1130
1131 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
1132         do {                                                            \
1133                 EFX_CHECK_REG((_enp), (_reg));                          \
1134                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
1135                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1136                     (_eqp));                                            \
1137                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
1138                     uint32_t, (_index),                                 \
1139                     uint32_t, _reg ## _OFST,                            \
1140                     uint32_t, (_eqp)->eq_u32[1],                        \
1141                     uint32_t, (_eqp)->eq_u32[0]);                       \
1142         _NOTE(CONSTANTCONDITION)                                        \
1143         } while (B_FALSE)
1144
1145 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
1146         do {                                                            \
1147                 EFX_CHECK_REG((_enp), (_reg));                          \
1148                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
1149                     uint32_t, (_index),                                 \
1150                     uint32_t, _reg ## _OFST,                            \
1151                     uint32_t, (_eqp)->eq_u32[1],                        \
1152                     uint32_t, (_eqp)->eq_u32[0]);                       \
1153                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
1154                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1155                     (_eqp));                                            \
1156         _NOTE(CONSTANTCONDITION)                                        \
1157         } while (B_FALSE)
1158
1159 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
1160         do {                                                            \
1161                 EFX_CHECK_REG((_enp), (_reg));                          \
1162                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
1163                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1164                     (_eop), (_lock));                                   \
1165                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
1166                     uint32_t, (_index),                                 \
1167                     uint32_t, _reg ## _OFST,                            \
1168                     uint32_t, (_eop)->eo_u32[3],                        \
1169                     uint32_t, (_eop)->eo_u32[2],                        \
1170                     uint32_t, (_eop)->eo_u32[1],                        \
1171                     uint32_t, (_eop)->eo_u32[0]);                       \
1172         _NOTE(CONSTANTCONDITION)                                        \
1173         } while (B_FALSE)
1174
1175 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
1176         do {                                                            \
1177                 EFX_CHECK_REG((_enp), (_reg));                          \
1178                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
1179                     uint32_t, (_index),                                 \
1180                     uint32_t, _reg ## _OFST,                            \
1181                     uint32_t, (_eop)->eo_u32[3],                        \
1182                     uint32_t, (_eop)->eo_u32[2],                        \
1183                     uint32_t, (_eop)->eo_u32[1],                        \
1184                     uint32_t, (_eop)->eo_u32[0]);                       \
1185                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
1186                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1187                     (_eop), (_lock));                                   \
1188         _NOTE(CONSTANTCONDITION)                                        \
1189         } while (B_FALSE)
1190
1191 /*
1192  * Accessors for memory BAR per-VI registers.
1193  *
1194  * The VI window size is 8KB for Medford and all earlier controllers.
1195  * For Medford2, the VI window size can be 8KB, 16KB or 64KB.
1196  */
1197
1198 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock)               \
1199         do {                                                            \
1200                 EFX_CHECK_REG((_enp), (_reg));                          \
1201                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
1202                     ((_reg ## _OFST) +                                  \
1203                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1204                     (_edp), (_lock));                                   \
1205                 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg,     \
1206                     uint32_t, (_index),                                 \
1207                     uint32_t, _reg ## _OFST,                            \
1208                     uint32_t, (_edp)->ed_u32[0]);                       \
1209         _NOTE(CONSTANTCONDITION)                                        \
1210         } while (B_FALSE)
1211
1212 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock)              \
1213         do {                                                            \
1214                 EFX_CHECK_REG((_enp), (_reg));                          \
1215                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1216                     uint32_t, (_index),                                 \
1217                     uint32_t, _reg ## _OFST,                            \
1218                     uint32_t, (_edp)->ed_u32[0]);                       \
1219                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1220                     ((_reg ## _OFST) +                                  \
1221                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1222                     (_edp), (_lock));                                   \
1223         _NOTE(CONSTANTCONDITION)                                        \
1224         } while (B_FALSE)
1225
1226 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock)             \
1227         do {                                                            \
1228                 EFX_CHECK_REG((_enp), (_reg));                          \
1229                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1230                     uint32_t, (_index),                                 \
1231                     uint32_t, _reg ## _OFST,                            \
1232                     uint32_t, (_edp)->ed_u32[0]);                       \
1233                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1234                     ((_reg ## _OFST) +                                  \
1235                     (2 * sizeof (efx_dword_t)) +                        \
1236                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1237                     (_edp), (_lock));                                   \
1238         _NOTE(CONSTANTCONDITION)                                        \
1239         } while (B_FALSE)
1240
1241 /*
1242  * Allow drivers to perform optimised 128-bit VI doorbell writes.
1243  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1244  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1245  * the need for locking in the host, and are the only ones known to be safe to
1246  * use 128-bites write with.
1247  */
1248 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop)            \
1249         do {                                                            \
1250                 EFX_CHECK_REG((_enp), (_reg));                          \
1251                 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo,                \
1252                     const char *, #_reg,                                \
1253                     uint32_t, (_index),                                 \
1254                     uint32_t, _reg ## _OFST,                            \
1255                     uint32_t, (_eop)->eo_u32[3],                        \
1256                     uint32_t, (_eop)->eo_u32[2],                        \
1257                     uint32_t, (_eop)->eo_u32[1],                        \
1258                     uint32_t, (_eop)->eo_u32[0]);                       \
1259                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1260                     (_reg ## _OFST +                                    \
1261                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1262                     (_eop));                                            \
1263         _NOTE(CONSTANTCONDITION)                                        \
1264         } while (B_FALSE)
1265
1266 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1267         do {                                                            \
1268                 unsigned int _new = (_wptr);                            \
1269                 unsigned int _old = (_owptr);                           \
1270                                                                         \
1271                 if ((_new) >= (_old))                                   \
1272                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1273                             (_old) * sizeof (efx_desc_t),               \
1274                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1275                 else                                                    \
1276                         /*                                              \
1277                          * It is cheaper to sync entire map than sync   \
1278                          * two parts especially when offset/size are    \
1279                          * ignored and entire map is synced in any case.\
1280                          */                                             \
1281                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1282                             0,                                          \
1283                             (_entries) * sizeof (efx_desc_t));          \
1284         _NOTE(CONSTANTCONDITION)                                        \
1285         } while (B_FALSE)
1286
1287 extern  __checkReturn   efx_rc_t
1288 efx_mac_select(
1289         __in            efx_nic_t *enp);
1290
1291 extern  void
1292 efx_mac_multicast_hash_compute(
1293         __in_ecount(6*count)            uint8_t const *addrs,
1294         __in                            int count,
1295         __out                           efx_oword_t *hash_low,
1296         __out                           efx_oword_t *hash_high);
1297
1298 extern  __checkReturn   efx_rc_t
1299 efx_phy_probe(
1300         __in            efx_nic_t *enp);
1301
1302 extern                  void
1303 efx_phy_unprobe(
1304         __in            efx_nic_t *enp);
1305
1306 #if EFSYS_OPT_VPD
1307
1308 /* VPD utility functions */
1309
1310 extern  __checkReturn           efx_rc_t
1311 efx_vpd_hunk_length(
1312         __in_bcount(size)       caddr_t data,
1313         __in                    size_t size,
1314         __out                   size_t *lengthp);
1315
1316 extern  __checkReturn           efx_rc_t
1317 efx_vpd_hunk_verify(
1318         __in_bcount(size)       caddr_t data,
1319         __in                    size_t size,
1320         __out_opt               boolean_t *cksummedp);
1321
1322 extern  __checkReturn           efx_rc_t
1323 efx_vpd_hunk_reinit(
1324         __in_bcount(size)       caddr_t data,
1325         __in                    size_t size,
1326         __in                    boolean_t wantpid);
1327
1328 extern  __checkReturn           efx_rc_t
1329 efx_vpd_hunk_get(
1330         __in_bcount(size)       caddr_t data,
1331         __in                    size_t size,
1332         __in                    efx_vpd_tag_t tag,
1333         __in                    efx_vpd_keyword_t keyword,
1334         __out                   unsigned int *payloadp,
1335         __out                   uint8_t *paylenp);
1336
1337 extern  __checkReturn                   efx_rc_t
1338 efx_vpd_hunk_next(
1339         __in_bcount(size)               caddr_t data,
1340         __in                            size_t size,
1341         __out                           efx_vpd_tag_t *tagp,
1342         __out                           efx_vpd_keyword_t *keyword,
1343         __out_opt                       unsigned int *payloadp,
1344         __out_opt                       uint8_t *paylenp,
1345         __inout                         unsigned int *contp);
1346
1347 extern  __checkReturn           efx_rc_t
1348 efx_vpd_hunk_set(
1349         __in_bcount(size)       caddr_t data,
1350         __in                    size_t size,
1351         __in                    efx_vpd_value_t *evvp);
1352
1353 #endif  /* EFSYS_OPT_VPD */
1354
1355 #if EFSYS_OPT_MCDI
1356
1357 extern  __checkReturn           efx_rc_t
1358 efx_mcdi_set_workaround(
1359         __in                    efx_nic_t *enp,
1360         __in                    uint32_t type,
1361         __in                    boolean_t enabled,
1362         __out_opt               uint32_t *flagsp);
1363
1364 extern  __checkReturn           efx_rc_t
1365 efx_mcdi_get_workarounds(
1366         __in                    efx_nic_t *enp,
1367         __out_opt               uint32_t *implementedp,
1368         __out_opt               uint32_t *enabledp);
1369
1370 #endif /* EFSYS_OPT_MCDI */
1371
1372 #if EFSYS_OPT_MAC_STATS
1373
1374 /*
1375  * Closed range of stats (i.e. the first and the last are included).
1376  * The last must be greater or equal (if the range is one item only) to
1377  * the first.
1378  */
1379 struct efx_mac_stats_range {
1380         efx_mac_stat_t          first;
1381         efx_mac_stat_t          last;
1382 };
1383
1384 typedef enum efx_stats_action_e {
1385         EFX_STATS_CLEAR,
1386         EFX_STATS_UPLOAD,
1387         EFX_STATS_ENABLE_NOEVENTS,
1388         EFX_STATS_ENABLE_EVENTS,
1389         EFX_STATS_DISABLE,
1390 } efx_stats_action_t;
1391
1392 extern                                  efx_rc_t
1393 efx_mac_stats_mask_add_ranges(
1394         __inout_bcount(mask_size)       uint32_t *maskp,
1395         __in                            size_t mask_size,
1396         __in_ecount(rng_count)          const struct efx_mac_stats_range *rngp,
1397         __in                            unsigned int rng_count);
1398
1399 extern  __checkReturn   efx_rc_t
1400 efx_mcdi_mac_stats(
1401         __in            efx_nic_t *enp,
1402         __in            uint32_t vport_id,
1403         __in_opt        efsys_mem_t *esmp,
1404         __in            efx_stats_action_t action,
1405         __in            uint16_t period_ms);
1406
1407 #endif  /* EFSYS_OPT_MAC_STATS */
1408
1409 #ifdef  __cplusplus
1410 }
1411 #endif
1412
1413 #endif  /* _SYS_EFX_IMPL_H */