drivers/net/sfc/base/efx_impl.h

   1 /*
   2  * Copyright (c) 2007-2016 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  */
  30
  31 #ifndef _SYS_EFX_IMPL_H
  32 #define _SYS_EFX_IMPL_H
  33
  34 #include "efx.h"
  35 #include "efx_regs.h"
  36 #include "efx_regs_ef10.h"
  37
  38 /* FIXME: Add definition for driver generated software events */
  39 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  40 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  41 #endif
  42
  43
  44 #if EFSYS_OPT_SIENA
  45 #include "siena_impl.h"
  46 #endif  /* EFSYS_OPT_SIENA */
  47
  48 #if EFSYS_OPT_HUNTINGTON
  49 #include "hunt_impl.h"
  50 #endif  /* EFSYS_OPT_HUNTINGTON */
  51
  52 #if EFSYS_OPT_MEDFORD
  53 #include "medford_impl.h"
  54 #endif  /* EFSYS_OPT_MEDFORD */
  55
  56 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
  57 #include "ef10_impl.h"
  58 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
  59
  60 #ifdef  __cplusplus
  61 extern "C" {
  62 #endif
  63
  64 #define EFX_MOD_MCDI            0x00000001
  65 #define EFX_MOD_PROBE           0x00000002
  66 #define EFX_MOD_NVRAM           0x00000004
  67 #define EFX_MOD_VPD             0x00000008
  68 #define EFX_MOD_NIC             0x00000010
  69 #define EFX_MOD_INTR            0x00000020
  70 #define EFX_MOD_EV              0x00000040
  71 #define EFX_MOD_RX              0x00000080
  72 #define EFX_MOD_TX              0x00000100
  73 #define EFX_MOD_PORT            0x00000200
  74 #define EFX_MOD_MON             0x00000400
  75 #define EFX_MOD_FILTER          0x00001000
  76 #define EFX_MOD_LIC             0x00002000
  77
  78 #define EFX_RESET_PHY           0x00000001
  79 #define EFX_RESET_RXQ_ERR       0x00000002
  80 #define EFX_RESET_TXQ_ERR       0x00000004
  81
  82 typedef enum efx_mac_type_e {
  83         EFX_MAC_INVALID = 0,
  84         EFX_MAC_SIENA,
  85         EFX_MAC_HUNTINGTON,
  86         EFX_MAC_MEDFORD,
  87         EFX_MAC_NTYPES
  88 } efx_mac_type_t;
  89
  90 typedef struct efx_ev_ops_s {
  91         efx_rc_t        (*eevo_init)(efx_nic_t *);
  92         void            (*eevo_fini)(efx_nic_t *);
  93         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  94                                           efsys_mem_t *, size_t, uint32_t,
  95                                           uint32_t, uint32_t, efx_evq_t *);
  96         void            (*eevo_qdestroy)(efx_evq_t *);
  97         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  98         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  99         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
 100 #if EFSYS_OPT_QSTATS
 101         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
 102 #endif
 103 } efx_ev_ops_t;
 104
 105 typedef struct efx_tx_ops_s {
 106         efx_rc_t        (*etxo_init)(efx_nic_t *);
 107         void            (*etxo_fini)(efx_nic_t *);
 108         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 109                                         unsigned int, unsigned int,
 110                                         efsys_mem_t *, size_t,
 111                                         uint32_t, uint16_t,
 112                                         efx_evq_t *, efx_txq_t *,
 113                                         unsigned int *);
 114         void            (*etxo_qdestroy)(efx_txq_t *);
 115         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 116                                       unsigned int, unsigned int,
 117                                       unsigned int *);
 118         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 119         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 120         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 121         void            (*etxo_qenable)(efx_txq_t *);
 122         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 123         void            (*etxo_qpio_disable)(efx_txq_t *);
 124         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 125                                            size_t);
 126         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 127                                            unsigned int *);
 128         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 129                                       unsigned int, unsigned int,
 130                                       unsigned int *);
 131         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 132                                                 size_t, boolean_t,
 133                                                 efx_desc_t *);
 134         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 135                                                 uint32_t, uint8_t,
 136                                                 efx_desc_t *);
 137         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 138                                                 uint32_t, uint16_t,
 139                                                 efx_desc_t *, int);
 140         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 141                                                 efx_desc_t *);
 142 #if EFSYS_OPT_QSTATS
 143         void            (*etxo_qstats_update)(efx_txq_t *,
 144                                               efsys_stat_t *);
 145 #endif
 146 } efx_tx_ops_t;
 147
 148 typedef struct efx_rx_ops_s {
 149         efx_rc_t        (*erxo_init)(efx_nic_t *);
 150         void            (*erxo_fini)(efx_nic_t *);
 151 #if EFSYS_OPT_RX_SCATTER
 152         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 153 #endif
 154 #if EFSYS_OPT_RX_SCALE
 155         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
 156                                                efx_rx_hash_type_t, boolean_t);
 157         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
 158         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
 159                                               size_t);
 160         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 161                                             uint8_t *);
 162 #endif /* EFSYS_OPT_RX_SCALE */
 163         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 164                                               uint16_t *);
 165         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 166                                       unsigned int, unsigned int,
 167                                       unsigned int);
 168         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 169 #if EFSYS_OPT_RX_PACKED_STREAM
 170         void            (*erxo_qps_update_credits)(efx_rxq_t *);
 171         uint8_t *       (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
 172                                                 uint32_t, uint32_t,
 173                                                 uint16_t *, uint32_t *, uint32_t *);
 174 #endif
 175         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 176         void            (*erxo_qenable)(efx_rxq_t *);
 177         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 178                                         unsigned int, efx_rxq_type_t,
 179                                         efsys_mem_t *, size_t, uint32_t,
 180                                         efx_evq_t *, efx_rxq_t *);
 181         void            (*erxo_qdestroy)(efx_rxq_t *);
 182 } efx_rx_ops_t;
 183
 184 typedef struct efx_mac_ops_s {
 185         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 186         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 187         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 188         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 189         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 190         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 191         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 192         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 193                                                       efx_rxq_t *, boolean_t);
 194         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 195 #if EFSYS_OPT_LOOPBACK
 196         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 197                                             efx_loopback_type_t);
 198 #endif  /* EFSYS_OPT_LOOPBACK */
 199 #if EFSYS_OPT_MAC_STATS
 200         efx_rc_t        (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
 201         efx_rc_t        (*emo_stats_clear)(efx_nic_t *);
 202         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 203         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 204                                               uint16_t, boolean_t);
 205         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 206                                             efsys_stat_t *, uint32_t *);
 207 #endif  /* EFSYS_OPT_MAC_STATS */
 208 } efx_mac_ops_t;
 209
 210 typedef struct efx_phy_ops_s {
 211         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 212         efx_rc_t        (*epo_reset)(efx_nic_t *);
 213         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 214         efx_rc_t        (*epo_verify)(efx_nic_t *);
 215         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 216 #if EFSYS_OPT_PHY_STATS
 217         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 218                                             uint32_t *);
 219 #endif  /* EFSYS_OPT_PHY_STATS */
 220 #if EFSYS_OPT_BIST
 221         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 222         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 223         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 224                                          efx_bist_result_t *, uint32_t *,
 225                                          unsigned long *, size_t);
 226         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 227 #endif  /* EFSYS_OPT_BIST */
 228 } efx_phy_ops_t;
 229
 230 #if EFSYS_OPT_FILTER
 231 typedef struct efx_filter_ops_s {
 232         efx_rc_t        (*efo_init)(efx_nic_t *);
 233         void            (*efo_fini)(efx_nic_t *);
 234         efx_rc_t        (*efo_restore)(efx_nic_t *);
 235         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 236                                    boolean_t may_replace);
 237         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 238         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
 239         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 240                                    boolean_t, boolean_t, boolean_t,
 241                                    uint8_t const *, uint32_t);
 242 } efx_filter_ops_t;
 243
 244 extern  __checkReturn   efx_rc_t
 245 efx_filter_reconfigure(
 246         __in                            efx_nic_t *enp,
 247         __in_ecount(6)                  uint8_t const *mac_addr,
 248         __in                            boolean_t all_unicst,
 249         __in                            boolean_t mulcst,
 250         __in                            boolean_t all_mulcst,
 251         __in                            boolean_t brdcst,
 252         __in_ecount(6*count)            uint8_t const *addrs,
 253         __in                            uint32_t count);
 254
 255 #endif /* EFSYS_OPT_FILTER */
 256
 257
 258 typedef struct efx_port_s {
 259         efx_mac_type_t          ep_mac_type;
 260         uint32_t                ep_phy_type;
 261         uint8_t                 ep_port;
 262         uint32_t                ep_mac_pdu;
 263         uint8_t                 ep_mac_addr[6];
 264         efx_link_mode_t         ep_link_mode;
 265         boolean_t               ep_all_unicst;
 266         boolean_t               ep_mulcst;
 267         boolean_t               ep_all_mulcst;
 268         boolean_t               ep_brdcst;
 269         unsigned int            ep_fcntl;
 270         boolean_t               ep_fcntl_autoneg;
 271         efx_oword_t             ep_multicst_hash[2];
 272         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 273                                                     EFX_MAC_MULTICAST_LIST_MAX];
 274         uint32_t                ep_mulcst_addr_count;
 275 #if EFSYS_OPT_LOOPBACK
 276         efx_loopback_type_t     ep_loopback_type;
 277         efx_link_mode_t         ep_loopback_link_mode;
 278 #endif  /* EFSYS_OPT_LOOPBACK */
 279 #if EFSYS_OPT_PHY_FLAGS
 280         uint32_t                ep_phy_flags;
 281 #endif  /* EFSYS_OPT_PHY_FLAGS */
 282 #if EFSYS_OPT_PHY_LED_CONTROL
 283         efx_phy_led_mode_t      ep_phy_led_mode;
 284 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 285         efx_phy_media_type_t    ep_fixed_port_type;
 286         efx_phy_media_type_t    ep_module_type;
 287         uint32_t                ep_adv_cap_mask;
 288         uint32_t                ep_lp_cap_mask;
 289         uint32_t                ep_default_adv_cap_mask;
 290         uint32_t                ep_phy_cap_mask;
 291         boolean_t               ep_mac_drain;
 292         boolean_t               ep_mac_stats_pending;
 293 #if EFSYS_OPT_BIST
 294         efx_bist_type_t         ep_current_bist;
 295 #endif
 296         const efx_mac_ops_t     *ep_emop;
 297         const efx_phy_ops_t     *ep_epop;
 298 } efx_port_t;
 299
 300 typedef struct efx_mon_ops_s {
 301 #if EFSYS_OPT_MON_STATS
 302         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 303                                             efx_mon_stat_value_t *);
 304 #endif  /* EFSYS_OPT_MON_STATS */
 305 } efx_mon_ops_t;
 306
 307 typedef struct efx_mon_s {
 308         efx_mon_type_t          em_type;
 309         const efx_mon_ops_t     *em_emop;
 310 } efx_mon_t;
 311
 312 typedef struct efx_intr_ops_s {
 313         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 314         void            (*eio_enable)(efx_nic_t *);
 315         void            (*eio_disable)(efx_nic_t *);
 316         void            (*eio_disable_unlocked)(efx_nic_t *);
 317         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 318         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 319         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 320                                  boolean_t *);
 321         void            (*eio_fatal)(efx_nic_t *);
 322         void            (*eio_fini)(efx_nic_t *);
 323 } efx_intr_ops_t;
 324
 325 typedef struct efx_intr_s {
 326         const efx_intr_ops_t    *ei_eiop;
 327         efsys_mem_t             *ei_esmp;
 328         efx_intr_type_t         ei_type;
 329         unsigned int            ei_level;
 330 } efx_intr_t;
 331
 332 typedef struct efx_nic_ops_s {
 333         efx_rc_t        (*eno_probe)(efx_nic_t *);
 334         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 335         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 336         efx_rc_t        (*eno_reset)(efx_nic_t *);
 337         efx_rc_t        (*eno_init)(efx_nic_t *);
 338         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 339         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 340                                         uint32_t *, size_t *);
 341 #if EFSYS_OPT_DIAG
 342         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 343 #endif  /* EFSYS_OPT_DIAG */
 344         void            (*eno_fini)(efx_nic_t *);
 345         void            (*eno_unprobe)(efx_nic_t *);
 346 } efx_nic_ops_t;
 347
 348 #ifndef EFX_TXQ_LIMIT_TARGET
 349 #define EFX_TXQ_LIMIT_TARGET 259
 350 #endif
 351 #ifndef EFX_RXQ_LIMIT_TARGET
 352 #define EFX_RXQ_LIMIT_TARGET 512
 353 #endif
 354 #ifndef EFX_TXQ_DC_SIZE
 355 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
 356 #endif
 357 #ifndef EFX_RXQ_DC_SIZE
 358 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
 359 #endif
 360
 361 #if EFSYS_OPT_FILTER
 362
 363 #if EFSYS_OPT_SIENA
 364
 365 typedef struct siena_filter_spec_s {
 366         uint8_t         sfs_type;
 367         uint32_t        sfs_flags;
 368         uint32_t        sfs_dmaq_id;
 369         uint32_t        sfs_dword[3];
 370 } siena_filter_spec_t;
 371
 372 typedef enum siena_filter_type_e {
 373         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 374         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 375         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 376         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 377         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 378         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 379
 380         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 381         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 382         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 383         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 384         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 385         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 386
 387         EFX_SIENA_FILTER_NTYPES
 388 } siena_filter_type_t;
 389
 390 typedef enum siena_filter_tbl_id_e {
 391         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 392         EFX_SIENA_FILTER_TBL_RX_MAC,
 393         EFX_SIENA_FILTER_TBL_TX_IP,
 394         EFX_SIENA_FILTER_TBL_TX_MAC,
 395         EFX_SIENA_FILTER_NTBLS
 396 } siena_filter_tbl_id_t;
 397
 398 typedef struct siena_filter_tbl_s {
 399         int                     sft_size;       /* number of entries */
 400         int                     sft_used;       /* active count */
 401         uint32_t                *sft_bitmap;    /* active bitmap */
 402         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 403 } siena_filter_tbl_t;
 404
 405 typedef struct siena_filter_s {
 406         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 407         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 408 } siena_filter_t;
 409
 410 #endif  /* EFSYS_OPT_SIENA */
 411
 412 typedef struct efx_filter_s {
 413 #if EFSYS_OPT_SIENA
 414         siena_filter_t          *ef_siena_filter;
 415 #endif /* EFSYS_OPT_SIENA */
 416 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 417         ef10_filter_table_t     *ef_ef10_filter_table;
 418 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 419 } efx_filter_t;
 420
 421 #if EFSYS_OPT_SIENA
 422
 423 extern                  void
 424 siena_filter_tbl_clear(
 425         __in            efx_nic_t *enp,
 426         __in            siena_filter_tbl_id_t tbl);
 427
 428 #endif  /* EFSYS_OPT_SIENA */
 429
 430 #endif  /* EFSYS_OPT_FILTER */
 431
 432 #if EFSYS_OPT_MCDI
 433
 434 typedef struct efx_mcdi_ops_s {
 435         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 436         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 437                                         void *, size_t);
 438         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 439         boolean_t       (*emco_poll_response)(efx_nic_t *);
 440         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 441         void            (*emco_fini)(efx_nic_t *);
 442         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 443                                             efx_mcdi_feature_id_t, boolean_t *);
 444         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 445                                             uint32_t *);
 446 } efx_mcdi_ops_t;
 447
 448 typedef struct efx_mcdi_s {
 449         const efx_mcdi_ops_t            *em_emcop;
 450         const efx_mcdi_transport_t      *em_emtp;
 451         efx_mcdi_iface_t                em_emip;
 452 } efx_mcdi_t;
 453
 454 #endif /* EFSYS_OPT_MCDI */
 455
 456 #if EFSYS_OPT_NVRAM
 457 typedef struct efx_nvram_ops_s {
 458 #if EFSYS_OPT_DIAG
 459         efx_rc_t        (*envo_test)(efx_nic_t *);
 460 #endif  /* EFSYS_OPT_DIAG */
 461         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 462                                             uint32_t *);
 463         efx_rc_t        (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
 464         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 465         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 466                                             unsigned int, caddr_t, size_t);
 467         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 468                                             unsigned int, size_t);
 469         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 470                                             unsigned int, caddr_t, size_t);
 471         efx_rc_t        (*envo_partn_rw_finish)(efx_nic_t *, uint32_t);
 472         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 473                                             uint32_t *, uint16_t *);
 474         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 475                                             uint16_t *);
 476         efx_rc_t        (*envo_buffer_validate)(efx_nic_t *, uint32_t,
 477                                             caddr_t, size_t);
 478 } efx_nvram_ops_t;
 479 #endif /* EFSYS_OPT_NVRAM */
 480
 481 #if EFSYS_OPT_VPD
 482 typedef struct efx_vpd_ops_s {
 483         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 484         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 485         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 486         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 487         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 488         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 489                                         efx_vpd_value_t *);
 490         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 491                                         efx_vpd_value_t *);
 492         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 493                                         efx_vpd_value_t *, unsigned int *);
 494         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 495         void            (*evpdo_fini)(efx_nic_t *);
 496 } efx_vpd_ops_t;
 497 #endif  /* EFSYS_OPT_VPD */
 498
 499 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 500
 501         __checkReturn           efx_rc_t
 502 efx_mcdi_nvram_partitions(
 503         __in                    efx_nic_t *enp,
 504         __out_bcount(size)      caddr_t data,
 505         __in                    size_t size,
 506         __out                   unsigned int *npartnp);
 507
 508         __checkReturn           efx_rc_t
 509 efx_mcdi_nvram_metadata(
 510         __in                    efx_nic_t *enp,
 511         __in                    uint32_t partn,
 512         __out                   uint32_t *subtypep,
 513         __out_ecount(4)         uint16_t version[4],
 514         __out_bcount_opt(size)  char *descp,
 515         __in                    size_t size);
 516
 517         __checkReturn           efx_rc_t
 518 efx_mcdi_nvram_info(
 519         __in                    efx_nic_t *enp,
 520         __in                    uint32_t partn,
 521         __out_opt               size_t *sizep,
 522         __out_opt               uint32_t *addressp,
 523         __out_opt               uint32_t *erase_sizep,
 524         __out_opt               uint32_t *write_sizep);
 525
 526         __checkReturn           efx_rc_t
 527 efx_mcdi_nvram_update_start(
 528         __in                    efx_nic_t *enp,
 529         __in                    uint32_t partn);
 530
 531         __checkReturn           efx_rc_t
 532 efx_mcdi_nvram_read(
 533         __in                    efx_nic_t *enp,
 534         __in                    uint32_t partn,
 535         __in                    uint32_t offset,
 536         __out_bcount(size)      caddr_t data,
 537         __in                    size_t size,
 538         __in                    uint32_t mode);
 539
 540         __checkReturn           efx_rc_t
 541 efx_mcdi_nvram_erase(
 542         __in                    efx_nic_t *enp,
 543         __in                    uint32_t partn,
 544         __in                    uint32_t offset,
 545         __in                    size_t size);
 546
 547         __checkReturn           efx_rc_t
 548 efx_mcdi_nvram_write(
 549         __in                    efx_nic_t *enp,
 550         __in                    uint32_t partn,
 551         __in                    uint32_t offset,
 552         __out_bcount(size)      caddr_t data,
 553         __in                    size_t size);
 554
 555         __checkReturn           efx_rc_t
 556 efx_mcdi_nvram_update_finish(
 557         __in                    efx_nic_t *enp,
 558         __in                    uint32_t partn,
 559         __in                    boolean_t reboot,
 560         __out_opt               uint32_t *resultp);
 561
 562 #if EFSYS_OPT_DIAG
 563
 564         __checkReturn           efx_rc_t
 565 efx_mcdi_nvram_test(
 566         __in                    efx_nic_t *enp,
 567         __in                    uint32_t partn);
 568
 569 #endif  /* EFSYS_OPT_DIAG */
 570
 571 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 572
 573 #if EFSYS_OPT_LICENSING
 574
 575 typedef struct efx_lic_ops_s {
 576         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 577         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 578         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 579         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 580                                       size_t *, uint8_t *);
 581         efx_rc_t        (*elo_find_start)
 582                                 (efx_nic_t *, caddr_t, size_t, uint32_t *);
 583         efx_rc_t        (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
 584                                 uint32_t, uint32_t *);
 585         boolean_t       (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
 586                                 uint32_t, uint32_t *, uint32_t *);
 587         boolean_t       (*elo_validate_key)(efx_nic_t *,
 588                                 caddr_t, uint32_t);
 589         efx_rc_t        (*elo_read_key)(efx_nic_t *,
 590                                 caddr_t, size_t, uint32_t, uint32_t,
 591                                 caddr_t, size_t, uint32_t *);
 592         efx_rc_t        (*elo_write_key)(efx_nic_t *,
 593                                 caddr_t, size_t, uint32_t,
 594                                 caddr_t, uint32_t, uint32_t *);
 595         efx_rc_t        (*elo_delete_key)(efx_nic_t *,
 596                                 caddr_t, size_t, uint32_t,
 597                                 uint32_t, uint32_t, uint32_t *);
 598         efx_rc_t        (*elo_create_partition)(efx_nic_t *,
 599                                 caddr_t, size_t);
 600         efx_rc_t        (*elo_finish_partition)(efx_nic_t *,
 601                                 caddr_t, size_t);
 602 } efx_lic_ops_t;
 603
 604 #endif
 605
 606 typedef struct efx_drv_cfg_s {
 607         uint32_t                edc_min_vi_count;
 608         uint32_t                edc_max_vi_count;
 609
 610         uint32_t                edc_max_piobuf_count;
 611         uint32_t                edc_pio_alloc_size;
 612 } efx_drv_cfg_t;
 613
 614 struct efx_nic_s {
 615         uint32_t                en_magic;
 616         efx_family_t            en_family;
 617         uint32_t                en_features;
 618         efsys_identifier_t      *en_esip;
 619         efsys_lock_t            *en_eslp;
 620         efsys_bar_t             *en_esbp;
 621         unsigned int            en_mod_flags;
 622         unsigned int            en_reset_flags;
 623         efx_nic_cfg_t           en_nic_cfg;
 624         efx_drv_cfg_t           en_drv_cfg;
 625         efx_port_t              en_port;
 626         efx_mon_t               en_mon;
 627         efx_intr_t              en_intr;
 628         uint32_t                en_ev_qcount;
 629         uint32_t                en_rx_qcount;
 630         uint32_t                en_tx_qcount;
 631         const efx_nic_ops_t     *en_enop;
 632         const efx_ev_ops_t      *en_eevop;
 633         const efx_tx_ops_t      *en_etxop;
 634         const efx_rx_ops_t      *en_erxop;
 635 #if EFSYS_OPT_FILTER
 636         efx_filter_t            en_filter;
 637         const efx_filter_ops_t  *en_efop;
 638 #endif  /* EFSYS_OPT_FILTER */
 639 #if EFSYS_OPT_MCDI
 640         efx_mcdi_t              en_mcdi;
 641 #endif  /* EFSYS_OPT_MCDI */
 642 #if EFSYS_OPT_NVRAM
 643         efx_nvram_type_t        en_nvram_locked;
 644         const efx_nvram_ops_t   *en_envop;
 645 #endif  /* EFSYS_OPT_NVRAM */
 646 #if EFSYS_OPT_VPD
 647         const efx_vpd_ops_t     *en_evpdop;
 648 #endif  /* EFSYS_OPT_VPD */
 649 #if EFSYS_OPT_RX_SCALE
 650         efx_rx_hash_support_t   en_hash_support;
 651         efx_rx_scale_support_t  en_rss_support;
 652         uint32_t                en_rss_context;
 653 #endif  /* EFSYS_OPT_RX_SCALE */
 654         uint32_t                en_vport_id;
 655 #if EFSYS_OPT_LICENSING
 656         const efx_lic_ops_t     *en_elop;
 657         boolean_t               en_licensing_supported;
 658 #endif
 659         union {
 660 #if EFSYS_OPT_SIENA
 661                 struct {
 662 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 663                         unsigned int            enu_partn_mask;
 664 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 665 #if EFSYS_OPT_VPD
 666                         caddr_t                 enu_svpd;
 667                         size_t                  enu_svpd_length;
 668 #endif  /* EFSYS_OPT_VPD */
 669                         int                     enu_unused;
 670                 } siena;
 671 #endif  /* EFSYS_OPT_SIENA */
 672                 int     enu_unused;
 673         } en_u;
 674 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
 675         union en_arch {
 676                 struct {
 677                         int                     ena_vi_base;
 678                         int                     ena_vi_count;
 679                         int                     ena_vi_shift;
 680 #if EFSYS_OPT_VPD
 681                         caddr_t                 ena_svpd;
 682                         size_t                  ena_svpd_length;
 683 #endif  /* EFSYS_OPT_VPD */
 684                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 685                         uint32_t                ena_piobuf_count;
 686                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 687                         uint32_t                ena_pio_write_vi_base;
 688                         /* Memory BAR mapping regions */
 689                         uint32_t                ena_uc_mem_map_offset;
 690                         size_t                  ena_uc_mem_map_size;
 691                         uint32_t                ena_wc_mem_map_offset;
 692                         size_t                  ena_wc_mem_map_size;
 693                 } ef10;
 694         } en_arch;
 695 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
 696 };
 697
 698
 699 #define EFX_NIC_MAGIC   0x02121996
 700
 701 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 702     const efx_ev_callbacks_t *, void *);
 703
 704 typedef struct efx_evq_rxq_state_s {
 705         unsigned int                    eers_rx_read_ptr;
 706         unsigned int                    eers_rx_mask;
 707 #if EFSYS_OPT_RX_PACKED_STREAM
 708         unsigned int                    eers_rx_stream_npackets;
 709         boolean_t                       eers_rx_packed_stream;
 710         unsigned int                    eers_rx_packed_stream_credits;
 711 #endif
 712 } efx_evq_rxq_state_t;
 713
 714 struct efx_evq_s {
 715         uint32_t                        ee_magic;
 716         efx_nic_t                       *ee_enp;
 717         unsigned int                    ee_index;
 718         unsigned int                    ee_mask;
 719         efsys_mem_t                     *ee_esmp;
 720 #if EFSYS_OPT_QSTATS
 721         uint32_t                        ee_stat[EV_NQSTATS];
 722 #endif  /* EFSYS_OPT_QSTATS */
 723
 724         efx_ev_handler_t                ee_rx;
 725         efx_ev_handler_t                ee_tx;
 726         efx_ev_handler_t                ee_driver;
 727         efx_ev_handler_t                ee_global;
 728         efx_ev_handler_t                ee_drv_gen;
 729 #if EFSYS_OPT_MCDI
 730         efx_ev_handler_t                ee_mcdi;
 731 #endif  /* EFSYS_OPT_MCDI */
 732
 733         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 734
 735         uint32_t                        ee_flags;
 736 };
 737
 738 #define EFX_EVQ_MAGIC   0x08081997
 739
 740 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 741
 742 struct efx_rxq_s {
 743         uint32_t                        er_magic;
 744         efx_nic_t                       *er_enp;
 745         efx_evq_t                       *er_eep;
 746         unsigned int                    er_index;
 747         unsigned int                    er_label;
 748         unsigned int                    er_mask;
 749         efsys_mem_t                     *er_esmp;
 750 };
 751
 752 #define EFX_RXQ_MAGIC   0x15022005
 753
 754 struct efx_txq_s {
 755         uint32_t                        et_magic;
 756         efx_nic_t                       *et_enp;
 757         unsigned int                    et_index;
 758         unsigned int                    et_mask;
 759         efsys_mem_t                     *et_esmp;
 760 #if EFSYS_OPT_HUNTINGTON
 761         uint32_t                        et_pio_bufnum;
 762         uint32_t                        et_pio_blknum;
 763         uint32_t                        et_pio_write_offset;
 764         uint32_t                        et_pio_offset;
 765         size_t                          et_pio_size;
 766 #endif
 767 #if EFSYS_OPT_QSTATS
 768         uint32_t                        et_stat[TX_NQSTATS];
 769 #endif  /* EFSYS_OPT_QSTATS */
 770 };
 771
 772 #define EFX_TXQ_MAGIC   0x05092005
 773
 774 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 775         do {                                                            \
 776                 (_dst)[0] = (_src)[0];                                  \
 777                 (_dst)[1] = (_src)[1];                                  \
 778                 (_dst)[2] = (_src)[2];                                  \
 779                 (_dst)[3] = (_src)[3];                                  \
 780                 (_dst)[4] = (_src)[4];                                  \
 781                 (_dst)[5] = (_src)[5];                                  \
 782         _NOTE(CONSTANTCONDITION)                                        \
 783         } while (B_FALSE)
 784
 785 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 786         do {                                                            \
 787                 uint16_t *_d = (uint16_t *)(_dst);                      \
 788                 _d[0] = 0xffff;                                         \
 789                 _d[1] = 0xffff;                                         \
 790                 _d[2] = 0xffff;                                         \
 791         _NOTE(CONSTANTCONDITION)                                        \
 792         } while (B_FALSE)
 793
 794 #if EFSYS_OPT_CHECK_REG
 795 #define EFX_CHECK_REG(_enp, _reg)                                       \
 796         do {                                                            \
 797                 const char *name = #_reg;                               \
 798                 char min = name[4];                                     \
 799                 char max = name[5];                                     \
 800                 char rev;                                               \
 801                                                                         \
 802                 switch ((_enp)->en_family) {                            \
 803                 case EFX_FAMILY_SIENA:                                  \
 804                         rev = 'C';                                      \
 805                         break;                                          \
 806                                                                         \
 807                 case EFX_FAMILY_HUNTINGTON:                             \
 808                         rev = 'D';                                      \
 809                         break;                                          \
 810                                                                         \
 811                 case EFX_FAMILY_MEDFORD:                                \
 812                         rev = 'E';                                      \
 813                         break;                                          \
 814                                                                         \
 815                 default:                                                \
 816                         rev = '?';                                      \
 817                         break;                                          \
 818                 }                                                       \
 819                                                                         \
 820                 EFSYS_ASSERT3S(rev, >=, min);                           \
 821                 EFSYS_ASSERT3S(rev, <=, max);                           \
 822                                                                         \
 823         _NOTE(CONSTANTCONDITION)                                        \
 824         } while (B_FALSE)
 825 #else
 826 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 827         _NOTE(CONSTANTCONDITION)                                        \
 828         } while (B_FALSE)
 829 #endif
 830
 831 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 832         do {                                                            \
 833                 EFX_CHECK_REG((_enp), (_reg));                          \
 834                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 835                     (_edp), (_lock));                                   \
 836                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 837                     uint32_t, _reg ## _OFST,                            \
 838                     uint32_t, (_edp)->ed_u32[0]);                       \
 839         _NOTE(CONSTANTCONDITION)                                        \
 840         } while (B_FALSE)
 841
 842 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 843         do {                                                            \
 844                 EFX_CHECK_REG((_enp), (_reg));                          \
 845                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 846                     uint32_t, _reg ## _OFST,                            \
 847                     uint32_t, (_edp)->ed_u32[0]);                       \
 848                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 849                     (_edp), (_lock));                                   \
 850         _NOTE(CONSTANTCONDITION)                                        \
 851         } while (B_FALSE)
 852
 853 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 854         do {                                                            \
 855                 EFX_CHECK_REG((_enp), (_reg));                          \
 856                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 857                     (_eqp));                                            \
 858                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 859                     uint32_t, _reg ## _OFST,                            \
 860                     uint32_t, (_eqp)->eq_u32[1],                        \
 861                     uint32_t, (_eqp)->eq_u32[0]);                       \
 862         _NOTE(CONSTANTCONDITION)                                        \
 863         } while (B_FALSE)
 864
 865 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 866         do {                                                            \
 867                 EFX_CHECK_REG((_enp), (_reg));                          \
 868                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 869                     uint32_t, _reg ## _OFST,                            \
 870                     uint32_t, (_eqp)->eq_u32[1],                        \
 871                     uint32_t, (_eqp)->eq_u32[0]);                       \
 872                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 873                     (_eqp));                                            \
 874         _NOTE(CONSTANTCONDITION)                                        \
 875         } while (B_FALSE)
 876
 877 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 878         do {                                                            \
 879                 EFX_CHECK_REG((_enp), (_reg));                          \
 880                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 881                     (_eop), B_TRUE);                                    \
 882                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 883                     uint32_t, _reg ## _OFST,                            \
 884                     uint32_t, (_eop)->eo_u32[3],                        \
 885                     uint32_t, (_eop)->eo_u32[2],                        \
 886                     uint32_t, (_eop)->eo_u32[1],                        \
 887                     uint32_t, (_eop)->eo_u32[0]);                       \
 888         _NOTE(CONSTANTCONDITION)                                        \
 889         } while (B_FALSE)
 890
 891 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 892         do {                                                            \
 893                 EFX_CHECK_REG((_enp), (_reg));                          \
 894                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 895                     uint32_t, _reg ## _OFST,                            \
 896                     uint32_t, (_eop)->eo_u32[3],                        \
 897                     uint32_t, (_eop)->eo_u32[2],                        \
 898                     uint32_t, (_eop)->eo_u32[1],                        \
 899                     uint32_t, (_eop)->eo_u32[0]);                       \
 900                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 901                     (_eop), B_TRUE);                                    \
 902         _NOTE(CONSTANTCONDITION)                                        \
 903         } while (B_FALSE)
 904
 905 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 906         do {                                                            \
 907                 EFX_CHECK_REG((_enp), (_reg));                          \
 908                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 909                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 910                     (_edp), (_lock));                                   \
 911                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 912                     uint32_t, (_index),                                 \
 913                     uint32_t, _reg ## _OFST,                            \
 914                     uint32_t, (_edp)->ed_u32[0]);                       \
 915         _NOTE(CONSTANTCONDITION)                                        \
 916         } while (B_FALSE)
 917
 918 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
 919         do {                                                            \
 920                 EFX_CHECK_REG((_enp), (_reg));                          \
 921                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 922                     uint32_t, (_index),                                 \
 923                     uint32_t, _reg ## _OFST,                            \
 924                     uint32_t, (_edp)->ed_u32[0]);                       \
 925                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 926                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 927                     (_edp), (_lock));                                   \
 928         _NOTE(CONSTANTCONDITION)                                        \
 929         } while (B_FALSE)
 930
 931 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)            \
 932         do {                                                            \
 933                 EFX_CHECK_REG((_enp), (_reg));                          \
 934                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 935                     uint32_t, (_index),                                 \
 936                     uint32_t, _reg ## _OFST,                            \
 937                     uint32_t, (_edp)->ed_u32[0]);                       \
 938                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 939                     (_reg ## _OFST +                                    \
 940                     (2 * sizeof (efx_dword_t)) +                        \
 941                     ((_index) * _reg ## _STEP)),                        \
 942                     (_edp), (_lock));                                   \
 943         _NOTE(CONSTANTCONDITION)                                        \
 944         } while (B_FALSE)
 945
 946 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
 947         do {                                                            \
 948                 EFX_CHECK_REG((_enp), (_reg));                          \
 949                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 950                     uint32_t, (_index),                                 \
 951                     uint32_t, _reg ## _OFST,                            \
 952                     uint32_t, (_edp)->ed_u32[0]);                       \
 953                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 954                     (_reg ## _OFST +                                    \
 955                     (3 * sizeof (efx_dword_t)) +                        \
 956                     ((_index) * _reg ## _STEP)),                        \
 957                     (_edp), (_lock));                                   \
 958         _NOTE(CONSTANTCONDITION)                                        \
 959         } while (B_FALSE)
 960
 961 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
 962         do {                                                            \
 963                 EFX_CHECK_REG((_enp), (_reg));                          \
 964                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
 965                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 966                     (_eqp));                                            \
 967                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
 968                     uint32_t, (_index),                                 \
 969                     uint32_t, _reg ## _OFST,                            \
 970                     uint32_t, (_eqp)->eq_u32[1],                        \
 971                     uint32_t, (_eqp)->eq_u32[0]);                       \
 972         _NOTE(CONSTANTCONDITION)                                        \
 973         } while (B_FALSE)
 974
 975 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
 976         do {                                                            \
 977                 EFX_CHECK_REG((_enp), (_reg));                          \
 978                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
 979                     uint32_t, (_index),                                 \
 980                     uint32_t, _reg ## _OFST,                            \
 981                     uint32_t, (_eqp)->eq_u32[1],                        \
 982                     uint32_t, (_eqp)->eq_u32[0]);                       \
 983                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
 984                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 985                     (_eqp));                                            \
 986         _NOTE(CONSTANTCONDITION)                                        \
 987         } while (B_FALSE)
 988
 989 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
 990         do {                                                            \
 991                 EFX_CHECK_REG((_enp), (_reg));                          \
 992                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
 993                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 994                     (_eop), (_lock));                                   \
 995                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
 996                     uint32_t, (_index),                                 \
 997                     uint32_t, _reg ## _OFST,                            \
 998                     uint32_t, (_eop)->eo_u32[3],                        \
 999                     uint32_t, (_eop)->eo_u32[2],                        \
1000                     uint32_t, (_eop)->eo_u32[1],                        \
1001                     uint32_t, (_eop)->eo_u32[0]);                       \
1002         _NOTE(CONSTANTCONDITION)                                        \
1003         } while (B_FALSE)
1004
1005 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
1006         do {                                                            \
1007                 EFX_CHECK_REG((_enp), (_reg));                          \
1008                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
1009                     uint32_t, (_index),                                 \
1010                     uint32_t, _reg ## _OFST,                            \
1011                     uint32_t, (_eop)->eo_u32[3],                        \
1012                     uint32_t, (_eop)->eo_u32[2],                        \
1013                     uint32_t, (_eop)->eo_u32[1],                        \
1014                     uint32_t, (_eop)->eo_u32[0]);                       \
1015                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
1016                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1017                     (_eop), (_lock));                                   \
1018         _NOTE(CONSTANTCONDITION)                                        \
1019         } while (B_FALSE)
1020
1021 /*
1022  * Allow drivers to perform optimised 128-bit doorbell writes.
1023  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1024  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1025  * the need for locking in the host, and are the only ones known to be safe to
1026  * use 128-bites write with.
1027  */
1028 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)           \
1029         do {                                                            \
1030                 EFX_CHECK_REG((_enp), (_reg));                          \
1031                 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,               \
1032                     const char *,                                       \
1033                     #_reg,                                              \
1034                     uint32_t, (_index),                                 \
1035                     uint32_t, _reg ## _OFST,                            \
1036                     uint32_t, (_eop)->eo_u32[3],                        \
1037                     uint32_t, (_eop)->eo_u32[2],                        \
1038                     uint32_t, (_eop)->eo_u32[1],                        \
1039                     uint32_t, (_eop)->eo_u32[0]);                       \
1040                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1041                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1042                     (_eop));                                            \
1043         _NOTE(CONSTANTCONDITION)                                        \
1044         } while (B_FALSE)
1045
1046 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1047         do {                                                            \
1048                 unsigned int _new = (_wptr);                            \
1049                 unsigned int _old = (_owptr);                           \
1050                                                                         \
1051                 if ((_new) >= (_old))                                   \
1052                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1053                             (_old) * sizeof (efx_desc_t),               \
1054                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1055                 else                                                    \
1056                         /*                                              \
1057                          * It is cheaper to sync entire map than sync   \
1058                          * two parts especially when offset/size are    \
1059                          * ignored and entire map is synced in any case.\
1060                          */                                             \
1061                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1062                             0,                                          \
1063                             (_entries) * sizeof (efx_desc_t));          \
1064         _NOTE(CONSTANTCONDITION)                                        \
1065         } while (B_FALSE)
1066
1067 extern  __checkReturn   efx_rc_t
1068 efx_nic_biu_test(
1069         __in            efx_nic_t *enp);
1070
1071 extern  __checkReturn   efx_rc_t
1072 efx_mac_select(
1073         __in            efx_nic_t *enp);
1074
1075 extern  void
1076 efx_mac_multicast_hash_compute(
1077         __in_ecount(6*count)            uint8_t const *addrs,
1078         __in                            int count,
1079         __out                           efx_oword_t *hash_low,
1080         __out                           efx_oword_t *hash_high);
1081
1082 extern  __checkReturn   efx_rc_t
1083 efx_phy_probe(
1084         __in            efx_nic_t *enp);
1085
1086 extern                  void
1087 efx_phy_unprobe(
1088         __in            efx_nic_t *enp);
1089
1090 #if EFSYS_OPT_VPD
1091
1092 /* VPD utility functions */
1093
1094 extern  __checkReturn           efx_rc_t
1095 efx_vpd_hunk_length(
1096         __in_bcount(size)       caddr_t data,
1097         __in                    size_t size,
1098         __out                   size_t *lengthp);
1099
1100 extern  __checkReturn           efx_rc_t
1101 efx_vpd_hunk_verify(
1102         __in_bcount(size)       caddr_t data,
1103         __in                    size_t size,
1104         __out_opt               boolean_t *cksummedp);
1105
1106 extern  __checkReturn           efx_rc_t
1107 efx_vpd_hunk_reinit(
1108         __in_bcount(size)       caddr_t data,
1109         __in                    size_t size,
1110         __in                    boolean_t wantpid);
1111
1112 extern  __checkReturn           efx_rc_t
1113 efx_vpd_hunk_get(
1114         __in_bcount(size)       caddr_t data,
1115         __in                    size_t size,
1116         __in                    efx_vpd_tag_t tag,
1117         __in                    efx_vpd_keyword_t keyword,
1118         __out                   unsigned int *payloadp,
1119         __out                   uint8_t *paylenp);
1120
1121 extern  __checkReturn                   efx_rc_t
1122 efx_vpd_hunk_next(
1123         __in_bcount(size)               caddr_t data,
1124         __in                            size_t size,
1125         __out                           efx_vpd_tag_t *tagp,
1126         __out                           efx_vpd_keyword_t *keyword,
1127         __out_opt                       unsigned int *payloadp,
1128         __out_opt                       uint8_t *paylenp,
1129         __inout                         unsigned int *contp);
1130
1131 extern  __checkReturn           efx_rc_t
1132 efx_vpd_hunk_set(
1133         __in_bcount(size)       caddr_t data,
1134         __in                    size_t size,
1135         __in                    efx_vpd_value_t *evvp);
1136
1137 #endif  /* EFSYS_OPT_VPD */
1138
1139 #if EFSYS_OPT_DIAG
1140
1141 extern  efx_sram_pattern_fn_t   __efx_sram_pattern_fns[];
1142
1143 typedef struct efx_register_set_s {
1144         unsigned int            address;
1145         unsigned int            step;
1146         unsigned int            rows;
1147         efx_oword_t             mask;
1148 } efx_register_set_t;
1149
1150 extern  __checkReturn   efx_rc_t
1151 efx_nic_test_registers(
1152         __in            efx_nic_t *enp,
1153         __in            efx_register_set_t *rsp,
1154         __in            size_t count);
1155
1156 extern  __checkReturn   efx_rc_t
1157 efx_nic_test_tables(
1158         __in            efx_nic_t *enp,
1159         __in            efx_register_set_t *rsp,
1160         __in            efx_pattern_type_t pattern,
1161         __in            size_t count);
1162
1163 #endif  /* EFSYS_OPT_DIAG */
1164
1165 #if EFSYS_OPT_MCDI
1166
1167 extern  __checkReturn           efx_rc_t
1168 efx_mcdi_set_workaround(
1169         __in                    efx_nic_t *enp,
1170         __in                    uint32_t type,
1171         __in                    boolean_t enabled,
1172         __out_opt               uint32_t *flagsp);
1173
1174 extern  __checkReturn           efx_rc_t
1175 efx_mcdi_get_workarounds(
1176         __in                    efx_nic_t *enp,
1177         __out_opt               uint32_t *implementedp,
1178         __out_opt               uint32_t *enabledp);
1179
1180 #endif /* EFSYS_OPT_MCDI */
1181
1182 #if EFSYS_OPT_MAC_STATS
1183
1184 /*
1185  * Closed range of stats (i.e. the first and the last are included).
1186  * The last must be greater or equal (if the range is one item only) to
1187  * the first.
1188  */
1189 struct efx_mac_stats_range {
1190         efx_mac_stat_t          first;
1191         efx_mac_stat_t          last;
1192 };
1193
1194 extern                                  efx_rc_t
1195 efx_mac_stats_mask_add_ranges(
1196         __inout_bcount(mask_size)       uint32_t *maskp,
1197         __in                            size_t mask_size,
1198         __in_ecount(rng_count)          const struct efx_mac_stats_range *rngp,
1199         __in                            unsigned int rng_count);
1200
1201 #endif  /* EFSYS_OPT_MAC_STATS */
1202
1203 #ifdef  __cplusplus
1204 }
1205 #endif
1206
1207 #endif  /* _SYS_EFX_IMPL_H */