drivers/net/sfc/base/efx_impl.h

   1 /*
   2  * Copyright (c) 2007-2016 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  */
  30
  31 #ifndef _SYS_EFX_IMPL_H
  32 #define _SYS_EFX_IMPL_H
  33
  34 #include "efx.h"
  35 #include "efx_regs.h"
  36 #include "efx_regs_ef10.h"
  37
  38 /* FIXME: Add definition for driver generated software events */
  39 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  40 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  41 #endif
  42
  43
  44 #if EFSYS_OPT_SIENA
  45 #include "siena_impl.h"
  46 #endif  /* EFSYS_OPT_SIENA */
  47
  48 #if EFSYS_OPT_HUNTINGTON
  49 #include "hunt_impl.h"
  50 #endif  /* EFSYS_OPT_HUNTINGTON */
  51
  52 #if EFSYS_OPT_MEDFORD
  53 #include "medford_impl.h"
  54 #endif  /* EFSYS_OPT_MEDFORD */
  55
  56 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
  57 #include "ef10_impl.h"
  58 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
  59
  60 #ifdef  __cplusplus
  61 extern "C" {
  62 #endif
  63
  64 #define EFX_MOD_MCDI            0x00000001
  65 #define EFX_MOD_PROBE           0x00000002
  66 #define EFX_MOD_NVRAM           0x00000004
  67 #define EFX_MOD_VPD             0x00000008
  68 #define EFX_MOD_NIC             0x00000010
  69 #define EFX_MOD_INTR            0x00000020
  70 #define EFX_MOD_EV              0x00000040
  71 #define EFX_MOD_RX              0x00000080
  72 #define EFX_MOD_TX              0x00000100
  73 #define EFX_MOD_PORT            0x00000200
  74 #define EFX_MOD_MON             0x00000400
  75 #define EFX_MOD_FILTER          0x00001000
  76 #define EFX_MOD_LIC             0x00002000
  77
  78 #define EFX_RESET_PHY           0x00000001
  79 #define EFX_RESET_RXQ_ERR       0x00000002
  80 #define EFX_RESET_TXQ_ERR       0x00000004
  81
  82 typedef enum efx_mac_type_e {
  83         EFX_MAC_INVALID = 0,
  84         EFX_MAC_SIENA,
  85         EFX_MAC_HUNTINGTON,
  86         EFX_MAC_MEDFORD,
  87         EFX_MAC_NTYPES
  88 } efx_mac_type_t;
  89
  90 typedef struct efx_ev_ops_s {
  91         efx_rc_t        (*eevo_init)(efx_nic_t *);
  92         void            (*eevo_fini)(efx_nic_t *);
  93         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  94                                           efsys_mem_t *, size_t, uint32_t,
  95                                           uint32_t, uint32_t, efx_evq_t *);
  96         void            (*eevo_qdestroy)(efx_evq_t *);
  97         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  98         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  99         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
 100 #if EFSYS_OPT_QSTATS
 101         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
 102 #endif
 103 } efx_ev_ops_t;
 104
 105 typedef struct efx_tx_ops_s {
 106         efx_rc_t        (*etxo_init)(efx_nic_t *);
 107         void            (*etxo_fini)(efx_nic_t *);
 108         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 109                                         unsigned int, unsigned int,
 110                                         efsys_mem_t *, size_t,
 111                                         uint32_t, uint16_t,
 112                                         efx_evq_t *, efx_txq_t *,
 113                                         unsigned int *);
 114         void            (*etxo_qdestroy)(efx_txq_t *);
 115         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 116                                       unsigned int, unsigned int,
 117                                       unsigned int *);
 118         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 119         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 120         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 121         void            (*etxo_qenable)(efx_txq_t *);
 122         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 123         void            (*etxo_qpio_disable)(efx_txq_t *);
 124         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 125                                            size_t);
 126         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 127                                            unsigned int *);
 128         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 129                                       unsigned int, unsigned int,
 130                                       unsigned int *);
 131         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 132                                                 size_t, boolean_t,
 133                                                 efx_desc_t *);
 134         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 135                                                 uint32_t, uint8_t,
 136                                                 efx_desc_t *);
 137         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 138                                                 uint32_t, uint16_t,
 139                                                 efx_desc_t *, int);
 140         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 141                                                 efx_desc_t *);
 142 #if EFSYS_OPT_QSTATS
 143         void            (*etxo_qstats_update)(efx_txq_t *,
 144                                               efsys_stat_t *);
 145 #endif
 146 } efx_tx_ops_t;
 147
 148 typedef struct efx_rx_ops_s {
 149         efx_rc_t        (*erxo_init)(efx_nic_t *);
 150         void            (*erxo_fini)(efx_nic_t *);
 151 #if EFSYS_OPT_RX_SCATTER
 152         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 153 #endif
 154         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 155                                               uint16_t *);
 156         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 157                                       unsigned int, unsigned int,
 158                                       unsigned int);
 159         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 160         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 161         void            (*erxo_qenable)(efx_rxq_t *);
 162         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 163                                         unsigned int, efx_rxq_type_t,
 164                                         efsys_mem_t *, size_t, uint32_t,
 165                                         efx_evq_t *, efx_rxq_t *);
 166         void            (*erxo_qdestroy)(efx_rxq_t *);
 167 } efx_rx_ops_t;
 168
 169 typedef struct efx_mac_ops_s {
 170         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 171         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 172         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 173         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 174         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 175         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 176         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 177         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 178                                                       efx_rxq_t *, boolean_t);
 179         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 180 #if EFSYS_OPT_MAC_STATS
 181         efx_rc_t        (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
 182         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 183         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 184                                               uint16_t, boolean_t);
 185         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 186                                             efsys_stat_t *, uint32_t *);
 187 #endif  /* EFSYS_OPT_MAC_STATS */
 188 } efx_mac_ops_t;
 189
 190 typedef struct efx_phy_ops_s {
 191         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 192         efx_rc_t        (*epo_reset)(efx_nic_t *);
 193         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 194         efx_rc_t        (*epo_verify)(efx_nic_t *);
 195         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 196 #if EFSYS_OPT_PHY_STATS
 197         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 198                                             uint32_t *);
 199 #endif  /* EFSYS_OPT_PHY_STATS */
 200 #if EFSYS_OPT_BIST
 201         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 202         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 203         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 204                                          efx_bist_result_t *, uint32_t *,
 205                                          unsigned long *, size_t);
 206         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 207 #endif  /* EFSYS_OPT_BIST */
 208 } efx_phy_ops_t;
 209
 210 #if EFSYS_OPT_FILTER
 211 typedef struct efx_filter_ops_s {
 212         efx_rc_t        (*efo_init)(efx_nic_t *);
 213         void            (*efo_fini)(efx_nic_t *);
 214         efx_rc_t        (*efo_restore)(efx_nic_t *);
 215         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 216                                    boolean_t may_replace);
 217         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 218         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
 219         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 220                                    boolean_t, boolean_t, boolean_t,
 221                                    uint8_t const *, uint32_t);
 222 } efx_filter_ops_t;
 223
 224 extern  __checkReturn   efx_rc_t
 225 efx_filter_reconfigure(
 226         __in                            efx_nic_t *enp,
 227         __in_ecount(6)                  uint8_t const *mac_addr,
 228         __in                            boolean_t all_unicst,
 229         __in                            boolean_t mulcst,
 230         __in                            boolean_t all_mulcst,
 231         __in                            boolean_t brdcst,
 232         __in_ecount(6*count)            uint8_t const *addrs,
 233         __in                            uint32_t count);
 234
 235 #endif /* EFSYS_OPT_FILTER */
 236
 237
 238 typedef struct efx_port_s {
 239         efx_mac_type_t          ep_mac_type;
 240         uint32_t                ep_phy_type;
 241         uint8_t                 ep_port;
 242         uint32_t                ep_mac_pdu;
 243         uint8_t                 ep_mac_addr[6];
 244         efx_link_mode_t         ep_link_mode;
 245         boolean_t               ep_all_unicst;
 246         boolean_t               ep_mulcst;
 247         boolean_t               ep_all_mulcst;
 248         boolean_t               ep_brdcst;
 249         unsigned int            ep_fcntl;
 250         boolean_t               ep_fcntl_autoneg;
 251         efx_oword_t             ep_multicst_hash[2];
 252         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 253                                                     EFX_MAC_MULTICAST_LIST_MAX];
 254         uint32_t                ep_mulcst_addr_count;
 255 #if EFSYS_OPT_PHY_FLAGS
 256         uint32_t                ep_phy_flags;
 257 #endif  /* EFSYS_OPT_PHY_FLAGS */
 258 #if EFSYS_OPT_PHY_LED_CONTROL
 259         efx_phy_led_mode_t      ep_phy_led_mode;
 260 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 261         efx_phy_media_type_t    ep_fixed_port_type;
 262         efx_phy_media_type_t    ep_module_type;
 263         uint32_t                ep_adv_cap_mask;
 264         uint32_t                ep_lp_cap_mask;
 265         uint32_t                ep_default_adv_cap_mask;
 266         uint32_t                ep_phy_cap_mask;
 267         boolean_t               ep_mac_drain;
 268         boolean_t               ep_mac_stats_pending;
 269 #if EFSYS_OPT_BIST
 270         efx_bist_type_t         ep_current_bist;
 271 #endif
 272         const efx_mac_ops_t     *ep_emop;
 273         const efx_phy_ops_t     *ep_epop;
 274 } efx_port_t;
 275
 276 typedef struct efx_mon_ops_s {
 277 } efx_mon_ops_t;
 278
 279 typedef struct efx_mon_s {
 280         efx_mon_type_t          em_type;
 281         const efx_mon_ops_t     *em_emop;
 282 } efx_mon_t;
 283
 284 typedef struct efx_intr_ops_s {
 285         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 286         void            (*eio_enable)(efx_nic_t *);
 287         void            (*eio_disable)(efx_nic_t *);
 288         void            (*eio_disable_unlocked)(efx_nic_t *);
 289         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 290         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 291         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 292                                  boolean_t *);
 293         void            (*eio_fatal)(efx_nic_t *);
 294         void            (*eio_fini)(efx_nic_t *);
 295 } efx_intr_ops_t;
 296
 297 typedef struct efx_intr_s {
 298         const efx_intr_ops_t    *ei_eiop;
 299         efsys_mem_t             *ei_esmp;
 300         efx_intr_type_t         ei_type;
 301         unsigned int            ei_level;
 302 } efx_intr_t;
 303
 304 typedef struct efx_nic_ops_s {
 305         efx_rc_t        (*eno_probe)(efx_nic_t *);
 306         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 307         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 308         efx_rc_t        (*eno_reset)(efx_nic_t *);
 309         efx_rc_t        (*eno_init)(efx_nic_t *);
 310         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 311         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 312                                         uint32_t *, size_t *);
 313 #if EFSYS_OPT_DIAG
 314         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 315 #endif  /* EFSYS_OPT_DIAG */
 316         void            (*eno_fini)(efx_nic_t *);
 317         void            (*eno_unprobe)(efx_nic_t *);
 318 } efx_nic_ops_t;
 319
 320 #ifndef EFX_TXQ_LIMIT_TARGET
 321 #define EFX_TXQ_LIMIT_TARGET 259
 322 #endif
 323 #ifndef EFX_RXQ_LIMIT_TARGET
 324 #define EFX_RXQ_LIMIT_TARGET 512
 325 #endif
 326 #ifndef EFX_TXQ_DC_SIZE
 327 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
 328 #endif
 329 #ifndef EFX_RXQ_DC_SIZE
 330 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
 331 #endif
 332
 333 #if EFSYS_OPT_FILTER
 334
 335 #if EFSYS_OPT_SIENA
 336
 337 typedef struct siena_filter_spec_s {
 338         uint8_t         sfs_type;
 339         uint32_t        sfs_flags;
 340         uint32_t        sfs_dmaq_id;
 341         uint32_t        sfs_dword[3];
 342 } siena_filter_spec_t;
 343
 344 typedef enum siena_filter_type_e {
 345         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 346         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 347         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 348         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 349         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 350         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 351
 352         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 353         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 354         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 355         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 356         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 357         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 358
 359         EFX_SIENA_FILTER_NTYPES
 360 } siena_filter_type_t;
 361
 362 typedef enum siena_filter_tbl_id_e {
 363         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 364         EFX_SIENA_FILTER_TBL_RX_MAC,
 365         EFX_SIENA_FILTER_TBL_TX_IP,
 366         EFX_SIENA_FILTER_TBL_TX_MAC,
 367         EFX_SIENA_FILTER_NTBLS
 368 } siena_filter_tbl_id_t;
 369
 370 typedef struct siena_filter_tbl_s {
 371         int                     sft_size;       /* number of entries */
 372         int                     sft_used;       /* active count */
 373         uint32_t                *sft_bitmap;    /* active bitmap */
 374         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 375 } siena_filter_tbl_t;
 376
 377 typedef struct siena_filter_s {
 378         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 379         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 380 } siena_filter_t;
 381
 382 #endif  /* EFSYS_OPT_SIENA */
 383
 384 typedef struct efx_filter_s {
 385 #if EFSYS_OPT_SIENA
 386         siena_filter_t          *ef_siena_filter;
 387 #endif /* EFSYS_OPT_SIENA */
 388 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 389         ef10_filter_table_t     *ef_ef10_filter_table;
 390 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 391 } efx_filter_t;
 392
 393 #if EFSYS_OPT_SIENA
 394
 395 extern                  void
 396 siena_filter_tbl_clear(
 397         __in            efx_nic_t *enp,
 398         __in            siena_filter_tbl_id_t tbl);
 399
 400 #endif  /* EFSYS_OPT_SIENA */
 401
 402 #endif  /* EFSYS_OPT_FILTER */
 403
 404 #if EFSYS_OPT_MCDI
 405
 406 typedef struct efx_mcdi_ops_s {
 407         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 408         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 409                                         void *, size_t);
 410         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 411         boolean_t       (*emco_poll_response)(efx_nic_t *);
 412         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 413         void            (*emco_fini)(efx_nic_t *);
 414         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 415                                             efx_mcdi_feature_id_t, boolean_t *);
 416         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 417                                             uint32_t *);
 418 } efx_mcdi_ops_t;
 419
 420 typedef struct efx_mcdi_s {
 421         const efx_mcdi_ops_t            *em_emcop;
 422         const efx_mcdi_transport_t      *em_emtp;
 423         efx_mcdi_iface_t                em_emip;
 424 } efx_mcdi_t;
 425
 426 #endif /* EFSYS_OPT_MCDI */
 427
 428 typedef struct efx_drv_cfg_s {
 429         uint32_t                edc_min_vi_count;
 430         uint32_t                edc_max_vi_count;
 431
 432         uint32_t                edc_max_piobuf_count;
 433         uint32_t                edc_pio_alloc_size;
 434 } efx_drv_cfg_t;
 435
 436 struct efx_nic_s {
 437         uint32_t                en_magic;
 438         efx_family_t            en_family;
 439         uint32_t                en_features;
 440         efsys_identifier_t      *en_esip;
 441         efsys_lock_t            *en_eslp;
 442         efsys_bar_t             *en_esbp;
 443         unsigned int            en_mod_flags;
 444         unsigned int            en_reset_flags;
 445         efx_nic_cfg_t           en_nic_cfg;
 446         efx_drv_cfg_t           en_drv_cfg;
 447         efx_port_t              en_port;
 448         efx_mon_t               en_mon;
 449         efx_intr_t              en_intr;
 450         uint32_t                en_ev_qcount;
 451         uint32_t                en_rx_qcount;
 452         uint32_t                en_tx_qcount;
 453         const efx_nic_ops_t     *en_enop;
 454         const efx_ev_ops_t      *en_eevop;
 455         const efx_tx_ops_t      *en_etxop;
 456         const efx_rx_ops_t      *en_erxop;
 457 #if EFSYS_OPT_FILTER
 458         efx_filter_t            en_filter;
 459         const efx_filter_ops_t  *en_efop;
 460 #endif  /* EFSYS_OPT_FILTER */
 461 #if EFSYS_OPT_MCDI
 462         efx_mcdi_t              en_mcdi;
 463 #endif  /* EFSYS_OPT_MCDI */
 464         uint32_t                en_vport_id;
 465         union {
 466 #if EFSYS_OPT_SIENA
 467                 struct {
 468                         int                     enu_unused;
 469                 } siena;
 470 #endif  /* EFSYS_OPT_SIENA */
 471                 int     enu_unused;
 472         } en_u;
 473 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
 474         union en_arch {
 475                 struct {
 476                         int                     ena_vi_base;
 477                         int                     ena_vi_count;
 478                         int                     ena_vi_shift;
 479                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 480                         uint32_t                ena_piobuf_count;
 481                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 482                         uint32_t                ena_pio_write_vi_base;
 483                         /* Memory BAR mapping regions */
 484                         uint32_t                ena_uc_mem_map_offset;
 485                         size_t                  ena_uc_mem_map_size;
 486                         uint32_t                ena_wc_mem_map_offset;
 487                         size_t                  ena_wc_mem_map_size;
 488                 } ef10;
 489         } en_arch;
 490 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
 491 };
 492
 493
 494 #define EFX_NIC_MAGIC   0x02121996
 495
 496 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 497     const efx_ev_callbacks_t *, void *);
 498
 499 typedef struct efx_evq_rxq_state_s {
 500         unsigned int                    eers_rx_read_ptr;
 501         unsigned int                    eers_rx_mask;
 502 } efx_evq_rxq_state_t;
 503
 504 struct efx_evq_s {
 505         uint32_t                        ee_magic;
 506         efx_nic_t                       *ee_enp;
 507         unsigned int                    ee_index;
 508         unsigned int                    ee_mask;
 509         efsys_mem_t                     *ee_esmp;
 510 #if EFSYS_OPT_QSTATS
 511         uint32_t                        ee_stat[EV_NQSTATS];
 512 #endif  /* EFSYS_OPT_QSTATS */
 513
 514         efx_ev_handler_t                ee_rx;
 515         efx_ev_handler_t                ee_tx;
 516         efx_ev_handler_t                ee_driver;
 517         efx_ev_handler_t                ee_global;
 518         efx_ev_handler_t                ee_drv_gen;
 519 #if EFSYS_OPT_MCDI
 520         efx_ev_handler_t                ee_mcdi;
 521 #endif  /* EFSYS_OPT_MCDI */
 522
 523         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 524
 525         uint32_t                        ee_flags;
 526 };
 527
 528 #define EFX_EVQ_MAGIC   0x08081997
 529
 530 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 531
 532 struct efx_rxq_s {
 533         uint32_t                        er_magic;
 534         efx_nic_t                       *er_enp;
 535         efx_evq_t                       *er_eep;
 536         unsigned int                    er_index;
 537         unsigned int                    er_label;
 538         unsigned int                    er_mask;
 539         efsys_mem_t                     *er_esmp;
 540 };
 541
 542 #define EFX_RXQ_MAGIC   0x15022005
 543
 544 struct efx_txq_s {
 545         uint32_t                        et_magic;
 546         efx_nic_t                       *et_enp;
 547         unsigned int                    et_index;
 548         unsigned int                    et_mask;
 549         efsys_mem_t                     *et_esmp;
 550 #if EFSYS_OPT_HUNTINGTON
 551         uint32_t                        et_pio_bufnum;
 552         uint32_t                        et_pio_blknum;
 553         uint32_t                        et_pio_write_offset;
 554         uint32_t                        et_pio_offset;
 555         size_t                          et_pio_size;
 556 #endif
 557 #if EFSYS_OPT_QSTATS
 558         uint32_t                        et_stat[TX_NQSTATS];
 559 #endif  /* EFSYS_OPT_QSTATS */
 560 };
 561
 562 #define EFX_TXQ_MAGIC   0x05092005
 563
 564 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 565         do {                                                            \
 566                 (_dst)[0] = (_src)[0];                                  \
 567                 (_dst)[1] = (_src)[1];                                  \
 568                 (_dst)[2] = (_src)[2];                                  \
 569                 (_dst)[3] = (_src)[3];                                  \
 570                 (_dst)[4] = (_src)[4];                                  \
 571                 (_dst)[5] = (_src)[5];                                  \
 572         _NOTE(CONSTANTCONDITION)                                        \
 573         } while (B_FALSE)
 574
 575 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 576         do {                                                            \
 577                 uint16_t *_d = (uint16_t *)(_dst);                      \
 578                 _d[0] = 0xffff;                                         \
 579                 _d[1] = 0xffff;                                         \
 580                 _d[2] = 0xffff;                                         \
 581         _NOTE(CONSTANTCONDITION)                                        \
 582         } while (B_FALSE)
 583
 584 #if EFSYS_OPT_CHECK_REG
 585 #define EFX_CHECK_REG(_enp, _reg)                                       \
 586         do {                                                            \
 587                 const char *name = #_reg;                               \
 588                 char min = name[4];                                     \
 589                 char max = name[5];                                     \
 590                 char rev;                                               \
 591                                                                         \
 592                 switch ((_enp)->en_family) {                            \
 593                 case EFX_FAMILY_SIENA:                                  \
 594                         rev = 'C';                                      \
 595                         break;                                          \
 596                                                                         \
 597                 case EFX_FAMILY_HUNTINGTON:                             \
 598                         rev = 'D';                                      \
 599                         break;                                          \
 600                                                                         \
 601                 case EFX_FAMILY_MEDFORD:                                \
 602                         rev = 'E';                                      \
 603                         break;                                          \
 604                                                                         \
 605                 default:                                                \
 606                         rev = '?';                                      \
 607                         break;                                          \
 608                 }                                                       \
 609                                                                         \
 610                 EFSYS_ASSERT3S(rev, >=, min);                           \
 611                 EFSYS_ASSERT3S(rev, <=, max);                           \
 612                                                                         \
 613         _NOTE(CONSTANTCONDITION)                                        \
 614         } while (B_FALSE)
 615 #else
 616 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 617         _NOTE(CONSTANTCONDITION)                                        \
 618         } while (B_FALSE)
 619 #endif
 620
 621 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 622         do {                                                            \
 623                 EFX_CHECK_REG((_enp), (_reg));                          \
 624                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 625                     (_edp), (_lock));                                   \
 626                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 627                     uint32_t, _reg ## _OFST,                            \
 628                     uint32_t, (_edp)->ed_u32[0]);                       \
 629         _NOTE(CONSTANTCONDITION)                                        \
 630         } while (B_FALSE)
 631
 632 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 633         do {                                                            \
 634                 EFX_CHECK_REG((_enp), (_reg));                          \
 635                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 636                     uint32_t, _reg ## _OFST,                            \
 637                     uint32_t, (_edp)->ed_u32[0]);                       \
 638                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 639                     (_edp), (_lock));                                   \
 640         _NOTE(CONSTANTCONDITION)                                        \
 641         } while (B_FALSE)
 642
 643 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 644         do {                                                            \
 645                 EFX_CHECK_REG((_enp), (_reg));                          \
 646                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 647                     (_eqp));                                            \
 648                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 649                     uint32_t, _reg ## _OFST,                            \
 650                     uint32_t, (_eqp)->eq_u32[1],                        \
 651                     uint32_t, (_eqp)->eq_u32[0]);                       \
 652         _NOTE(CONSTANTCONDITION)                                        \
 653         } while (B_FALSE)
 654
 655 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 656         do {                                                            \
 657                 EFX_CHECK_REG((_enp), (_reg));                          \
 658                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 659                     uint32_t, _reg ## _OFST,                            \
 660                     uint32_t, (_eqp)->eq_u32[1],                        \
 661                     uint32_t, (_eqp)->eq_u32[0]);                       \
 662                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 663                     (_eqp));                                            \
 664         _NOTE(CONSTANTCONDITION)                                        \
 665         } while (B_FALSE)
 666
 667 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 668         do {                                                            \
 669                 EFX_CHECK_REG((_enp), (_reg));                          \
 670                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 671                     (_eop), B_TRUE);                                    \
 672                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 673                     uint32_t, _reg ## _OFST,                            \
 674                     uint32_t, (_eop)->eo_u32[3],                        \
 675                     uint32_t, (_eop)->eo_u32[2],                        \
 676                     uint32_t, (_eop)->eo_u32[1],                        \
 677                     uint32_t, (_eop)->eo_u32[0]);                       \
 678         _NOTE(CONSTANTCONDITION)                                        \
 679         } while (B_FALSE)
 680
 681 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 682         do {                                                            \
 683                 EFX_CHECK_REG((_enp), (_reg));                          \
 684                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 685                     uint32_t, _reg ## _OFST,                            \
 686                     uint32_t, (_eop)->eo_u32[3],                        \
 687                     uint32_t, (_eop)->eo_u32[2],                        \
 688                     uint32_t, (_eop)->eo_u32[1],                        \
 689                     uint32_t, (_eop)->eo_u32[0]);                       \
 690                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 691                     (_eop), B_TRUE);                                    \
 692         _NOTE(CONSTANTCONDITION)                                        \
 693         } while (B_FALSE)
 694
 695 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 696         do {                                                            \
 697                 EFX_CHECK_REG((_enp), (_reg));                          \
 698                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 699                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 700                     (_edp), (_lock));                                   \
 701                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 702                     uint32_t, (_index),                                 \
 703                     uint32_t, _reg ## _OFST,                            \
 704                     uint32_t, (_edp)->ed_u32[0]);                       \
 705         _NOTE(CONSTANTCONDITION)                                        \
 706         } while (B_FALSE)
 707
 708 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
 709         do {                                                            \
 710                 EFX_CHECK_REG((_enp), (_reg));                          \
 711                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 712                     uint32_t, (_index),                                 \
 713                     uint32_t, _reg ## _OFST,                            \
 714                     uint32_t, (_edp)->ed_u32[0]);                       \
 715                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 716                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 717                     (_edp), (_lock));                                   \
 718         _NOTE(CONSTANTCONDITION)                                        \
 719         } while (B_FALSE)
 720
 721 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)            \
 722         do {                                                            \
 723                 EFX_CHECK_REG((_enp), (_reg));                          \
 724                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 725                     uint32_t, (_index),                                 \
 726                     uint32_t, _reg ## _OFST,                            \
 727                     uint32_t, (_edp)->ed_u32[0]);                       \
 728                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 729                     (_reg ## _OFST +                                    \
 730                     (2 * sizeof (efx_dword_t)) +                        \
 731                     ((_index) * _reg ## _STEP)),                        \
 732                     (_edp), (_lock));                                   \
 733         _NOTE(CONSTANTCONDITION)                                        \
 734         } while (B_FALSE)
 735
 736 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
 737         do {                                                            \
 738                 EFX_CHECK_REG((_enp), (_reg));                          \
 739                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 740                     uint32_t, (_index),                                 \
 741                     uint32_t, _reg ## _OFST,                            \
 742                     uint32_t, (_edp)->ed_u32[0]);                       \
 743                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 744                     (_reg ## _OFST +                                    \
 745                     (3 * sizeof (efx_dword_t)) +                        \
 746                     ((_index) * _reg ## _STEP)),                        \
 747                     (_edp), (_lock));                                   \
 748         _NOTE(CONSTANTCONDITION)                                        \
 749         } while (B_FALSE)
 750
 751 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
 752         do {                                                            \
 753                 EFX_CHECK_REG((_enp), (_reg));                          \
 754                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
 755                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 756                     (_eqp));                                            \
 757                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
 758                     uint32_t, (_index),                                 \
 759                     uint32_t, _reg ## _OFST,                            \
 760                     uint32_t, (_eqp)->eq_u32[1],                        \
 761                     uint32_t, (_eqp)->eq_u32[0]);                       \
 762         _NOTE(CONSTANTCONDITION)                                        \
 763         } while (B_FALSE)
 764
 765 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
 766         do {                                                            \
 767                 EFX_CHECK_REG((_enp), (_reg));                          \
 768                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
 769                     uint32_t, (_index),                                 \
 770                     uint32_t, _reg ## _OFST,                            \
 771                     uint32_t, (_eqp)->eq_u32[1],                        \
 772                     uint32_t, (_eqp)->eq_u32[0]);                       \
 773                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
 774                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 775                     (_eqp));                                            \
 776         _NOTE(CONSTANTCONDITION)                                        \
 777         } while (B_FALSE)
 778
 779 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
 780         do {                                                            \
 781                 EFX_CHECK_REG((_enp), (_reg));                          \
 782                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
 783                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 784                     (_eop), (_lock));                                   \
 785                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
 786                     uint32_t, (_index),                                 \
 787                     uint32_t, _reg ## _OFST,                            \
 788                     uint32_t, (_eop)->eo_u32[3],                        \
 789                     uint32_t, (_eop)->eo_u32[2],                        \
 790                     uint32_t, (_eop)->eo_u32[1],                        \
 791                     uint32_t, (_eop)->eo_u32[0]);                       \
 792         _NOTE(CONSTANTCONDITION)                                        \
 793         } while (B_FALSE)
 794
 795 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
 796         do {                                                            \
 797                 EFX_CHECK_REG((_enp), (_reg));                          \
 798                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
 799                     uint32_t, (_index),                                 \
 800                     uint32_t, _reg ## _OFST,                            \
 801                     uint32_t, (_eop)->eo_u32[3],                        \
 802                     uint32_t, (_eop)->eo_u32[2],                        \
 803                     uint32_t, (_eop)->eo_u32[1],                        \
 804                     uint32_t, (_eop)->eo_u32[0]);                       \
 805                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
 806                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 807                     (_eop), (_lock));                                   \
 808         _NOTE(CONSTANTCONDITION)                                        \
 809         } while (B_FALSE)
 810
 811 /*
 812  * Allow drivers to perform optimised 128-bit doorbell writes.
 813  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
 814  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
 815  * the need for locking in the host, and are the only ones known to be safe to
 816  * use 128-bites write with.
 817  */
 818 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)           \
 819         do {                                                            \
 820                 EFX_CHECK_REG((_enp), (_reg));                          \
 821                 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,               \
 822                     const char *,                                       \
 823                     #_reg,                                              \
 824                     uint32_t, (_index),                                 \
 825                     uint32_t, _reg ## _OFST,                            \
 826                     uint32_t, (_eop)->eo_u32[3],                        \
 827                     uint32_t, (_eop)->eo_u32[2],                        \
 828                     uint32_t, (_eop)->eo_u32[1],                        \
 829                     uint32_t, (_eop)->eo_u32[0]);                       \
 830                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
 831                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 832                     (_eop));                                            \
 833         _NOTE(CONSTANTCONDITION)                                        \
 834         } while (B_FALSE)
 835
 836 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
 837         do {                                                            \
 838                 unsigned int _new = (_wptr);                            \
 839                 unsigned int _old = (_owptr);                           \
 840                                                                         \
 841                 if ((_new) >= (_old))                                   \
 842                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
 843                             (_old) * sizeof (efx_desc_t),               \
 844                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
 845                 else                                                    \
 846                         /*                                              \
 847                          * It is cheaper to sync entire map than sync   \
 848                          * two parts especially when offset/size are    \
 849                          * ignored and entire map is synced in any case.\
 850                          */                                             \
 851                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
 852                             0,                                          \
 853                             (_entries) * sizeof (efx_desc_t));          \
 854         _NOTE(CONSTANTCONDITION)                                        \
 855         } while (B_FALSE)
 856
 857 extern  __checkReturn   efx_rc_t
 858 efx_nic_biu_test(
 859         __in            efx_nic_t *enp);
 860
 861 extern  __checkReturn   efx_rc_t
 862 efx_mac_select(
 863         __in            efx_nic_t *enp);
 864
 865 extern  void
 866 efx_mac_multicast_hash_compute(
 867         __in_ecount(6*count)            uint8_t const *addrs,
 868         __in                            int count,
 869         __out                           efx_oword_t *hash_low,
 870         __out                           efx_oword_t *hash_high);
 871
 872 extern  __checkReturn   efx_rc_t
 873 efx_phy_probe(
 874         __in            efx_nic_t *enp);
 875
 876 extern                  void
 877 efx_phy_unprobe(
 878         __in            efx_nic_t *enp);
 879
 880 #if EFSYS_OPT_DIAG
 881
 882 extern  efx_sram_pattern_fn_t   __efx_sram_pattern_fns[];
 883
 884 typedef struct efx_register_set_s {
 885         unsigned int            address;
 886         unsigned int            step;
 887         unsigned int            rows;
 888         efx_oword_t             mask;
 889 } efx_register_set_t;
 890
 891 extern  __checkReturn   efx_rc_t
 892 efx_nic_test_registers(
 893         __in            efx_nic_t *enp,
 894         __in            efx_register_set_t *rsp,
 895         __in            size_t count);
 896
 897 extern  __checkReturn   efx_rc_t
 898 efx_nic_test_tables(
 899         __in            efx_nic_t *enp,
 900         __in            efx_register_set_t *rsp,
 901         __in            efx_pattern_type_t pattern,
 902         __in            size_t count);
 903
 904 #endif  /* EFSYS_OPT_DIAG */
 905
 906 #if EFSYS_OPT_MCDI
 907
 908 extern  __checkReturn           efx_rc_t
 909 efx_mcdi_set_workaround(
 910         __in                    efx_nic_t *enp,
 911         __in                    uint32_t type,
 912         __in                    boolean_t enabled,
 913         __out_opt               uint32_t *flagsp);
 914
 915 extern  __checkReturn           efx_rc_t
 916 efx_mcdi_get_workarounds(
 917         __in                    efx_nic_t *enp,
 918         __out_opt               uint32_t *implementedp,
 919         __out_opt               uint32_t *enabledp);
 920
 921 #endif /* EFSYS_OPT_MCDI */
 922
 923 #if EFSYS_OPT_MAC_STATS
 924
 925 /*
 926  * Closed range of stats (i.e. the first and the last are included).
 927  * The last must be greater or equal (if the range is one item only) to
 928  * the first.
 929  */
 930 struct efx_mac_stats_range {
 931         efx_mac_stat_t          first;
 932         efx_mac_stat_t          last;
 933 };
 934
 935 extern                                  efx_rc_t
 936 efx_mac_stats_mask_add_ranges(
 937         __inout_bcount(mask_size)       uint32_t *maskp,
 938         __in                            size_t mask_size,
 939         __in_ecount(rng_count)          const struct efx_mac_stats_range *rngp,
 940         __in                            unsigned int rng_count);
 941
 942 #endif  /* EFSYS_OPT_MAC_STATS */
 943
 944 #ifdef  __cplusplus
 945 }
 946 #endif
 947
 948 #endif  /* _SYS_EFX_IMPL_H */