drivers/net/sfc/base/efx_impl.h

   1 /*
   2  * Copyright (c) 2007-2016 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  */
  30
  31 #ifndef _SYS_EFX_IMPL_H
  32 #define _SYS_EFX_IMPL_H
  33
  34 #include "efx.h"
  35 #include "efx_regs.h"
  36 #include "efx_regs_ef10.h"
  37
  38 /* FIXME: Add definition for driver generated software events */
  39 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  40 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  41 #endif
  42
  43
  44 #if EFSYS_OPT_SIENA
  45 #include "siena_impl.h"
  46 #endif  /* EFSYS_OPT_SIENA */
  47
  48 #if EFSYS_OPT_HUNTINGTON
  49 #include "hunt_impl.h"
  50 #endif  /* EFSYS_OPT_HUNTINGTON */
  51
  52 #if EFSYS_OPT_MEDFORD
  53 #include "medford_impl.h"
  54 #endif  /* EFSYS_OPT_MEDFORD */
  55
  56 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
  57 #include "ef10_impl.h"
  58 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
  59
  60 #ifdef  __cplusplus
  61 extern "C" {
  62 #endif
  63
  64 #define EFX_MOD_MCDI            0x00000001
  65 #define EFX_MOD_PROBE           0x00000002
  66 #define EFX_MOD_NVRAM           0x00000004
  67 #define EFX_MOD_VPD             0x00000008
  68 #define EFX_MOD_NIC             0x00000010
  69 #define EFX_MOD_INTR            0x00000020
  70 #define EFX_MOD_EV              0x00000040
  71 #define EFX_MOD_RX              0x00000080
  72 #define EFX_MOD_TX              0x00000100
  73 #define EFX_MOD_PORT            0x00000200
  74 #define EFX_MOD_MON             0x00000400
  75 #define EFX_MOD_FILTER          0x00001000
  76 #define EFX_MOD_LIC             0x00002000
  77
  78 #define EFX_RESET_PHY           0x00000001
  79 #define EFX_RESET_RXQ_ERR       0x00000002
  80 #define EFX_RESET_TXQ_ERR       0x00000004
  81
  82 typedef enum efx_mac_type_e {
  83         EFX_MAC_INVALID = 0,
  84         EFX_MAC_SIENA,
  85         EFX_MAC_HUNTINGTON,
  86         EFX_MAC_MEDFORD,
  87         EFX_MAC_NTYPES
  88 } efx_mac_type_t;
  89
  90 typedef struct efx_ev_ops_s {
  91         efx_rc_t        (*eevo_init)(efx_nic_t *);
  92         void            (*eevo_fini)(efx_nic_t *);
  93         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  94                                           efsys_mem_t *, size_t, uint32_t,
  95                                           uint32_t, uint32_t, efx_evq_t *);
  96         void            (*eevo_qdestroy)(efx_evq_t *);
  97         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  98         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  99         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
 100 #if EFSYS_OPT_QSTATS
 101         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
 102 #endif
 103 } efx_ev_ops_t;
 104
 105 typedef struct efx_tx_ops_s {
 106         efx_rc_t        (*etxo_init)(efx_nic_t *);
 107         void            (*etxo_fini)(efx_nic_t *);
 108         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 109                                         unsigned int, unsigned int,
 110                                         efsys_mem_t *, size_t,
 111                                         uint32_t, uint16_t,
 112                                         efx_evq_t *, efx_txq_t *,
 113                                         unsigned int *);
 114         void            (*etxo_qdestroy)(efx_txq_t *);
 115         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 116                                       unsigned int, unsigned int,
 117                                       unsigned int *);
 118         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 119         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 120         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 121         void            (*etxo_qenable)(efx_txq_t *);
 122         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 123         void            (*etxo_qpio_disable)(efx_txq_t *);
 124         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 125                                            size_t);
 126         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 127                                            unsigned int *);
 128         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 129                                       unsigned int, unsigned int,
 130                                       unsigned int *);
 131         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 132                                                 size_t, boolean_t,
 133                                                 efx_desc_t *);
 134         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 135                                                 uint32_t, uint8_t,
 136                                                 efx_desc_t *);
 137         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 138                                                 uint32_t, uint16_t,
 139                                                 efx_desc_t *, int);
 140         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 141                                                 efx_desc_t *);
 142 #if EFSYS_OPT_QSTATS
 143         void            (*etxo_qstats_update)(efx_txq_t *,
 144                                               efsys_stat_t *);
 145 #endif
 146 } efx_tx_ops_t;
 147
 148 typedef struct efx_rx_ops_s {
 149         efx_rc_t        (*erxo_init)(efx_nic_t *);
 150         void            (*erxo_fini)(efx_nic_t *);
 151 #if EFSYS_OPT_RX_SCATTER
 152         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 153 #endif
 154 #if EFSYS_OPT_RX_SCALE
 155         efx_rc_t        (*erxo_scale_context_alloc)(efx_nic_t *,
 156                                                     efx_rx_scale_context_type_t,
 157                                                     uint32_t, uint32_t *);
 158         efx_rc_t        (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
 159         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
 160                                                efx_rx_hash_alg_t,
 161                                                efx_rx_hash_type_t, boolean_t);
 162         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
 163                                               uint8_t *, size_t);
 164         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
 165                                               unsigned int *, size_t);
 166         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 167                                             uint8_t *);
 168 #endif /* EFSYS_OPT_RX_SCALE */
 169         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 170                                               uint16_t *);
 171         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 172                                       unsigned int, unsigned int,
 173                                       unsigned int);
 174         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 175 #if EFSYS_OPT_RX_PACKED_STREAM
 176         void            (*erxo_qpush_ps_credits)(efx_rxq_t *);
 177         uint8_t *       (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
 178                                                 uint32_t, uint32_t,
 179                                                 uint16_t *, uint32_t *, uint32_t *);
 180 #endif
 181         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 182         void            (*erxo_qenable)(efx_rxq_t *);
 183         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 184                                         unsigned int, efx_rxq_type_t,
 185                                         efsys_mem_t *, size_t, uint32_t,
 186                                         efx_evq_t *, efx_rxq_t *);
 187         void            (*erxo_qdestroy)(efx_rxq_t *);
 188 } efx_rx_ops_t;
 189
 190 typedef struct efx_mac_ops_s {
 191         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 192         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 193         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 194         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 195         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 196         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 197         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 198         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 199                                                       efx_rxq_t *, boolean_t);
 200         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 201 #if EFSYS_OPT_LOOPBACK
 202         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 203                                             efx_loopback_type_t);
 204 #endif  /* EFSYS_OPT_LOOPBACK */
 205 #if EFSYS_OPT_MAC_STATS
 206         efx_rc_t        (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
 207         efx_rc_t        (*emo_stats_clear)(efx_nic_t *);
 208         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 209         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 210                                               uint16_t, boolean_t);
 211         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 212                                             efsys_stat_t *, uint32_t *);
 213 #endif  /* EFSYS_OPT_MAC_STATS */
 214 } efx_mac_ops_t;
 215
 216 typedef struct efx_phy_ops_s {
 217         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 218         efx_rc_t        (*epo_reset)(efx_nic_t *);
 219         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 220         efx_rc_t        (*epo_verify)(efx_nic_t *);
 221         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 222 #if EFSYS_OPT_PHY_STATS
 223         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 224                                             uint32_t *);
 225 #endif  /* EFSYS_OPT_PHY_STATS */
 226 #if EFSYS_OPT_BIST
 227         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 228         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 229         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 230                                          efx_bist_result_t *, uint32_t *,
 231                                          unsigned long *, size_t);
 232         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 233 #endif  /* EFSYS_OPT_BIST */
 234 } efx_phy_ops_t;
 235
 236 #if EFSYS_OPT_FILTER
 237 typedef struct efx_filter_ops_s {
 238         efx_rc_t        (*efo_init)(efx_nic_t *);
 239         void            (*efo_fini)(efx_nic_t *);
 240         efx_rc_t        (*efo_restore)(efx_nic_t *);
 241         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 242                                    boolean_t may_replace);
 243         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 244         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *,
 245                                    size_t, size_t *);
 246         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 247                                    boolean_t, boolean_t, boolean_t,
 248                                    uint8_t const *, uint32_t);
 249 } efx_filter_ops_t;
 250
 251 extern  __checkReturn   efx_rc_t
 252 efx_filter_reconfigure(
 253         __in                            efx_nic_t *enp,
 254         __in_ecount(6)                  uint8_t const *mac_addr,
 255         __in                            boolean_t all_unicst,
 256         __in                            boolean_t mulcst,
 257         __in                            boolean_t all_mulcst,
 258         __in                            boolean_t brdcst,
 259         __in_ecount(6*count)            uint8_t const *addrs,
 260         __in                            uint32_t count);
 261
 262 #endif /* EFSYS_OPT_FILTER */
 263
 264
 265 typedef struct efx_port_s {
 266         efx_mac_type_t          ep_mac_type;
 267         uint32_t                ep_phy_type;
 268         uint8_t                 ep_port;
 269         uint32_t                ep_mac_pdu;
 270         uint8_t                 ep_mac_addr[6];
 271         efx_link_mode_t         ep_link_mode;
 272         boolean_t               ep_all_unicst;
 273         boolean_t               ep_mulcst;
 274         boolean_t               ep_all_mulcst;
 275         boolean_t               ep_brdcst;
 276         unsigned int            ep_fcntl;
 277         boolean_t               ep_fcntl_autoneg;
 278         efx_oword_t             ep_multicst_hash[2];
 279         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 280                                                     EFX_MAC_MULTICAST_LIST_MAX];
 281         uint32_t                ep_mulcst_addr_count;
 282 #if EFSYS_OPT_LOOPBACK
 283         efx_loopback_type_t     ep_loopback_type;
 284         efx_link_mode_t         ep_loopback_link_mode;
 285 #endif  /* EFSYS_OPT_LOOPBACK */
 286 #if EFSYS_OPT_PHY_FLAGS
 287         uint32_t                ep_phy_flags;
 288 #endif  /* EFSYS_OPT_PHY_FLAGS */
 289 #if EFSYS_OPT_PHY_LED_CONTROL
 290         efx_phy_led_mode_t      ep_phy_led_mode;
 291 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 292         efx_phy_media_type_t    ep_fixed_port_type;
 293         efx_phy_media_type_t    ep_module_type;
 294         uint32_t                ep_adv_cap_mask;
 295         uint32_t                ep_lp_cap_mask;
 296         uint32_t                ep_default_adv_cap_mask;
 297         uint32_t                ep_phy_cap_mask;
 298         boolean_t               ep_mac_drain;
 299         boolean_t               ep_mac_stats_pending;
 300 #if EFSYS_OPT_BIST
 301         efx_bist_type_t         ep_current_bist;
 302 #endif
 303         const efx_mac_ops_t     *ep_emop;
 304         const efx_phy_ops_t     *ep_epop;
 305 } efx_port_t;
 306
 307 typedef struct efx_mon_ops_s {
 308 #if EFSYS_OPT_MON_STATS
 309         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 310                                             efx_mon_stat_value_t *);
 311 #endif  /* EFSYS_OPT_MON_STATS */
 312 } efx_mon_ops_t;
 313
 314 typedef struct efx_mon_s {
 315         efx_mon_type_t          em_type;
 316         const efx_mon_ops_t     *em_emop;
 317 } efx_mon_t;
 318
 319 typedef struct efx_intr_ops_s {
 320         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 321         void            (*eio_enable)(efx_nic_t *);
 322         void            (*eio_disable)(efx_nic_t *);
 323         void            (*eio_disable_unlocked)(efx_nic_t *);
 324         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 325         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 326         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 327                                  boolean_t *);
 328         void            (*eio_fatal)(efx_nic_t *);
 329         void            (*eio_fini)(efx_nic_t *);
 330 } efx_intr_ops_t;
 331
 332 typedef struct efx_intr_s {
 333         const efx_intr_ops_t    *ei_eiop;
 334         efsys_mem_t             *ei_esmp;
 335         efx_intr_type_t         ei_type;
 336         unsigned int            ei_level;
 337 } efx_intr_t;
 338
 339 typedef struct efx_nic_ops_s {
 340         efx_rc_t        (*eno_probe)(efx_nic_t *);
 341         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 342         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 343         efx_rc_t        (*eno_reset)(efx_nic_t *);
 344         efx_rc_t        (*eno_init)(efx_nic_t *);
 345         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 346         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 347                                         uint32_t *, size_t *);
 348 #if EFSYS_OPT_DIAG
 349         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 350 #endif  /* EFSYS_OPT_DIAG */
 351         void            (*eno_fini)(efx_nic_t *);
 352         void            (*eno_unprobe)(efx_nic_t *);
 353 } efx_nic_ops_t;
 354
 355 #ifndef EFX_TXQ_LIMIT_TARGET
 356 #define EFX_TXQ_LIMIT_TARGET 259
 357 #endif
 358 #ifndef EFX_RXQ_LIMIT_TARGET
 359 #define EFX_RXQ_LIMIT_TARGET 512
 360 #endif
 361
 362
 363 #if EFSYS_OPT_FILTER
 364
 365 #if EFSYS_OPT_SIENA
 366
 367 typedef struct siena_filter_spec_s {
 368         uint8_t         sfs_type;
 369         uint32_t        sfs_flags;
 370         uint32_t        sfs_dmaq_id;
 371         uint32_t        sfs_dword[3];
 372 } siena_filter_spec_t;
 373
 374 typedef enum siena_filter_type_e {
 375         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 376         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 377         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 378         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 379         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 380         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 381
 382         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 383         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 384         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 385         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 386         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 387         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 388
 389         EFX_SIENA_FILTER_NTYPES
 390 } siena_filter_type_t;
 391
 392 typedef enum siena_filter_tbl_id_e {
 393         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 394         EFX_SIENA_FILTER_TBL_RX_MAC,
 395         EFX_SIENA_FILTER_TBL_TX_IP,
 396         EFX_SIENA_FILTER_TBL_TX_MAC,
 397         EFX_SIENA_FILTER_NTBLS
 398 } siena_filter_tbl_id_t;
 399
 400 typedef struct siena_filter_tbl_s {
 401         int                     sft_size;       /* number of entries */
 402         int                     sft_used;       /* active count */
 403         uint32_t                *sft_bitmap;    /* active bitmap */
 404         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 405 } siena_filter_tbl_t;
 406
 407 typedef struct siena_filter_s {
 408         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 409         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 410 } siena_filter_t;
 411
 412 #endif  /* EFSYS_OPT_SIENA */
 413
 414 typedef struct efx_filter_s {
 415 #if EFSYS_OPT_SIENA
 416         siena_filter_t          *ef_siena_filter;
 417 #endif /* EFSYS_OPT_SIENA */
 418 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 419         ef10_filter_table_t     *ef_ef10_filter_table;
 420 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 421 } efx_filter_t;
 422
 423 #if EFSYS_OPT_SIENA
 424
 425 extern                  void
 426 siena_filter_tbl_clear(
 427         __in            efx_nic_t *enp,
 428         __in            siena_filter_tbl_id_t tbl);
 429
 430 #endif  /* EFSYS_OPT_SIENA */
 431
 432 #endif  /* EFSYS_OPT_FILTER */
 433
 434 #if EFSYS_OPT_MCDI
 435
 436 typedef struct efx_mcdi_ops_s {
 437         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 438         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 439                                         void *, size_t);
 440         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 441         boolean_t       (*emco_poll_response)(efx_nic_t *);
 442         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 443         void            (*emco_fini)(efx_nic_t *);
 444         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 445                                             efx_mcdi_feature_id_t, boolean_t *);
 446         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 447                                             uint32_t *);
 448 } efx_mcdi_ops_t;
 449
 450 typedef struct efx_mcdi_s {
 451         const efx_mcdi_ops_t            *em_emcop;
 452         const efx_mcdi_transport_t      *em_emtp;
 453         efx_mcdi_iface_t                em_emip;
 454 } efx_mcdi_t;
 455
 456 #endif /* EFSYS_OPT_MCDI */
 457
 458 #if EFSYS_OPT_NVRAM
 459
 460 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
 461 #define EFX_NVRAM_PARTN_INVALID         (0xffffffffu)
 462
 463 typedef struct efx_nvram_ops_s {
 464 #if EFSYS_OPT_DIAG
 465         efx_rc_t        (*envo_test)(efx_nic_t *);
 466 #endif  /* EFSYS_OPT_DIAG */
 467         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 468                                             uint32_t *);
 469         efx_rc_t        (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
 470         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 471         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 472                                             unsigned int, caddr_t, size_t);
 473         efx_rc_t        (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
 474                                             unsigned int, caddr_t, size_t);
 475         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 476                                             unsigned int, size_t);
 477         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 478                                             unsigned int, caddr_t, size_t);
 479         efx_rc_t        (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
 480                                             uint32_t *);
 481         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 482                                             uint32_t *, uint16_t *);
 483         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 484                                             uint16_t *);
 485         efx_rc_t        (*envo_buffer_validate)(efx_nic_t *, uint32_t,
 486                                             caddr_t, size_t);
 487 } efx_nvram_ops_t;
 488 #endif /* EFSYS_OPT_NVRAM */
 489
 490 #if EFSYS_OPT_VPD
 491 typedef struct efx_vpd_ops_s {
 492         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 493         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 494         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 495         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 496         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 497         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 498                                         efx_vpd_value_t *);
 499         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 500                                         efx_vpd_value_t *);
 501         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 502                                         efx_vpd_value_t *, unsigned int *);
 503         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 504         void            (*evpdo_fini)(efx_nic_t *);
 505 } efx_vpd_ops_t;
 506 #endif  /* EFSYS_OPT_VPD */
 507
 508 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 509
 510         __checkReturn           efx_rc_t
 511 efx_mcdi_nvram_partitions(
 512         __in                    efx_nic_t *enp,
 513         __out_bcount(size)      caddr_t data,
 514         __in                    size_t size,
 515         __out                   unsigned int *npartnp);
 516
 517         __checkReturn           efx_rc_t
 518 efx_mcdi_nvram_metadata(
 519         __in                    efx_nic_t *enp,
 520         __in                    uint32_t partn,
 521         __out                   uint32_t *subtypep,
 522         __out_ecount(4)         uint16_t version[4],
 523         __out_bcount_opt(size)  char *descp,
 524         __in                    size_t size);
 525
 526         __checkReturn           efx_rc_t
 527 efx_mcdi_nvram_info(
 528         __in                    efx_nic_t *enp,
 529         __in                    uint32_t partn,
 530         __out_opt               size_t *sizep,
 531         __out_opt               uint32_t *addressp,
 532         __out_opt               uint32_t *erase_sizep,
 533         __out_opt               uint32_t *write_sizep);
 534
 535         __checkReturn           efx_rc_t
 536 efx_mcdi_nvram_update_start(
 537         __in                    efx_nic_t *enp,
 538         __in                    uint32_t partn);
 539
 540         __checkReturn           efx_rc_t
 541 efx_mcdi_nvram_read(
 542         __in                    efx_nic_t *enp,
 543         __in                    uint32_t partn,
 544         __in                    uint32_t offset,
 545         __out_bcount(size)      caddr_t data,
 546         __in                    size_t size,
 547         __in                    uint32_t mode);
 548
 549         __checkReturn           efx_rc_t
 550 efx_mcdi_nvram_erase(
 551         __in                    efx_nic_t *enp,
 552         __in                    uint32_t partn,
 553         __in                    uint32_t offset,
 554         __in                    size_t size);
 555
 556         __checkReturn           efx_rc_t
 557 efx_mcdi_nvram_write(
 558         __in                    efx_nic_t *enp,
 559         __in                    uint32_t partn,
 560         __in                    uint32_t offset,
 561         __out_bcount(size)      caddr_t data,
 562         __in                    size_t size);
 563
 564         __checkReturn           efx_rc_t
 565 efx_mcdi_nvram_update_finish(
 566         __in                    efx_nic_t *enp,
 567         __in                    uint32_t partn,
 568         __in                    boolean_t reboot,
 569         __out_opt               uint32_t *verify_resultp);
 570
 571 #if EFSYS_OPT_DIAG
 572
 573         __checkReturn           efx_rc_t
 574 efx_mcdi_nvram_test(
 575         __in                    efx_nic_t *enp,
 576         __in                    uint32_t partn);
 577
 578 #endif  /* EFSYS_OPT_DIAG */
 579
 580 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 581
 582 #if EFSYS_OPT_LICENSING
 583
 584 typedef struct efx_lic_ops_s {
 585         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 586         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 587         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 588         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 589                                       size_t *, uint8_t *);
 590         efx_rc_t        (*elo_find_start)
 591                                 (efx_nic_t *, caddr_t, size_t, uint32_t *);
 592         efx_rc_t        (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
 593                                 uint32_t, uint32_t *);
 594         boolean_t       (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
 595                                 uint32_t, uint32_t *, uint32_t *);
 596         boolean_t       (*elo_validate_key)(efx_nic_t *,
 597                                 caddr_t, uint32_t);
 598         efx_rc_t        (*elo_read_key)(efx_nic_t *,
 599                                 caddr_t, size_t, uint32_t, uint32_t,
 600                                 caddr_t, size_t, uint32_t *);
 601         efx_rc_t        (*elo_write_key)(efx_nic_t *,
 602                                 caddr_t, size_t, uint32_t,
 603                                 caddr_t, uint32_t, uint32_t *);
 604         efx_rc_t        (*elo_delete_key)(efx_nic_t *,
 605                                 caddr_t, size_t, uint32_t,
 606                                 uint32_t, uint32_t, uint32_t *);
 607         efx_rc_t        (*elo_create_partition)(efx_nic_t *,
 608                                 caddr_t, size_t);
 609         efx_rc_t        (*elo_finish_partition)(efx_nic_t *,
 610                                 caddr_t, size_t);
 611 } efx_lic_ops_t;
 612
 613 #endif
 614
 615 typedef struct efx_drv_cfg_s {
 616         uint32_t                edc_min_vi_count;
 617         uint32_t                edc_max_vi_count;
 618
 619         uint32_t                edc_max_piobuf_count;
 620         uint32_t                edc_pio_alloc_size;
 621 } efx_drv_cfg_t;
 622
 623 struct efx_nic_s {
 624         uint32_t                en_magic;
 625         efx_family_t            en_family;
 626         uint32_t                en_features;
 627         efsys_identifier_t      *en_esip;
 628         efsys_lock_t            *en_eslp;
 629         efsys_bar_t             *en_esbp;
 630         unsigned int            en_mod_flags;
 631         unsigned int            en_reset_flags;
 632         efx_nic_cfg_t           en_nic_cfg;
 633         efx_drv_cfg_t           en_drv_cfg;
 634         efx_port_t              en_port;
 635         efx_mon_t               en_mon;
 636         efx_intr_t              en_intr;
 637         uint32_t                en_ev_qcount;
 638         uint32_t                en_rx_qcount;
 639         uint32_t                en_tx_qcount;
 640         const efx_nic_ops_t     *en_enop;
 641         const efx_ev_ops_t      *en_eevop;
 642         const efx_tx_ops_t      *en_etxop;
 643         const efx_rx_ops_t      *en_erxop;
 644 #if EFSYS_OPT_FILTER
 645         efx_filter_t            en_filter;
 646         const efx_filter_ops_t  *en_efop;
 647 #endif  /* EFSYS_OPT_FILTER */
 648 #if EFSYS_OPT_MCDI
 649         efx_mcdi_t              en_mcdi;
 650 #endif  /* EFSYS_OPT_MCDI */
 651 #if EFSYS_OPT_NVRAM
 652         uint32_t                en_nvram_partn_locked;
 653         const efx_nvram_ops_t   *en_envop;
 654 #endif  /* EFSYS_OPT_NVRAM */
 655 #if EFSYS_OPT_VPD
 656         const efx_vpd_ops_t     *en_evpdop;
 657 #endif  /* EFSYS_OPT_VPD */
 658 #if EFSYS_OPT_RX_SCALE
 659         efx_rx_hash_support_t           en_hash_support;
 660         efx_rx_scale_context_type_t     en_rss_context_type;
 661         uint32_t                        en_rss_context;
 662 #endif  /* EFSYS_OPT_RX_SCALE */
 663         uint32_t                en_vport_id;
 664 #if EFSYS_OPT_LICENSING
 665         const efx_lic_ops_t     *en_elop;
 666         boolean_t               en_licensing_supported;
 667 #endif
 668         union {
 669 #if EFSYS_OPT_SIENA
 670                 struct {
 671 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 672                         unsigned int            enu_partn_mask;
 673 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 674 #if EFSYS_OPT_VPD
 675                         caddr_t                 enu_svpd;
 676                         size_t                  enu_svpd_length;
 677 #endif  /* EFSYS_OPT_VPD */
 678                         int                     enu_unused;
 679                 } siena;
 680 #endif  /* EFSYS_OPT_SIENA */
 681                 int     enu_unused;
 682         } en_u;
 683 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
 684         union en_arch {
 685                 struct {
 686                         int                     ena_vi_base;
 687                         int                     ena_vi_count;
 688                         int                     ena_vi_shift;
 689 #if EFSYS_OPT_VPD
 690                         caddr_t                 ena_svpd;
 691                         size_t                  ena_svpd_length;
 692 #endif  /* EFSYS_OPT_VPD */
 693                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 694                         uint32_t                ena_piobuf_count;
 695                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 696                         uint32_t                ena_pio_write_vi_base;
 697                         /* Memory BAR mapping regions */
 698                         uint32_t                ena_uc_mem_map_offset;
 699                         size_t                  ena_uc_mem_map_size;
 700                         uint32_t                ena_wc_mem_map_offset;
 701                         size_t                  ena_wc_mem_map_size;
 702                 } ef10;
 703         } en_arch;
 704 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
 705 };
 706
 707
 708 #define EFX_NIC_MAGIC   0x02121996
 709
 710 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 711     const efx_ev_callbacks_t *, void *);
 712
 713 typedef struct efx_evq_rxq_state_s {
 714         unsigned int                    eers_rx_read_ptr;
 715         unsigned int                    eers_rx_mask;
 716 #if EFSYS_OPT_RX_PACKED_STREAM
 717         unsigned int                    eers_rx_stream_npackets;
 718         boolean_t                       eers_rx_packed_stream;
 719         unsigned int                    eers_rx_packed_stream_credits;
 720 #endif
 721 } efx_evq_rxq_state_t;
 722
 723 struct efx_evq_s {
 724         uint32_t                        ee_magic;
 725         efx_nic_t                       *ee_enp;
 726         unsigned int                    ee_index;
 727         unsigned int                    ee_mask;
 728         efsys_mem_t                     *ee_esmp;
 729 #if EFSYS_OPT_QSTATS
 730         uint32_t                        ee_stat[EV_NQSTATS];
 731 #endif  /* EFSYS_OPT_QSTATS */
 732
 733         efx_ev_handler_t                ee_rx;
 734         efx_ev_handler_t                ee_tx;
 735         efx_ev_handler_t                ee_driver;
 736         efx_ev_handler_t                ee_global;
 737         efx_ev_handler_t                ee_drv_gen;
 738 #if EFSYS_OPT_MCDI
 739         efx_ev_handler_t                ee_mcdi;
 740 #endif  /* EFSYS_OPT_MCDI */
 741
 742         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 743
 744         uint32_t                        ee_flags;
 745 };
 746
 747 #define EFX_EVQ_MAGIC   0x08081997
 748
 749 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 750
 751 struct efx_rxq_s {
 752         uint32_t                        er_magic;
 753         efx_nic_t                       *er_enp;
 754         efx_evq_t                       *er_eep;
 755         unsigned int                    er_index;
 756         unsigned int                    er_label;
 757         unsigned int                    er_mask;
 758         efsys_mem_t                     *er_esmp;
 759         efx_evq_rxq_state_t             *er_ev_qstate;
 760 };
 761
 762 #define EFX_RXQ_MAGIC   0x15022005
 763
 764 struct efx_txq_s {
 765         uint32_t                        et_magic;
 766         efx_nic_t                       *et_enp;
 767         unsigned int                    et_index;
 768         unsigned int                    et_mask;
 769         efsys_mem_t                     *et_esmp;
 770 #if EFSYS_OPT_HUNTINGTON
 771         uint32_t                        et_pio_bufnum;
 772         uint32_t                        et_pio_blknum;
 773         uint32_t                        et_pio_write_offset;
 774         uint32_t                        et_pio_offset;
 775         size_t                          et_pio_size;
 776 #endif
 777 #if EFSYS_OPT_QSTATS
 778         uint32_t                        et_stat[TX_NQSTATS];
 779 #endif  /* EFSYS_OPT_QSTATS */
 780 };
 781
 782 #define EFX_TXQ_MAGIC   0x05092005
 783
 784 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 785         do {                                                            \
 786                 (_dst)[0] = (_src)[0];                                  \
 787                 (_dst)[1] = (_src)[1];                                  \
 788                 (_dst)[2] = (_src)[2];                                  \
 789                 (_dst)[3] = (_src)[3];                                  \
 790                 (_dst)[4] = (_src)[4];                                  \
 791                 (_dst)[5] = (_src)[5];                                  \
 792         _NOTE(CONSTANTCONDITION)                                        \
 793         } while (B_FALSE)
 794
 795 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 796         do {                                                            \
 797                 uint16_t *_d = (uint16_t *)(_dst);                      \
 798                 _d[0] = 0xffff;                                         \
 799                 _d[1] = 0xffff;                                         \
 800                 _d[2] = 0xffff;                                         \
 801         _NOTE(CONSTANTCONDITION)                                        \
 802         } while (B_FALSE)
 803
 804 #if EFSYS_OPT_CHECK_REG
 805 #define EFX_CHECK_REG(_enp, _reg)                                       \
 806         do {                                                            \
 807                 const char *name = #_reg;                               \
 808                 char min = name[4];                                     \
 809                 char max = name[5];                                     \
 810                 char rev;                                               \
 811                                                                         \
 812                 switch ((_enp)->en_family) {                            \
 813                 case EFX_FAMILY_SIENA:                                  \
 814                         rev = 'C';                                      \
 815                         break;                                          \
 816                                                                         \
 817                 case EFX_FAMILY_HUNTINGTON:                             \
 818                         rev = 'D';                                      \
 819                         break;                                          \
 820                                                                         \
 821                 case EFX_FAMILY_MEDFORD:                                \
 822                         rev = 'E';                                      \
 823                         break;                                          \
 824                                                                         \
 825                 default:                                                \
 826                         rev = '?';                                      \
 827                         break;                                          \
 828                 }                                                       \
 829                                                                         \
 830                 EFSYS_ASSERT3S(rev, >=, min);                           \
 831                 EFSYS_ASSERT3S(rev, <=, max);                           \
 832                                                                         \
 833         _NOTE(CONSTANTCONDITION)                                        \
 834         } while (B_FALSE)
 835 #else
 836 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 837         _NOTE(CONSTANTCONDITION)                                        \
 838         } while (B_FALSE)
 839 #endif
 840
 841 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 842         do {                                                            \
 843                 EFX_CHECK_REG((_enp), (_reg));                          \
 844                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 845                     (_edp), (_lock));                                   \
 846                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 847                     uint32_t, _reg ## _OFST,                            \
 848                     uint32_t, (_edp)->ed_u32[0]);                       \
 849         _NOTE(CONSTANTCONDITION)                                        \
 850         } while (B_FALSE)
 851
 852 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 853         do {                                                            \
 854                 EFX_CHECK_REG((_enp), (_reg));                          \
 855                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 856                     uint32_t, _reg ## _OFST,                            \
 857                     uint32_t, (_edp)->ed_u32[0]);                       \
 858                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 859                     (_edp), (_lock));                                   \
 860         _NOTE(CONSTANTCONDITION)                                        \
 861         } while (B_FALSE)
 862
 863 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 864         do {                                                            \
 865                 EFX_CHECK_REG((_enp), (_reg));                          \
 866                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 867                     (_eqp));                                            \
 868                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 869                     uint32_t, _reg ## _OFST,                            \
 870                     uint32_t, (_eqp)->eq_u32[1],                        \
 871                     uint32_t, (_eqp)->eq_u32[0]);                       \
 872         _NOTE(CONSTANTCONDITION)                                        \
 873         } while (B_FALSE)
 874
 875 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 876         do {                                                            \
 877                 EFX_CHECK_REG((_enp), (_reg));                          \
 878                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 879                     uint32_t, _reg ## _OFST,                            \
 880                     uint32_t, (_eqp)->eq_u32[1],                        \
 881                     uint32_t, (_eqp)->eq_u32[0]);                       \
 882                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 883                     (_eqp));                                            \
 884         _NOTE(CONSTANTCONDITION)                                        \
 885         } while (B_FALSE)
 886
 887 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 888         do {                                                            \
 889                 EFX_CHECK_REG((_enp), (_reg));                          \
 890                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 891                     (_eop), B_TRUE);                                    \
 892                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 893                     uint32_t, _reg ## _OFST,                            \
 894                     uint32_t, (_eop)->eo_u32[3],                        \
 895                     uint32_t, (_eop)->eo_u32[2],                        \
 896                     uint32_t, (_eop)->eo_u32[1],                        \
 897                     uint32_t, (_eop)->eo_u32[0]);                       \
 898         _NOTE(CONSTANTCONDITION)                                        \
 899         } while (B_FALSE)
 900
 901 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 902         do {                                                            \
 903                 EFX_CHECK_REG((_enp), (_reg));                          \
 904                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 905                     uint32_t, _reg ## _OFST,                            \
 906                     uint32_t, (_eop)->eo_u32[3],                        \
 907                     uint32_t, (_eop)->eo_u32[2],                        \
 908                     uint32_t, (_eop)->eo_u32[1],                        \
 909                     uint32_t, (_eop)->eo_u32[0]);                       \
 910                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 911                     (_eop), B_TRUE);                                    \
 912         _NOTE(CONSTANTCONDITION)                                        \
 913         } while (B_FALSE)
 914
 915 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 916         do {                                                            \
 917                 EFX_CHECK_REG((_enp), (_reg));                          \
 918                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 919                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 920                     (_edp), (_lock));                                   \
 921                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 922                     uint32_t, (_index),                                 \
 923                     uint32_t, _reg ## _OFST,                            \
 924                     uint32_t, (_edp)->ed_u32[0]);                       \
 925         _NOTE(CONSTANTCONDITION)                                        \
 926         } while (B_FALSE)
 927
 928 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
 929         do {                                                            \
 930                 EFX_CHECK_REG((_enp), (_reg));                          \
 931                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 932                     uint32_t, (_index),                                 \
 933                     uint32_t, _reg ## _OFST,                            \
 934                     uint32_t, (_edp)->ed_u32[0]);                       \
 935                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 936                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 937                     (_edp), (_lock));                                   \
 938         _NOTE(CONSTANTCONDITION)                                        \
 939         } while (B_FALSE)
 940
 941 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)            \
 942         do {                                                            \
 943                 EFX_CHECK_REG((_enp), (_reg));                          \
 944                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 945                     uint32_t, (_index),                                 \
 946                     uint32_t, _reg ## _OFST,                            \
 947                     uint32_t, (_edp)->ed_u32[0]);                       \
 948                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 949                     (_reg ## _OFST +                                    \
 950                     (2 * sizeof (efx_dword_t)) +                        \
 951                     ((_index) * _reg ## _STEP)),                        \
 952                     (_edp), (_lock));                                   \
 953         _NOTE(CONSTANTCONDITION)                                        \
 954         } while (B_FALSE)
 955
 956 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
 957         do {                                                            \
 958                 EFX_CHECK_REG((_enp), (_reg));                          \
 959                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 960                     uint32_t, (_index),                                 \
 961                     uint32_t, _reg ## _OFST,                            \
 962                     uint32_t, (_edp)->ed_u32[0]);                       \
 963                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 964                     (_reg ## _OFST +                                    \
 965                     (3 * sizeof (efx_dword_t)) +                        \
 966                     ((_index) * _reg ## _STEP)),                        \
 967                     (_edp), (_lock));                                   \
 968         _NOTE(CONSTANTCONDITION)                                        \
 969         } while (B_FALSE)
 970
 971 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
 972         do {                                                            \
 973                 EFX_CHECK_REG((_enp), (_reg));                          \
 974                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
 975                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 976                     (_eqp));                                            \
 977                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
 978                     uint32_t, (_index),                                 \
 979                     uint32_t, _reg ## _OFST,                            \
 980                     uint32_t, (_eqp)->eq_u32[1],                        \
 981                     uint32_t, (_eqp)->eq_u32[0]);                       \
 982         _NOTE(CONSTANTCONDITION)                                        \
 983         } while (B_FALSE)
 984
 985 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
 986         do {                                                            \
 987                 EFX_CHECK_REG((_enp), (_reg));                          \
 988                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
 989                     uint32_t, (_index),                                 \
 990                     uint32_t, _reg ## _OFST,                            \
 991                     uint32_t, (_eqp)->eq_u32[1],                        \
 992                     uint32_t, (_eqp)->eq_u32[0]);                       \
 993                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
 994                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 995                     (_eqp));                                            \
 996         _NOTE(CONSTANTCONDITION)                                        \
 997         } while (B_FALSE)
 998
 999 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
1000         do {                                                            \
1001                 EFX_CHECK_REG((_enp), (_reg));                          \
1002                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
1003                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1004                     (_eop), (_lock));                                   \
1005                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
1006                     uint32_t, (_index),                                 \
1007                     uint32_t, _reg ## _OFST,                            \
1008                     uint32_t, (_eop)->eo_u32[3],                        \
1009                     uint32_t, (_eop)->eo_u32[2],                        \
1010                     uint32_t, (_eop)->eo_u32[1],                        \
1011                     uint32_t, (_eop)->eo_u32[0]);                       \
1012         _NOTE(CONSTANTCONDITION)                                        \
1013         } while (B_FALSE)
1014
1015 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
1016         do {                                                            \
1017                 EFX_CHECK_REG((_enp), (_reg));                          \
1018                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
1019                     uint32_t, (_index),                                 \
1020                     uint32_t, _reg ## _OFST,                            \
1021                     uint32_t, (_eop)->eo_u32[3],                        \
1022                     uint32_t, (_eop)->eo_u32[2],                        \
1023                     uint32_t, (_eop)->eo_u32[1],                        \
1024                     uint32_t, (_eop)->eo_u32[0]);                       \
1025                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
1026                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1027                     (_eop), (_lock));                                   \
1028         _NOTE(CONSTANTCONDITION)                                        \
1029         } while (B_FALSE)
1030
1031 /*
1032  * Allow drivers to perform optimised 128-bit doorbell writes.
1033  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1034  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1035  * the need for locking in the host, and are the only ones known to be safe to
1036  * use 128-bites write with.
1037  */
1038 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)           \
1039         do {                                                            \
1040                 EFX_CHECK_REG((_enp), (_reg));                          \
1041                 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,               \
1042                     const char *, #_reg,                                \
1043                     uint32_t, (_index),                                 \
1044                     uint32_t, _reg ## _OFST,                            \
1045                     uint32_t, (_eop)->eo_u32[3],                        \
1046                     uint32_t, (_eop)->eo_u32[2],                        \
1047                     uint32_t, (_eop)->eo_u32[1],                        \
1048                     uint32_t, (_eop)->eo_u32[0]);                       \
1049                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1050                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1051                     (_eop));                                            \
1052         _NOTE(CONSTANTCONDITION)                                        \
1053         } while (B_FALSE)
1054
1055 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1056         do {                                                            \
1057                 unsigned int _new = (_wptr);                            \
1058                 unsigned int _old = (_owptr);                           \
1059                                                                         \
1060                 if ((_new) >= (_old))                                   \
1061                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1062                             (_old) * sizeof (efx_desc_t),               \
1063                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1064                 else                                                    \
1065                         /*                                              \
1066                          * It is cheaper to sync entire map than sync   \
1067                          * two parts especially when offset/size are    \
1068                          * ignored and entire map is synced in any case.\
1069                          */                                             \
1070                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1071                             0,                                          \
1072                             (_entries) * sizeof (efx_desc_t));          \
1073         _NOTE(CONSTANTCONDITION)                                        \
1074         } while (B_FALSE)
1075
1076 extern  __checkReturn   efx_rc_t
1077 efx_mac_select(
1078         __in            efx_nic_t *enp);
1079
1080 extern  void
1081 efx_mac_multicast_hash_compute(
1082         __in_ecount(6*count)            uint8_t const *addrs,
1083         __in                            int count,
1084         __out                           efx_oword_t *hash_low,
1085         __out                           efx_oword_t *hash_high);
1086
1087 extern  __checkReturn   efx_rc_t
1088 efx_phy_probe(
1089         __in            efx_nic_t *enp);
1090
1091 extern                  void
1092 efx_phy_unprobe(
1093         __in            efx_nic_t *enp);
1094
1095 #if EFSYS_OPT_VPD
1096
1097 /* VPD utility functions */
1098
1099 extern  __checkReturn           efx_rc_t
1100 efx_vpd_hunk_length(
1101         __in_bcount(size)       caddr_t data,
1102         __in                    size_t size,
1103         __out                   size_t *lengthp);
1104
1105 extern  __checkReturn           efx_rc_t
1106 efx_vpd_hunk_verify(
1107         __in_bcount(size)       caddr_t data,
1108         __in                    size_t size,
1109         __out_opt               boolean_t *cksummedp);
1110
1111 extern  __checkReturn           efx_rc_t
1112 efx_vpd_hunk_reinit(
1113         __in_bcount(size)       caddr_t data,
1114         __in                    size_t size,
1115         __in                    boolean_t wantpid);
1116
1117 extern  __checkReturn           efx_rc_t
1118 efx_vpd_hunk_get(
1119         __in_bcount(size)       caddr_t data,
1120         __in                    size_t size,
1121         __in                    efx_vpd_tag_t tag,
1122         __in                    efx_vpd_keyword_t keyword,
1123         __out                   unsigned int *payloadp,
1124         __out                   uint8_t *paylenp);
1125
1126 extern  __checkReturn                   efx_rc_t
1127 efx_vpd_hunk_next(
1128         __in_bcount(size)               caddr_t data,
1129         __in                            size_t size,
1130         __out                           efx_vpd_tag_t *tagp,
1131         __out                           efx_vpd_keyword_t *keyword,
1132         __out_opt                       unsigned int *payloadp,
1133         __out_opt                       uint8_t *paylenp,
1134         __inout                         unsigned int *contp);
1135
1136 extern  __checkReturn           efx_rc_t
1137 efx_vpd_hunk_set(
1138         __in_bcount(size)       caddr_t data,
1139         __in                    size_t size,
1140         __in                    efx_vpd_value_t *evvp);
1141
1142 #endif  /* EFSYS_OPT_VPD */
1143
1144 #if EFSYS_OPT_MCDI
1145
1146 extern  __checkReturn           efx_rc_t
1147 efx_mcdi_set_workaround(
1148         __in                    efx_nic_t *enp,
1149         __in                    uint32_t type,
1150         __in                    boolean_t enabled,
1151         __out_opt               uint32_t *flagsp);
1152
1153 extern  __checkReturn           efx_rc_t
1154 efx_mcdi_get_workarounds(
1155         __in                    efx_nic_t *enp,
1156         __out_opt               uint32_t *implementedp,
1157         __out_opt               uint32_t *enabledp);
1158
1159 #endif /* EFSYS_OPT_MCDI */
1160
1161 #if EFSYS_OPT_MAC_STATS
1162
1163 /*
1164  * Closed range of stats (i.e. the first and the last are included).
1165  * The last must be greater or equal (if the range is one item only) to
1166  * the first.
1167  */
1168 struct efx_mac_stats_range {
1169         efx_mac_stat_t          first;
1170         efx_mac_stat_t          last;
1171 };
1172
1173 extern                                  efx_rc_t
1174 efx_mac_stats_mask_add_ranges(
1175         __inout_bcount(mask_size)       uint32_t *maskp,
1176         __in                            size_t mask_size,
1177         __in_ecount(rng_count)          const struct efx_mac_stats_range *rngp,
1178         __in                            unsigned int rng_count);
1179
1180 #endif  /* EFSYS_OPT_MAC_STATS */
1181
1182 #ifdef  __cplusplus
1183 }
1184 #endif
1185
1186 #endif  /* _SYS_EFX_IMPL_H */