2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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31 #ifndef _SYS_EFX_IMPL_H
32 #define _SYS_EFX_IMPL_H
36 #include "efx_regs_ef10.h"
38 /* FIXME: Add definition for driver generated software events */
39 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
40 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
45 #include "siena_impl.h"
46 #endif /* EFSYS_OPT_SIENA */
48 #if EFSYS_OPT_HUNTINGTON
49 #include "hunt_impl.h"
50 #endif /* EFSYS_OPT_HUNTINGTON */
53 #include "medford_impl.h"
54 #endif /* EFSYS_OPT_MEDFORD */
56 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
57 #include "ef10_impl.h"
58 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
64 #define EFX_MOD_MCDI 0x00000001
65 #define EFX_MOD_PROBE 0x00000002
66 #define EFX_MOD_NVRAM 0x00000004
67 #define EFX_MOD_VPD 0x00000008
68 #define EFX_MOD_NIC 0x00000010
69 #define EFX_MOD_INTR 0x00000020
70 #define EFX_MOD_EV 0x00000040
71 #define EFX_MOD_RX 0x00000080
72 #define EFX_MOD_TX 0x00000100
73 #define EFX_MOD_PORT 0x00000200
74 #define EFX_MOD_MON 0x00000400
75 #define EFX_MOD_FILTER 0x00001000
76 #define EFX_MOD_LIC 0x00002000
78 #define EFX_RESET_PHY 0x00000001
79 #define EFX_RESET_RXQ_ERR 0x00000002
80 #define EFX_RESET_TXQ_ERR 0x00000004
82 typedef enum efx_mac_type_e {
90 typedef struct efx_ev_ops_s {
91 efx_rc_t (*eevo_init)(efx_nic_t *);
92 void (*eevo_fini)(efx_nic_t *);
93 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
94 efsys_mem_t *, size_t, uint32_t,
95 uint32_t, uint32_t, efx_evq_t *);
96 void (*eevo_qdestroy)(efx_evq_t *);
97 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
98 void (*eevo_qpost)(efx_evq_t *, uint16_t);
99 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
101 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
105 typedef struct efx_tx_ops_s {
106 efx_rc_t (*etxo_init)(efx_nic_t *);
107 void (*etxo_fini)(efx_nic_t *);
108 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
109 unsigned int, unsigned int,
110 efsys_mem_t *, size_t,
112 efx_evq_t *, efx_txq_t *,
114 void (*etxo_qdestroy)(efx_txq_t *);
115 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
116 unsigned int, unsigned int,
118 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
119 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
120 efx_rc_t (*etxo_qflush)(efx_txq_t *);
121 void (*etxo_qenable)(efx_txq_t *);
122 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
123 void (*etxo_qpio_disable)(efx_txq_t *);
124 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
126 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
128 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
129 unsigned int, unsigned int,
131 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
134 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
137 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
140 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
143 void (*etxo_qstats_update)(efx_txq_t *,
148 typedef struct efx_rx_ops_s {
149 efx_rc_t (*erxo_init)(efx_nic_t *);
150 void (*erxo_fini)(efx_nic_t *);
151 #if EFSYS_OPT_RX_SCATTER
152 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
154 #if EFSYS_OPT_RX_SCALE
155 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
156 efx_rx_hash_type_t, boolean_t);
157 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
158 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
160 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
162 #endif /* EFSYS_OPT_RX_SCALE */
163 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
165 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
166 unsigned int, unsigned int,
168 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
169 #if EFSYS_OPT_RX_PACKED_STREAM
170 void (*erxo_qps_update_credits)(efx_rxq_t *);
171 uint8_t * (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
173 uint16_t *, uint32_t *, uint32_t *);
175 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
176 void (*erxo_qenable)(efx_rxq_t *);
177 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
178 unsigned int, efx_rxq_type_t,
179 efsys_mem_t *, size_t, uint32_t,
180 efx_evq_t *, efx_rxq_t *);
181 void (*erxo_qdestroy)(efx_rxq_t *);
184 typedef struct efx_mac_ops_s {
185 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
186 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
187 efx_rc_t (*emo_addr_set)(efx_nic_t *);
188 efx_rc_t (*emo_pdu_set)(efx_nic_t *);
189 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *);
190 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
191 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
192 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
193 efx_rxq_t *, boolean_t);
194 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
195 #if EFSYS_OPT_LOOPBACK
196 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
197 efx_loopback_type_t);
198 #endif /* EFSYS_OPT_LOOPBACK */
199 #if EFSYS_OPT_MAC_STATS
200 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
201 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
202 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
203 uint16_t, boolean_t);
204 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
205 efsys_stat_t *, uint32_t *);
206 #endif /* EFSYS_OPT_MAC_STATS */
209 typedef struct efx_phy_ops_s {
210 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
211 efx_rc_t (*epo_reset)(efx_nic_t *);
212 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
213 efx_rc_t (*epo_verify)(efx_nic_t *);
214 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
215 #if EFSYS_OPT_PHY_STATS
216 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
218 #endif /* EFSYS_OPT_PHY_STATS */
220 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
221 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
222 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
223 efx_bist_result_t *, uint32_t *,
224 unsigned long *, size_t);
225 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
226 #endif /* EFSYS_OPT_BIST */
230 typedef struct efx_filter_ops_s {
231 efx_rc_t (*efo_init)(efx_nic_t *);
232 void (*efo_fini)(efx_nic_t *);
233 efx_rc_t (*efo_restore)(efx_nic_t *);
234 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
235 boolean_t may_replace);
236 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
237 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
238 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
239 boolean_t, boolean_t, boolean_t,
240 uint8_t const *, uint32_t);
243 extern __checkReturn efx_rc_t
244 efx_filter_reconfigure(
246 __in_ecount(6) uint8_t const *mac_addr,
247 __in boolean_t all_unicst,
248 __in boolean_t mulcst,
249 __in boolean_t all_mulcst,
250 __in boolean_t brdcst,
251 __in_ecount(6*count) uint8_t const *addrs,
252 __in uint32_t count);
254 #endif /* EFSYS_OPT_FILTER */
257 typedef struct efx_port_s {
258 efx_mac_type_t ep_mac_type;
259 uint32_t ep_phy_type;
262 uint8_t ep_mac_addr[6];
263 efx_link_mode_t ep_link_mode;
264 boolean_t ep_all_unicst;
266 boolean_t ep_all_mulcst;
268 unsigned int ep_fcntl;
269 boolean_t ep_fcntl_autoneg;
270 efx_oword_t ep_multicst_hash[2];
271 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
272 EFX_MAC_MULTICAST_LIST_MAX];
273 uint32_t ep_mulcst_addr_count;
274 #if EFSYS_OPT_LOOPBACK
275 efx_loopback_type_t ep_loopback_type;
276 efx_link_mode_t ep_loopback_link_mode;
277 #endif /* EFSYS_OPT_LOOPBACK */
278 #if EFSYS_OPT_PHY_FLAGS
279 uint32_t ep_phy_flags;
280 #endif /* EFSYS_OPT_PHY_FLAGS */
281 #if EFSYS_OPT_PHY_LED_CONTROL
282 efx_phy_led_mode_t ep_phy_led_mode;
283 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
284 efx_phy_media_type_t ep_fixed_port_type;
285 efx_phy_media_type_t ep_module_type;
286 uint32_t ep_adv_cap_mask;
287 uint32_t ep_lp_cap_mask;
288 uint32_t ep_default_adv_cap_mask;
289 uint32_t ep_phy_cap_mask;
290 boolean_t ep_mac_drain;
291 boolean_t ep_mac_stats_pending;
293 efx_bist_type_t ep_current_bist;
295 const efx_mac_ops_t *ep_emop;
296 const efx_phy_ops_t *ep_epop;
299 typedef struct efx_mon_ops_s {
300 #if EFSYS_OPT_MON_STATS
301 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
302 efx_mon_stat_value_t *);
303 #endif /* EFSYS_OPT_MON_STATS */
306 typedef struct efx_mon_s {
307 efx_mon_type_t em_type;
308 const efx_mon_ops_t *em_emop;
311 typedef struct efx_intr_ops_s {
312 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
313 void (*eio_enable)(efx_nic_t *);
314 void (*eio_disable)(efx_nic_t *);
315 void (*eio_disable_unlocked)(efx_nic_t *);
316 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
317 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
318 void (*eio_status_message)(efx_nic_t *, unsigned int,
320 void (*eio_fatal)(efx_nic_t *);
321 void (*eio_fini)(efx_nic_t *);
324 typedef struct efx_intr_s {
325 const efx_intr_ops_t *ei_eiop;
326 efsys_mem_t *ei_esmp;
327 efx_intr_type_t ei_type;
328 unsigned int ei_level;
331 typedef struct efx_nic_ops_s {
332 efx_rc_t (*eno_probe)(efx_nic_t *);
333 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
334 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
335 efx_rc_t (*eno_reset)(efx_nic_t *);
336 efx_rc_t (*eno_init)(efx_nic_t *);
337 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
338 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
339 uint32_t *, size_t *);
341 efx_rc_t (*eno_register_test)(efx_nic_t *);
342 #endif /* EFSYS_OPT_DIAG */
343 void (*eno_fini)(efx_nic_t *);
344 void (*eno_unprobe)(efx_nic_t *);
347 #ifndef EFX_TXQ_LIMIT_TARGET
348 #define EFX_TXQ_LIMIT_TARGET 259
350 #ifndef EFX_RXQ_LIMIT_TARGET
351 #define EFX_RXQ_LIMIT_TARGET 512
353 #ifndef EFX_TXQ_DC_SIZE
354 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
356 #ifndef EFX_RXQ_DC_SIZE
357 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
364 typedef struct siena_filter_spec_s {
367 uint32_t sfs_dmaq_id;
368 uint32_t sfs_dword[3];
369 } siena_filter_spec_t;
371 typedef enum siena_filter_type_e {
372 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
373 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */
374 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
375 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */
376 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
377 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
379 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
380 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
381 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
382 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */
383 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */
384 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */
386 EFX_SIENA_FILTER_NTYPES
387 } siena_filter_type_t;
389 typedef enum siena_filter_tbl_id_e {
390 EFX_SIENA_FILTER_TBL_RX_IP = 0,
391 EFX_SIENA_FILTER_TBL_RX_MAC,
392 EFX_SIENA_FILTER_TBL_TX_IP,
393 EFX_SIENA_FILTER_TBL_TX_MAC,
394 EFX_SIENA_FILTER_NTBLS
395 } siena_filter_tbl_id_t;
397 typedef struct siena_filter_tbl_s {
398 int sft_size; /* number of entries */
399 int sft_used; /* active count */
400 uint32_t *sft_bitmap; /* active bitmap */
401 siena_filter_spec_t *sft_spec; /* array of saved specs */
402 } siena_filter_tbl_t;
404 typedef struct siena_filter_s {
405 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS];
406 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES];
409 #endif /* EFSYS_OPT_SIENA */
411 typedef struct efx_filter_s {
413 siena_filter_t *ef_siena_filter;
414 #endif /* EFSYS_OPT_SIENA */
415 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
416 ef10_filter_table_t *ef_ef10_filter_table;
417 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
423 siena_filter_tbl_clear(
425 __in siena_filter_tbl_id_t tbl);
427 #endif /* EFSYS_OPT_SIENA */
429 #endif /* EFSYS_OPT_FILTER */
433 typedef struct efx_mcdi_ops_s {
434 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
435 void (*emco_send_request)(efx_nic_t *, void *, size_t,
437 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
438 boolean_t (*emco_poll_response)(efx_nic_t *);
439 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
440 void (*emco_fini)(efx_nic_t *);
441 efx_rc_t (*emco_feature_supported)(efx_nic_t *,
442 efx_mcdi_feature_id_t, boolean_t *);
443 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
447 typedef struct efx_mcdi_s {
448 const efx_mcdi_ops_t *em_emcop;
449 const efx_mcdi_transport_t *em_emtp;
450 efx_mcdi_iface_t em_emip;
453 #endif /* EFSYS_OPT_MCDI */
455 typedef struct efx_drv_cfg_s {
456 uint32_t edc_min_vi_count;
457 uint32_t edc_max_vi_count;
459 uint32_t edc_max_piobuf_count;
460 uint32_t edc_pio_alloc_size;
465 efx_family_t en_family;
466 uint32_t en_features;
467 efsys_identifier_t *en_esip;
468 efsys_lock_t *en_eslp;
469 efsys_bar_t *en_esbp;
470 unsigned int en_mod_flags;
471 unsigned int en_reset_flags;
472 efx_nic_cfg_t en_nic_cfg;
473 efx_drv_cfg_t en_drv_cfg;
477 uint32_t en_ev_qcount;
478 uint32_t en_rx_qcount;
479 uint32_t en_tx_qcount;
480 const efx_nic_ops_t *en_enop;
481 const efx_ev_ops_t *en_eevop;
482 const efx_tx_ops_t *en_etxop;
483 const efx_rx_ops_t *en_erxop;
485 efx_filter_t en_filter;
486 const efx_filter_ops_t *en_efop;
487 #endif /* EFSYS_OPT_FILTER */
490 #endif /* EFSYS_OPT_MCDI */
491 #if EFSYS_OPT_RX_SCALE
492 efx_rx_hash_support_t en_hash_support;
493 efx_rx_scale_support_t en_rss_support;
494 uint32_t en_rss_context;
495 #endif /* EFSYS_OPT_RX_SCALE */
496 uint32_t en_vport_id;
502 #endif /* EFSYS_OPT_SIENA */
505 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
511 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
512 uint32_t ena_piobuf_count;
513 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
514 uint32_t ena_pio_write_vi_base;
515 /* Memory BAR mapping regions */
516 uint32_t ena_uc_mem_map_offset;
517 size_t ena_uc_mem_map_size;
518 uint32_t ena_wc_mem_map_offset;
519 size_t ena_wc_mem_map_size;
522 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
526 #define EFX_NIC_MAGIC 0x02121996
528 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
529 const efx_ev_callbacks_t *, void *);
531 typedef struct efx_evq_rxq_state_s {
532 unsigned int eers_rx_read_ptr;
533 unsigned int eers_rx_mask;
534 #if EFSYS_OPT_RX_PACKED_STREAM
535 unsigned int eers_rx_stream_npackets;
536 boolean_t eers_rx_packed_stream;
537 unsigned int eers_rx_packed_stream_credits;
539 } efx_evq_rxq_state_t;
544 unsigned int ee_index;
545 unsigned int ee_mask;
546 efsys_mem_t *ee_esmp;
548 uint32_t ee_stat[EV_NQSTATS];
549 #endif /* EFSYS_OPT_QSTATS */
551 efx_ev_handler_t ee_rx;
552 efx_ev_handler_t ee_tx;
553 efx_ev_handler_t ee_driver;
554 efx_ev_handler_t ee_global;
555 efx_ev_handler_t ee_drv_gen;
557 efx_ev_handler_t ee_mcdi;
558 #endif /* EFSYS_OPT_MCDI */
560 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
565 #define EFX_EVQ_MAGIC 0x08081997
567 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
573 unsigned int er_index;
574 unsigned int er_label;
575 unsigned int er_mask;
576 efsys_mem_t *er_esmp;
579 #define EFX_RXQ_MAGIC 0x15022005
584 unsigned int et_index;
585 unsigned int et_mask;
586 efsys_mem_t *et_esmp;
587 #if EFSYS_OPT_HUNTINGTON
588 uint32_t et_pio_bufnum;
589 uint32_t et_pio_blknum;
590 uint32_t et_pio_write_offset;
591 uint32_t et_pio_offset;
595 uint32_t et_stat[TX_NQSTATS];
596 #endif /* EFSYS_OPT_QSTATS */
599 #define EFX_TXQ_MAGIC 0x05092005
601 #define EFX_MAC_ADDR_COPY(_dst, _src) \
603 (_dst)[0] = (_src)[0]; \
604 (_dst)[1] = (_src)[1]; \
605 (_dst)[2] = (_src)[2]; \
606 (_dst)[3] = (_src)[3]; \
607 (_dst)[4] = (_src)[4]; \
608 (_dst)[5] = (_src)[5]; \
609 _NOTE(CONSTANTCONDITION) \
612 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
614 uint16_t *_d = (uint16_t *)(_dst); \
618 _NOTE(CONSTANTCONDITION) \
621 #if EFSYS_OPT_CHECK_REG
622 #define EFX_CHECK_REG(_enp, _reg) \
624 const char *name = #_reg; \
625 char min = name[4]; \
626 char max = name[5]; \
629 switch ((_enp)->en_family) { \
630 case EFX_FAMILY_SIENA: \
634 case EFX_FAMILY_HUNTINGTON: \
638 case EFX_FAMILY_MEDFORD: \
647 EFSYS_ASSERT3S(rev, >=, min); \
648 EFSYS_ASSERT3S(rev, <=, max); \
650 _NOTE(CONSTANTCONDITION) \
653 #define EFX_CHECK_REG(_enp, _reg) do { \
654 _NOTE(CONSTANTCONDITION) \
658 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
660 EFX_CHECK_REG((_enp), (_reg)); \
661 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
663 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
664 uint32_t, _reg ## _OFST, \
665 uint32_t, (_edp)->ed_u32[0]); \
666 _NOTE(CONSTANTCONDITION) \
669 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
671 EFX_CHECK_REG((_enp), (_reg)); \
672 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
673 uint32_t, _reg ## _OFST, \
674 uint32_t, (_edp)->ed_u32[0]); \
675 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
677 _NOTE(CONSTANTCONDITION) \
680 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
682 EFX_CHECK_REG((_enp), (_reg)); \
683 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
685 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
686 uint32_t, _reg ## _OFST, \
687 uint32_t, (_eqp)->eq_u32[1], \
688 uint32_t, (_eqp)->eq_u32[0]); \
689 _NOTE(CONSTANTCONDITION) \
692 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
694 EFX_CHECK_REG((_enp), (_reg)); \
695 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
696 uint32_t, _reg ## _OFST, \
697 uint32_t, (_eqp)->eq_u32[1], \
698 uint32_t, (_eqp)->eq_u32[0]); \
699 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
701 _NOTE(CONSTANTCONDITION) \
704 #define EFX_BAR_READO(_enp, _reg, _eop) \
706 EFX_CHECK_REG((_enp), (_reg)); \
707 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
709 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
710 uint32_t, _reg ## _OFST, \
711 uint32_t, (_eop)->eo_u32[3], \
712 uint32_t, (_eop)->eo_u32[2], \
713 uint32_t, (_eop)->eo_u32[1], \
714 uint32_t, (_eop)->eo_u32[0]); \
715 _NOTE(CONSTANTCONDITION) \
718 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
720 EFX_CHECK_REG((_enp), (_reg)); \
721 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
722 uint32_t, _reg ## _OFST, \
723 uint32_t, (_eop)->eo_u32[3], \
724 uint32_t, (_eop)->eo_u32[2], \
725 uint32_t, (_eop)->eo_u32[1], \
726 uint32_t, (_eop)->eo_u32[0]); \
727 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
729 _NOTE(CONSTANTCONDITION) \
732 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
734 EFX_CHECK_REG((_enp), (_reg)); \
735 EFSYS_BAR_READD((_enp)->en_esbp, \
736 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
738 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
739 uint32_t, (_index), \
740 uint32_t, _reg ## _OFST, \
741 uint32_t, (_edp)->ed_u32[0]); \
742 _NOTE(CONSTANTCONDITION) \
745 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
747 EFX_CHECK_REG((_enp), (_reg)); \
748 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
749 uint32_t, (_index), \
750 uint32_t, _reg ## _OFST, \
751 uint32_t, (_edp)->ed_u32[0]); \
752 EFSYS_BAR_WRITED((_enp)->en_esbp, \
753 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
755 _NOTE(CONSTANTCONDITION) \
758 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \
760 EFX_CHECK_REG((_enp), (_reg)); \
761 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
762 uint32_t, (_index), \
763 uint32_t, _reg ## _OFST, \
764 uint32_t, (_edp)->ed_u32[0]); \
765 EFSYS_BAR_WRITED((_enp)->en_esbp, \
767 (2 * sizeof (efx_dword_t)) + \
768 ((_index) * _reg ## _STEP)), \
770 _NOTE(CONSTANTCONDITION) \
773 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
775 EFX_CHECK_REG((_enp), (_reg)); \
776 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
777 uint32_t, (_index), \
778 uint32_t, _reg ## _OFST, \
779 uint32_t, (_edp)->ed_u32[0]); \
780 EFSYS_BAR_WRITED((_enp)->en_esbp, \
782 (3 * sizeof (efx_dword_t)) + \
783 ((_index) * _reg ## _STEP)), \
785 _NOTE(CONSTANTCONDITION) \
788 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
790 EFX_CHECK_REG((_enp), (_reg)); \
791 EFSYS_BAR_READQ((_enp)->en_esbp, \
792 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
794 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
795 uint32_t, (_index), \
796 uint32_t, _reg ## _OFST, \
797 uint32_t, (_eqp)->eq_u32[1], \
798 uint32_t, (_eqp)->eq_u32[0]); \
799 _NOTE(CONSTANTCONDITION) \
802 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
804 EFX_CHECK_REG((_enp), (_reg)); \
805 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
806 uint32_t, (_index), \
807 uint32_t, _reg ## _OFST, \
808 uint32_t, (_eqp)->eq_u32[1], \
809 uint32_t, (_eqp)->eq_u32[0]); \
810 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
811 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
813 _NOTE(CONSTANTCONDITION) \
816 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
818 EFX_CHECK_REG((_enp), (_reg)); \
819 EFSYS_BAR_READO((_enp)->en_esbp, \
820 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
822 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
823 uint32_t, (_index), \
824 uint32_t, _reg ## _OFST, \
825 uint32_t, (_eop)->eo_u32[3], \
826 uint32_t, (_eop)->eo_u32[2], \
827 uint32_t, (_eop)->eo_u32[1], \
828 uint32_t, (_eop)->eo_u32[0]); \
829 _NOTE(CONSTANTCONDITION) \
832 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
834 EFX_CHECK_REG((_enp), (_reg)); \
835 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
836 uint32_t, (_index), \
837 uint32_t, _reg ## _OFST, \
838 uint32_t, (_eop)->eo_u32[3], \
839 uint32_t, (_eop)->eo_u32[2], \
840 uint32_t, (_eop)->eo_u32[1], \
841 uint32_t, (_eop)->eo_u32[0]); \
842 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
843 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
845 _NOTE(CONSTANTCONDITION) \
849 * Allow drivers to perform optimised 128-bit doorbell writes.
850 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
851 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
852 * the need for locking in the host, and are the only ones known to be safe to
853 * use 128-bites write with.
855 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
857 EFX_CHECK_REG((_enp), (_reg)); \
858 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
861 uint32_t, (_index), \
862 uint32_t, _reg ## _OFST, \
863 uint32_t, (_eop)->eo_u32[3], \
864 uint32_t, (_eop)->eo_u32[2], \
865 uint32_t, (_eop)->eo_u32[1], \
866 uint32_t, (_eop)->eo_u32[0]); \
867 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
868 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
870 _NOTE(CONSTANTCONDITION) \
873 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
875 unsigned int _new = (_wptr); \
876 unsigned int _old = (_owptr); \
878 if ((_new) >= (_old)) \
879 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
880 (_old) * sizeof (efx_desc_t), \
881 ((_new) - (_old)) * sizeof (efx_desc_t)); \
884 * It is cheaper to sync entire map than sync \
885 * two parts especially when offset/size are \
886 * ignored and entire map is synced in any case.\
888 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
890 (_entries) * sizeof (efx_desc_t)); \
891 _NOTE(CONSTANTCONDITION) \
894 extern __checkReturn efx_rc_t
896 __in efx_nic_t *enp);
898 extern __checkReturn efx_rc_t
900 __in efx_nic_t *enp);
903 efx_mac_multicast_hash_compute(
904 __in_ecount(6*count) uint8_t const *addrs,
906 __out efx_oword_t *hash_low,
907 __out efx_oword_t *hash_high);
909 extern __checkReturn efx_rc_t
911 __in efx_nic_t *enp);
915 __in efx_nic_t *enp);
919 extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[];
921 typedef struct efx_register_set_s {
922 unsigned int address;
926 } efx_register_set_t;
928 extern __checkReturn efx_rc_t
929 efx_nic_test_registers(
931 __in efx_register_set_t *rsp,
934 extern __checkReturn efx_rc_t
937 __in efx_register_set_t *rsp,
938 __in efx_pattern_type_t pattern,
941 #endif /* EFSYS_OPT_DIAG */
945 extern __checkReturn efx_rc_t
946 efx_mcdi_set_workaround(
949 __in boolean_t enabled,
950 __out_opt uint32_t *flagsp);
952 extern __checkReturn efx_rc_t
953 efx_mcdi_get_workarounds(
955 __out_opt uint32_t *implementedp,
956 __out_opt uint32_t *enabledp);
958 #endif /* EFSYS_OPT_MCDI */
960 #if EFSYS_OPT_MAC_STATS
963 * Closed range of stats (i.e. the first and the last are included).
964 * The last must be greater or equal (if the range is one item only) to
967 struct efx_mac_stats_range {
968 efx_mac_stat_t first;
973 efx_mac_stats_mask_add_ranges(
974 __inout_bcount(mask_size) uint32_t *maskp,
975 __in size_t mask_size,
976 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp,
977 __in unsigned int rng_count);
979 #endif /* EFSYS_OPT_MAC_STATS */
985 #endif /* _SYS_EFX_IMPL_H */