drivers/net/sfc/base/efx_impl.h

   1 /*
   2  * Copyright (c) 2007-2016 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  */
  30
  31 #ifndef _SYS_EFX_IMPL_H
  32 #define _SYS_EFX_IMPL_H
  33
  34 #include "efx.h"
  35 #include "efx_regs.h"
  36 #include "efx_regs_ef10.h"
  37
  38 /* FIXME: Add definition for driver generated software events */
  39 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  40 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  41 #endif
  42
  43
  44 #if EFSYS_OPT_SIENA
  45 #include "siena_impl.h"
  46 #endif  /* EFSYS_OPT_SIENA */
  47
  48 #ifdef  __cplusplus
  49 extern "C" {
  50 #endif
  51
  52 #define EFX_MOD_MCDI            0x00000001
  53 #define EFX_MOD_PROBE           0x00000002
  54 #define EFX_MOD_NVRAM           0x00000004
  55 #define EFX_MOD_VPD             0x00000008
  56 #define EFX_MOD_NIC             0x00000010
  57 #define EFX_MOD_INTR            0x00000020
  58 #define EFX_MOD_EV              0x00000040
  59 #define EFX_MOD_RX              0x00000080
  60 #define EFX_MOD_TX              0x00000100
  61 #define EFX_MOD_PORT            0x00000200
  62 #define EFX_MOD_MON             0x00000400
  63 #define EFX_MOD_FILTER          0x00001000
  64 #define EFX_MOD_LIC             0x00002000
  65
  66 #define EFX_RESET_PHY           0x00000001
  67 #define EFX_RESET_RXQ_ERR       0x00000002
  68 #define EFX_RESET_TXQ_ERR       0x00000004
  69
  70 typedef enum efx_mac_type_e {
  71         EFX_MAC_INVALID = 0,
  72         EFX_MAC_SIENA,
  73         EFX_MAC_HUNTINGTON,
  74         EFX_MAC_MEDFORD,
  75         EFX_MAC_NTYPES
  76 } efx_mac_type_t;
  77
  78 typedef struct efx_ev_ops_s {
  79         efx_rc_t        (*eevo_init)(efx_nic_t *);
  80         void            (*eevo_fini)(efx_nic_t *);
  81         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  82                                           efsys_mem_t *, size_t, uint32_t,
  83                                           uint32_t, uint32_t, efx_evq_t *);
  84         void            (*eevo_qdestroy)(efx_evq_t *);
  85         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  86         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  87         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
  88 } efx_ev_ops_t;
  89
  90 typedef struct efx_tx_ops_s {
  91         efx_rc_t        (*etxo_init)(efx_nic_t *);
  92         void            (*etxo_fini)(efx_nic_t *);
  93         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
  94                                         unsigned int, unsigned int,
  95                                         efsys_mem_t *, size_t,
  96                                         uint32_t, uint16_t,
  97                                         efx_evq_t *, efx_txq_t *,
  98                                         unsigned int *);
  99         void            (*etxo_qdestroy)(efx_txq_t *);
 100         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 101                                       unsigned int, unsigned int,
 102                                       unsigned int *);
 103         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 104         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 105         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 106         void            (*etxo_qenable)(efx_txq_t *);
 107         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 108         void            (*etxo_qpio_disable)(efx_txq_t *);
 109         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 110                                            size_t);
 111         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 112                                            unsigned int *);
 113         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 114                                       unsigned int, unsigned int,
 115                                       unsigned int *);
 116         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 117                                                 size_t, boolean_t,
 118                                                 efx_desc_t *);
 119         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 120                                                 uint32_t, uint8_t,
 121                                                 efx_desc_t *);
 122         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 123                                                 uint32_t, uint16_t,
 124                                                 efx_desc_t *, int);
 125         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 126                                                 efx_desc_t *);
 127 } efx_tx_ops_t;
 128
 129 typedef struct efx_rx_ops_s {
 130         efx_rc_t        (*erxo_init)(efx_nic_t *);
 131         void            (*erxo_fini)(efx_nic_t *);
 132         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 133                                               uint16_t *);
 134         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 135                                       unsigned int, unsigned int,
 136                                       unsigned int);
 137         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 138         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 139         void            (*erxo_qenable)(efx_rxq_t *);
 140         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 141                                         unsigned int, efx_rxq_type_t,
 142                                         efsys_mem_t *, size_t, uint32_t,
 143                                         efx_evq_t *, efx_rxq_t *);
 144         void            (*erxo_qdestroy)(efx_rxq_t *);
 145 } efx_rx_ops_t;
 146
 147 typedef struct efx_mac_ops_s {
 148         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 149         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 150         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 151         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 152         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 153         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 154         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 155         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 156                                                       efx_rxq_t *, boolean_t);
 157         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 158 } efx_mac_ops_t;
 159
 160 typedef struct efx_phy_ops_s {
 161         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 162         efx_rc_t        (*epo_reset)(efx_nic_t *);
 163         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 164         efx_rc_t        (*epo_verify)(efx_nic_t *);
 165         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 166 } efx_phy_ops_t;
 167
 168 #if EFSYS_OPT_FILTER
 169 typedef struct efx_filter_ops_s {
 170         efx_rc_t        (*efo_init)(efx_nic_t *);
 171         void            (*efo_fini)(efx_nic_t *);
 172         efx_rc_t        (*efo_restore)(efx_nic_t *);
 173         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 174                                    boolean_t may_replace);
 175         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 176         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
 177         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 178                                    boolean_t, boolean_t, boolean_t,
 179                                    uint8_t const *, uint32_t);
 180 } efx_filter_ops_t;
 181
 182 extern  __checkReturn   efx_rc_t
 183 efx_filter_reconfigure(
 184         __in                            efx_nic_t *enp,
 185         __in_ecount(6)                  uint8_t const *mac_addr,
 186         __in                            boolean_t all_unicst,
 187         __in                            boolean_t mulcst,
 188         __in                            boolean_t all_mulcst,
 189         __in                            boolean_t brdcst,
 190         __in_ecount(6*count)            uint8_t const *addrs,
 191         __in                            uint32_t count);
 192
 193 #endif /* EFSYS_OPT_FILTER */
 194
 195
 196 typedef struct efx_port_s {
 197         efx_mac_type_t          ep_mac_type;
 198         uint32_t                ep_phy_type;
 199         uint8_t                 ep_port;
 200         uint32_t                ep_mac_pdu;
 201         uint8_t                 ep_mac_addr[6];
 202         efx_link_mode_t         ep_link_mode;
 203         boolean_t               ep_all_unicst;
 204         boolean_t               ep_mulcst;
 205         boolean_t               ep_all_mulcst;
 206         boolean_t               ep_brdcst;
 207         unsigned int            ep_fcntl;
 208         boolean_t               ep_fcntl_autoneg;
 209         efx_oword_t             ep_multicst_hash[2];
 210         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 211                                                     EFX_MAC_MULTICAST_LIST_MAX];
 212         uint32_t                ep_mulcst_addr_count;
 213         efx_phy_media_type_t    ep_fixed_port_type;
 214         efx_phy_media_type_t    ep_module_type;
 215         uint32_t                ep_adv_cap_mask;
 216         uint32_t                ep_lp_cap_mask;
 217         uint32_t                ep_default_adv_cap_mask;
 218         uint32_t                ep_phy_cap_mask;
 219         boolean_t               ep_mac_drain;
 220         boolean_t               ep_mac_stats_pending;
 221         const efx_mac_ops_t     *ep_emop;
 222         const efx_phy_ops_t     *ep_epop;
 223 } efx_port_t;
 224
 225 typedef struct efx_mon_ops_s {
 226 } efx_mon_ops_t;
 227
 228 typedef struct efx_mon_s {
 229         efx_mon_type_t          em_type;
 230         const efx_mon_ops_t     *em_emop;
 231 } efx_mon_t;
 232
 233 typedef struct efx_intr_ops_s {
 234         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 235         void            (*eio_enable)(efx_nic_t *);
 236         void            (*eio_disable)(efx_nic_t *);
 237         void            (*eio_disable_unlocked)(efx_nic_t *);
 238         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 239         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 240         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 241                                  boolean_t *);
 242         void            (*eio_fatal)(efx_nic_t *);
 243         void            (*eio_fini)(efx_nic_t *);
 244 } efx_intr_ops_t;
 245
 246 typedef struct efx_intr_s {
 247         const efx_intr_ops_t    *ei_eiop;
 248         efsys_mem_t             *ei_esmp;
 249         efx_intr_type_t         ei_type;
 250         unsigned int            ei_level;
 251 } efx_intr_t;
 252
 253 typedef struct efx_nic_ops_s {
 254         efx_rc_t        (*eno_probe)(efx_nic_t *);
 255         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 256         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 257         efx_rc_t        (*eno_reset)(efx_nic_t *);
 258         efx_rc_t        (*eno_init)(efx_nic_t *);
 259         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 260         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 261                                         uint32_t *, size_t *);
 262         void            (*eno_fini)(efx_nic_t *);
 263         void            (*eno_unprobe)(efx_nic_t *);
 264 } efx_nic_ops_t;
 265
 266 #ifndef EFX_TXQ_LIMIT_TARGET
 267 #define EFX_TXQ_LIMIT_TARGET 259
 268 #endif
 269 #ifndef EFX_RXQ_LIMIT_TARGET
 270 #define EFX_RXQ_LIMIT_TARGET 512
 271 #endif
 272 #ifndef EFX_TXQ_DC_SIZE
 273 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
 274 #endif
 275 #ifndef EFX_RXQ_DC_SIZE
 276 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
 277 #endif
 278
 279 #if EFSYS_OPT_FILTER
 280
 281 #if EFSYS_OPT_SIENA
 282
 283 typedef struct siena_filter_spec_s {
 284         uint8_t         sfs_type;
 285         uint32_t        sfs_flags;
 286         uint32_t        sfs_dmaq_id;
 287         uint32_t        sfs_dword[3];
 288 } siena_filter_spec_t;
 289
 290 typedef enum siena_filter_type_e {
 291         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 292         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 293         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 294         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 295         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 296         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 297
 298         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 299         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 300         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 301         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 302         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 303         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 304
 305         EFX_SIENA_FILTER_NTYPES
 306 } siena_filter_type_t;
 307
 308 typedef enum siena_filter_tbl_id_e {
 309         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 310         EFX_SIENA_FILTER_TBL_RX_MAC,
 311         EFX_SIENA_FILTER_TBL_TX_IP,
 312         EFX_SIENA_FILTER_TBL_TX_MAC,
 313         EFX_SIENA_FILTER_NTBLS
 314 } siena_filter_tbl_id_t;
 315
 316 typedef struct siena_filter_tbl_s {
 317         int                     sft_size;       /* number of entries */
 318         int                     sft_used;       /* active count */
 319         uint32_t                *sft_bitmap;    /* active bitmap */
 320         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 321 } siena_filter_tbl_t;
 322
 323 typedef struct siena_filter_s {
 324         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 325         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 326 } siena_filter_t;
 327
 328 #endif  /* EFSYS_OPT_SIENA */
 329
 330 typedef struct efx_filter_s {
 331 #if EFSYS_OPT_SIENA
 332         siena_filter_t          *ef_siena_filter;
 333 #endif /* EFSYS_OPT_SIENA */
 334 } efx_filter_t;
 335
 336 #if EFSYS_OPT_SIENA
 337
 338 extern                  void
 339 siena_filter_tbl_clear(
 340         __in            efx_nic_t *enp,
 341         __in            siena_filter_tbl_id_t tbl);
 342
 343 #endif  /* EFSYS_OPT_SIENA */
 344
 345 #endif  /* EFSYS_OPT_FILTER */
 346
 347 #if EFSYS_OPT_MCDI
 348
 349 typedef struct efx_mcdi_ops_s {
 350         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 351         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 352                                         void *, size_t);
 353         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 354         boolean_t       (*emco_poll_response)(efx_nic_t *);
 355         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 356         void            (*emco_fini)(efx_nic_t *);
 357         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 358                                             efx_mcdi_feature_id_t, boolean_t *);
 359         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 360                                             uint32_t *);
 361 } efx_mcdi_ops_t;
 362
 363 typedef struct efx_mcdi_s {
 364         const efx_mcdi_ops_t            *em_emcop;
 365         const efx_mcdi_transport_t      *em_emtp;
 366         efx_mcdi_iface_t                em_emip;
 367 } efx_mcdi_t;
 368
 369 #endif /* EFSYS_OPT_MCDI */
 370
 371 typedef struct efx_drv_cfg_s {
 372         uint32_t                edc_min_vi_count;
 373         uint32_t                edc_max_vi_count;
 374
 375         uint32_t                edc_max_piobuf_count;
 376         uint32_t                edc_pio_alloc_size;
 377 } efx_drv_cfg_t;
 378
 379 struct efx_nic_s {
 380         uint32_t                en_magic;
 381         efx_family_t            en_family;
 382         uint32_t                en_features;
 383         efsys_identifier_t      *en_esip;
 384         efsys_lock_t            *en_eslp;
 385         efsys_bar_t             *en_esbp;
 386         unsigned int            en_mod_flags;
 387         unsigned int            en_reset_flags;
 388         efx_nic_cfg_t           en_nic_cfg;
 389         efx_drv_cfg_t           en_drv_cfg;
 390         efx_port_t              en_port;
 391         efx_mon_t               en_mon;
 392         efx_intr_t              en_intr;
 393         uint32_t                en_ev_qcount;
 394         uint32_t                en_rx_qcount;
 395         uint32_t                en_tx_qcount;
 396         const efx_nic_ops_t     *en_enop;
 397         const efx_ev_ops_t      *en_eevop;
 398         const efx_tx_ops_t      *en_etxop;
 399         const efx_rx_ops_t      *en_erxop;
 400 #if EFSYS_OPT_FILTER
 401         efx_filter_t            en_filter;
 402         const efx_filter_ops_t  *en_efop;
 403 #endif  /* EFSYS_OPT_FILTER */
 404 #if EFSYS_OPT_MCDI
 405         efx_mcdi_t              en_mcdi;
 406 #endif  /* EFSYS_OPT_MCDI */
 407         uint32_t                en_vport_id;
 408         union {
 409 #if EFSYS_OPT_SIENA
 410                 struct {
 411                         int                     enu_unused;
 412                 } siena;
 413 #endif  /* EFSYS_OPT_SIENA */
 414                 int     enu_unused;
 415         } en_u;
 416 };
 417
 418
 419 #define EFX_NIC_MAGIC   0x02121996
 420
 421 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 422     const efx_ev_callbacks_t *, void *);
 423
 424 typedef struct efx_evq_rxq_state_s {
 425         unsigned int                    eers_rx_read_ptr;
 426         unsigned int                    eers_rx_mask;
 427 } efx_evq_rxq_state_t;
 428
 429 struct efx_evq_s {
 430         uint32_t                        ee_magic;
 431         efx_nic_t                       *ee_enp;
 432         unsigned int                    ee_index;
 433         unsigned int                    ee_mask;
 434         efsys_mem_t                     *ee_esmp;
 435
 436         efx_ev_handler_t                ee_rx;
 437         efx_ev_handler_t                ee_tx;
 438         efx_ev_handler_t                ee_driver;
 439         efx_ev_handler_t                ee_global;
 440         efx_ev_handler_t                ee_drv_gen;
 441 #if EFSYS_OPT_MCDI
 442         efx_ev_handler_t                ee_mcdi;
 443 #endif  /* EFSYS_OPT_MCDI */
 444
 445         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 446
 447         uint32_t                        ee_flags;
 448 };
 449
 450 #define EFX_EVQ_MAGIC   0x08081997
 451
 452 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 453
 454 struct efx_rxq_s {
 455         uint32_t                        er_magic;
 456         efx_nic_t                       *er_enp;
 457         efx_evq_t                       *er_eep;
 458         unsigned int                    er_index;
 459         unsigned int                    er_label;
 460         unsigned int                    er_mask;
 461         efsys_mem_t                     *er_esmp;
 462 };
 463
 464 #define EFX_RXQ_MAGIC   0x15022005
 465
 466 struct efx_txq_s {
 467         uint32_t                        et_magic;
 468         efx_nic_t                       *et_enp;
 469         unsigned int                    et_index;
 470         unsigned int                    et_mask;
 471         efsys_mem_t                     *et_esmp;
 472 };
 473
 474 #define EFX_TXQ_MAGIC   0x05092005
 475
 476 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 477         do {                                                            \
 478                 (_dst)[0] = (_src)[0];                                  \
 479                 (_dst)[1] = (_src)[1];                                  \
 480                 (_dst)[2] = (_src)[2];                                  \
 481                 (_dst)[3] = (_src)[3];                                  \
 482                 (_dst)[4] = (_src)[4];                                  \
 483                 (_dst)[5] = (_src)[5];                                  \
 484         _NOTE(CONSTANTCONDITION)                                        \
 485         } while (B_FALSE)
 486
 487 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 488         do {                                                            \
 489                 uint16_t *_d = (uint16_t *)(_dst);                      \
 490                 _d[0] = 0xffff;                                         \
 491                 _d[1] = 0xffff;                                         \
 492                 _d[2] = 0xffff;                                         \
 493         _NOTE(CONSTANTCONDITION)                                        \
 494         } while (B_FALSE)
 495
 496 #if EFSYS_OPT_CHECK_REG
 497 #define EFX_CHECK_REG(_enp, _reg)                                       \
 498         do {                                                            \
 499                 const char *name = #_reg;                               \
 500                 char min = name[4];                                     \
 501                 char max = name[5];                                     \
 502                 char rev;                                               \
 503                                                                         \
 504                 switch ((_enp)->en_family) {                            \
 505                 case EFX_FAMILY_SIENA:                                  \
 506                         rev = 'C';                                      \
 507                         break;                                          \
 508                                                                         \
 509                 case EFX_FAMILY_HUNTINGTON:                             \
 510                         rev = 'D';                                      \
 511                         break;                                          \
 512                                                                         \
 513                 case EFX_FAMILY_MEDFORD:                                \
 514                         rev = 'E';                                      \
 515                         break;                                          \
 516                                                                         \
 517                 default:                                                \
 518                         rev = '?';                                      \
 519                         break;                                          \
 520                 }                                                       \
 521                                                                         \
 522                 EFSYS_ASSERT3S(rev, >=, min);                           \
 523                 EFSYS_ASSERT3S(rev, <=, max);                           \
 524                                                                         \
 525         _NOTE(CONSTANTCONDITION)                                        \
 526         } while (B_FALSE)
 527 #else
 528 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 529         _NOTE(CONSTANTCONDITION)                                        \
 530         } while (B_FALSE)
 531 #endif
 532
 533 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 534         do {                                                            \
 535                 EFX_CHECK_REG((_enp), (_reg));                          \
 536                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 537                     (_edp), (_lock));                                   \
 538                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 539                     uint32_t, _reg ## _OFST,                            \
 540                     uint32_t, (_edp)->ed_u32[0]);                       \
 541         _NOTE(CONSTANTCONDITION)                                        \
 542         } while (B_FALSE)
 543
 544 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 545         do {                                                            \
 546                 EFX_CHECK_REG((_enp), (_reg));                          \
 547                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 548                     uint32_t, _reg ## _OFST,                            \
 549                     uint32_t, (_edp)->ed_u32[0]);                       \
 550                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 551                     (_edp), (_lock));                                   \
 552         _NOTE(CONSTANTCONDITION)                                        \
 553         } while (B_FALSE)
 554
 555 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 556         do {                                                            \
 557                 EFX_CHECK_REG((_enp), (_reg));                          \
 558                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 559                     (_eqp));                                            \
 560                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 561                     uint32_t, _reg ## _OFST,                            \
 562                     uint32_t, (_eqp)->eq_u32[1],                        \
 563                     uint32_t, (_eqp)->eq_u32[0]);                       \
 564         _NOTE(CONSTANTCONDITION)                                        \
 565         } while (B_FALSE)
 566
 567 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 568         do {                                                            \
 569                 EFX_CHECK_REG((_enp), (_reg));                          \
 570                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 571                     uint32_t, _reg ## _OFST,                            \
 572                     uint32_t, (_eqp)->eq_u32[1],                        \
 573                     uint32_t, (_eqp)->eq_u32[0]);                       \
 574                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 575                     (_eqp));                                            \
 576         _NOTE(CONSTANTCONDITION)                                        \
 577         } while (B_FALSE)
 578
 579 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 580         do {                                                            \
 581                 EFX_CHECK_REG((_enp), (_reg));                          \
 582                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 583                     (_eop), B_TRUE);                                    \
 584                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 585                     uint32_t, _reg ## _OFST,                            \
 586                     uint32_t, (_eop)->eo_u32[3],                        \
 587                     uint32_t, (_eop)->eo_u32[2],                        \
 588                     uint32_t, (_eop)->eo_u32[1],                        \
 589                     uint32_t, (_eop)->eo_u32[0]);                       \
 590         _NOTE(CONSTANTCONDITION)                                        \
 591         } while (B_FALSE)
 592
 593 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 594         do {                                                            \
 595                 EFX_CHECK_REG((_enp), (_reg));                          \
 596                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 597                     uint32_t, _reg ## _OFST,                            \
 598                     uint32_t, (_eop)->eo_u32[3],                        \
 599                     uint32_t, (_eop)->eo_u32[2],                        \
 600                     uint32_t, (_eop)->eo_u32[1],                        \
 601                     uint32_t, (_eop)->eo_u32[0]);                       \
 602                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 603                     (_eop), B_TRUE);                                    \
 604         _NOTE(CONSTANTCONDITION)                                        \
 605         } while (B_FALSE)
 606
 607 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 608         do {                                                            \
 609                 EFX_CHECK_REG((_enp), (_reg));                          \
 610                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 611                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 612                     (_edp), (_lock));                                   \
 613                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 614                     uint32_t, (_index),                                 \
 615                     uint32_t, _reg ## _OFST,                            \
 616                     uint32_t, (_edp)->ed_u32[0]);                       \
 617         _NOTE(CONSTANTCONDITION)                                        \
 618         } while (B_FALSE)
 619
 620 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
 621         do {                                                            \
 622                 EFX_CHECK_REG((_enp), (_reg));                          \
 623                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 624                     uint32_t, (_index),                                 \
 625                     uint32_t, _reg ## _OFST,                            \
 626                     uint32_t, (_edp)->ed_u32[0]);                       \
 627                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 628                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 629                     (_edp), (_lock));                                   \
 630         _NOTE(CONSTANTCONDITION)                                        \
 631         } while (B_FALSE)
 632
 633 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)            \
 634         do {                                                            \
 635                 EFX_CHECK_REG((_enp), (_reg));                          \
 636                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 637                     uint32_t, (_index),                                 \
 638                     uint32_t, _reg ## _OFST,                            \
 639                     uint32_t, (_edp)->ed_u32[0]);                       \
 640                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 641                     (_reg ## _OFST +                                    \
 642                     (2 * sizeof (efx_dword_t)) +                        \
 643                     ((_index) * _reg ## _STEP)),                        \
 644                     (_edp), (_lock));                                   \
 645         _NOTE(CONSTANTCONDITION)                                        \
 646         } while (B_FALSE)
 647
 648 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
 649         do {                                                            \
 650                 EFX_CHECK_REG((_enp), (_reg));                          \
 651                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 652                     uint32_t, (_index),                                 \
 653                     uint32_t, _reg ## _OFST,                            \
 654                     uint32_t, (_edp)->ed_u32[0]);                       \
 655                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 656                     (_reg ## _OFST +                                    \
 657                     (3 * sizeof (efx_dword_t)) +                        \
 658                     ((_index) * _reg ## _STEP)),                        \
 659                     (_edp), (_lock));                                   \
 660         _NOTE(CONSTANTCONDITION)                                        \
 661         } while (B_FALSE)
 662
 663 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
 664         do {                                                            \
 665                 EFX_CHECK_REG((_enp), (_reg));                          \
 666                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
 667                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 668                     (_eqp));                                            \
 669                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
 670                     uint32_t, (_index),                                 \
 671                     uint32_t, _reg ## _OFST,                            \
 672                     uint32_t, (_eqp)->eq_u32[1],                        \
 673                     uint32_t, (_eqp)->eq_u32[0]);                       \
 674         _NOTE(CONSTANTCONDITION)                                        \
 675         } while (B_FALSE)
 676
 677 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
 678         do {                                                            \
 679                 EFX_CHECK_REG((_enp), (_reg));                          \
 680                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
 681                     uint32_t, (_index),                                 \
 682                     uint32_t, _reg ## _OFST,                            \
 683                     uint32_t, (_eqp)->eq_u32[1],                        \
 684                     uint32_t, (_eqp)->eq_u32[0]);                       \
 685                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
 686                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 687                     (_eqp));                                            \
 688         _NOTE(CONSTANTCONDITION)                                        \
 689         } while (B_FALSE)
 690
 691 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
 692         do {                                                            \
 693                 EFX_CHECK_REG((_enp), (_reg));                          \
 694                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
 695                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 696                     (_eop), (_lock));                                   \
 697                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
 698                     uint32_t, (_index),                                 \
 699                     uint32_t, _reg ## _OFST,                            \
 700                     uint32_t, (_eop)->eo_u32[3],                        \
 701                     uint32_t, (_eop)->eo_u32[2],                        \
 702                     uint32_t, (_eop)->eo_u32[1],                        \
 703                     uint32_t, (_eop)->eo_u32[0]);                       \
 704         _NOTE(CONSTANTCONDITION)                                        \
 705         } while (B_FALSE)
 706
 707 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
 708         do {                                                            \
 709                 EFX_CHECK_REG((_enp), (_reg));                          \
 710                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
 711                     uint32_t, (_index),                                 \
 712                     uint32_t, _reg ## _OFST,                            \
 713                     uint32_t, (_eop)->eo_u32[3],                        \
 714                     uint32_t, (_eop)->eo_u32[2],                        \
 715                     uint32_t, (_eop)->eo_u32[1],                        \
 716                     uint32_t, (_eop)->eo_u32[0]);                       \
 717                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
 718                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 719                     (_eop), (_lock));                                   \
 720         _NOTE(CONSTANTCONDITION)                                        \
 721         } while (B_FALSE)
 722
 723 /*
 724  * Allow drivers to perform optimised 128-bit doorbell writes.
 725  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
 726  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
 727  * the need for locking in the host, and are the only ones known to be safe to
 728  * use 128-bites write with.
 729  */
 730 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)           \
 731         do {                                                            \
 732                 EFX_CHECK_REG((_enp), (_reg));                          \
 733                 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,               \
 734                     const char *,                                       \
 735                     #_reg,                                              \
 736                     uint32_t, (_index),                                 \
 737                     uint32_t, _reg ## _OFST,                            \
 738                     uint32_t, (_eop)->eo_u32[3],                        \
 739                     uint32_t, (_eop)->eo_u32[2],                        \
 740                     uint32_t, (_eop)->eo_u32[1],                        \
 741                     uint32_t, (_eop)->eo_u32[0]);                       \
 742                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
 743                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 744                     (_eop));                                            \
 745         _NOTE(CONSTANTCONDITION)                                        \
 746         } while (B_FALSE)
 747
 748 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
 749         do {                                                            \
 750                 unsigned int _new = (_wptr);                            \
 751                 unsigned int _old = (_owptr);                           \
 752                                                                         \
 753                 if ((_new) >= (_old))                                   \
 754                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
 755                             (_old) * sizeof (efx_desc_t),               \
 756                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
 757                 else                                                    \
 758                         /*                                              \
 759                          * It is cheaper to sync entire map than sync   \
 760                          * two parts especially when offset/size are    \
 761                          * ignored and entire map is synced in any case.\
 762                          */                                             \
 763                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
 764                             0,                                          \
 765                             (_entries) * sizeof (efx_desc_t));          \
 766         _NOTE(CONSTANTCONDITION)                                        \
 767         } while (B_FALSE)
 768
 769 extern  __checkReturn   efx_rc_t
 770 efx_nic_biu_test(
 771         __in            efx_nic_t *enp);
 772
 773 extern  __checkReturn   efx_rc_t
 774 efx_mac_select(
 775         __in            efx_nic_t *enp);
 776
 777 extern  void
 778 efx_mac_multicast_hash_compute(
 779         __in_ecount(6*count)            uint8_t const *addrs,
 780         __in                            int count,
 781         __out                           efx_oword_t *hash_low,
 782         __out                           efx_oword_t *hash_high);
 783
 784 extern  __checkReturn   efx_rc_t
 785 efx_phy_probe(
 786         __in            efx_nic_t *enp);
 787
 788 extern                  void
 789 efx_phy_unprobe(
 790         __in            efx_nic_t *enp);
 791
 792 #if EFSYS_OPT_MCDI
 793
 794 extern  __checkReturn           efx_rc_t
 795 efx_mcdi_set_workaround(
 796         __in                    efx_nic_t *enp,
 797         __in                    uint32_t type,
 798         __in                    boolean_t enabled,
 799         __out_opt               uint32_t *flagsp);
 800
 801 extern  __checkReturn           efx_rc_t
 802 efx_mcdi_get_workarounds(
 803         __in                    efx_nic_t *enp,
 804         __out_opt               uint32_t *implementedp,
 805         __out_opt               uint32_t *enabledp);
 806
 807 #endif /* EFSYS_OPT_MCDI */
 808
 809 #ifdef  __cplusplus
 810 }
 811 #endif
 812
 813 #endif  /* _SYS_EFX_IMPL_H */