drivers/net/sfc/base/efx_nic.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2007-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9
  10         __checkReturn   efx_rc_t
  11 efx_family(
  12         __in            uint16_t venid,
  13         __in            uint16_t devid,
  14         __out           efx_family_t *efp)
  15 {
  16         if (venid == EFX_PCI_VENID_SFC) {
  17                 switch (devid) {
  18 #if EFSYS_OPT_SIENA
  19                 case EFX_PCI_DEVID_SIENA_F1_UNINIT:
  20                         /*
  21                          * Hardware default for PF0 of uninitialised Siena.
  22                          * manftest must be able to cope with this device id.
  23                          */
  24                         *efp = EFX_FAMILY_SIENA;
  25                         return (0);
  26
  27                 case EFX_PCI_DEVID_BETHPAGE:
  28                 case EFX_PCI_DEVID_SIENA:
  29                         *efp = EFX_FAMILY_SIENA;
  30                         return (0);
  31 #endif /* EFSYS_OPT_SIENA */
  32
  33 #if EFSYS_OPT_HUNTINGTON
  34                 case EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT:
  35                         /*
  36                          * Hardware default for PF0 of uninitialised Huntington.
  37                          * manftest must be able to cope with this device id.
  38                          */
  39                         *efp = EFX_FAMILY_HUNTINGTON;
  40                         return (0);
  41
  42                 case EFX_PCI_DEVID_FARMINGDALE:
  43                 case EFX_PCI_DEVID_GREENPORT:
  44                         *efp = EFX_FAMILY_HUNTINGTON;
  45                         return (0);
  46
  47                 case EFX_PCI_DEVID_FARMINGDALE_VF:
  48                 case EFX_PCI_DEVID_GREENPORT_VF:
  49                         *efp = EFX_FAMILY_HUNTINGTON;
  50                         return (0);
  51 #endif /* EFSYS_OPT_HUNTINGTON */
  52
  53 #if EFSYS_OPT_MEDFORD
  54                 case EFX_PCI_DEVID_MEDFORD_PF_UNINIT:
  55                         /*
  56                          * Hardware default for PF0 of uninitialised Medford.
  57                          * manftest must be able to cope with this device id.
  58                          */
  59                         *efp = EFX_FAMILY_MEDFORD;
  60                         return (0);
  61
  62                 case EFX_PCI_DEVID_MEDFORD:
  63                         *efp = EFX_FAMILY_MEDFORD;
  64                         return (0);
  65
  66                 case EFX_PCI_DEVID_MEDFORD_VF:
  67                         *efp = EFX_FAMILY_MEDFORD;
  68                         return (0);
  69 #endif /* EFSYS_OPT_MEDFORD */
  70
  71 #if EFSYS_OPT_MEDFORD2
  72                 case EFX_PCI_DEVID_MEDFORD2_PF_UNINIT:
  73                         /*
  74                          * Hardware default for PF0 of uninitialised Medford2.
  75                          * manftest must be able to cope with this device id.
  76                          */
  77                         *efp = EFX_FAMILY_MEDFORD2;
  78                         return (0);
  79
  80                 case EFX_PCI_DEVID_MEDFORD2:
  81                         *efp = EFX_FAMILY_MEDFORD2;
  82                         return (0);
  83
  84                 case EFX_PCI_DEVID_MEDFORD2_VF:
  85                         *efp = EFX_FAMILY_MEDFORD2;
  86                         return (0);
  87 #endif /* EFSYS_OPT_MEDFORD2 */
  88
  89                 case EFX_PCI_DEVID_FALCON:      /* Obsolete, not supported */
  90                 default:
  91                         break;
  92                 }
  93         }
  94
  95         *efp = EFX_FAMILY_INVALID;
  96         return (ENOTSUP);
  97 }
  98
  99 #if EFSYS_OPT_SIENA
 100
 101 static const efx_nic_ops_t      __efx_nic_siena_ops = {
 102         siena_nic_probe,                /* eno_probe */
 103         NULL,                           /* eno_board_cfg */
 104         NULL,                           /* eno_set_drv_limits */
 105         siena_nic_reset,                /* eno_reset */
 106         siena_nic_init,                 /* eno_init */
 107         NULL,                           /* eno_get_vi_pool */
 108         NULL,                           /* eno_get_bar_region */
 109 #if EFSYS_OPT_DIAG
 110         siena_nic_register_test,        /* eno_register_test */
 111 #endif  /* EFSYS_OPT_DIAG */
 112         siena_nic_fini,                 /* eno_fini */
 113         siena_nic_unprobe,              /* eno_unprobe */
 114 };
 115
 116 #endif  /* EFSYS_OPT_SIENA */
 117
 118 #if EFSYS_OPT_HUNTINGTON
 119
 120 static const efx_nic_ops_t      __efx_nic_hunt_ops = {
 121         ef10_nic_probe,                 /* eno_probe */
 122         hunt_board_cfg,                 /* eno_board_cfg */
 123         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 124         ef10_nic_reset,                 /* eno_reset */
 125         ef10_nic_init,                  /* eno_init */
 126         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 127         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 128 #if EFSYS_OPT_DIAG
 129         ef10_nic_register_test,         /* eno_register_test */
 130 #endif  /* EFSYS_OPT_DIAG */
 131         ef10_nic_fini,                  /* eno_fini */
 132         ef10_nic_unprobe,               /* eno_unprobe */
 133 };
 134
 135 #endif  /* EFSYS_OPT_HUNTINGTON */
 136
 137 #if EFSYS_OPT_MEDFORD
 138
 139 static const efx_nic_ops_t      __efx_nic_medford_ops = {
 140         ef10_nic_probe,                 /* eno_probe */
 141         medford_board_cfg,              /* eno_board_cfg */
 142         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 143         ef10_nic_reset,                 /* eno_reset */
 144         ef10_nic_init,                  /* eno_init */
 145         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 146         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 147 #if EFSYS_OPT_DIAG
 148         ef10_nic_register_test,         /* eno_register_test */
 149 #endif  /* EFSYS_OPT_DIAG */
 150         ef10_nic_fini,                  /* eno_fini */
 151         ef10_nic_unprobe,               /* eno_unprobe */
 152 };
 153
 154 #endif  /* EFSYS_OPT_MEDFORD */
 155
 156 #if EFSYS_OPT_MEDFORD2
 157
 158 static const efx_nic_ops_t      __efx_nic_medford2_ops = {
 159         ef10_nic_probe,                 /* eno_probe */
 160         medford2_board_cfg,             /* eno_board_cfg */
 161         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 162         ef10_nic_reset,                 /* eno_reset */
 163         ef10_nic_init,                  /* eno_init */
 164         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 165         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 166 #if EFSYS_OPT_DIAG
 167         ef10_nic_register_test,         /* eno_register_test */
 168 #endif  /* EFSYS_OPT_DIAG */
 169         ef10_nic_fini,                  /* eno_fini */
 170         ef10_nic_unprobe,               /* eno_unprobe */
 171 };
 172
 173 #endif  /* EFSYS_OPT_MEDFORD2 */
 174
 175
 176         __checkReturn   efx_rc_t
 177 efx_nic_create(
 178         __in            efx_family_t family,
 179         __in            efsys_identifier_t *esip,
 180         __in            efsys_bar_t *esbp,
 181         __in            efsys_lock_t *eslp,
 182         __deref_out     efx_nic_t **enpp)
 183 {
 184         efx_nic_t *enp;
 185         efx_rc_t rc;
 186
 187         EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);
 188         EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);
 189
 190         /* Allocate a NIC object */
 191         EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);
 192
 193         if (enp == NULL) {
 194                 rc = ENOMEM;
 195                 goto fail1;
 196         }
 197
 198         enp->en_magic = EFX_NIC_MAGIC;
 199
 200         switch (family) {
 201 #if EFSYS_OPT_SIENA
 202         case EFX_FAMILY_SIENA:
 203                 enp->en_enop = &__efx_nic_siena_ops;
 204                 enp->en_features =
 205                     EFX_FEATURE_IPV6 |
 206                     EFX_FEATURE_LFSR_HASH_INSERT |
 207                     EFX_FEATURE_LINK_EVENTS |
 208                     EFX_FEATURE_PERIODIC_MAC_STATS |
 209                     EFX_FEATURE_MCDI |
 210                     EFX_FEATURE_LOOKAHEAD_SPLIT |
 211                     EFX_FEATURE_MAC_HEADER_FILTERS |
 212                     EFX_FEATURE_TX_SRC_FILTERS;
 213                 break;
 214 #endif  /* EFSYS_OPT_SIENA */
 215
 216 #if EFSYS_OPT_HUNTINGTON
 217         case EFX_FAMILY_HUNTINGTON:
 218                 enp->en_enop = &__efx_nic_hunt_ops;
 219                 enp->en_features =
 220                     EFX_FEATURE_IPV6 |
 221                     EFX_FEATURE_LINK_EVENTS |
 222                     EFX_FEATURE_PERIODIC_MAC_STATS |
 223                     EFX_FEATURE_MCDI |
 224                     EFX_FEATURE_MAC_HEADER_FILTERS |
 225                     EFX_FEATURE_MCDI_DMA |
 226                     EFX_FEATURE_PIO_BUFFERS |
 227                     EFX_FEATURE_FW_ASSISTED_TSO |
 228                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 229                     EFX_FEATURE_PACKED_STREAM;
 230                 break;
 231 #endif  /* EFSYS_OPT_HUNTINGTON */
 232
 233 #if EFSYS_OPT_MEDFORD
 234         case EFX_FAMILY_MEDFORD:
 235                 enp->en_enop = &__efx_nic_medford_ops;
 236                 /*
 237                  * FW_ASSISTED_TSO omitted as Medford only supports firmware
 238                  * assisted TSO version 2, not the v1 scheme used on Huntington.
 239                  */
 240                 enp->en_features =
 241                     EFX_FEATURE_IPV6 |
 242                     EFX_FEATURE_LINK_EVENTS |
 243                     EFX_FEATURE_PERIODIC_MAC_STATS |
 244                     EFX_FEATURE_MCDI |
 245                     EFX_FEATURE_MAC_HEADER_FILTERS |
 246                     EFX_FEATURE_MCDI_DMA |
 247                     EFX_FEATURE_PIO_BUFFERS |
 248                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 249                     EFX_FEATURE_PACKED_STREAM;
 250                 break;
 251 #endif  /* EFSYS_OPT_MEDFORD */
 252
 253 #if EFSYS_OPT_MEDFORD2
 254         case EFX_FAMILY_MEDFORD2:
 255                 enp->en_enop = &__efx_nic_medford2_ops;
 256                 enp->en_features =
 257                     EFX_FEATURE_IPV6 |
 258                     EFX_FEATURE_LINK_EVENTS |
 259                     EFX_FEATURE_PERIODIC_MAC_STATS |
 260                     EFX_FEATURE_MCDI |
 261                     EFX_FEATURE_MAC_HEADER_FILTERS |
 262                     EFX_FEATURE_MCDI_DMA |
 263                     EFX_FEATURE_PIO_BUFFERS |
 264                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 265                     EFX_FEATURE_PACKED_STREAM;
 266                 break;
 267 #endif  /* EFSYS_OPT_MEDFORD2 */
 268
 269         default:
 270                 rc = ENOTSUP;
 271                 goto fail2;
 272         }
 273
 274         enp->en_family = family;
 275         enp->en_esip = esip;
 276         enp->en_esbp = esbp;
 277         enp->en_eslp = eslp;
 278
 279         *enpp = enp;
 280
 281         return (0);
 282
 283 fail2:
 284         EFSYS_PROBE(fail2);
 285
 286         enp->en_magic = 0;
 287
 288         /* Free the NIC object */
 289         EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
 290
 291 fail1:
 292         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 293
 294         return (rc);
 295 }
 296
 297         __checkReturn   efx_rc_t
 298 efx_nic_probe(
 299         __in            efx_nic_t *enp)
 300 {
 301         const efx_nic_ops_t *enop;
 302         efx_rc_t rc;
 303
 304         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 305 #if EFSYS_OPT_MCDI
 306         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 307 #endif  /* EFSYS_OPT_MCDI */
 308         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
 309
 310         enop = enp->en_enop;
 311         if ((rc = enop->eno_probe(enp)) != 0)
 312                 goto fail1;
 313
 314         if ((rc = efx_phy_probe(enp)) != 0)
 315                 goto fail2;
 316
 317         enp->en_mod_flags |= EFX_MOD_PROBE;
 318
 319         return (0);
 320
 321 fail2:
 322         EFSYS_PROBE(fail2);
 323
 324         enop->eno_unprobe(enp);
 325
 326 fail1:
 327         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 328
 329         return (rc);
 330 }
 331
 332         __checkReturn   efx_rc_t
 333 efx_nic_set_drv_limits(
 334         __inout         efx_nic_t *enp,
 335         __in            efx_drv_limits_t *edlp)
 336 {
 337         const efx_nic_ops_t *enop = enp->en_enop;
 338         efx_rc_t rc;
 339
 340         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 341         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 342
 343         if (enop->eno_set_drv_limits != NULL) {
 344                 if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)
 345                         goto fail1;
 346         }
 347
 348         return (0);
 349
 350 fail1:
 351         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 352
 353         return (rc);
 354 }
 355
 356         __checkReturn   efx_rc_t
 357 efx_nic_get_bar_region(
 358         __in            efx_nic_t *enp,
 359         __in            efx_nic_region_t region,
 360         __out           uint32_t *offsetp,
 361         __out           size_t *sizep)
 362 {
 363         const efx_nic_ops_t *enop = enp->en_enop;
 364         efx_rc_t rc;
 365
 366         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 367         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 368         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 369
 370         if (enop->eno_get_bar_region == NULL) {
 371                 rc = ENOTSUP;
 372                 goto fail1;
 373         }
 374         if ((rc = (enop->eno_get_bar_region)(enp,
 375                     region, offsetp, sizep)) != 0) {
 376                 goto fail2;
 377         }
 378
 379         return (0);
 380
 381 fail2:
 382         EFSYS_PROBE(fail2);
 383
 384 fail1:
 385         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 386
 387         return (rc);
 388 }
 389
 390
 391         __checkReturn   efx_rc_t
 392 efx_nic_get_vi_pool(
 393         __in            efx_nic_t *enp,
 394         __out           uint32_t *evq_countp,
 395         __out           uint32_t *rxq_countp,
 396         __out           uint32_t *txq_countp)
 397 {
 398         const efx_nic_ops_t *enop = enp->en_enop;
 399         efx_nic_cfg_t *encp = &enp->en_nic_cfg;
 400         efx_rc_t rc;
 401
 402         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 403         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 404         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 405
 406         if (enop->eno_get_vi_pool != NULL) {
 407                 uint32_t vi_count = 0;
 408
 409                 if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)
 410                         goto fail1;
 411
 412                 *evq_countp = vi_count;
 413                 *rxq_countp = vi_count;
 414                 *txq_countp = vi_count;
 415         } else {
 416                 /* Use NIC limits as default value */
 417                 *evq_countp = encp->enc_evq_limit;
 418                 *rxq_countp = encp->enc_rxq_limit;
 419                 *txq_countp = encp->enc_txq_limit;
 420         }
 421
 422         return (0);
 423
 424 fail1:
 425         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 426
 427         return (rc);
 428 }
 429
 430
 431         __checkReturn   efx_rc_t
 432 efx_nic_init(
 433         __in            efx_nic_t *enp)
 434 {
 435         const efx_nic_ops_t *enop = enp->en_enop;
 436         efx_rc_t rc;
 437
 438         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 439         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 440
 441         if (enp->en_mod_flags & EFX_MOD_NIC) {
 442                 rc = EINVAL;
 443                 goto fail1;
 444         }
 445
 446         if ((rc = enop->eno_init(enp)) != 0)
 447                 goto fail2;
 448
 449         enp->en_mod_flags |= EFX_MOD_NIC;
 450
 451         return (0);
 452
 453 fail2:
 454         EFSYS_PROBE(fail2);
 455 fail1:
 456         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 457
 458         return (rc);
 459 }
 460
 461                         void
 462 efx_nic_fini(
 463         __in            efx_nic_t *enp)
 464 {
 465         const efx_nic_ops_t *enop = enp->en_enop;
 466
 467         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 468         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
 469         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);
 470         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
 471         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
 472         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 473         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 474
 475         enop->eno_fini(enp);
 476
 477         enp->en_mod_flags &= ~EFX_MOD_NIC;
 478 }
 479
 480                         void
 481 efx_nic_unprobe(
 482         __in            efx_nic_t *enp)
 483 {
 484         const efx_nic_ops_t *enop = enp->en_enop;
 485
 486         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 487 #if EFSYS_OPT_MCDI
 488         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 489 #endif  /* EFSYS_OPT_MCDI */
 490         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 491         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
 492         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
 493         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
 494         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 495         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 496
 497         efx_phy_unprobe(enp);
 498
 499         enop->eno_unprobe(enp);
 500
 501         enp->en_mod_flags &= ~EFX_MOD_PROBE;
 502 }
 503
 504                         void
 505 efx_nic_destroy(
 506         __in    efx_nic_t *enp)
 507 {
 508         efsys_identifier_t *esip = enp->en_esip;
 509
 510         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 511         EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
 512
 513         enp->en_family = EFX_FAMILY_INVALID;
 514         enp->en_esip = NULL;
 515         enp->en_esbp = NULL;
 516         enp->en_eslp = NULL;
 517
 518         enp->en_enop = NULL;
 519
 520         enp->en_magic = 0;
 521
 522         /* Free the NIC object */
 523         EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
 524 }
 525
 526         __checkReturn   efx_rc_t
 527 efx_nic_reset(
 528         __in            efx_nic_t *enp)
 529 {
 530         const efx_nic_ops_t *enop = enp->en_enop;
 531         unsigned int mod_flags;
 532         efx_rc_t rc;
 533
 534         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 535         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
 536         /*
 537          * All modules except the MCDI, PROBE, NVRAM, VPD, MON
 538          * (which we do not reset here) must have been shut down or never
 539          * initialized.
 540          *
 541          * A rule of thumb here is: If the controller or MC reboots, is *any*
 542          * state lost. If it's lost and needs reapplying, then the module
 543          * *must* not be initialised during the reset.
 544          */
 545         mod_flags = enp->en_mod_flags;
 546         mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |
 547                     EFX_MOD_VPD | EFX_MOD_MON);
 548         EFSYS_ASSERT3U(mod_flags, ==, 0);
 549         if (mod_flags != 0) {
 550                 rc = EINVAL;
 551                 goto fail1;
 552         }
 553
 554         if ((rc = enop->eno_reset(enp)) != 0)
 555                 goto fail2;
 556
 557         return (0);
 558
 559 fail2:
 560         EFSYS_PROBE(fail2);
 561 fail1:
 562         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 563
 564         return (rc);
 565 }
 566
 567                         const efx_nic_cfg_t *
 568 efx_nic_cfg_get(
 569         __in            efx_nic_t *enp)
 570 {
 571         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 572
 573         return (&(enp->en_nic_cfg));
 574 }
 575
 576         __checkReturn           efx_rc_t
 577 efx_nic_get_fw_version(
 578         __in                    efx_nic_t *enp,
 579         __out                   efx_nic_fw_info_t *enfip)
 580 {
 581         uint16_t mc_fw_version[4];
 582         efx_rc_t rc;
 583
 584         if (enfip == NULL) {
 585                 rc = EINVAL;
 586                 goto fail1;
 587         }
 588
 589         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 590         EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
 591
 592         rc = efx_mcdi_version(enp, mc_fw_version, NULL, NULL);
 593         if (rc != 0)
 594                 goto fail2;
 595
 596         rc = efx_mcdi_get_capabilities(enp, NULL,
 597             &enfip->enfi_rx_dpcpu_fw_id,
 598             &enfip->enfi_tx_dpcpu_fw_id,
 599             NULL, NULL);
 600         if (rc == 0) {
 601                 enfip->enfi_dpcpu_fw_ids_valid = B_TRUE;
 602         } else if (rc == ENOTSUP) {
 603                 enfip->enfi_dpcpu_fw_ids_valid = B_FALSE;
 604                 enfip->enfi_rx_dpcpu_fw_id = 0;
 605                 enfip->enfi_tx_dpcpu_fw_id = 0;
 606         } else {
 607                 goto fail3;
 608         }
 609
 610         memcpy(enfip->enfi_mc_fw_version, mc_fw_version,
 611             sizeof (mc_fw_version));
 612
 613         return (0);
 614
 615 fail3:
 616         EFSYS_PROBE(fail3);
 617 fail2:
 618         EFSYS_PROBE(fail2);
 619 fail1:
 620         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 621
 622         return (rc);
 623 }
 624
 625 #if EFSYS_OPT_DIAG
 626
 627         __checkReturn   efx_rc_t
 628 efx_nic_register_test(
 629         __in            efx_nic_t *enp)
 630 {
 631         const efx_nic_ops_t *enop = enp->en_enop;
 632         efx_rc_t rc;
 633
 634         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 635         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 636         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
 637
 638         if ((rc = enop->eno_register_test(enp)) != 0)
 639                 goto fail1;
 640
 641         return (0);
 642
 643 fail1:
 644         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 645
 646         return (rc);
 647 }
 648
 649 #endif  /* EFSYS_OPT_DIAG */
 650
 651 #if EFSYS_OPT_LOOPBACK
 652
 653 extern                  void
 654 efx_loopback_mask(
 655         __in    efx_loopback_kind_t loopback_kind,
 656         __out   efx_qword_t *maskp)
 657 {
 658         efx_qword_t mask;
 659
 660         EFSYS_ASSERT3U(loopback_kind, <, EFX_LOOPBACK_NKINDS);
 661         EFSYS_ASSERT(maskp != NULL);
 662
 663         /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespace agree */
 664         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_NONE == EFX_LOOPBACK_OFF);
 665         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_DATA == EFX_LOOPBACK_DATA);
 666         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMAC == EFX_LOOPBACK_GMAC);
 667         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII == EFX_LOOPBACK_XGMII);
 668         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGXS == EFX_LOOPBACK_XGXS);
 669         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI == EFX_LOOPBACK_XAUI);
 670         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII == EFX_LOOPBACK_GMII);
 671         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII == EFX_LOOPBACK_SGMII);
 672         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGBR == EFX_LOOPBACK_XGBR);
 673         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI == EFX_LOOPBACK_XFI);
 674         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_FAR == EFX_LOOPBACK_XAUI_FAR);
 675         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII_FAR == EFX_LOOPBACK_GMII_FAR);
 676         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII_FAR == EFX_LOOPBACK_SGMII_FAR);
 677         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_FAR == EFX_LOOPBACK_XFI_FAR);
 678         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GPHY == EFX_LOOPBACK_GPHY);
 679         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PHYXS == EFX_LOOPBACK_PHY_XS);
 680         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PCS == EFX_LOOPBACK_PCS);
 681         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMAPMD == EFX_LOOPBACK_PMA_PMD);
 682         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XPORT == EFX_LOOPBACK_XPORT);
 683         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII_WS == EFX_LOOPBACK_XGMII_WS);
 684         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_WS == EFX_LOOPBACK_XAUI_WS);
 685         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_WS_FAR ==
 686             EFX_LOOPBACK_XAUI_WS_FAR);
 687         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_WS_NEAR ==
 688             EFX_LOOPBACK_XAUI_WS_NEAR);
 689         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII_WS == EFX_LOOPBACK_GMII_WS);
 690         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_WS == EFX_LOOPBACK_XFI_WS);
 691         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_WS_FAR ==
 692             EFX_LOOPBACK_XFI_WS_FAR);
 693         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PHYXS_WS == EFX_LOOPBACK_PHYXS_WS);
 694         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMA_INT == EFX_LOOPBACK_PMA_INT);
 695         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_NEAR == EFX_LOOPBACK_SD_NEAR);
 696         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FAR == EFX_LOOPBACK_SD_FAR);
 697         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMA_INT_WS ==
 698             EFX_LOOPBACK_PMA_INT_WS);
 699         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FEP2_WS ==
 700             EFX_LOOPBACK_SD_FEP2_WS);
 701         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FEP1_5_WS ==
 702             EFX_LOOPBACK_SD_FEP1_5_WS);
 703         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FEP_WS == EFX_LOOPBACK_SD_FEP_WS);
 704         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FES_WS == EFX_LOOPBACK_SD_FES_WS);
 705
 706         /* Build bitmask of possible loopback types */
 707         EFX_ZERO_QWORD(mask);
 708
 709         if ((loopback_kind == EFX_LOOPBACK_KIND_OFF) ||
 710             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 711                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_OFF);
 712         }
 713
 714         if ((loopback_kind == EFX_LOOPBACK_KIND_MAC) ||
 715             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 716                 /*
 717                  * The "MAC" grouping has historically been used by drivers to
 718                  * mean loopbacks supported by on-chip hardware. Keep that
 719                  * meaning here, and include on-chip PHY layer loopbacks.
 720                  */
 721                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_DATA);
 722                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMAC);
 723                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGMII);
 724                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGXS);
 725                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI);
 726                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII);
 727                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII);
 728                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGBR);
 729                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI);
 730                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI_FAR);
 731                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII_FAR);
 732                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII_FAR);
 733                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI_FAR);
 734                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_INT);
 735                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_NEAR);
 736                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_FAR);
 737         }
 738
 739         if ((loopback_kind == EFX_LOOPBACK_KIND_PHY) ||
 740             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 741                 /*
 742                  * The "PHY" grouping has historically been used by drivers to
 743                  * mean loopbacks supported by off-chip hardware. Keep that
 744                  * meaning here.
 745                  */
 746                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GPHY);
 747                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PHY_XS);
 748                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PCS);
 749                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_PMD);
 750         }
 751
 752         *maskp = mask;
 753 }
 754
 755         __checkReturn   efx_rc_t
 756 efx_mcdi_get_loopback_modes(
 757         __in            efx_nic_t *enp)
 758 {
 759         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 760         efx_mcdi_req_t req;
 761         uint8_t payload[MAX(MC_CMD_GET_LOOPBACK_MODES_IN_LEN,
 762                             MC_CMD_GET_LOOPBACK_MODES_OUT_LEN)];
 763         efx_qword_t mask;
 764         efx_qword_t modes;
 765         efx_rc_t rc;
 766
 767         (void) memset(payload, 0, sizeof (payload));
 768         req.emr_cmd = MC_CMD_GET_LOOPBACK_MODES;
 769         req.emr_in_buf = payload;
 770         req.emr_in_length = MC_CMD_GET_LOOPBACK_MODES_IN_LEN;
 771         req.emr_out_buf = payload;
 772         req.emr_out_length = MC_CMD_GET_LOOPBACK_MODES_OUT_LEN;
 773
 774         efx_mcdi_execute(enp, &req);
 775
 776         if (req.emr_rc != 0) {
 777                 rc = req.emr_rc;
 778                 goto fail1;
 779         }
 780
 781         if (req.emr_out_length_used <
 782             MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST +
 783             MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN) {
 784                 rc = EMSGSIZE;
 785                 goto fail2;
 786         }
 787
 788         /*
 789          * We assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree
 790          * in efx_loopback_mask() and in siena_phy.c:siena_phy_get_link().
 791          */
 792         efx_loopback_mask(EFX_LOOPBACK_KIND_ALL, &mask);
 793
 794         EFX_AND_QWORD(mask,
 795             *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_SUGGESTED));
 796
 797         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_100M);
 798         EFX_AND_QWORD(modes, mask);
 799         encp->enc_loopback_types[EFX_LINK_100FDX] = modes;
 800
 801         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_1G);
 802         EFX_AND_QWORD(modes, mask);
 803         encp->enc_loopback_types[EFX_LINK_1000FDX] = modes;
 804
 805         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_10G);
 806         EFX_AND_QWORD(modes, mask);
 807         encp->enc_loopback_types[EFX_LINK_10000FDX] = modes;
 808
 809         if (req.emr_out_length_used >=
 810             MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST +
 811             MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN) {
 812                 /* Response includes 40G loopback modes */
 813                 modes =
 814                     *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_40G);
 815                 EFX_AND_QWORD(modes, mask);
 816                 encp->enc_loopback_types[EFX_LINK_40000FDX] = modes;
 817         }
 818
 819         EFX_ZERO_QWORD(modes);
 820         EFX_SET_QWORD_BIT(modes, EFX_LOOPBACK_OFF);
 821         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100FDX]);
 822         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_1000FDX]);
 823         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_10000FDX]);
 824         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_40000FDX]);
 825         encp->enc_loopback_types[EFX_LINK_UNKNOWN] = modes;
 826
 827         return (0);
 828
 829 fail2:
 830         EFSYS_PROBE(fail2);
 831 fail1:
 832         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 833
 834         return (rc);
 835 }
 836
 837 #endif /* EFSYS_OPT_LOOPBACK */
 838
 839         __checkReturn   efx_rc_t
 840 efx_nic_calculate_pcie_link_bandwidth(
 841         __in            uint32_t pcie_link_width,
 842         __in            uint32_t pcie_link_gen,
 843         __out           uint32_t *bandwidth_mbpsp)
 844 {
 845         uint32_t lane_bandwidth;
 846         uint32_t total_bandwidth;
 847         efx_rc_t rc;
 848
 849         if ((pcie_link_width == 0) || (pcie_link_width > 16) ||
 850             !ISP2(pcie_link_width)) {
 851                 rc = EINVAL;
 852                 goto fail1;
 853         }
 854
 855         switch (pcie_link_gen) {
 856         case EFX_PCIE_LINK_SPEED_GEN1:
 857                 /* 2.5 Gb/s raw bandwidth with 8b/10b encoding */
 858                 lane_bandwidth = 2000;
 859                 break;
 860         case EFX_PCIE_LINK_SPEED_GEN2:
 861                 /* 5.0 Gb/s raw bandwidth with 8b/10b encoding */
 862                 lane_bandwidth = 4000;
 863                 break;
 864         case EFX_PCIE_LINK_SPEED_GEN3:
 865                 /* 8.0 Gb/s raw bandwidth with 128b/130b encoding */
 866                 lane_bandwidth = 7877;
 867                 break;
 868         default:
 869                 rc = EINVAL;
 870                 goto fail2;
 871         }
 872
 873         total_bandwidth = lane_bandwidth * pcie_link_width;
 874         *bandwidth_mbpsp = total_bandwidth;
 875
 876         return (0);
 877
 878 fail2:
 879         EFSYS_PROBE(fail2);
 880 fail1:
 881         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 882
 883         return (rc);
 884 }
 885
 886
 887         __checkReturn   efx_rc_t
 888 efx_nic_check_pcie_link_speed(
 889         __in            efx_nic_t *enp,
 890         __in            uint32_t pcie_link_width,
 891         __in            uint32_t pcie_link_gen,
 892         __out           efx_pcie_link_performance_t *resultp)
 893 {
 894         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 895         uint32_t bandwidth;
 896         efx_pcie_link_performance_t result;
 897         efx_rc_t rc;
 898
 899         if ((encp->enc_required_pcie_bandwidth_mbps == 0) ||
 900             (pcie_link_width == 0) || (pcie_link_width == 32) ||
 901             (pcie_link_gen == 0)) {
 902                 /*
 903                  * No usable info on what is required and/or in use. In virtual
 904                  * machines, sometimes the PCIe link width is reported as 0 or
 905                  * 32, or the speed as 0.
 906                  */
 907                 result = EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH;
 908                 goto out;
 909         }
 910
 911         /* Calculate the available bandwidth in megabits per second */
 912         rc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width,
 913                                             pcie_link_gen, &bandwidth);
 914         if (rc != 0)
 915                 goto fail1;
 916
 917         if (bandwidth < encp->enc_required_pcie_bandwidth_mbps) {
 918                 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH;
 919         } else if (pcie_link_gen < encp->enc_max_pcie_link_gen) {
 920                 /* The link provides enough bandwidth but not optimal latency */
 921                 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY;
 922         } else {
 923                 result = EFX_PCIE_LINK_PERFORMANCE_OPTIMAL;
 924         }
 925
 926 out:
 927         *resultp = result;
 928
 929         return (0);
 930
 931 fail1:
 932         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 933
 934         return (rc);
 935 }