drivers/net/sfc/base/efx_rx.c

   1 /*
   2  * Copyright (c) 2007-2016 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  */
  30
  31 #include "efx.h"
  32 #include "efx_impl.h"
  33
  34
  35 #if EFSYS_OPT_SIENA
  36
  37 static  __checkReturn   efx_rc_t
  38 siena_rx_init(
  39         __in            efx_nic_t *enp);
  40
  41 static                  void
  42 siena_rx_fini(
  43         __in            efx_nic_t *enp);
  44
  45 #if EFSYS_OPT_RX_SCATTER
  46 static  __checkReturn   efx_rc_t
  47 siena_rx_scatter_enable(
  48         __in            efx_nic_t *enp,
  49         __in            unsigned int buf_size);
  50 #endif /* EFSYS_OPT_RX_SCATTER */
  51
  52 #if EFSYS_OPT_RX_SCALE
  53 static  __checkReturn   efx_rc_t
  54 siena_rx_scale_mode_set(
  55         __in            efx_nic_t *enp,
  56         __in            efx_rx_hash_alg_t alg,
  57         __in            efx_rx_hash_type_t type,
  58         __in            boolean_t insert);
  59
  60 static  __checkReturn   efx_rc_t
  61 siena_rx_scale_key_set(
  62         __in            efx_nic_t *enp,
  63         __in_ecount(n)  uint8_t *key,
  64         __in            size_t n);
  65
  66 static  __checkReturn   efx_rc_t
  67 siena_rx_scale_tbl_set(
  68         __in            efx_nic_t *enp,
  69         __in_ecount(n)  unsigned int *table,
  70         __in            size_t n);
  71
  72 static  __checkReturn   uint32_t
  73 siena_rx_prefix_hash(
  74         __in            efx_nic_t *enp,
  75         __in            efx_rx_hash_alg_t func,
  76         __in            uint8_t *buffer);
  77
  78 #endif /* EFSYS_OPT_RX_SCALE */
  79
  80 static  __checkReturn   efx_rc_t
  81 siena_rx_prefix_pktlen(
  82         __in            efx_nic_t *enp,
  83         __in            uint8_t *buffer,
  84         __out           uint16_t *lengthp);
  85
  86 static                  void
  87 siena_rx_qpost(
  88         __in            efx_rxq_t *erp,
  89         __in_ecount(n)  efsys_dma_addr_t *addrp,
  90         __in            size_t size,
  91         __in            unsigned int n,
  92         __in            unsigned int completed,
  93         __in            unsigned int added);
  94
  95 static                  void
  96 siena_rx_qpush(
  97         __in            efx_rxq_t *erp,
  98         __in            unsigned int added,
  99         __inout         unsigned int *pushedp);
 100
 101 static  __checkReturn   efx_rc_t
 102 siena_rx_qflush(
 103         __in            efx_rxq_t *erp);
 104
 105 static                  void
 106 siena_rx_qenable(
 107         __in            efx_rxq_t *erp);
 108
 109 static  __checkReturn   efx_rc_t
 110 siena_rx_qcreate(
 111         __in            efx_nic_t *enp,
 112         __in            unsigned int index,
 113         __in            unsigned int label,
 114         __in            efx_rxq_type_t type,
 115         __in            efsys_mem_t *esmp,
 116         __in            size_t n,
 117         __in            uint32_t id,
 118         __in            efx_evq_t *eep,
 119         __in            efx_rxq_t *erp);
 120
 121 static                  void
 122 siena_rx_qdestroy(
 123         __in            efx_rxq_t *erp);
 124
 125 #endif /* EFSYS_OPT_SIENA */
 126
 127
 128 #if EFSYS_OPT_SIENA
 129 static const efx_rx_ops_t __efx_rx_siena_ops = {
 130         siena_rx_init,                          /* erxo_init */
 131         siena_rx_fini,                          /* erxo_fini */
 132 #if EFSYS_OPT_RX_SCATTER
 133         siena_rx_scatter_enable,                /* erxo_scatter_enable */
 134 #endif
 135 #if EFSYS_OPT_RX_SCALE
 136         siena_rx_scale_mode_set,                /* erxo_scale_mode_set */
 137         siena_rx_scale_key_set,                 /* erxo_scale_key_set */
 138         siena_rx_scale_tbl_set,                 /* erxo_scale_tbl_set */
 139         siena_rx_prefix_hash,                   /* erxo_prefix_hash */
 140 #endif
 141         siena_rx_prefix_pktlen,                 /* erxo_prefix_pktlen */
 142         siena_rx_qpost,                         /* erxo_qpost */
 143         siena_rx_qpush,                         /* erxo_qpush */
 144         siena_rx_qflush,                        /* erxo_qflush */
 145         siena_rx_qenable,                       /* erxo_qenable */
 146         siena_rx_qcreate,                       /* erxo_qcreate */
 147         siena_rx_qdestroy,                      /* erxo_qdestroy */
 148 };
 149 #endif  /* EFSYS_OPT_SIENA */
 150
 151 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 152 static const efx_rx_ops_t __efx_rx_ef10_ops = {
 153         ef10_rx_init,                           /* erxo_init */
 154         ef10_rx_fini,                           /* erxo_fini */
 155 #if EFSYS_OPT_RX_SCATTER
 156         ef10_rx_scatter_enable,                 /* erxo_scatter_enable */
 157 #endif
 158 #if EFSYS_OPT_RX_SCALE
 159         ef10_rx_scale_mode_set,                 /* erxo_scale_mode_set */
 160         ef10_rx_scale_key_set,                  /* erxo_scale_key_set */
 161         ef10_rx_scale_tbl_set,                  /* erxo_scale_tbl_set */
 162         ef10_rx_prefix_hash,                    /* erxo_prefix_hash */
 163 #endif
 164         ef10_rx_prefix_pktlen,                  /* erxo_prefix_pktlen */
 165         ef10_rx_qpost,                          /* erxo_qpost */
 166         ef10_rx_qpush,                          /* erxo_qpush */
 167         ef10_rx_qflush,                         /* erxo_qflush */
 168         ef10_rx_qenable,                        /* erxo_qenable */
 169         ef10_rx_qcreate,                        /* erxo_qcreate */
 170         ef10_rx_qdestroy,                       /* erxo_qdestroy */
 171 };
 172 #endif  /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 173
 174
 175         __checkReturn   efx_rc_t
 176 efx_rx_init(
 177         __inout         efx_nic_t *enp)
 178 {
 179         const efx_rx_ops_t *erxop;
 180         efx_rc_t rc;
 181
 182         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 183         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 184
 185         if (!(enp->en_mod_flags & EFX_MOD_EV)) {
 186                 rc = EINVAL;
 187                 goto fail1;
 188         }
 189
 190         if (enp->en_mod_flags & EFX_MOD_RX) {
 191                 rc = EINVAL;
 192                 goto fail2;
 193         }
 194
 195         switch (enp->en_family) {
 196 #if EFSYS_OPT_SIENA
 197         case EFX_FAMILY_SIENA:
 198                 erxop = &__efx_rx_siena_ops;
 199                 break;
 200 #endif /* EFSYS_OPT_SIENA */
 201
 202 #if EFSYS_OPT_HUNTINGTON
 203         case EFX_FAMILY_HUNTINGTON:
 204                 erxop = &__efx_rx_ef10_ops;
 205                 break;
 206 #endif /* EFSYS_OPT_HUNTINGTON */
 207
 208 #if EFSYS_OPT_MEDFORD
 209         case EFX_FAMILY_MEDFORD:
 210                 erxop = &__efx_rx_ef10_ops;
 211                 break;
 212 #endif /* EFSYS_OPT_MEDFORD */
 213
 214         default:
 215                 EFSYS_ASSERT(0);
 216                 rc = ENOTSUP;
 217                 goto fail3;
 218         }
 219
 220         if ((rc = erxop->erxo_init(enp)) != 0)
 221                 goto fail4;
 222
 223         enp->en_erxop = erxop;
 224         enp->en_mod_flags |= EFX_MOD_RX;
 225         return (0);
 226
 227 fail4:
 228         EFSYS_PROBE(fail4);
 229 fail3:
 230         EFSYS_PROBE(fail3);
 231 fail2:
 232         EFSYS_PROBE(fail2);
 233 fail1:
 234         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 235
 236         enp->en_erxop = NULL;
 237         enp->en_mod_flags &= ~EFX_MOD_RX;
 238         return (rc);
 239 }
 240
 241                         void
 242 efx_rx_fini(
 243         __in            efx_nic_t *enp)
 244 {
 245         const efx_rx_ops_t *erxop = enp->en_erxop;
 246
 247         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 248         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 249         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 250         EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0);
 251
 252         erxop->erxo_fini(enp);
 253
 254         enp->en_erxop = NULL;
 255         enp->en_mod_flags &= ~EFX_MOD_RX;
 256 }
 257
 258 #if EFSYS_OPT_RX_SCATTER
 259         __checkReturn   efx_rc_t
 260 efx_rx_scatter_enable(
 261         __in            efx_nic_t *enp,
 262         __in            unsigned int buf_size)
 263 {
 264         const efx_rx_ops_t *erxop = enp->en_erxop;
 265         efx_rc_t rc;
 266
 267         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 268         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 269
 270         if ((rc = erxop->erxo_scatter_enable(enp, buf_size)) != 0)
 271                 goto fail1;
 272
 273         return (0);
 274
 275 fail1:
 276         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 277         return (rc);
 278 }
 279 #endif  /* EFSYS_OPT_RX_SCATTER */
 280
 281 #if EFSYS_OPT_RX_SCALE
 282         __checkReturn   efx_rc_t
 283 efx_rx_hash_support_get(
 284         __in            efx_nic_t *enp,
 285         __out           efx_rx_hash_support_t *supportp)
 286 {
 287         efx_rc_t rc;
 288
 289         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 290         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 291
 292         if (supportp == NULL) {
 293                 rc = EINVAL;
 294                 goto fail1;
 295         }
 296
 297         /* Report if resources are available to insert RX hash value */
 298         *supportp = enp->en_hash_support;
 299
 300         return (0);
 301
 302 fail1:
 303         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 304
 305         return (rc);
 306 }
 307
 308         __checkReturn   efx_rc_t
 309 efx_rx_scale_support_get(
 310         __in            efx_nic_t *enp,
 311         __out           efx_rx_scale_support_t *supportp)
 312 {
 313         efx_rc_t rc;
 314
 315         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 316         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 317
 318         if (supportp == NULL) {
 319                 rc = EINVAL;
 320                 goto fail1;
 321         }
 322
 323         /* Report if resources are available to support RSS */
 324         *supportp = enp->en_rss_support;
 325
 326         return (0);
 327
 328 fail1:
 329         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 330
 331         return (rc);
 332 }
 333
 334         __checkReturn   efx_rc_t
 335 efx_rx_scale_mode_set(
 336         __in            efx_nic_t *enp,
 337         __in            efx_rx_hash_alg_t alg,
 338         __in            efx_rx_hash_type_t type,
 339         __in            boolean_t insert)
 340 {
 341         const efx_rx_ops_t *erxop = enp->en_erxop;
 342         efx_rc_t rc;
 343
 344         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 345         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 346
 347         if (erxop->erxo_scale_mode_set != NULL) {
 348                 if ((rc = erxop->erxo_scale_mode_set(enp, alg,
 349                             type, insert)) != 0)
 350                         goto fail1;
 351         }
 352
 353         return (0);
 354
 355 fail1:
 356         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 357         return (rc);
 358 }
 359 #endif  /* EFSYS_OPT_RX_SCALE */
 360
 361 #if EFSYS_OPT_RX_SCALE
 362         __checkReturn   efx_rc_t
 363 efx_rx_scale_key_set(
 364         __in            efx_nic_t *enp,
 365         __in_ecount(n)  uint8_t *key,
 366         __in            size_t n)
 367 {
 368         const efx_rx_ops_t *erxop = enp->en_erxop;
 369         efx_rc_t rc;
 370
 371         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 372         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 373
 374         if ((rc = erxop->erxo_scale_key_set(enp, key, n)) != 0)
 375                 goto fail1;
 376
 377         return (0);
 378
 379 fail1:
 380         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 381
 382         return (rc);
 383 }
 384 #endif  /* EFSYS_OPT_RX_SCALE */
 385
 386 #if EFSYS_OPT_RX_SCALE
 387         __checkReturn   efx_rc_t
 388 efx_rx_scale_tbl_set(
 389         __in            efx_nic_t *enp,
 390         __in_ecount(n)  unsigned int *table,
 391         __in            size_t n)
 392 {
 393         const efx_rx_ops_t *erxop = enp->en_erxop;
 394         efx_rc_t rc;
 395
 396         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 397         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 398
 399         if ((rc = erxop->erxo_scale_tbl_set(enp, table, n)) != 0)
 400                 goto fail1;
 401
 402         return (0);
 403
 404 fail1:
 405         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 406
 407         return (rc);
 408 }
 409 #endif  /* EFSYS_OPT_RX_SCALE */
 410
 411                         void
 412 efx_rx_qpost(
 413         __in            efx_rxq_t *erp,
 414         __in_ecount(n)  efsys_dma_addr_t *addrp,
 415         __in            size_t size,
 416         __in            unsigned int n,
 417         __in            unsigned int completed,
 418         __in            unsigned int added)
 419 {
 420         efx_nic_t *enp = erp->er_enp;
 421         const efx_rx_ops_t *erxop = enp->en_erxop;
 422
 423         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 424
 425         erxop->erxo_qpost(erp, addrp, size, n, completed, added);
 426 }
 427
 428                         void
 429 efx_rx_qpush(
 430         __in            efx_rxq_t *erp,
 431         __in            unsigned int added,
 432         __inout         unsigned int *pushedp)
 433 {
 434         efx_nic_t *enp = erp->er_enp;
 435         const efx_rx_ops_t *erxop = enp->en_erxop;
 436
 437         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 438
 439         erxop->erxo_qpush(erp, added, pushedp);
 440 }
 441
 442         __checkReturn   efx_rc_t
 443 efx_rx_qflush(
 444         __in            efx_rxq_t *erp)
 445 {
 446         efx_nic_t *enp = erp->er_enp;
 447         const efx_rx_ops_t *erxop = enp->en_erxop;
 448         efx_rc_t rc;
 449
 450         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 451
 452         if ((rc = erxop->erxo_qflush(erp)) != 0)
 453                 goto fail1;
 454
 455         return (0);
 456
 457 fail1:
 458         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 459
 460         return (rc);
 461 }
 462
 463                         void
 464 efx_rx_qenable(
 465         __in            efx_rxq_t *erp)
 466 {
 467         efx_nic_t *enp = erp->er_enp;
 468         const efx_rx_ops_t *erxop = enp->en_erxop;
 469
 470         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 471
 472         erxop->erxo_qenable(erp);
 473 }
 474
 475         __checkReturn   efx_rc_t
 476 efx_rx_qcreate(
 477         __in            efx_nic_t *enp,
 478         __in            unsigned int index,
 479         __in            unsigned int label,
 480         __in            efx_rxq_type_t type,
 481         __in            efsys_mem_t *esmp,
 482         __in            size_t n,
 483         __in            uint32_t id,
 484         __in            efx_evq_t *eep,
 485         __deref_out     efx_rxq_t **erpp)
 486 {
 487         const efx_rx_ops_t *erxop = enp->en_erxop;
 488         efx_rxq_t *erp;
 489         efx_rc_t rc;
 490
 491         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 492         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 493
 494         /* Allocate an RXQ object */
 495         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp);
 496
 497         if (erp == NULL) {
 498                 rc = ENOMEM;
 499                 goto fail1;
 500         }
 501
 502         erp->er_magic = EFX_RXQ_MAGIC;
 503         erp->er_enp = enp;
 504         erp->er_index = index;
 505         erp->er_mask = n - 1;
 506         erp->er_esmp = esmp;
 507
 508         if ((rc = erxop->erxo_qcreate(enp, index, label, type, esmp, n, id,
 509             eep, erp)) != 0)
 510                 goto fail2;
 511
 512         enp->en_rx_qcount++;
 513         *erpp = erp;
 514
 515         return (0);
 516
 517 fail2:
 518         EFSYS_PROBE(fail2);
 519
 520         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
 521 fail1:
 522         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 523
 524         return (rc);
 525 }
 526
 527                         void
 528 efx_rx_qdestroy(
 529         __in            efx_rxq_t *erp)
 530 {
 531         efx_nic_t *enp = erp->er_enp;
 532         const efx_rx_ops_t *erxop = enp->en_erxop;
 533
 534         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 535
 536         erxop->erxo_qdestroy(erp);
 537 }
 538
 539         __checkReturn   efx_rc_t
 540 efx_pseudo_hdr_pkt_length_get(
 541         __in            efx_rxq_t *erp,
 542         __in            uint8_t *buffer,
 543         __out           uint16_t *lengthp)
 544 {
 545         efx_nic_t *enp = erp->er_enp;
 546         const efx_rx_ops_t *erxop = enp->en_erxop;
 547
 548         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 549
 550         return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp));
 551 }
 552
 553 #if EFSYS_OPT_RX_SCALE
 554         __checkReturn   uint32_t
 555 efx_pseudo_hdr_hash_get(
 556         __in            efx_rxq_t *erp,
 557         __in            efx_rx_hash_alg_t func,
 558         __in            uint8_t *buffer)
 559 {
 560         efx_nic_t *enp = erp->er_enp;
 561         const efx_rx_ops_t *erxop = enp->en_erxop;
 562
 563         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 564
 565         EFSYS_ASSERT3U(enp->en_hash_support, ==, EFX_RX_HASH_AVAILABLE);
 566         return (erxop->erxo_prefix_hash(enp, func, buffer));
 567 }
 568 #endif  /* EFSYS_OPT_RX_SCALE */
 569
 570 #if EFSYS_OPT_SIENA
 571
 572 static  __checkReturn   efx_rc_t
 573 siena_rx_init(
 574         __in            efx_nic_t *enp)
 575 {
 576         efx_oword_t oword;
 577         unsigned int index;
 578
 579         EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
 580
 581         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0);
 582         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);
 583         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);
 584         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);
 585         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0);
 586         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32);
 587         EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
 588
 589         /* Zero the RSS table */
 590         for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS;
 591             index++) {
 592                 EFX_ZERO_OWORD(oword);
 593                 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
 594                                     index, &oword, B_TRUE);
 595         }
 596
 597 #if EFSYS_OPT_RX_SCALE
 598         /* The RSS key and indirection table are writable. */
 599         enp->en_rss_support = EFX_RX_SCALE_EXCLUSIVE;
 600
 601         /* Hardware can insert RX hash with/without RSS */
 602         enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
 603 #endif  /* EFSYS_OPT_RX_SCALE */
 604
 605         return (0);
 606 }
 607
 608 #if EFSYS_OPT_RX_SCATTER
 609 static  __checkReturn   efx_rc_t
 610 siena_rx_scatter_enable(
 611         __in            efx_nic_t *enp,
 612         __in            unsigned int buf_size)
 613 {
 614         unsigned int nbuf32;
 615         efx_oword_t oword;
 616         efx_rc_t rc;
 617
 618         nbuf32 = buf_size / 32;
 619         if ((nbuf32 == 0) ||
 620             (nbuf32 >= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH)) ||
 621             ((buf_size % 32) != 0)) {
 622                 rc = EINVAL;
 623                 goto fail1;
 624         }
 625
 626         if (enp->en_rx_qcount > 0) {
 627                 rc = EBUSY;
 628                 goto fail2;
 629         }
 630
 631         /* Set scatter buffer size */
 632         EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
 633         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, nbuf32);
 634         EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
 635
 636         /* Enable scatter for packets not matching a filter */
 637         EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
 638         EFX_SET_OWORD_FIELD(oword, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, 1);
 639         EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
 640
 641         return (0);
 642
 643 fail2:
 644         EFSYS_PROBE(fail2);
 645 fail1:
 646         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 647
 648         return (rc);
 649 }
 650 #endif  /* EFSYS_OPT_RX_SCATTER */
 651
 652
 653 #define EFX_RX_LFSR_HASH(_enp, _insert)                                 \
 654         do {                                                            \
 655                 efx_oword_t oword;                                      \
 656                                                                         \
 657                 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword);        \
 658                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);      \
 659                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);       \
 660                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);       \
 661                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR,    \
 662                     (_insert) ? 1 : 0);                                 \
 663                 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword);       \
 664                                                                         \
 665                 if ((_enp)->en_family == EFX_FAMILY_SIENA) {            \
 666                         EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3,   \
 667                             &oword);                                    \
 668                         EFX_SET_OWORD_FIELD(oword,                      \
 669                             FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0);        \
 670                         EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3,  \
 671                             &oword);                                    \
 672                 }                                                       \
 673                                                                         \
 674                 _NOTE(CONSTANTCONDITION)                                \
 675         } while (B_FALSE)
 676
 677 #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp)             \
 678         do {                                                            \
 679                 efx_oword_t oword;                                      \
 680                                                                         \
 681                 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword);        \
 682                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1);      \
 683                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH,           \
 684                     (_ip) ? 1 : 0);                                     \
 685                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP,           \
 686                     (_tcp) ? 0 : 1);                                    \
 687                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR,    \
 688                     (_insert) ? 1 : 0);                                 \
 689                 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword);       \
 690                                                                         \
 691                 _NOTE(CONSTANTCONDITION)                                \
 692         } while (B_FALSE)
 693
 694 #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc)                 \
 695         do {                                                            \
 696                 efx_oword_t oword;                                      \
 697                                                                         \
 698                 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword);  \
 699                 EFX_SET_OWORD_FIELD(oword,                              \
 700                     FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1);                \
 701                 EFX_SET_OWORD_FIELD(oword,                              \
 702                     FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \
 703                 EFX_SET_OWORD_FIELD(oword,                              \
 704                     FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1);   \
 705                 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
 706                                                                         \
 707                 (_rc) = 0;                                              \
 708                                                                         \
 709                 _NOTE(CONSTANTCONDITION)                                \
 710         } while (B_FALSE)
 711
 712
 713 #if EFSYS_OPT_RX_SCALE
 714
 715 static  __checkReturn   efx_rc_t
 716 siena_rx_scale_mode_set(
 717         __in            efx_nic_t *enp,
 718         __in            efx_rx_hash_alg_t alg,
 719         __in            efx_rx_hash_type_t type,
 720         __in            boolean_t insert)
 721 {
 722         efx_rc_t rc;
 723
 724         switch (alg) {
 725         case EFX_RX_HASHALG_LFSR:
 726                 EFX_RX_LFSR_HASH(enp, insert);
 727                 break;
 728
 729         case EFX_RX_HASHALG_TOEPLITZ:
 730                 EFX_RX_TOEPLITZ_IPV4_HASH(enp, insert,
 731                     type & (1 << EFX_RX_HASH_IPV4),
 732                     type & (1 << EFX_RX_HASH_TCPIPV4));
 733
 734                 EFX_RX_TOEPLITZ_IPV6_HASH(enp,
 735                     type & (1 << EFX_RX_HASH_IPV6),
 736                     type & (1 << EFX_RX_HASH_TCPIPV6),
 737                     rc);
 738                 if (rc != 0)
 739                         goto fail1;
 740
 741                 break;
 742
 743         default:
 744                 rc = EINVAL;
 745                 goto fail2;
 746         }
 747
 748         return (0);
 749
 750 fail2:
 751         EFSYS_PROBE(fail2);
 752 fail1:
 753         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 754
 755         EFX_RX_LFSR_HASH(enp, B_FALSE);
 756
 757         return (rc);
 758 }
 759 #endif
 760
 761 #if EFSYS_OPT_RX_SCALE
 762 static  __checkReturn   efx_rc_t
 763 siena_rx_scale_key_set(
 764         __in            efx_nic_t *enp,
 765         __in_ecount(n)  uint8_t *key,
 766         __in            size_t n)
 767 {
 768         efx_oword_t oword;
 769         unsigned int byte;
 770         unsigned int offset;
 771         efx_rc_t rc;
 772
 773         byte = 0;
 774
 775         /* Write Toeplitz IPv4 hash key */
 776         EFX_ZERO_OWORD(oword);
 777         for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
 778             offset > 0 && byte < n;
 779             --offset)
 780                 oword.eo_u8[offset - 1] = key[byte++];
 781
 782         EFX_BAR_WRITEO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
 783
 784         byte = 0;
 785
 786         /* Verify Toeplitz IPv4 hash key */
 787         EFX_BAR_READO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
 788         for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
 789             offset > 0 && byte < n;
 790             --offset) {
 791                 if (oword.eo_u8[offset - 1] != key[byte++]) {
 792                         rc = EFAULT;
 793                         goto fail1;
 794                 }
 795         }
 796
 797         if ((enp->en_features & EFX_FEATURE_IPV6) == 0)
 798                 goto done;
 799
 800         byte = 0;
 801
 802         /* Write Toeplitz IPv6 hash key 3 */
 803         EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
 804         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
 805             FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
 806             offset > 0 && byte < n;
 807             --offset)
 808                 oword.eo_u8[offset - 1] = key[byte++];
 809
 810         EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
 811
 812         /* Write Toeplitz IPv6 hash key 2 */
 813         EFX_ZERO_OWORD(oword);
 814         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
 815             FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
 816             offset > 0 && byte < n;
 817             --offset)
 818                 oword.eo_u8[offset - 1] = key[byte++];
 819
 820         EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
 821
 822         /* Write Toeplitz IPv6 hash key 1 */
 823         EFX_ZERO_OWORD(oword);
 824         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
 825             FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
 826             offset > 0 && byte < n;
 827             --offset)
 828                 oword.eo_u8[offset - 1] = key[byte++];
 829
 830         EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
 831
 832         byte = 0;
 833
 834         /* Verify Toeplitz IPv6 hash key 3 */
 835         EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
 836         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
 837             FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
 838             offset > 0 && byte < n;
 839             --offset) {
 840                 if (oword.eo_u8[offset - 1] != key[byte++]) {
 841                         rc = EFAULT;
 842                         goto fail2;
 843                 }
 844         }
 845
 846         /* Verify Toeplitz IPv6 hash key 2 */
 847         EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
 848         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
 849             FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
 850             offset > 0 && byte < n;
 851             --offset) {
 852                 if (oword.eo_u8[offset - 1] != key[byte++]) {
 853                         rc = EFAULT;
 854                         goto fail3;
 855                 }
 856         }
 857
 858         /* Verify Toeplitz IPv6 hash key 1 */
 859         EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
 860         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
 861             FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
 862             offset > 0 && byte < n;
 863             --offset) {
 864                 if (oword.eo_u8[offset - 1] != key[byte++]) {
 865                         rc = EFAULT;
 866                         goto fail4;
 867                 }
 868         }
 869
 870 done:
 871         return (0);
 872
 873 fail4:
 874         EFSYS_PROBE(fail4);
 875 fail3:
 876         EFSYS_PROBE(fail3);
 877 fail2:
 878         EFSYS_PROBE(fail2);
 879 fail1:
 880         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 881
 882         return (rc);
 883 }
 884 #endif
 885
 886 #if EFSYS_OPT_RX_SCALE
 887 static  __checkReturn   efx_rc_t
 888 siena_rx_scale_tbl_set(
 889         __in            efx_nic_t *enp,
 890         __in_ecount(n)  unsigned int *table,
 891         __in            size_t n)
 892 {
 893         efx_oword_t oword;
 894         int index;
 895         efx_rc_t rc;
 896
 897         EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS);
 898         EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH));
 899
 900         if (n > FR_BZ_RX_INDIRECTION_TBL_ROWS) {
 901                 rc = EINVAL;
 902                 goto fail1;
 903         }
 904
 905         for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; index++) {
 906                 uint32_t byte;
 907
 908                 /* Calculate the entry to place in the table */
 909                 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
 910
 911                 EFSYS_PROBE2(table, int, index, uint32_t, byte);
 912
 913                 EFX_POPULATE_OWORD_1(oword, FRF_BZ_IT_QUEUE, byte);
 914
 915                 /* Write the table */
 916                 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
 917                                     index, &oword, B_TRUE);
 918         }
 919
 920         for (index = FR_BZ_RX_INDIRECTION_TBL_ROWS - 1; index >= 0; --index) {
 921                 uint32_t byte;
 922
 923                 /* Determine if we're starting a new batch */
 924                 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
 925
 926                 /* Read the table */
 927                 EFX_BAR_TBL_READO(enp, FR_BZ_RX_INDIRECTION_TBL,
 928                                     index, &oword, B_TRUE);
 929
 930                 /* Verify the entry */
 931                 if (EFX_OWORD_FIELD(oword, FRF_BZ_IT_QUEUE) != byte) {
 932                         rc = EFAULT;
 933                         goto fail2;
 934                 }
 935         }
 936
 937         return (0);
 938
 939 fail2:
 940         EFSYS_PROBE(fail2);
 941 fail1:
 942         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 943
 944         return (rc);
 945 }
 946 #endif
 947
 948 /*
 949  * Falcon/Siena pseudo-header
 950  * --------------------------
 951  *
 952  * Receive packets are prefixed by an optional 16 byte pseudo-header.
 953  * The pseudo-header is a byte array of one of the forms:
 954  *
 955  *  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15
 956  * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT
 957  * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL
 958  *
 959  * where:
 960  *   TT.TT.TT.TT   Toeplitz hash (32-bit big-endian)
 961  *   LL.LL         LFSR hash     (16-bit big-endian)
 962  */
 963
 964 #if EFSYS_OPT_RX_SCALE
 965 static  __checkReturn   uint32_t
 966 siena_rx_prefix_hash(
 967         __in            efx_nic_t *enp,
 968         __in            efx_rx_hash_alg_t func,
 969         __in            uint8_t *buffer)
 970 {
 971         _NOTE(ARGUNUSED(enp))
 972
 973         switch (func) {
 974         case EFX_RX_HASHALG_TOEPLITZ:
 975                 return ((buffer[12] << 24) |
 976                     (buffer[13] << 16) |
 977                     (buffer[14] <<  8) |
 978                     buffer[15]);
 979
 980         case EFX_RX_HASHALG_LFSR:
 981                 return ((buffer[14] << 8) | buffer[15]);
 982
 983         default:
 984                 EFSYS_ASSERT(0);
 985                 return (0);
 986         }
 987 }
 988 #endif /* EFSYS_OPT_RX_SCALE */
 989
 990 static  __checkReturn   efx_rc_t
 991 siena_rx_prefix_pktlen(
 992         __in            efx_nic_t *enp,
 993         __in            uint8_t *buffer,
 994         __out           uint16_t *lengthp)
 995 {
 996         _NOTE(ARGUNUSED(enp, buffer, lengthp))
 997
 998         /* Not supported by Falcon/Siena hardware */
 999         EFSYS_ASSERT(0);
1000         return (ENOTSUP);
1001 }
1002
1003
1004 static                  void
1005 siena_rx_qpost(
1006         __in            efx_rxq_t *erp,
1007         __in_ecount(n)  efsys_dma_addr_t *addrp,
1008         __in            size_t size,
1009         __in            unsigned int n,
1010         __in            unsigned int completed,
1011         __in            unsigned int added)
1012 {
1013         efx_qword_t qword;
1014         unsigned int i;
1015         unsigned int offset;
1016         unsigned int id;
1017
1018         /* The client driver must not overfill the queue */
1019         EFSYS_ASSERT3U(added - completed + n, <=,
1020             EFX_RXQ_LIMIT(erp->er_mask + 1));
1021
1022         id = added & (erp->er_mask);
1023         for (i = 0; i < n; i++) {
1024                 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
1025                     unsigned int, id, efsys_dma_addr_t, addrp[i],
1026                     size_t, size);
1027
1028                 EFX_POPULATE_QWORD_3(qword,
1029                     FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size),
1030                     FSF_AZ_RX_KER_BUF_ADDR_DW0,
1031                     (uint32_t)(addrp[i] & 0xffffffff),
1032                     FSF_AZ_RX_KER_BUF_ADDR_DW1,
1033                     (uint32_t)(addrp[i] >> 32));
1034
1035                 offset = id * sizeof (efx_qword_t);
1036                 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
1037
1038                 id = (id + 1) & (erp->er_mask);
1039         }
1040 }
1041
1042 static                  void
1043 siena_rx_qpush(
1044         __in    efx_rxq_t *erp,
1045         __in    unsigned int added,
1046         __inout unsigned int *pushedp)
1047 {
1048         efx_nic_t *enp = erp->er_enp;
1049         unsigned int pushed = *pushedp;
1050         uint32_t wptr;
1051         efx_oword_t oword;
1052         efx_dword_t dword;
1053
1054         /* All descriptors are pushed */
1055         *pushedp = added;
1056
1057         /* Push the populated descriptors out */
1058         wptr = added & erp->er_mask;
1059
1060         EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr);
1061
1062         /* Only write the third DWORD */
1063         EFX_POPULATE_DWORD_1(dword,
1064             EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
1065
1066         /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
1067         EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
1068             wptr, pushed & erp->er_mask);
1069         EFSYS_PIO_WRITE_BARRIER();
1070         EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,
1071                             erp->er_index, &dword, B_FALSE);
1072 }
1073
1074 static  __checkReturn   efx_rc_t
1075 siena_rx_qflush(
1076         __in    efx_rxq_t *erp)
1077 {
1078         efx_nic_t *enp = erp->er_enp;
1079         efx_oword_t oword;
1080         uint32_t label;
1081
1082         label = erp->er_index;
1083
1084         /* Flush the queue */
1085         EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
1086             FRF_AZ_RX_FLUSH_DESCQ, label);
1087         EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword);
1088
1089         return (0);
1090 }
1091
1092 static          void
1093 siena_rx_qenable(
1094         __in    efx_rxq_t *erp)
1095 {
1096         efx_nic_t *enp = erp->er_enp;
1097         efx_oword_t oword;
1098
1099         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
1100
1101         EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL,
1102                             erp->er_index, &oword, B_TRUE);
1103
1104         EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0);
1105         EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0);
1106         EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1);
1107
1108         EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1109                             erp->er_index, &oword, B_TRUE);
1110 }
1111
1112 static  __checkReturn   efx_rc_t
1113 siena_rx_qcreate(
1114         __in            efx_nic_t *enp,
1115         __in            unsigned int index,
1116         __in            unsigned int label,
1117         __in            efx_rxq_type_t type,
1118         __in            efsys_mem_t *esmp,
1119         __in            size_t n,
1120         __in            uint32_t id,
1121         __in            efx_evq_t *eep,
1122         __in            efx_rxq_t *erp)
1123 {
1124         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1125         efx_oword_t oword;
1126         uint32_t size;
1127         boolean_t jumbo;
1128         efx_rc_t rc;
1129
1130         _NOTE(ARGUNUSED(esmp))
1131
1132         EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
1133             (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH));
1134         EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1135         EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
1136
1137         EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
1138         EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
1139
1140         if (!ISP2(n) || (n < EFX_RXQ_MINNDESCS) || (n > EFX_RXQ_MAXNDESCS)) {
1141                 rc = EINVAL;
1142                 goto fail1;
1143         }
1144         if (index >= encp->enc_rxq_limit) {
1145                 rc = EINVAL;
1146                 goto fail2;
1147         }
1148         for (size = 0; (1 << size) <= (EFX_RXQ_MAXNDESCS / EFX_RXQ_MINNDESCS);
1149             size++)
1150                 if ((1 << size) == (int)(n / EFX_RXQ_MINNDESCS))
1151                         break;
1152         if (id + (1 << size) >= encp->enc_buftbl_limit) {
1153                 rc = EINVAL;
1154                 goto fail3;
1155         }
1156
1157         switch (type) {
1158         case EFX_RXQ_TYPE_DEFAULT:
1159                 jumbo = B_FALSE;
1160                 break;
1161
1162 #if EFSYS_OPT_RX_SCATTER
1163         case EFX_RXQ_TYPE_SCATTER:
1164                 if (enp->en_family < EFX_FAMILY_SIENA) {
1165                         rc = EINVAL;
1166                         goto fail4;
1167                 }
1168                 jumbo = B_TRUE;
1169                 break;
1170 #endif  /* EFSYS_OPT_RX_SCATTER */
1171
1172         default:
1173                 rc = EINVAL;
1174                 goto fail4;
1175         }
1176
1177         /* Set up the new descriptor queue */
1178         EFX_POPULATE_OWORD_7(oword,
1179             FRF_AZ_RX_DESCQ_BUF_BASE_ID, id,
1180             FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index,
1181             FRF_AZ_RX_DESCQ_OWNER_ID, 0,
1182             FRF_AZ_RX_DESCQ_LABEL, label,
1183             FRF_AZ_RX_DESCQ_SIZE, size,
1184             FRF_AZ_RX_DESCQ_TYPE, 0,
1185             FRF_AZ_RX_DESCQ_JUMBO, jumbo);
1186
1187         EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1188                             erp->er_index, &oword, B_TRUE);
1189
1190         return (0);
1191
1192 fail4:
1193         EFSYS_PROBE(fail4);
1194 fail3:
1195         EFSYS_PROBE(fail3);
1196 fail2:
1197         EFSYS_PROBE(fail2);
1198 fail1:
1199         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1200
1201         return (rc);
1202 }
1203
1204 static          void
1205 siena_rx_qdestroy(
1206         __in    efx_rxq_t *erp)
1207 {
1208         efx_nic_t *enp = erp->er_enp;
1209         efx_oword_t oword;
1210
1211         EFSYS_ASSERT(enp->en_rx_qcount != 0);
1212         --enp->en_rx_qcount;
1213
1214         /* Purge descriptor queue */
1215         EFX_ZERO_OWORD(oword);
1216
1217         EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1218                             erp->er_index, &oword, B_TRUE);
1219
1220         /* Free the RXQ object */
1221         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1222 }
1223
1224 static          void
1225 siena_rx_fini(
1226         __in    efx_nic_t *enp)
1227 {
1228         _NOTE(ARGUNUSED(enp))
1229 }
1230
1231 #endif /* EFSYS_OPT_SIENA */