drivers/net/sfc/base/efx_rx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2007-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9
  10
  11 #if EFSYS_OPT_SIENA
  12
  13 static  __checkReturn   efx_rc_t
  14 siena_rx_init(
  15         __in            efx_nic_t *enp);
  16
  17 static                  void
  18 siena_rx_fini(
  19         __in            efx_nic_t *enp);
  20
  21 #if EFSYS_OPT_RX_SCATTER
  22 static  __checkReturn   efx_rc_t
  23 siena_rx_scatter_enable(
  24         __in            efx_nic_t *enp,
  25         __in            unsigned int buf_size);
  26 #endif /* EFSYS_OPT_RX_SCATTER */
  27
  28 #if EFSYS_OPT_RX_SCALE
  29 static  __checkReturn   efx_rc_t
  30 siena_rx_scale_mode_set(
  31         __in            efx_nic_t *enp,
  32         __in            uint32_t rss_context,
  33         __in            efx_rx_hash_alg_t alg,
  34         __in            efx_rx_hash_type_t type,
  35         __in            boolean_t insert);
  36
  37 static  __checkReturn   efx_rc_t
  38 siena_rx_scale_key_set(
  39         __in            efx_nic_t *enp,
  40         __in            uint32_t rss_context,
  41         __in_ecount(n)  uint8_t *key,
  42         __in            size_t n);
  43
  44 static  __checkReturn   efx_rc_t
  45 siena_rx_scale_tbl_set(
  46         __in            efx_nic_t *enp,
  47         __in            uint32_t rss_context,
  48         __in_ecount(n)  unsigned int *table,
  49         __in            size_t n);
  50
  51 static  __checkReturn   uint32_t
  52 siena_rx_prefix_hash(
  53         __in            efx_nic_t *enp,
  54         __in            efx_rx_hash_alg_t func,
  55         __in            uint8_t *buffer);
  56
  57 #endif /* EFSYS_OPT_RX_SCALE */
  58
  59 static  __checkReturn   efx_rc_t
  60 siena_rx_prefix_pktlen(
  61         __in            efx_nic_t *enp,
  62         __in            uint8_t *buffer,
  63         __out           uint16_t *lengthp);
  64
  65 static                          void
  66 siena_rx_qpost(
  67         __in                    efx_rxq_t *erp,
  68         __in_ecount(ndescs)     efsys_dma_addr_t *addrp,
  69         __in                    size_t size,
  70         __in                    unsigned int ndescs,
  71         __in                    unsigned int completed,
  72         __in                    unsigned int added);
  73
  74 static                  void
  75 siena_rx_qpush(
  76         __in            efx_rxq_t *erp,
  77         __in            unsigned int added,
  78         __inout         unsigned int *pushedp);
  79
  80 #if EFSYS_OPT_RX_PACKED_STREAM
  81 static          void
  82 siena_rx_qpush_ps_credits(
  83         __in            efx_rxq_t *erp);
  84
  85 static  __checkReturn   uint8_t *
  86 siena_rx_qps_packet_info(
  87         __in            efx_rxq_t *erp,
  88         __in            uint8_t *buffer,
  89         __in            uint32_t buffer_length,
  90         __in            uint32_t current_offset,
  91         __out           uint16_t *lengthp,
  92         __out           uint32_t *next_offsetp,
  93         __out           uint32_t *timestamp);
  94 #endif
  95
  96 static  __checkReturn   efx_rc_t
  97 siena_rx_qflush(
  98         __in            efx_rxq_t *erp);
  99
 100 static                  void
 101 siena_rx_qenable(
 102         __in            efx_rxq_t *erp);
 103
 104 static  __checkReturn   efx_rc_t
 105 siena_rx_qcreate(
 106         __in            efx_nic_t *enp,
 107         __in            unsigned int index,
 108         __in            unsigned int label,
 109         __in            efx_rxq_type_t type,
 110         __in            const efx_rxq_type_data_t *type_data,
 111         __in            efsys_mem_t *esmp,
 112         __in            size_t ndescs,
 113         __in            uint32_t id,
 114         __in            unsigned int flags,
 115         __in            efx_evq_t *eep,
 116         __in            efx_rxq_t *erp);
 117
 118 static                  void
 119 siena_rx_qdestroy(
 120         __in            efx_rxq_t *erp);
 121
 122 #endif /* EFSYS_OPT_SIENA */
 123
 124
 125 #if EFSYS_OPT_SIENA
 126 static const efx_rx_ops_t __efx_rx_siena_ops = {
 127         siena_rx_init,                          /* erxo_init */
 128         siena_rx_fini,                          /* erxo_fini */
 129 #if EFSYS_OPT_RX_SCATTER
 130         siena_rx_scatter_enable,                /* erxo_scatter_enable */
 131 #endif
 132 #if EFSYS_OPT_RX_SCALE
 133         NULL,                                   /* erxo_scale_context_alloc */
 134         NULL,                                   /* erxo_scale_context_free */
 135         siena_rx_scale_mode_set,                /* erxo_scale_mode_set */
 136         siena_rx_scale_key_set,                 /* erxo_scale_key_set */
 137         siena_rx_scale_tbl_set,                 /* erxo_scale_tbl_set */
 138         siena_rx_prefix_hash,                   /* erxo_prefix_hash */
 139 #endif
 140         siena_rx_prefix_pktlen,                 /* erxo_prefix_pktlen */
 141         siena_rx_qpost,                         /* erxo_qpost */
 142         siena_rx_qpush,                         /* erxo_qpush */
 143 #if EFSYS_OPT_RX_PACKED_STREAM
 144         siena_rx_qpush_ps_credits,              /* erxo_qpush_ps_credits */
 145         siena_rx_qps_packet_info,               /* erxo_qps_packet_info */
 146 #endif
 147         siena_rx_qflush,                        /* erxo_qflush */
 148         siena_rx_qenable,                       /* erxo_qenable */
 149         siena_rx_qcreate,                       /* erxo_qcreate */
 150         siena_rx_qdestroy,                      /* erxo_qdestroy */
 151 };
 152 #endif  /* EFSYS_OPT_SIENA */
 153
 154 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
 155 static const efx_rx_ops_t __efx_rx_ef10_ops = {
 156         ef10_rx_init,                           /* erxo_init */
 157         ef10_rx_fini,                           /* erxo_fini */
 158 #if EFSYS_OPT_RX_SCATTER
 159         ef10_rx_scatter_enable,                 /* erxo_scatter_enable */
 160 #endif
 161 #if EFSYS_OPT_RX_SCALE
 162         ef10_rx_scale_context_alloc,            /* erxo_scale_context_alloc */
 163         ef10_rx_scale_context_free,             /* erxo_scale_context_free */
 164         ef10_rx_scale_mode_set,                 /* erxo_scale_mode_set */
 165         ef10_rx_scale_key_set,                  /* erxo_scale_key_set */
 166         ef10_rx_scale_tbl_set,                  /* erxo_scale_tbl_set */
 167         ef10_rx_prefix_hash,                    /* erxo_prefix_hash */
 168 #endif
 169         ef10_rx_prefix_pktlen,                  /* erxo_prefix_pktlen */
 170         ef10_rx_qpost,                          /* erxo_qpost */
 171         ef10_rx_qpush,                          /* erxo_qpush */
 172 #if EFSYS_OPT_RX_PACKED_STREAM
 173         ef10_rx_qpush_ps_credits,               /* erxo_qpush_ps_credits */
 174         ef10_rx_qps_packet_info,                /* erxo_qps_packet_info */
 175 #endif
 176         ef10_rx_qflush,                         /* erxo_qflush */
 177         ef10_rx_qenable,                        /* erxo_qenable */
 178         ef10_rx_qcreate,                        /* erxo_qcreate */
 179         ef10_rx_qdestroy,                       /* erxo_qdestroy */
 180 };
 181 #endif  /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
 182
 183
 184         __checkReturn   efx_rc_t
 185 efx_rx_init(
 186         __inout         efx_nic_t *enp)
 187 {
 188         const efx_rx_ops_t *erxop;
 189         efx_rc_t rc;
 190
 191         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 192         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 193
 194         if (!(enp->en_mod_flags & EFX_MOD_EV)) {
 195                 rc = EINVAL;
 196                 goto fail1;
 197         }
 198
 199         if (enp->en_mod_flags & EFX_MOD_RX) {
 200                 rc = EINVAL;
 201                 goto fail2;
 202         }
 203
 204         switch (enp->en_family) {
 205 #if EFSYS_OPT_SIENA
 206         case EFX_FAMILY_SIENA:
 207                 erxop = &__efx_rx_siena_ops;
 208                 break;
 209 #endif /* EFSYS_OPT_SIENA */
 210
 211 #if EFSYS_OPT_HUNTINGTON
 212         case EFX_FAMILY_HUNTINGTON:
 213                 erxop = &__efx_rx_ef10_ops;
 214                 break;
 215 #endif /* EFSYS_OPT_HUNTINGTON */
 216
 217 #if EFSYS_OPT_MEDFORD
 218         case EFX_FAMILY_MEDFORD:
 219                 erxop = &__efx_rx_ef10_ops;
 220                 break;
 221 #endif /* EFSYS_OPT_MEDFORD */
 222
 223 #if EFSYS_OPT_MEDFORD2
 224         case EFX_FAMILY_MEDFORD2:
 225                 erxop = &__efx_rx_ef10_ops;
 226                 break;
 227 #endif /* EFSYS_OPT_MEDFORD2 */
 228
 229         default:
 230                 EFSYS_ASSERT(0);
 231                 rc = ENOTSUP;
 232                 goto fail3;
 233         }
 234
 235         if ((rc = erxop->erxo_init(enp)) != 0)
 236                 goto fail4;
 237
 238         enp->en_erxop = erxop;
 239         enp->en_mod_flags |= EFX_MOD_RX;
 240         return (0);
 241
 242 fail4:
 243         EFSYS_PROBE(fail4);
 244 fail3:
 245         EFSYS_PROBE(fail3);
 246 fail2:
 247         EFSYS_PROBE(fail2);
 248 fail1:
 249         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 250
 251         enp->en_erxop = NULL;
 252         enp->en_mod_flags &= ~EFX_MOD_RX;
 253         return (rc);
 254 }
 255
 256                         void
 257 efx_rx_fini(
 258         __in            efx_nic_t *enp)
 259 {
 260         const efx_rx_ops_t *erxop = enp->en_erxop;
 261
 262         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 263         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 264         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 265         EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0);
 266
 267         erxop->erxo_fini(enp);
 268
 269         enp->en_erxop = NULL;
 270         enp->en_mod_flags &= ~EFX_MOD_RX;
 271 }
 272
 273 #if EFSYS_OPT_RX_SCATTER
 274         __checkReturn   efx_rc_t
 275 efx_rx_scatter_enable(
 276         __in            efx_nic_t *enp,
 277         __in            unsigned int buf_size)
 278 {
 279         const efx_rx_ops_t *erxop = enp->en_erxop;
 280         efx_rc_t rc;
 281
 282         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 283         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 284
 285         if ((rc = erxop->erxo_scatter_enable(enp, buf_size)) != 0)
 286                 goto fail1;
 287
 288         return (0);
 289
 290 fail1:
 291         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 292         return (rc);
 293 }
 294 #endif  /* EFSYS_OPT_RX_SCATTER */
 295
 296 #if EFSYS_OPT_RX_SCALE
 297         __checkReturn                           efx_rc_t
 298 efx_rx_scale_hash_flags_get(
 299         __in                                    efx_nic_t *enp,
 300         __in                                    efx_rx_hash_alg_t hash_alg,
 301         __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp,
 302         __in                                    unsigned int max_nflags,
 303         __out                                   unsigned int *nflagsp)
 304 {
 305         efx_nic_cfg_t *encp = &enp->en_nic_cfg;
 306         unsigned int nflags = 0;
 307         efx_rc_t rc;
 308
 309         if (flagsp == NULL || nflagsp == NULL) {
 310                 rc = EINVAL;
 311                 goto fail1;
 312         }
 313
 314         if ((encp->enc_rx_scale_hash_alg_mask & (1U << hash_alg)) == 0) {
 315                 nflags = 0;
 316                 goto done;
 317         }
 318
 319         /* Helper to add flags word to flags array without buffer overflow */
 320 #define INSERT_FLAGS(_flags)                    \
 321         do {                                    \
 322                 if (nflags >= max_nflags) {     \
 323                         rc = E2BIG;             \
 324                         goto fail2;             \
 325                 }                               \
 326                 *(flagsp + nflags) = (_flags);  \
 327                 nflags++;                       \
 328                                                 \
 329                 _NOTE(CONSTANTCONDITION)        \
 330         } while (B_FALSE)
 331
 332         if (encp->enc_rx_scale_l4_hash_supported != B_FALSE) {
 333                 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 4TUPLE));
 334                 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 4TUPLE));
 335         }
 336
 337         if ((encp->enc_rx_scale_l4_hash_supported != B_FALSE) &&
 338             (encp->enc_rx_scale_additional_modes_supported != B_FALSE)) {
 339                 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 2TUPLE_DST));
 340                 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 2TUPLE_SRC));
 341
 342                 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 2TUPLE_DST));
 343                 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 2TUPLE_SRC));
 344
 345                 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 4TUPLE));
 346                 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 2TUPLE_DST));
 347                 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 2TUPLE_SRC));
 348
 349                 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 4TUPLE));
 350                 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 2TUPLE_DST));
 351                 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 2TUPLE_SRC));
 352         }
 353
 354         INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 2TUPLE));
 355         INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 2TUPLE));
 356
 357         INSERT_FLAGS(EFX_RX_HASH(IPV4, 2TUPLE));
 358         INSERT_FLAGS(EFX_RX_HASH(IPV6, 2TUPLE));
 359
 360         if (encp->enc_rx_scale_additional_modes_supported != B_FALSE) {
 361                 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 1TUPLE_DST));
 362                 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 1TUPLE_SRC));
 363
 364                 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 1TUPLE_DST));
 365                 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 1TUPLE_SRC));
 366
 367                 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 2TUPLE));
 368                 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 1TUPLE_DST));
 369                 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 1TUPLE_SRC));
 370
 371                 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 2TUPLE));
 372                 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 1TUPLE_DST));
 373                 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 1TUPLE_SRC));
 374
 375                 INSERT_FLAGS(EFX_RX_HASH(IPV4, 1TUPLE_DST));
 376                 INSERT_FLAGS(EFX_RX_HASH(IPV4, 1TUPLE_SRC));
 377
 378                 INSERT_FLAGS(EFX_RX_HASH(IPV6, 1TUPLE_DST));
 379                 INSERT_FLAGS(EFX_RX_HASH(IPV6, 1TUPLE_SRC));
 380         }
 381
 382         INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, DISABLE));
 383         INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, DISABLE));
 384
 385         INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, DISABLE));
 386         INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, DISABLE));
 387
 388         INSERT_FLAGS(EFX_RX_HASH(IPV4, DISABLE));
 389         INSERT_FLAGS(EFX_RX_HASH(IPV6, DISABLE));
 390
 391 #undef INSERT_FLAGS
 392
 393 done:
 394         *nflagsp = nflags;
 395         return (0);
 396
 397 fail2:
 398         EFSYS_PROBE(fail2);
 399 fail1:
 400         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 401
 402         return (rc);
 403 }
 404
 405         __checkReturn   efx_rc_t
 406 efx_rx_hash_default_support_get(
 407         __in            efx_nic_t *enp,
 408         __out           efx_rx_hash_support_t *supportp)
 409 {
 410         efx_rc_t rc;
 411
 412         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 413         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 414
 415         if (supportp == NULL) {
 416                 rc = EINVAL;
 417                 goto fail1;
 418         }
 419
 420         /*
 421          * Report the hashing support the client gets by default if it
 422          * does not allocate an RSS context itself.
 423          */
 424         *supportp = enp->en_hash_support;
 425
 426         return (0);
 427
 428 fail1:
 429         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 430
 431         return (rc);
 432 }
 433
 434         __checkReturn   efx_rc_t
 435 efx_rx_scale_default_support_get(
 436         __in            efx_nic_t *enp,
 437         __out           efx_rx_scale_context_type_t *typep)
 438 {
 439         efx_rc_t rc;
 440
 441         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 442         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 443
 444         if (typep == NULL) {
 445                 rc = EINVAL;
 446                 goto fail1;
 447         }
 448
 449         /*
 450          * Report the RSS support the client gets by default if it
 451          * does not allocate an RSS context itself.
 452          */
 453         *typep = enp->en_rss_context_type;
 454
 455         return (0);
 456
 457 fail1:
 458         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 459
 460         return (rc);
 461 }
 462 #endif  /* EFSYS_OPT_RX_SCALE */
 463
 464 #if EFSYS_OPT_RX_SCALE
 465         __checkReturn   efx_rc_t
 466 efx_rx_scale_context_alloc(
 467         __in            efx_nic_t *enp,
 468         __in            efx_rx_scale_context_type_t type,
 469         __in            uint32_t num_queues,
 470         __out           uint32_t *rss_contextp)
 471 {
 472         const efx_rx_ops_t *erxop = enp->en_erxop;
 473         efx_rc_t rc;
 474
 475         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 476         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 477
 478         if (erxop->erxo_scale_context_alloc == NULL) {
 479                 rc = ENOTSUP;
 480                 goto fail1;
 481         }
 482         if ((rc = erxop->erxo_scale_context_alloc(enp, type,
 483                             num_queues, rss_contextp)) != 0) {
 484                 goto fail2;
 485         }
 486
 487         return (0);
 488
 489 fail2:
 490         EFSYS_PROBE(fail2);
 491 fail1:
 492         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 493         return (rc);
 494 }
 495 #endif  /* EFSYS_OPT_RX_SCALE */
 496
 497 #if EFSYS_OPT_RX_SCALE
 498         __checkReturn   efx_rc_t
 499 efx_rx_scale_context_free(
 500         __in            efx_nic_t *enp,
 501         __in            uint32_t rss_context)
 502 {
 503         const efx_rx_ops_t *erxop = enp->en_erxop;
 504         efx_rc_t rc;
 505
 506         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 507         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 508
 509         if (erxop->erxo_scale_context_free == NULL) {
 510                 rc = ENOTSUP;
 511                 goto fail1;
 512         }
 513         if ((rc = erxop->erxo_scale_context_free(enp, rss_context)) != 0)
 514                 goto fail2;
 515
 516         return (0);
 517
 518 fail2:
 519         EFSYS_PROBE(fail2);
 520 fail1:
 521         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 522         return (rc);
 523 }
 524 #endif  /* EFSYS_OPT_RX_SCALE */
 525
 526 #if EFSYS_OPT_RX_SCALE
 527         __checkReturn   efx_rc_t
 528 efx_rx_scale_mode_set(
 529         __in            efx_nic_t *enp,
 530         __in            uint32_t rss_context,
 531         __in            efx_rx_hash_alg_t alg,
 532         __in            efx_rx_hash_type_t type,
 533         __in            boolean_t insert)
 534 {
 535         const efx_rx_ops_t *erxop = enp->en_erxop;
 536         unsigned int type_flags[EFX_RX_HASH_NFLAGS];
 537         unsigned int type_nflags;
 538         efx_rx_hash_type_t type_check;
 539         unsigned int i;
 540         efx_rc_t rc;
 541
 542         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 543         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 544
 545         /*
 546          * Legacy flags and modern bits cannot be
 547          * used at the same time in the hash type.
 548          */
 549         if ((type & EFX_RX_HASH_LEGACY_MASK) &&
 550             (type & ~EFX_RX_HASH_LEGACY_MASK)) {
 551                 rc = EINVAL;
 552                 goto fail1;
 553         }
 554
 555         /*
 556          * Translate legacy flags to the new representation
 557          * so that chip-specific handlers will consider the
 558          * new flags only.
 559          */
 560         if (type & EFX_RX_HASH_IPV4) {
 561                 type |= EFX_RX_HASH(IPV4, 2TUPLE);
 562                 type |= EFX_RX_HASH(IPV4_TCP, 2TUPLE);
 563                 type |= EFX_RX_HASH(IPV4_UDP, 2TUPLE);
 564         }
 565
 566         if (type & EFX_RX_HASH_TCPIPV4)
 567                 type |= EFX_RX_HASH(IPV4_TCP, 4TUPLE);
 568
 569         if (type & EFX_RX_HASH_IPV6) {
 570                 type |= EFX_RX_HASH(IPV6, 2TUPLE);
 571                 type |= EFX_RX_HASH(IPV6_TCP, 2TUPLE);
 572                 type |= EFX_RX_HASH(IPV6_UDP, 2TUPLE);
 573         }
 574
 575         if (type & EFX_RX_HASH_TCPIPV6)
 576                 type |= EFX_RX_HASH(IPV6_TCP, 4TUPLE);
 577
 578         type &= ~EFX_RX_HASH_LEGACY_MASK;
 579         type_check = type;
 580
 581         /*
 582          * Get the list of supported hash flags and sanitise the input.
 583          */
 584         rc = efx_rx_scale_hash_flags_get(enp, alg, type_flags,
 585                                     EFX_ARRAY_SIZE(type_flags), &type_nflags);
 586         if (rc != 0)
 587                 goto fail2;
 588
 589         for (i = 0; i < type_nflags; ++i) {
 590                 if ((type_check & type_flags[i]) == type_flags[i])
 591                         type_check &= ~(type_flags[i]);
 592         }
 593
 594         if (type_check != 0) {
 595                 rc = EINVAL;
 596                 goto fail3;
 597         }
 598
 599         if (erxop->erxo_scale_mode_set != NULL) {
 600                 if ((rc = erxop->erxo_scale_mode_set(enp, rss_context, alg,
 601                             type, insert)) != 0)
 602                         goto fail4;
 603         }
 604
 605         return (0);
 606
 607 fail4:
 608         EFSYS_PROBE(fail4);
 609 fail3:
 610         EFSYS_PROBE(fail3);
 611 fail2:
 612         EFSYS_PROBE(fail2);
 613 fail1:
 614         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 615         return (rc);
 616 }
 617 #endif  /* EFSYS_OPT_RX_SCALE */
 618
 619 #if EFSYS_OPT_RX_SCALE
 620         __checkReturn   efx_rc_t
 621 efx_rx_scale_key_set(
 622         __in            efx_nic_t *enp,
 623         __in            uint32_t rss_context,
 624         __in_ecount(n)  uint8_t *key,
 625         __in            size_t n)
 626 {
 627         const efx_rx_ops_t *erxop = enp->en_erxop;
 628         efx_rc_t rc;
 629
 630         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 631         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 632
 633         if ((rc = erxop->erxo_scale_key_set(enp, rss_context, key, n)) != 0)
 634                 goto fail1;
 635
 636         return (0);
 637
 638 fail1:
 639         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 640
 641         return (rc);
 642 }
 643 #endif  /* EFSYS_OPT_RX_SCALE */
 644
 645 #if EFSYS_OPT_RX_SCALE
 646         __checkReturn   efx_rc_t
 647 efx_rx_scale_tbl_set(
 648         __in            efx_nic_t *enp,
 649         __in            uint32_t rss_context,
 650         __in_ecount(n)  unsigned int *table,
 651         __in            size_t n)
 652 {
 653         const efx_rx_ops_t *erxop = enp->en_erxop;
 654         efx_rc_t rc;
 655
 656         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 657         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 658
 659         if ((rc = erxop->erxo_scale_tbl_set(enp, rss_context, table, n)) != 0)
 660                 goto fail1;
 661
 662         return (0);
 663
 664 fail1:
 665         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 666
 667         return (rc);
 668 }
 669 #endif  /* EFSYS_OPT_RX_SCALE */
 670
 671                                 void
 672 efx_rx_qpost(
 673         __in                    efx_rxq_t *erp,
 674         __in_ecount(ndescs)     efsys_dma_addr_t *addrp,
 675         __in                    size_t size,
 676         __in                    unsigned int ndescs,
 677         __in                    unsigned int completed,
 678         __in                    unsigned int added)
 679 {
 680         efx_nic_t *enp = erp->er_enp;
 681         const efx_rx_ops_t *erxop = enp->en_erxop;
 682
 683         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 684
 685         erxop->erxo_qpost(erp, addrp, size, ndescs, completed, added);
 686 }
 687
 688 #if EFSYS_OPT_RX_PACKED_STREAM
 689
 690                         void
 691 efx_rx_qpush_ps_credits(
 692         __in            efx_rxq_t *erp)
 693 {
 694         efx_nic_t *enp = erp->er_enp;
 695         const efx_rx_ops_t *erxop = enp->en_erxop;
 696
 697         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 698
 699         erxop->erxo_qpush_ps_credits(erp);
 700 }
 701
 702         __checkReturn   uint8_t *
 703 efx_rx_qps_packet_info(
 704         __in            efx_rxq_t *erp,
 705         __in            uint8_t *buffer,
 706         __in            uint32_t buffer_length,
 707         __in            uint32_t current_offset,
 708         __out           uint16_t *lengthp,
 709         __out           uint32_t *next_offsetp,
 710         __out           uint32_t *timestamp)
 711 {
 712         efx_nic_t *enp = erp->er_enp;
 713         const efx_rx_ops_t *erxop = enp->en_erxop;
 714
 715         return (erxop->erxo_qps_packet_info(erp, buffer,
 716                 buffer_length, current_offset, lengthp,
 717                 next_offsetp, timestamp));
 718 }
 719
 720 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
 721
 722                         void
 723 efx_rx_qpush(
 724         __in            efx_rxq_t *erp,
 725         __in            unsigned int added,
 726         __inout         unsigned int *pushedp)
 727 {
 728         efx_nic_t *enp = erp->er_enp;
 729         const efx_rx_ops_t *erxop = enp->en_erxop;
 730
 731         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 732
 733         erxop->erxo_qpush(erp, added, pushedp);
 734 }
 735
 736         __checkReturn   efx_rc_t
 737 efx_rx_qflush(
 738         __in            efx_rxq_t *erp)
 739 {
 740         efx_nic_t *enp = erp->er_enp;
 741         const efx_rx_ops_t *erxop = enp->en_erxop;
 742         efx_rc_t rc;
 743
 744         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 745
 746         if ((rc = erxop->erxo_qflush(erp)) != 0)
 747                 goto fail1;
 748
 749         return (0);
 750
 751 fail1:
 752         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 753
 754         return (rc);
 755 }
 756
 757                         void
 758 efx_rx_qenable(
 759         __in            efx_rxq_t *erp)
 760 {
 761         efx_nic_t *enp = erp->er_enp;
 762         const efx_rx_ops_t *erxop = enp->en_erxop;
 763
 764         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 765
 766         erxop->erxo_qenable(erp);
 767 }
 768
 769 static  __checkReturn   efx_rc_t
 770 efx_rx_qcreate_internal(
 771         __in            efx_nic_t *enp,
 772         __in            unsigned int index,
 773         __in            unsigned int label,
 774         __in            efx_rxq_type_t type,
 775         __in            const efx_rxq_type_data_t *type_data,
 776         __in            efsys_mem_t *esmp,
 777         __in            size_t ndescs,
 778         __in            uint32_t id,
 779         __in            unsigned int flags,
 780         __in            efx_evq_t *eep,
 781         __deref_out     efx_rxq_t **erpp)
 782 {
 783         const efx_rx_ops_t *erxop = enp->en_erxop;
 784         efx_rxq_t *erp;
 785         efx_rc_t rc;
 786
 787         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 788         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 789
 790         /* Allocate an RXQ object */
 791         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp);
 792
 793         if (erp == NULL) {
 794                 rc = ENOMEM;
 795                 goto fail1;
 796         }
 797
 798         erp->er_magic = EFX_RXQ_MAGIC;
 799         erp->er_enp = enp;
 800         erp->er_index = index;
 801         erp->er_mask = ndescs - 1;
 802         erp->er_esmp = esmp;
 803
 804         if ((rc = erxop->erxo_qcreate(enp, index, label, type, type_data, esmp,
 805             ndescs, id, flags, eep, erp)) != 0)
 806                 goto fail2;
 807
 808         enp->en_rx_qcount++;
 809         *erpp = erp;
 810
 811         return (0);
 812
 813 fail2:
 814         EFSYS_PROBE(fail2);
 815
 816         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
 817 fail1:
 818         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 819
 820         return (rc);
 821 }
 822
 823         __checkReturn   efx_rc_t
 824 efx_rx_qcreate(
 825         __in            efx_nic_t *enp,
 826         __in            unsigned int index,
 827         __in            unsigned int label,
 828         __in            efx_rxq_type_t type,
 829         __in            efsys_mem_t *esmp,
 830         __in            size_t ndescs,
 831         __in            uint32_t id,
 832         __in            unsigned int flags,
 833         __in            efx_evq_t *eep,
 834         __deref_out     efx_rxq_t **erpp)
 835 {
 836         return efx_rx_qcreate_internal(enp, index, label, type, NULL,
 837             esmp, ndescs, id, flags, eep, erpp);
 838 }
 839
 840 #if EFSYS_OPT_RX_PACKED_STREAM
 841
 842         __checkReturn   efx_rc_t
 843 efx_rx_qcreate_packed_stream(
 844         __in            efx_nic_t *enp,
 845         __in            unsigned int index,
 846         __in            unsigned int label,
 847         __in            uint32_t ps_buf_size,
 848         __in            efsys_mem_t *esmp,
 849         __in            size_t ndescs,
 850         __in            efx_evq_t *eep,
 851         __deref_out     efx_rxq_t **erpp)
 852 {
 853         efx_rxq_type_data_t type_data;
 854
 855         memset(&type_data, 0, sizeof (type_data));
 856
 857         type_data.ertd_packed_stream.eps_buf_size = ps_buf_size;
 858
 859         return efx_rx_qcreate_internal(enp, index, label,
 860             EFX_RXQ_TYPE_PACKED_STREAM, &type_data, esmp, ndescs,
 861             0 /* id unused on EF10 */, EFX_RXQ_FLAG_NONE, eep, erpp);
 862 }
 863
 864 #endif
 865
 866 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
 867
 868         __checkReturn   efx_rc_t
 869 efx_rx_qcreate_es_super_buffer(
 870         __in            efx_nic_t *enp,
 871         __in            unsigned int index,
 872         __in            unsigned int label,
 873         __in            uint32_t n_bufs_per_desc,
 874         __in            uint32_t max_dma_len,
 875         __in            uint32_t buf_stride,
 876         __in            uint32_t hol_block_timeout,
 877         __in            efsys_mem_t *esmp,
 878         __in            size_t ndescs,
 879         __in            unsigned int flags,
 880         __in            efx_evq_t *eep,
 881         __deref_out     efx_rxq_t **erpp)
 882 {
 883         efx_rc_t rc;
 884         efx_rxq_type_data_t type_data;
 885
 886         if (hol_block_timeout > EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX) {
 887                 rc = EINVAL;
 888                 goto fail1;
 889         }
 890
 891         memset(&type_data, 0, sizeof (type_data));
 892
 893         type_data.ertd_es_super_buffer.eessb_bufs_per_desc = n_bufs_per_desc;
 894         type_data.ertd_es_super_buffer.eessb_max_dma_len = max_dma_len;
 895         type_data.ertd_es_super_buffer.eessb_buf_stride = buf_stride;
 896         type_data.ertd_es_super_buffer.eessb_hol_block_timeout =
 897             hol_block_timeout;
 898
 899         rc = efx_rx_qcreate_internal(enp, index, label,
 900             EFX_RXQ_TYPE_ES_SUPER_BUFFER, &type_data, esmp, ndescs,
 901             0 /* id unused on EF10 */, flags, eep, erpp);
 902         if (rc != 0)
 903                 goto fail2;
 904
 905         return (0);
 906
 907 fail2:
 908         EFSYS_PROBE(fail2);
 909 fail1:
 910         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 911
 912         return (rc);
 913 }
 914
 915 #endif
 916
 917
 918                         void
 919 efx_rx_qdestroy(
 920         __in            efx_rxq_t *erp)
 921 {
 922         efx_nic_t *enp = erp->er_enp;
 923         const efx_rx_ops_t *erxop = enp->en_erxop;
 924
 925         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 926
 927         erxop->erxo_qdestroy(erp);
 928 }
 929
 930         __checkReturn   efx_rc_t
 931 efx_pseudo_hdr_pkt_length_get(
 932         __in            efx_rxq_t *erp,
 933         __in            uint8_t *buffer,
 934         __out           uint16_t *lengthp)
 935 {
 936         efx_nic_t *enp = erp->er_enp;
 937         const efx_rx_ops_t *erxop = enp->en_erxop;
 938
 939         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 940
 941         return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp));
 942 }
 943
 944 #if EFSYS_OPT_RX_SCALE
 945         __checkReturn   uint32_t
 946 efx_pseudo_hdr_hash_get(
 947         __in            efx_rxq_t *erp,
 948         __in            efx_rx_hash_alg_t func,
 949         __in            uint8_t *buffer)
 950 {
 951         efx_nic_t *enp = erp->er_enp;
 952         const efx_rx_ops_t *erxop = enp->en_erxop;
 953
 954         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 955
 956         EFSYS_ASSERT3U(enp->en_hash_support, ==, EFX_RX_HASH_AVAILABLE);
 957         return (erxop->erxo_prefix_hash(enp, func, buffer));
 958 }
 959 #endif  /* EFSYS_OPT_RX_SCALE */
 960
 961 #if EFSYS_OPT_SIENA
 962
 963 static  __checkReturn   efx_rc_t
 964 siena_rx_init(
 965         __in            efx_nic_t *enp)
 966 {
 967         efx_oword_t oword;
 968         unsigned int index;
 969
 970         EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
 971
 972         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0);
 973         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);
 974         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);
 975         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);
 976         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0);
 977         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32);
 978         EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
 979
 980         /* Zero the RSS table */
 981         for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS;
 982             index++) {
 983                 EFX_ZERO_OWORD(oword);
 984                 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
 985                                     index, &oword, B_TRUE);
 986         }
 987
 988 #if EFSYS_OPT_RX_SCALE
 989         /* The RSS key and indirection table are writable. */
 990         enp->en_rss_context_type = EFX_RX_SCALE_EXCLUSIVE;
 991
 992         /* Hardware can insert RX hash with/without RSS */
 993         enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
 994 #endif  /* EFSYS_OPT_RX_SCALE */
 995
 996         return (0);
 997 }
 998
 999 #if EFSYS_OPT_RX_SCATTER
1000 static  __checkReturn   efx_rc_t
1001 siena_rx_scatter_enable(
1002         __in            efx_nic_t *enp,
1003         __in            unsigned int buf_size)
1004 {
1005         unsigned int nbuf32;
1006         efx_oword_t oword;
1007         efx_rc_t rc;
1008
1009         nbuf32 = buf_size / 32;
1010         if ((nbuf32 == 0) ||
1011             (nbuf32 >= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH)) ||
1012             ((buf_size % 32) != 0)) {
1013                 rc = EINVAL;
1014                 goto fail1;
1015         }
1016
1017         if (enp->en_rx_qcount > 0) {
1018                 rc = EBUSY;
1019                 goto fail2;
1020         }
1021
1022         /* Set scatter buffer size */
1023         EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
1024         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, nbuf32);
1025         EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
1026
1027         /* Enable scatter for packets not matching a filter */
1028         EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
1029         EFX_SET_OWORD_FIELD(oword, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, 1);
1030         EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
1031
1032         return (0);
1033
1034 fail2:
1035         EFSYS_PROBE(fail2);
1036 fail1:
1037         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1038
1039         return (rc);
1040 }
1041 #endif  /* EFSYS_OPT_RX_SCATTER */
1042
1043
1044 #define EFX_RX_LFSR_HASH(_enp, _insert)                                 \
1045         do {                                                            \
1046                 efx_oword_t oword;                                      \
1047                                                                         \
1048                 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword);        \
1049                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);      \
1050                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);       \
1051                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);       \
1052                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR,    \
1053                     (_insert) ? 1 : 0);                                 \
1054                 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword);       \
1055                                                                         \
1056                 if ((_enp)->en_family == EFX_FAMILY_SIENA) {            \
1057                         EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3,   \
1058                             &oword);                                    \
1059                         EFX_SET_OWORD_FIELD(oword,                      \
1060                             FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0);        \
1061                         EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3,  \
1062                             &oword);                                    \
1063                 }                                                       \
1064                                                                         \
1065                 _NOTE(CONSTANTCONDITION)                                \
1066         } while (B_FALSE)
1067
1068 #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp)             \
1069         do {                                                            \
1070                 efx_oword_t oword;                                      \
1071                                                                         \
1072                 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword);        \
1073                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1);      \
1074                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH,           \
1075                     (_ip) ? 1 : 0);                                     \
1076                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP,           \
1077                     (_tcp) ? 0 : 1);                                    \
1078                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR,    \
1079                     (_insert) ? 1 : 0);                                 \
1080                 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword);       \
1081                                                                         \
1082                 _NOTE(CONSTANTCONDITION)                                \
1083         } while (B_FALSE)
1084
1085 #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc)                 \
1086         do {                                                            \
1087                 efx_oword_t oword;                                      \
1088                                                                         \
1089                 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword);  \
1090                 EFX_SET_OWORD_FIELD(oword,                              \
1091                     FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1);                \
1092                 EFX_SET_OWORD_FIELD(oword,                              \
1093                     FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \
1094                 EFX_SET_OWORD_FIELD(oword,                              \
1095                     FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1);   \
1096                 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
1097                                                                         \
1098                 (_rc) = 0;                                              \
1099                                                                         \
1100                 _NOTE(CONSTANTCONDITION)                                \
1101         } while (B_FALSE)
1102
1103
1104 #if EFSYS_OPT_RX_SCALE
1105
1106 static  __checkReturn   efx_rc_t
1107 siena_rx_scale_mode_set(
1108         __in            efx_nic_t *enp,
1109         __in            uint32_t rss_context,
1110         __in            efx_rx_hash_alg_t alg,
1111         __in            efx_rx_hash_type_t type,
1112         __in            boolean_t insert)
1113 {
1114         efx_rx_hash_type_t type_ipv4 = EFX_RX_HASH(IPV4, 2TUPLE);
1115         efx_rx_hash_type_t type_ipv4_tcp = EFX_RX_HASH(IPV4_TCP, 4TUPLE);
1116         efx_rx_hash_type_t type_ipv6 = EFX_RX_HASH(IPV6, 2TUPLE);
1117         efx_rx_hash_type_t type_ipv6_tcp = EFX_RX_HASH(IPV6_TCP, 4TUPLE);
1118         efx_rc_t rc;
1119
1120         if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1121                 rc = EINVAL;
1122                 goto fail1;
1123         }
1124
1125         switch (alg) {
1126         case EFX_RX_HASHALG_LFSR:
1127                 EFX_RX_LFSR_HASH(enp, insert);
1128                 break;
1129
1130         case EFX_RX_HASHALG_TOEPLITZ:
1131                 EFX_RX_TOEPLITZ_IPV4_HASH(enp, insert,
1132                     (type & type_ipv4) == type_ipv4,
1133                     (type & type_ipv4_tcp) == type_ipv4_tcp);
1134
1135                 EFX_RX_TOEPLITZ_IPV6_HASH(enp,
1136                     (type & type_ipv6) == type_ipv6,
1137                     (type & type_ipv6_tcp) == type_ipv6_tcp,
1138                     rc);
1139                 if (rc != 0)
1140                         goto fail2;
1141
1142                 break;
1143
1144         default:
1145                 rc = EINVAL;
1146                 goto fail3;
1147         }
1148
1149         return (0);
1150
1151 fail3:
1152         EFSYS_PROBE(fail3);
1153 fail2:
1154         EFSYS_PROBE(fail2);
1155 fail1:
1156         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1157
1158         EFX_RX_LFSR_HASH(enp, B_FALSE);
1159
1160         return (rc);
1161 }
1162 #endif
1163
1164 #if EFSYS_OPT_RX_SCALE
1165 static  __checkReturn   efx_rc_t
1166 siena_rx_scale_key_set(
1167         __in            efx_nic_t *enp,
1168         __in            uint32_t rss_context,
1169         __in_ecount(n)  uint8_t *key,
1170         __in            size_t n)
1171 {
1172         efx_oword_t oword;
1173         unsigned int byte;
1174         unsigned int offset;
1175         efx_rc_t rc;
1176
1177         if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1178                 rc = EINVAL;
1179                 goto fail1;
1180         }
1181
1182         byte = 0;
1183
1184         /* Write Toeplitz IPv4 hash key */
1185         EFX_ZERO_OWORD(oword);
1186         for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
1187             offset > 0 && byte < n;
1188             --offset)
1189                 oword.eo_u8[offset - 1] = key[byte++];
1190
1191         EFX_BAR_WRITEO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
1192
1193         byte = 0;
1194
1195         /* Verify Toeplitz IPv4 hash key */
1196         EFX_BAR_READO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
1197         for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
1198             offset > 0 && byte < n;
1199             --offset) {
1200                 if (oword.eo_u8[offset - 1] != key[byte++]) {
1201                         rc = EFAULT;
1202                         goto fail2;
1203                 }
1204         }
1205
1206         if ((enp->en_features & EFX_FEATURE_IPV6) == 0)
1207                 goto done;
1208
1209         byte = 0;
1210
1211         /* Write Toeplitz IPv6 hash key 3 */
1212         EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1213         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
1214             FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
1215             offset > 0 && byte < n;
1216             --offset)
1217                 oword.eo_u8[offset - 1] = key[byte++];
1218
1219         EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1220
1221         /* Write Toeplitz IPv6 hash key 2 */
1222         EFX_ZERO_OWORD(oword);
1223         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1224             FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1225             offset > 0 && byte < n;
1226             --offset)
1227                 oword.eo_u8[offset - 1] = key[byte++];
1228
1229         EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1230
1231         /* Write Toeplitz IPv6 hash key 1 */
1232         EFX_ZERO_OWORD(oword);
1233         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1234             FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1235             offset > 0 && byte < n;
1236             --offset)
1237                 oword.eo_u8[offset - 1] = key[byte++];
1238
1239         EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1240
1241         byte = 0;
1242
1243         /* Verify Toeplitz IPv6 hash key 3 */
1244         EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1245         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
1246             FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
1247             offset > 0 && byte < n;
1248             --offset) {
1249                 if (oword.eo_u8[offset - 1] != key[byte++]) {
1250                         rc = EFAULT;
1251                         goto fail3;
1252                 }
1253         }
1254
1255         /* Verify Toeplitz IPv6 hash key 2 */
1256         EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1257         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1258             FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1259             offset > 0 && byte < n;
1260             --offset) {
1261                 if (oword.eo_u8[offset - 1] != key[byte++]) {
1262                         rc = EFAULT;
1263                         goto fail4;
1264                 }
1265         }
1266
1267         /* Verify Toeplitz IPv6 hash key 1 */
1268         EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1269         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1270             FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1271             offset > 0 && byte < n;
1272             --offset) {
1273                 if (oword.eo_u8[offset - 1] != key[byte++]) {
1274                         rc = EFAULT;
1275                         goto fail5;
1276                 }
1277         }
1278
1279 done:
1280         return (0);
1281
1282 fail5:
1283         EFSYS_PROBE(fail5);
1284 fail4:
1285         EFSYS_PROBE(fail4);
1286 fail3:
1287         EFSYS_PROBE(fail3);
1288 fail2:
1289         EFSYS_PROBE(fail2);
1290 fail1:
1291         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1292
1293         return (rc);
1294 }
1295 #endif
1296
1297 #if EFSYS_OPT_RX_SCALE
1298 static  __checkReturn   efx_rc_t
1299 siena_rx_scale_tbl_set(
1300         __in            efx_nic_t *enp,
1301         __in            uint32_t rss_context,
1302         __in_ecount(n)  unsigned int *table,
1303         __in            size_t n)
1304 {
1305         efx_oword_t oword;
1306         int index;
1307         efx_rc_t rc;
1308
1309         EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS);
1310         EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH));
1311
1312         if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1313                 rc = EINVAL;
1314                 goto fail1;
1315         }
1316
1317         if (n > FR_BZ_RX_INDIRECTION_TBL_ROWS) {
1318                 rc = EINVAL;
1319                 goto fail2;
1320         }
1321
1322         for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; index++) {
1323                 uint32_t byte;
1324
1325                 /* Calculate the entry to place in the table */
1326                 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1327
1328                 EFSYS_PROBE2(table, int, index, uint32_t, byte);
1329
1330                 EFX_POPULATE_OWORD_1(oword, FRF_BZ_IT_QUEUE, byte);
1331
1332                 /* Write the table */
1333                 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
1334                                     index, &oword, B_TRUE);
1335         }
1336
1337         for (index = FR_BZ_RX_INDIRECTION_TBL_ROWS - 1; index >= 0; --index) {
1338                 uint32_t byte;
1339
1340                 /* Determine if we're starting a new batch */
1341                 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1342
1343                 /* Read the table */
1344                 EFX_BAR_TBL_READO(enp, FR_BZ_RX_INDIRECTION_TBL,
1345                                     index, &oword, B_TRUE);
1346
1347                 /* Verify the entry */
1348                 if (EFX_OWORD_FIELD(oword, FRF_BZ_IT_QUEUE) != byte) {
1349                         rc = EFAULT;
1350                         goto fail3;
1351                 }
1352         }
1353
1354         return (0);
1355
1356 fail3:
1357         EFSYS_PROBE(fail3);
1358 fail2:
1359         EFSYS_PROBE(fail2);
1360 fail1:
1361         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1362
1363         return (rc);
1364 }
1365 #endif
1366
1367 /*
1368  * Falcon/Siena pseudo-header
1369  * --------------------------
1370  *
1371  * Receive packets are prefixed by an optional 16 byte pseudo-header.
1372  * The pseudo-header is a byte array of one of the forms:
1373  *
1374  *  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15
1375  * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT
1376  * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL
1377  *
1378  * where:
1379  *   TT.TT.TT.TT   Toeplitz hash (32-bit big-endian)
1380  *   LL.LL         LFSR hash     (16-bit big-endian)
1381  */
1382
1383 #if EFSYS_OPT_RX_SCALE
1384 static  __checkReturn   uint32_t
1385 siena_rx_prefix_hash(
1386         __in            efx_nic_t *enp,
1387         __in            efx_rx_hash_alg_t func,
1388         __in            uint8_t *buffer)
1389 {
1390         _NOTE(ARGUNUSED(enp))
1391
1392         switch (func) {
1393         case EFX_RX_HASHALG_TOEPLITZ:
1394                 return ((buffer[12] << 24) |
1395                     (buffer[13] << 16) |
1396                     (buffer[14] <<  8) |
1397                     buffer[15]);
1398
1399         case EFX_RX_HASHALG_LFSR:
1400                 return ((buffer[14] << 8) | buffer[15]);
1401
1402         default:
1403                 EFSYS_ASSERT(0);
1404                 return (0);
1405         }
1406 }
1407 #endif /* EFSYS_OPT_RX_SCALE */
1408
1409 static  __checkReturn   efx_rc_t
1410 siena_rx_prefix_pktlen(
1411         __in            efx_nic_t *enp,
1412         __in            uint8_t *buffer,
1413         __out           uint16_t *lengthp)
1414 {
1415         _NOTE(ARGUNUSED(enp, buffer, lengthp))
1416
1417         /* Not supported by Falcon/Siena hardware */
1418         EFSYS_ASSERT(0);
1419         return (ENOTSUP);
1420 }
1421
1422
1423 static                          void
1424 siena_rx_qpost(
1425         __in                    efx_rxq_t *erp,
1426         __in_ecount(ndescs)     efsys_dma_addr_t *addrp,
1427         __in                    size_t size,
1428         __in                    unsigned int ndescs,
1429         __in                    unsigned int completed,
1430         __in                    unsigned int added)
1431 {
1432         efx_qword_t qword;
1433         unsigned int i;
1434         unsigned int offset;
1435         unsigned int id;
1436
1437         /* The client driver must not overfill the queue */
1438         EFSYS_ASSERT3U(added - completed + ndescs, <=,
1439             EFX_RXQ_LIMIT(erp->er_mask + 1));
1440
1441         id = added & (erp->er_mask);
1442         for (i = 0; i < ndescs; i++) {
1443                 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
1444                     unsigned int, id, efsys_dma_addr_t, addrp[i],
1445                     size_t, size);
1446
1447                 EFX_POPULATE_QWORD_3(qword,
1448                     FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size),
1449                     FSF_AZ_RX_KER_BUF_ADDR_DW0,
1450                     (uint32_t)(addrp[i] & 0xffffffff),
1451                     FSF_AZ_RX_KER_BUF_ADDR_DW1,
1452                     (uint32_t)(addrp[i] >> 32));
1453
1454                 offset = id * sizeof (efx_qword_t);
1455                 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
1456
1457                 id = (id + 1) & (erp->er_mask);
1458         }
1459 }
1460
1461 static                  void
1462 siena_rx_qpush(
1463         __in    efx_rxq_t *erp,
1464         __in    unsigned int added,
1465         __inout unsigned int *pushedp)
1466 {
1467         efx_nic_t *enp = erp->er_enp;
1468         unsigned int pushed = *pushedp;
1469         uint32_t wptr;
1470         efx_oword_t oword;
1471         efx_dword_t dword;
1472
1473         /* All descriptors are pushed */
1474         *pushedp = added;
1475
1476         /* Push the populated descriptors out */
1477         wptr = added & erp->er_mask;
1478
1479         EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr);
1480
1481         /* Only write the third DWORD */
1482         EFX_POPULATE_DWORD_1(dword,
1483             EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
1484
1485         /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
1486         EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
1487             wptr, pushed & erp->er_mask);
1488         EFSYS_PIO_WRITE_BARRIER();
1489         EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,
1490                             erp->er_index, &dword, B_FALSE);
1491 }
1492
1493 #if EFSYS_OPT_RX_PACKED_STREAM
1494 static          void
1495 siena_rx_qpush_ps_credits(
1496         __in            efx_rxq_t *erp)
1497 {
1498         /* Not supported by Siena hardware */
1499         EFSYS_ASSERT(0);
1500 }
1501
1502 static          uint8_t *
1503 siena_rx_qps_packet_info(
1504         __in            efx_rxq_t *erp,
1505         __in            uint8_t *buffer,
1506         __in            uint32_t buffer_length,
1507         __in            uint32_t current_offset,
1508         __out           uint16_t *lengthp,
1509         __out           uint32_t *next_offsetp,
1510         __out           uint32_t *timestamp)
1511 {
1512         /* Not supported by Siena hardware */
1513         EFSYS_ASSERT(0);
1514
1515         return (NULL);
1516 }
1517 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1518
1519 static  __checkReturn   efx_rc_t
1520 siena_rx_qflush(
1521         __in    efx_rxq_t *erp)
1522 {
1523         efx_nic_t *enp = erp->er_enp;
1524         efx_oword_t oword;
1525         uint32_t label;
1526
1527         label = erp->er_index;
1528
1529         /* Flush the queue */
1530         EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
1531             FRF_AZ_RX_FLUSH_DESCQ, label);
1532         EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword);
1533
1534         return (0);
1535 }
1536
1537 static          void
1538 siena_rx_qenable(
1539         __in    efx_rxq_t *erp)
1540 {
1541         efx_nic_t *enp = erp->er_enp;
1542         efx_oword_t oword;
1543
1544         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
1545
1546         EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL,
1547                             erp->er_index, &oword, B_TRUE);
1548
1549         EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0);
1550         EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0);
1551         EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1);
1552
1553         EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1554                             erp->er_index, &oword, B_TRUE);
1555 }
1556
1557 static  __checkReturn   efx_rc_t
1558 siena_rx_qcreate(
1559         __in            efx_nic_t *enp,
1560         __in            unsigned int index,
1561         __in            unsigned int label,
1562         __in            efx_rxq_type_t type,
1563         __in            const efx_rxq_type_data_t *type_data,
1564         __in            efsys_mem_t *esmp,
1565         __in            size_t ndescs,
1566         __in            uint32_t id,
1567         __in            unsigned int flags,
1568         __in            efx_evq_t *eep,
1569         __in            efx_rxq_t *erp)
1570 {
1571         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1572         efx_oword_t oword;
1573         uint32_t size;
1574         boolean_t jumbo = B_FALSE;
1575         efx_rc_t rc;
1576
1577         _NOTE(ARGUNUSED(esmp))
1578         _NOTE(ARGUNUSED(type_data))
1579
1580         EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
1581             (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH));
1582         EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1583         EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
1584
1585         EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
1586         EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
1587
1588         if (!ISP2(ndescs) ||
1589             (ndescs < EFX_RXQ_MINNDESCS) || (ndescs > EFX_RXQ_MAXNDESCS)) {
1590                 rc = EINVAL;
1591                 goto fail1;
1592         }
1593         if (index >= encp->enc_rxq_limit) {
1594                 rc = EINVAL;
1595                 goto fail2;
1596         }
1597         for (size = 0; (1 << size) <= (EFX_RXQ_MAXNDESCS / EFX_RXQ_MINNDESCS);
1598             size++)
1599                 if ((1 << size) == (int)(ndescs / EFX_RXQ_MINNDESCS))
1600                         break;
1601         if (id + (1 << size) >= encp->enc_buftbl_limit) {
1602                 rc = EINVAL;
1603                 goto fail3;
1604         }
1605
1606         switch (type) {
1607         case EFX_RXQ_TYPE_DEFAULT:
1608                 break;
1609
1610         default:
1611                 rc = EINVAL;
1612                 goto fail4;
1613         }
1614
1615         if (flags & EFX_RXQ_FLAG_SCATTER) {
1616 #if EFSYS_OPT_RX_SCATTER
1617                 jumbo = B_TRUE;
1618 #else
1619                 rc = EINVAL;
1620                 goto fail5;
1621 #endif  /* EFSYS_OPT_RX_SCATTER */
1622         }
1623
1624         /* Set up the new descriptor queue */
1625         EFX_POPULATE_OWORD_7(oword,
1626             FRF_AZ_RX_DESCQ_BUF_BASE_ID, id,
1627             FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index,
1628             FRF_AZ_RX_DESCQ_OWNER_ID, 0,
1629             FRF_AZ_RX_DESCQ_LABEL, label,
1630             FRF_AZ_RX_DESCQ_SIZE, size,
1631             FRF_AZ_RX_DESCQ_TYPE, 0,
1632             FRF_AZ_RX_DESCQ_JUMBO, jumbo);
1633
1634         EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1635                             erp->er_index, &oword, B_TRUE);
1636
1637         return (0);
1638
1639 #if !EFSYS_OPT_RX_SCATTER
1640 fail5:
1641         EFSYS_PROBE(fail5);
1642 #endif
1643 fail4:
1644         EFSYS_PROBE(fail4);
1645 fail3:
1646         EFSYS_PROBE(fail3);
1647 fail2:
1648         EFSYS_PROBE(fail2);
1649 fail1:
1650         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1651
1652         return (rc);
1653 }
1654
1655 static          void
1656 siena_rx_qdestroy(
1657         __in    efx_rxq_t *erp)
1658 {
1659         efx_nic_t *enp = erp->er_enp;
1660         efx_oword_t oword;
1661
1662         EFSYS_ASSERT(enp->en_rx_qcount != 0);
1663         --enp->en_rx_qcount;
1664
1665         /* Purge descriptor queue */
1666         EFX_ZERO_OWORD(oword);
1667
1668         EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1669                             erp->er_index, &oword, B_TRUE);
1670
1671         /* Free the RXQ object */
1672         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1673 }
1674
1675 static          void
1676 siena_rx_fini(
1677         __in    efx_nic_t *enp)
1678 {
1679         _NOTE(ARGUNUSED(enp))
1680 }
1681
1682 #endif /* EFSYS_OPT_SIENA */