2 * Copyright (c) 2009-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
38 __in uint32_t mcdi_cap,
39 __out uint32_t *maskp)
44 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10HDX_LBN))
45 mask |= (1 << EFX_PHY_CAP_10HDX);
46 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10FDX_LBN))
47 mask |= (1 << EFX_PHY_CAP_10FDX);
48 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100HDX_LBN))
49 mask |= (1 << EFX_PHY_CAP_100HDX);
50 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100FDX_LBN))
51 mask |= (1 << EFX_PHY_CAP_100FDX);
52 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000HDX_LBN))
53 mask |= (1 << EFX_PHY_CAP_1000HDX);
54 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000FDX_LBN))
55 mask |= (1 << EFX_PHY_CAP_1000FDX);
56 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10000FDX_LBN))
57 mask |= (1 << EFX_PHY_CAP_10000FDX);
58 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_PAUSE_LBN))
59 mask |= (1 << EFX_PHY_CAP_PAUSE);
60 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_ASYM_LBN))
61 mask |= (1 << EFX_PHY_CAP_ASYM);
62 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_AN_LBN))
63 mask |= (1 << EFX_PHY_CAP_AN);
69 siena_phy_decode_link_mode(
71 __in uint32_t link_flags,
72 __in unsigned int speed,
73 __in unsigned int fcntl,
74 __out efx_link_mode_t *link_modep,
75 __out unsigned int *fcntlp)
77 boolean_t fd = !!(link_flags &
78 (1 << MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN));
79 boolean_t up = !!(link_flags &
80 (1 << MC_CMD_GET_LINK_OUT_LINK_UP_LBN));
85 *link_modep = EFX_LINK_DOWN;
86 else if (speed == 10000 && fd)
87 *link_modep = EFX_LINK_10000FDX;
88 else if (speed == 1000)
89 *link_modep = fd ? EFX_LINK_1000FDX : EFX_LINK_1000HDX;
90 else if (speed == 100)
91 *link_modep = fd ? EFX_LINK_100FDX : EFX_LINK_100HDX;
93 *link_modep = fd ? EFX_LINK_10FDX : EFX_LINK_10HDX;
95 *link_modep = EFX_LINK_UNKNOWN;
97 if (fcntl == MC_CMD_FCNTL_OFF)
99 else if (fcntl == MC_CMD_FCNTL_RESPOND)
100 *fcntlp = EFX_FCNTL_RESPOND;
101 else if (fcntl == MC_CMD_FCNTL_BIDIR)
102 *fcntlp = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE;
104 EFSYS_PROBE1(mc_pcol_error, int, fcntl);
112 __in efx_qword_t *eqp,
113 __out efx_link_mode_t *link_modep)
115 efx_port_t *epp = &(enp->en_port);
116 unsigned int link_flags;
119 efx_link_mode_t link_mode;
120 uint32_t lp_cap_mask;
123 * Convert the LINKCHANGE speed enumeration into mbit/s, in the
124 * same way as GET_LINK encodes the speed
126 switch (MCDI_EV_FIELD(eqp, LINKCHANGE_SPEED)) {
127 case MCDI_EVENT_LINKCHANGE_SPEED_100M:
130 case MCDI_EVENT_LINKCHANGE_SPEED_1G:
133 case MCDI_EVENT_LINKCHANGE_SPEED_10G:
141 link_flags = MCDI_EV_FIELD(eqp, LINKCHANGE_LINK_FLAGS);
142 siena_phy_decode_link_mode(enp, link_flags, speed,
143 MCDI_EV_FIELD(eqp, LINKCHANGE_FCNTL),
145 siena_phy_decode_cap(MCDI_EV_FIELD(eqp, LINKCHANGE_LP_CAP),
149 * It's safe to update ep_lp_cap_mask without the driver's port lock
150 * because presumably any concurrently running efx_port_poll() is
151 * only going to arrive at the same value.
153 * ep_fcntl has two meanings. It's either the link common fcntl
154 * (if the PHY supports AN), or it's the forced link state. If
155 * the former, it's safe to update the value for the same reason as
156 * for ep_lp_cap_mask. If the latter, then just ignore the value,
157 * because we can race with efx_mac_fcntl_set().
159 epp->ep_lp_cap_mask = lp_cap_mask;
160 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_AN))
161 epp->ep_fcntl = fcntl;
163 *link_modep = link_mode;
166 __checkReturn efx_rc_t
169 __in boolean_t power)
176 /* Check if the PHY is a zombie */
177 if ((rc = siena_phy_verify(enp)) != 0)
180 enp->en_reset_flags |= EFX_RESET_PHY;
185 EFSYS_PROBE1(fail1, efx_rc_t, rc);
190 __checkReturn efx_rc_t
193 __out siena_link_state_t *slsp)
196 uint8_t payload[MAX(MC_CMD_GET_LINK_IN_LEN,
197 MC_CMD_GET_LINK_OUT_LEN)];
200 (void) memset(payload, 0, sizeof (payload));
201 req.emr_cmd = MC_CMD_GET_LINK;
202 req.emr_in_buf = payload;
203 req.emr_in_length = MC_CMD_GET_LINK_IN_LEN;
204 req.emr_out_buf = payload;
205 req.emr_out_length = MC_CMD_GET_LINK_OUT_LEN;
207 efx_mcdi_execute(enp, &req);
209 if (req.emr_rc != 0) {
214 if (req.emr_out_length_used < MC_CMD_GET_LINK_OUT_LEN) {
219 siena_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_CAP),
220 &slsp->sls_adv_cap_mask);
221 siena_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_LP_CAP),
222 &slsp->sls_lp_cap_mask);
224 siena_phy_decode_link_mode(enp, MCDI_OUT_DWORD(req, GET_LINK_OUT_FLAGS),
225 MCDI_OUT_DWORD(req, GET_LINK_OUT_LINK_SPEED),
226 MCDI_OUT_DWORD(req, GET_LINK_OUT_FCNTL),
227 &slsp->sls_link_mode, &slsp->sls_fcntl);
229 #if EFSYS_OPT_LOOPBACK
230 /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespace agree */
231 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_NONE == EFX_LOOPBACK_OFF);
232 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_DATA == EFX_LOOPBACK_DATA);
233 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMAC == EFX_LOOPBACK_GMAC);
234 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII == EFX_LOOPBACK_XGMII);
235 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGXS == EFX_LOOPBACK_XGXS);
236 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI == EFX_LOOPBACK_XAUI);
237 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII == EFX_LOOPBACK_GMII);
238 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII == EFX_LOOPBACK_SGMII);
239 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGBR == EFX_LOOPBACK_XGBR);
240 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI == EFX_LOOPBACK_XFI);
241 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_FAR == EFX_LOOPBACK_XAUI_FAR);
242 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII_FAR == EFX_LOOPBACK_GMII_FAR);
243 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII_FAR == EFX_LOOPBACK_SGMII_FAR);
244 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_FAR == EFX_LOOPBACK_XFI_FAR);
245 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GPHY == EFX_LOOPBACK_GPHY);
246 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PHYXS == EFX_LOOPBACK_PHY_XS);
247 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PCS == EFX_LOOPBACK_PCS);
248 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMAPMD == EFX_LOOPBACK_PMA_PMD);
250 slsp->sls_loopback = MCDI_OUT_DWORD(req, GET_LINK_OUT_LOOPBACK_MODE);
251 #endif /* EFSYS_OPT_LOOPBACK */
253 slsp->sls_mac_up = MCDI_OUT_DWORD(req, GET_LINK_OUT_MAC_FAULT) == 0;
260 EFSYS_PROBE1(fail1, efx_rc_t, rc);
265 __checkReturn efx_rc_t
266 siena_phy_reconfigure(
269 efx_port_t *epp = &(enp->en_port);
271 uint8_t payload[MAX(MAX(MC_CMD_SET_ID_LED_IN_LEN,
272 MC_CMD_SET_ID_LED_OUT_LEN),
273 MAX(MC_CMD_SET_LINK_IN_LEN,
274 MC_CMD_SET_LINK_OUT_LEN))];
276 #if EFSYS_OPT_PHY_LED_CONTROL
277 unsigned int led_mode;
282 (void) memset(payload, 0, sizeof (payload));
283 req.emr_cmd = MC_CMD_SET_LINK;
284 req.emr_in_buf = payload;
285 req.emr_in_length = MC_CMD_SET_LINK_IN_LEN;
286 req.emr_out_buf = payload;
287 req.emr_out_length = MC_CMD_SET_LINK_OUT_LEN;
289 cap_mask = epp->ep_adv_cap_mask;
290 MCDI_IN_POPULATE_DWORD_10(req, SET_LINK_IN_CAP,
291 PHY_CAP_10HDX, (cap_mask >> EFX_PHY_CAP_10HDX) & 0x1,
292 PHY_CAP_10FDX, (cap_mask >> EFX_PHY_CAP_10FDX) & 0x1,
293 PHY_CAP_100HDX, (cap_mask >> EFX_PHY_CAP_100HDX) & 0x1,
294 PHY_CAP_100FDX, (cap_mask >> EFX_PHY_CAP_100FDX) & 0x1,
295 PHY_CAP_1000HDX, (cap_mask >> EFX_PHY_CAP_1000HDX) & 0x1,
296 PHY_CAP_1000FDX, (cap_mask >> EFX_PHY_CAP_1000FDX) & 0x1,
297 PHY_CAP_10000FDX, (cap_mask >> EFX_PHY_CAP_10000FDX) & 0x1,
298 PHY_CAP_PAUSE, (cap_mask >> EFX_PHY_CAP_PAUSE) & 0x1,
299 PHY_CAP_ASYM, (cap_mask >> EFX_PHY_CAP_ASYM) & 0x1,
300 PHY_CAP_AN, (cap_mask >> EFX_PHY_CAP_AN) & 0x1);
302 #if EFSYS_OPT_LOOPBACK
303 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE,
304 epp->ep_loopback_type);
305 switch (epp->ep_loopback_link_mode) {
306 case EFX_LINK_100FDX:
309 case EFX_LINK_1000FDX:
312 case EFX_LINK_10000FDX:
319 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE, MC_CMD_LOOPBACK_NONE);
321 #endif /* EFSYS_OPT_LOOPBACK */
322 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_SPEED, speed);
324 #if EFSYS_OPT_PHY_FLAGS
325 MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, epp->ep_phy_flags);
327 MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, 0);
328 #endif /* EFSYS_OPT_PHY_FLAGS */
330 efx_mcdi_execute(enp, &req);
332 if (req.emr_rc != 0) {
337 /* And set the blink mode */
338 (void) memset(payload, 0, sizeof (payload));
339 req.emr_cmd = MC_CMD_SET_ID_LED;
340 req.emr_in_buf = payload;
341 req.emr_in_length = MC_CMD_SET_ID_LED_IN_LEN;
342 req.emr_out_buf = payload;
343 req.emr_out_length = MC_CMD_SET_ID_LED_OUT_LEN;
345 #if EFSYS_OPT_PHY_LED_CONTROL
346 switch (epp->ep_phy_led_mode) {
347 case EFX_PHY_LED_DEFAULT:
348 led_mode = MC_CMD_LED_DEFAULT;
350 case EFX_PHY_LED_OFF:
351 led_mode = MC_CMD_LED_OFF;
354 led_mode = MC_CMD_LED_ON;
358 led_mode = MC_CMD_LED_DEFAULT;
361 MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, led_mode);
363 MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, MC_CMD_LED_DEFAULT);
364 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
366 efx_mcdi_execute(enp, &req);
368 if (req.emr_rc != 0) {
378 EFSYS_PROBE1(fail1, efx_rc_t, rc);
383 __checkReturn efx_rc_t
388 uint8_t payload[MAX(MC_CMD_GET_PHY_STATE_IN_LEN,
389 MC_CMD_GET_PHY_STATE_OUT_LEN)];
393 (void) memset(payload, 0, sizeof (payload));
394 req.emr_cmd = MC_CMD_GET_PHY_STATE;
395 req.emr_in_buf = payload;
396 req.emr_in_length = MC_CMD_GET_PHY_STATE_IN_LEN;
397 req.emr_out_buf = payload;
398 req.emr_out_length = MC_CMD_GET_PHY_STATE_OUT_LEN;
400 efx_mcdi_execute(enp, &req);
402 if (req.emr_rc != 0) {
407 if (req.emr_out_length_used < MC_CMD_GET_PHY_STATE_OUT_LEN) {
412 state = MCDI_OUT_DWORD(req, GET_PHY_STATE_OUT_STATE);
413 if (state != MC_CMD_PHY_STATE_OK) {
414 if (state != MC_CMD_PHY_STATE_ZOMBIE)
415 EFSYS_PROBE1(mc_pcol_error, int, state);
427 EFSYS_PROBE1(fail1, efx_rc_t, rc);
432 __checkReturn efx_rc_t
435 __out uint32_t *ouip)
437 _NOTE(ARGUNUSED(enp, ouip))
442 #if EFSYS_OPT_PHY_STATS
444 #define SIENA_SIMPLE_STAT_SET(_vmask, _esmp, _smask, _stat, \
445 _mc_record, _efx_record) \
446 if ((_vmask) & (1ULL << (_mc_record))) { \
447 (_smask) |= (1ULL << (_efx_record)); \
448 if ((_stat) != NULL && !EFSYS_MEM_IS_NULL(_esmp)) { \
450 EFSYS_MEM_READD(_esmp, (_mc_record) * 4, &dword);\
451 (_stat)[_efx_record] = \
452 EFX_DWORD_FIELD(dword, EFX_DWORD_0); \
456 #define SIENA_SIMPLE_STAT_SET2(_vmask, _esmp, _smask, _stat, _record) \
457 SIENA_SIMPLE_STAT_SET(_vmask, _esmp, _smask, _stat, \
458 MC_CMD_ ## _record, \
459 EFX_PHY_STAT_ ## _record)
462 siena_phy_decode_stats(
465 __in_opt efsys_mem_t *esmp,
466 __out_opt uint64_t *smaskp,
467 __inout_ecount_opt(EFX_PHY_NSTATS) uint32_t *stat)
471 _NOTE(ARGUNUSED(enp))
473 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, OUI);
474 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_LINK_UP);
475 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_RX_FAULT);
476 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_TX_FAULT);
478 if (vmask & (1 << MC_CMD_PMA_PMD_SIGNAL)) {
479 smask |= ((1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_A) |
480 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_B) |
481 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_C) |
482 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_D));
483 if (stat != NULL && esmp != NULL && !EFSYS_MEM_IS_NULL(esmp)) {
486 EFSYS_MEM_READD(esmp, 4 * MC_CMD_PMA_PMD_SIGNAL,
488 sig = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
489 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_A] = (sig >> 1) & 1;
490 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_B] = (sig >> 2) & 1;
491 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_C] = (sig >> 3) & 1;
492 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_D] = (sig >> 4) & 1;
496 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_A,
498 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_B,
500 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_C,
502 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_D,
505 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_LINK_UP);
506 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_RX_FAULT);
507 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_TX_FAULT);
508 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BER);
509 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BLOCK_ERRORS);
511 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_LINK_UP,
512 EFX_PHY_STAT_PHY_XS_LINK_UP);
513 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_RX_FAULT,
514 EFX_PHY_STAT_PHY_XS_RX_FAULT);
515 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_TX_FAULT,
516 EFX_PHY_STAT_PHY_XS_TX_FAULT);
517 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_ALIGN,
518 EFX_PHY_STAT_PHY_XS_ALIGN);
520 if (vmask & (1 << MC_CMD_PHYXS_SYNC)) {
521 smask |= ((1 << EFX_PHY_STAT_PHY_XS_SYNC_A) |
522 (1 << EFX_PHY_STAT_PHY_XS_SYNC_B) |
523 (1 << EFX_PHY_STAT_PHY_XS_SYNC_C) |
524 (1 << EFX_PHY_STAT_PHY_XS_SYNC_D));
525 if (stat != NULL && !EFSYS_MEM_IS_NULL(esmp)) {
528 EFSYS_MEM_READD(esmp, 4 * MC_CMD_PHYXS_SYNC, &dword);
529 sync = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
530 stat[EFX_PHY_STAT_PHY_XS_SYNC_A] = (sync >> 0) & 1;
531 stat[EFX_PHY_STAT_PHY_XS_SYNC_B] = (sync >> 1) & 1;
532 stat[EFX_PHY_STAT_PHY_XS_SYNC_C] = (sync >> 2) & 1;
533 stat[EFX_PHY_STAT_PHY_XS_SYNC_D] = (sync >> 3) & 1;
537 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_LINK_UP);
538 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_COMPLETE);
540 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_CL22_LINK_UP,
541 EFX_PHY_STAT_CL22EXT_LINK_UP);
547 __checkReturn efx_rc_t
548 siena_phy_stats_update(
550 __in efsys_mem_t *esmp,
551 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat)
553 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
554 uint32_t vmask = encp->enc_mcdi_phy_stat_mask;
557 uint8_t payload[MAX(MC_CMD_PHY_STATS_IN_LEN,
558 MC_CMD_PHY_STATS_OUT_DMA_LEN)];
561 (void) memset(payload, 0, sizeof (payload));
562 req.emr_cmd = MC_CMD_PHY_STATS;
563 req.emr_in_buf = payload;
564 req.emr_in_length = MC_CMD_PHY_STATS_IN_LEN;
565 req.emr_out_buf = payload;
566 req.emr_out_length = MC_CMD_PHY_STATS_OUT_DMA_LEN;
568 MCDI_IN_SET_DWORD(req, PHY_STATS_IN_DMA_ADDR_LO,
569 EFSYS_MEM_ADDR(esmp) & 0xffffffff);
570 MCDI_IN_SET_DWORD(req, PHY_STATS_IN_DMA_ADDR_HI,
571 EFSYS_MEM_ADDR(esmp) >> 32);
573 efx_mcdi_execute(enp, &req);
575 if (req.emr_rc != 0) {
579 EFSYS_ASSERT3U(req.emr_out_length, ==, MC_CMD_PHY_STATS_OUT_DMA_LEN);
581 siena_phy_decode_stats(enp, vmask, esmp, &smask, stat);
582 EFSYS_ASSERT(smask == encp->enc_phy_stat_mask);
587 EFSYS_PROBE1(fail1, efx_rc_t, rc);
592 #endif /* EFSYS_OPT_PHY_STATS */
596 __checkReturn efx_rc_t
597 siena_phy_bist_start(
599 __in efx_bist_type_t type)
603 if ((rc = efx_mcdi_bist_start(enp, type)) != 0)
609 EFSYS_PROBE1(fail1, efx_rc_t, rc);
614 static __checkReturn unsigned long
615 siena_phy_sft9001_bist_status(
619 case MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY:
620 return (EFX_PHY_CABLE_STATUS_BUSY);
621 case MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT:
622 return (EFX_PHY_CABLE_STATUS_INTERPAIRSHORT);
623 case MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT:
624 return (EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT);
625 case MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN:
626 return (EFX_PHY_CABLE_STATUS_OPEN);
627 case MC_CMD_POLL_BIST_SFT9001_PAIR_OK:
628 return (EFX_PHY_CABLE_STATUS_OK);
630 return (EFX_PHY_CABLE_STATUS_INVALID);
634 __checkReturn efx_rc_t
637 __in efx_bist_type_t type,
638 __out efx_bist_result_t *resultp,
639 __out_opt __drv_when(count > 0, __notnull)
640 uint32_t *value_maskp,
641 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
642 unsigned long *valuesp,
645 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
646 uint8_t payload[MAX(MC_CMD_POLL_BIST_IN_LEN,
647 MCDI_CTL_SDU_LEN_MAX)];
648 uint32_t value_mask = 0;
653 (void) memset(payload, 0, sizeof (payload));
654 req.emr_cmd = MC_CMD_POLL_BIST;
655 req.emr_in_buf = payload;
656 req.emr_in_length = MC_CMD_POLL_BIST_IN_LEN;
657 req.emr_out_buf = payload;
658 req.emr_out_length = MCDI_CTL_SDU_LEN_MAX;
660 efx_mcdi_execute(enp, &req);
662 if (req.emr_rc != 0) {
667 if (req.emr_out_length_used < MC_CMD_POLL_BIST_OUT_RESULT_OFST + 4) {
673 (void) memset(valuesp, '\0', count * sizeof (unsigned long));
675 result = MCDI_OUT_DWORD(req, POLL_BIST_OUT_RESULT);
677 /* Extract PHY specific results */
678 if (result == MC_CMD_POLL_BIST_PASSED &&
679 encp->enc_phy_type == EFX_PHY_SFT9001B &&
680 req.emr_out_length_used >= MC_CMD_POLL_BIST_OUT_SFT9001_LEN &&
681 (type == EFX_BIST_TYPE_PHY_CABLE_SHORT ||
682 type == EFX_BIST_TYPE_PHY_CABLE_LONG)) {
685 if (count > EFX_BIST_PHY_CABLE_LENGTH_A) {
687 valuesp[EFX_BIST_PHY_CABLE_LENGTH_A] =
689 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A);
690 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_A);
693 if (count > EFX_BIST_PHY_CABLE_LENGTH_B) {
695 valuesp[EFX_BIST_PHY_CABLE_LENGTH_B] =
697 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B);
698 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_B);
701 if (count > EFX_BIST_PHY_CABLE_LENGTH_C) {
703 valuesp[EFX_BIST_PHY_CABLE_LENGTH_C] =
705 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C);
706 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_C);
709 if (count > EFX_BIST_PHY_CABLE_LENGTH_D) {
711 valuesp[EFX_BIST_PHY_CABLE_LENGTH_D] =
713 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D);
714 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_D);
717 if (count > EFX_BIST_PHY_CABLE_STATUS_A) {
718 if (valuesp != NULL) {
719 word = MCDI_OUT_WORD(req,
720 POLL_BIST_OUT_SFT9001_CABLE_STATUS_A);
721 valuesp[EFX_BIST_PHY_CABLE_STATUS_A] =
722 siena_phy_sft9001_bist_status(word);
724 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_A);
727 if (count > EFX_BIST_PHY_CABLE_STATUS_B) {
728 if (valuesp != NULL) {
729 word = MCDI_OUT_WORD(req,
730 POLL_BIST_OUT_SFT9001_CABLE_STATUS_B);
731 valuesp[EFX_BIST_PHY_CABLE_STATUS_B] =
732 siena_phy_sft9001_bist_status(word);
734 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_B);
737 if (count > EFX_BIST_PHY_CABLE_STATUS_C) {
738 if (valuesp != NULL) {
739 word = MCDI_OUT_WORD(req,
740 POLL_BIST_OUT_SFT9001_CABLE_STATUS_C);
741 valuesp[EFX_BIST_PHY_CABLE_STATUS_C] =
742 siena_phy_sft9001_bist_status(word);
744 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_C);
747 if (count > EFX_BIST_PHY_CABLE_STATUS_D) {
748 if (valuesp != NULL) {
749 word = MCDI_OUT_WORD(req,
750 POLL_BIST_OUT_SFT9001_CABLE_STATUS_D);
751 valuesp[EFX_BIST_PHY_CABLE_STATUS_D] =
752 siena_phy_sft9001_bist_status(word);
754 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_D);
757 } else if (result == MC_CMD_POLL_BIST_FAILED &&
758 encp->enc_phy_type == EFX_PHY_QLX111V &&
759 req.emr_out_length >= MC_CMD_POLL_BIST_OUT_MRSFP_LEN &&
760 count > EFX_BIST_FAULT_CODE) {
762 valuesp[EFX_BIST_FAULT_CODE] =
763 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MRSFP_TEST);
764 value_mask |= 1 << EFX_BIST_FAULT_CODE;
767 if (value_maskp != NULL)
768 *value_maskp = value_mask;
770 EFSYS_ASSERT(resultp != NULL);
771 if (result == MC_CMD_POLL_BIST_RUNNING)
772 *resultp = EFX_BIST_RESULT_RUNNING;
773 else if (result == MC_CMD_POLL_BIST_PASSED)
774 *resultp = EFX_BIST_RESULT_PASSED;
776 *resultp = EFX_BIST_RESULT_FAILED;
783 EFSYS_PROBE1(fail1, efx_rc_t, rc);
791 __in efx_bist_type_t type)
793 /* There is no way to stop BIST on Siena */
794 _NOTE(ARGUNUSED(enp, type))
797 #endif /* EFSYS_OPT_BIST */
799 #endif /* EFSYS_OPT_SIENA */