1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2018 Solarflare Communications Inc.
6 * This software was jointly developed between OKTET Labs (under contract
7 * for Solarflare) and Solarflare Communications, Inc.
17 /* Number of events in one cache line */
18 #define SFC_EF10_EV_PER_CACHE_LINE \
19 (RTE_CACHE_LINE_SIZE / sizeof(efx_qword_t))
21 #define SFC_EF10_EV_QCLEAR_MASK (~(SFC_EF10_EV_PER_CACHE_LINE - 1))
23 #if defined(SFC_EF10_EV_QCLEAR_USE_EFX)
25 sfc_ef10_ev_qclear_cache_line(void *ptr)
27 efx_qword_t *entry = ptr;
30 for (i = 0; i < SFC_EF10_EV_PER_CACHE_LINE; ++i)
31 EFX_SET_QWORD(entry[i]);
35 * It is possible to do it using AVX2 and AVX512F, but it shows less
39 sfc_ef10_ev_qclear_cache_line(void *ptr)
41 const __m128i val = _mm_set1_epi64x(UINT64_MAX);
45 RTE_BUILD_BUG_ON(sizeof(val) > RTE_CACHE_LINE_SIZE);
46 RTE_BUILD_BUG_ON(RTE_CACHE_LINE_SIZE % sizeof(val) != 0);
48 for (i = 0; i < RTE_CACHE_LINE_SIZE / sizeof(val); ++i)
49 _mm_store_si128(&addr[i], val);
54 sfc_ef10_ev_qclear(efx_qword_t *hw_ring, unsigned int ptr_mask,
55 unsigned int old_read_ptr, unsigned int read_ptr)
57 const unsigned int clear_ptr = read_ptr & SFC_EF10_EV_QCLEAR_MASK;
58 unsigned int old_clear_ptr = old_read_ptr & SFC_EF10_EV_QCLEAR_MASK;
60 while (old_clear_ptr != clear_ptr) {
61 sfc_ef10_ev_qclear_cache_line(
62 &hw_ring[old_clear_ptr & ptr_mask]);
63 old_clear_ptr += SFC_EF10_EV_PER_CACHE_LINE;
68 * Functions which push doorbell should care about correct
69 * ordering: store instructions which fill in EvQ ring should be
70 * retired from CPU and DMA sync before doorbell which will allow
71 * to use these event entries.
76 sfc_ef10_ev_present(const efx_qword_t ev)
78 return ~EFX_QWORD_FIELD(ev, EFX_DWORD_0) |
79 ~EFX_QWORD_FIELD(ev, EFX_DWORD_1);
84 * Alignment requirement for value written to RX WPTR:
85 * the WPTR must be aligned to an 8 descriptor boundary.
87 #define SFC_EF10_RX_WPTR_ALIGN 8u
90 sfc_ef10_rx_qpush(volatile void *doorbell, unsigned int added,
91 unsigned int ptr_mask)
95 /* Hardware has alignment restriction for WPTR */
96 RTE_BUILD_BUG_ON(SFC_RX_REFILL_BULK % SFC_EF10_RX_WPTR_ALIGN != 0);
97 SFC_ASSERT(RTE_ALIGN(added, SFC_EF10_RX_WPTR_ALIGN) == added);
99 EFX_POPULATE_DWORD_1(dword, ERF_DZ_RX_DESC_WPTR, added & ptr_mask);
101 /* DMA sync to device is not required */
104 * rte_write32() has rte_io_wmb() which guarantees that the STORE
105 * operations (i.e. Rx and event descriptor updates) that precede
106 * the rte_io_wmb() call are visible to NIC before the STORE
107 * operations that follow it (i.e. doorbell write).
109 rte_write32(dword.ed_u32[0], doorbell);
113 const uint32_t * sfc_ef10_supported_ptypes_get(uint32_t tunnel_encaps);
119 #endif /* _SFC_EF10_H */