drivers/net/sfc/sfc_ef100_rx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019-2020 Xilinx, Inc.
   4  * Copyright(c) 2018-2019 Solarflare Communications Inc.
   5  *
   6  * This software was jointly developed between OKTET Labs (under contract
   7  * for Solarflare) and Solarflare Communications, Inc.
   8  */
   9
  10 /* EF100 native datapath implementation */
  11
  12 #include <stdbool.h>
  13
  14 #include <rte_byteorder.h>
  15 #include <rte_mbuf_ptype.h>
  16 #include <rte_mbuf.h>
  17 #include <rte_io.h>
  18
  19 #include "efx_types.h"
  20 #include "efx_regs_ef100.h"
  21
  22 #include "sfc_debug.h"
  23 #include "sfc_tweak.h"
  24 #include "sfc_dp_rx.h"
  25 #include "sfc_kvargs.h"
  26 #include "sfc_ef100.h"
  27
  28
  29 #define sfc_ef100_rx_err(_rxq, ...) \
  30         SFC_DP_LOG(SFC_KVARG_DATAPATH_EF100, ERR, &(_rxq)->dp.dpq, __VA_ARGS__)
  31
  32 #define sfc_ef100_rx_debug(_rxq, ...) \
  33         SFC_DP_LOG(SFC_KVARG_DATAPATH_EF100, DEBUG, &(_rxq)->dp.dpq, \
  34                    __VA_ARGS__)
  35
  36 /**
  37  * Maximum number of descriptors/buffers in the Rx ring.
  38  * It should guarantee that corresponding event queue never overfill.
  39  * EF10 native datapath uses event queue of the same size as Rx queue.
  40  * Maximum number of events on datapath can be estimated as number of
  41  * Rx queue entries (one event per Rx buffer in the worst case) plus
  42  * Rx error and flush events.
  43  */
  44 #define SFC_EF100_RXQ_LIMIT(_ndesc) \
  45         ((_ndesc) - 1 /* head must not step on tail */ - \
  46          1 /* Rx error */ - 1 /* flush */)
  47
  48 struct sfc_ef100_rx_sw_desc {
  49         struct rte_mbuf                 *mbuf;
  50 };
  51
  52 struct sfc_ef100_rxq {
  53         /* Used on data path */
  54         unsigned int                    flags;
  55 #define SFC_EF100_RXQ_STARTED           0x1
  56 #define SFC_EF100_RXQ_NOT_RUNNING       0x2
  57 #define SFC_EF100_RXQ_EXCEPTION         0x4
  58         unsigned int                    ptr_mask;
  59         unsigned int                    evq_phase_bit_shift;
  60         unsigned int                    ready_pkts;
  61         unsigned int                    completed;
  62         unsigned int                    evq_read_ptr;
  63         volatile efx_qword_t            *evq_hw_ring;
  64         struct sfc_ef100_rx_sw_desc     *sw_ring;
  65         uint64_t                        rearm_data;
  66         uint16_t                        buf_size;
  67         uint16_t                        prefix_size;
  68
  69         /* Used on refill */
  70         unsigned int                    added;
  71         unsigned int                    max_fill_level;
  72         unsigned int                    refill_threshold;
  73         struct rte_mempool              *refill_mb_pool;
  74         efx_qword_t                     *rxq_hw_ring;
  75         volatile void                   *doorbell;
  76
  77         /* Datapath receive queue anchor */
  78         struct sfc_dp_rxq               dp;
  79 };
  80
  81 static inline struct sfc_ef100_rxq *
  82 sfc_ef100_rxq_by_dp_rxq(struct sfc_dp_rxq *dp_rxq)
  83 {
  84         return container_of(dp_rxq, struct sfc_ef100_rxq, dp);
  85 }
  86
  87 static inline void
  88 sfc_ef100_rx_qpush(struct sfc_ef100_rxq *rxq, unsigned int added)
  89 {
  90         efx_dword_t dword;
  91
  92         EFX_POPULATE_DWORD_1(dword, ERF_GZ_RX_RING_PIDX, added & rxq->ptr_mask);
  93
  94         /* DMA sync to device is not required */
  95
  96         /*
  97          * rte_write32() has rte_io_wmb() which guarantees that the STORE
  98          * operations (i.e. Rx and event descriptor updates) that precede
  99          * the rte_io_wmb() call are visible to NIC before the STORE
 100          * operations that follow it (i.e. doorbell write).
 101          */
 102         rte_write32(dword.ed_u32[0], rxq->doorbell);
 103
 104         sfc_ef100_rx_debug(rxq, "RxQ pushed doorbell at pidx %u (added=%u)",
 105                            EFX_DWORD_FIELD(dword, ERF_GZ_RX_RING_PIDX),
 106                            added);
 107 }
 108
 109 static void
 110 sfc_ef100_rx_qrefill(struct sfc_ef100_rxq *rxq)
 111 {
 112         const unsigned int ptr_mask = rxq->ptr_mask;
 113         unsigned int free_space;
 114         unsigned int bulks;
 115         void *objs[SFC_RX_REFILL_BULK];
 116         unsigned int added = rxq->added;
 117
 118         free_space = rxq->max_fill_level - (added - rxq->completed);
 119
 120         if (free_space < rxq->refill_threshold)
 121                 return;
 122
 123         bulks = free_space / RTE_DIM(objs);
 124         /* refill_threshold guarantees that bulks is positive */
 125         SFC_ASSERT(bulks > 0);
 126
 127         do {
 128                 unsigned int id;
 129                 unsigned int i;
 130
 131                 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs,
 132                                                   RTE_DIM(objs)) < 0)) {
 133                         struct rte_eth_dev_data *dev_data =
 134                                 rte_eth_devices[rxq->dp.dpq.port_id].data;
 135
 136                         /*
 137                          * It is hardly a safe way to increment counter
 138                          * from different contexts, but all PMDs do it.
 139                          */
 140                         dev_data->rx_mbuf_alloc_failed += RTE_DIM(objs);
 141                         /* Return if we have posted nothing yet */
 142                         if (added == rxq->added)
 143                                 return;
 144                         /* Push posted */
 145                         break;
 146                 }
 147
 148                 for (i = 0, id = added & ptr_mask;
 149                      i < RTE_DIM(objs);
 150                      ++i, ++id) {
 151                         struct rte_mbuf *m = objs[i];
 152                         struct sfc_ef100_rx_sw_desc *rxd;
 153                         rte_iova_t phys_addr;
 154
 155                         MBUF_RAW_ALLOC_CHECK(m);
 156
 157                         SFC_ASSERT((id & ~ptr_mask) == 0);
 158                         rxd = &rxq->sw_ring[id];
 159                         rxd->mbuf = m;
 160
 161                         /*
 162                          * Avoid writing to mbuf. It is cheaper to do it
 163                          * when we receive packet and fill in nearby
 164                          * structure members.
 165                          */
 166
 167                         phys_addr = rte_mbuf_data_iova_default(m);
 168                         EFX_POPULATE_QWORD_1(rxq->rxq_hw_ring[id],
 169                             ESF_GZ_RX_BUF_ADDR, phys_addr);
 170                 }
 171
 172                 added += RTE_DIM(objs);
 173         } while (--bulks > 0);
 174
 175         SFC_ASSERT(rxq->added != added);
 176         rxq->added = added;
 177         sfc_ef100_rx_qpush(rxq, added);
 178 }
 179
 180 static bool
 181 sfc_ef100_rx_prefix_to_offloads(const efx_oword_t *rx_prefix,
 182                                 struct rte_mbuf *m)
 183 {
 184         const efx_word_t *class;
 185         uint64_t ol_flags = 0;
 186
 187         RTE_BUILD_BUG_ON(EFX_LOW_BIT(ESF_GZ_RX_PREFIX_CLASS) % CHAR_BIT != 0);
 188         RTE_BUILD_BUG_ON(EFX_WIDTH(ESF_GZ_RX_PREFIX_CLASS) % CHAR_BIT != 0);
 189         RTE_BUILD_BUG_ON(EFX_WIDTH(ESF_GZ_RX_PREFIX_CLASS) / CHAR_BIT !=
 190                          sizeof(*class));
 191         class = (const efx_word_t *)((const uint8_t *)rx_prefix +
 192                 EFX_LOW_BIT(ESF_GZ_RX_PREFIX_CLASS) / CHAR_BIT);
 193         if (unlikely(EFX_WORD_FIELD(*class,
 194                                     ESF_GZ_RX_PREFIX_HCLASS_L2_STATUS) !=
 195                      ESE_GZ_RH_HCLASS_L2_STATUS_OK))
 196                 return false;
 197
 198         m->ol_flags = ol_flags;
 199         return true;
 200 }
 201
 202 static const uint8_t *
 203 sfc_ef100_rx_pkt_prefix(const struct rte_mbuf *m)
 204 {
 205         return (const uint8_t *)m->buf_addr + RTE_PKTMBUF_HEADROOM;
 206 }
 207
 208 static struct rte_mbuf *
 209 sfc_ef100_rx_next_mbuf(struct sfc_ef100_rxq *rxq)
 210 {
 211         struct rte_mbuf *m;
 212         unsigned int id;
 213
 214         /* mbuf associated with current Rx descriptor */
 215         m = rxq->sw_ring[rxq->completed++ & rxq->ptr_mask].mbuf;
 216
 217         /* completed is already moved to the next one */
 218         if (unlikely(rxq->completed == rxq->added))
 219                 goto done;
 220
 221         /*
 222          * Prefetch Rx prefix of the next packet.
 223          * Current packet is scattered and the next mbuf is its fragment
 224          * it simply prefetches some data - no harm since packet rate
 225          * should not be high if scatter is used.
 226          */
 227         id = rxq->completed & rxq->ptr_mask;
 228         rte_prefetch0(sfc_ef100_rx_pkt_prefix(rxq->sw_ring[id].mbuf));
 229
 230         if (unlikely(rxq->completed + 1 == rxq->added))
 231                 goto done;
 232
 233         /*
 234          * Prefetch mbuf control structure of the next after next Rx
 235          * descriptor.
 236          */
 237         id = (id == rxq->ptr_mask) ? 0 : (id + 1);
 238         rte_mbuf_prefetch_part1(rxq->sw_ring[id].mbuf);
 239
 240         /*
 241          * If the next time we'll need SW Rx descriptor from the next
 242          * cache line, try to make sure that we have it in cache.
 243          */
 244         if ((id & 0x7) == 0x7)
 245                 rte_prefetch0(&rxq->sw_ring[(id + 1) & rxq->ptr_mask]);
 246
 247 done:
 248         return m;
 249 }
 250
 251 static struct rte_mbuf **
 252 sfc_ef100_rx_process_ready_pkts(struct sfc_ef100_rxq *rxq,
 253                                 struct rte_mbuf **rx_pkts,
 254                                 struct rte_mbuf ** const rx_pkts_end)
 255 {
 256         while (rxq->ready_pkts > 0 && rx_pkts != rx_pkts_end) {
 257                 struct rte_mbuf *pkt;
 258                 struct rte_mbuf *lastseg;
 259                 const efx_oword_t *rx_prefix;
 260                 uint16_t pkt_len;
 261                 uint16_t seg_len;
 262                 bool deliver;
 263
 264                 rxq->ready_pkts--;
 265
 266                 pkt = sfc_ef100_rx_next_mbuf(rxq);
 267                 MBUF_RAW_ALLOC_CHECK(pkt);
 268
 269                 RTE_BUILD_BUG_ON(sizeof(pkt->rearm_data[0]) !=
 270                                  sizeof(rxq->rearm_data));
 271                 pkt->rearm_data[0] = rxq->rearm_data;
 272
 273                 /* data_off already moved past Rx prefix */
 274                 rx_prefix = (const efx_oword_t *)sfc_ef100_rx_pkt_prefix(pkt);
 275
 276                 pkt_len = EFX_OWORD_FIELD(rx_prefix[0],
 277                                           ESF_GZ_RX_PREFIX_LENGTH);
 278                 SFC_ASSERT(pkt_len > 0);
 279                 rte_pktmbuf_pkt_len(pkt) = pkt_len;
 280
 281                 seg_len = RTE_MIN(pkt_len, rxq->buf_size - rxq->prefix_size);
 282                 rte_pktmbuf_data_len(pkt) = seg_len;
 283
 284                 deliver = sfc_ef100_rx_prefix_to_offloads(rx_prefix, pkt);
 285
 286                 lastseg = pkt;
 287                 while ((pkt_len -= seg_len) > 0) {
 288                         struct rte_mbuf *seg;
 289
 290                         seg = sfc_ef100_rx_next_mbuf(rxq);
 291                         MBUF_RAW_ALLOC_CHECK(seg);
 292
 293                         seg->data_off = RTE_PKTMBUF_HEADROOM;
 294
 295                         seg_len = RTE_MIN(pkt_len, rxq->buf_size);
 296                         rte_pktmbuf_data_len(seg) = seg_len;
 297                         rte_pktmbuf_pkt_len(seg) = seg_len;
 298
 299                         pkt->nb_segs++;
 300                         lastseg->next = seg;
 301                         lastseg = seg;
 302                 }
 303
 304                 if (likely(deliver))
 305                         *rx_pkts++ = pkt;
 306                 else
 307                         rte_pktmbuf_free(pkt);
 308         }
 309
 310         return rx_pkts;
 311 }
 312
 313 static bool
 314 sfc_ef100_rx_get_event(struct sfc_ef100_rxq *rxq, efx_qword_t *ev)
 315 {
 316         *ev = rxq->evq_hw_ring[rxq->evq_read_ptr & rxq->ptr_mask];
 317
 318         if (!sfc_ef100_ev_present(ev,
 319                         (rxq->evq_read_ptr >> rxq->evq_phase_bit_shift) & 1))
 320                 return false;
 321
 322         if (unlikely(!sfc_ef100_ev_type_is(ev, ESE_GZ_EF100_EV_RX_PKTS))) {
 323                 /*
 324                  * Do not move read_ptr to keep the event for exception
 325                  * handling by the control path.
 326                  */
 327                 rxq->flags |= SFC_EF100_RXQ_EXCEPTION;
 328                 sfc_ef100_rx_err(rxq,
 329                         "RxQ exception at EvQ ptr %u(%#x), event %08x:%08x",
 330                         rxq->evq_read_ptr, rxq->evq_read_ptr & rxq->ptr_mask,
 331                         EFX_QWORD_FIELD(*ev, EFX_DWORD_1),
 332                         EFX_QWORD_FIELD(*ev, EFX_DWORD_0));
 333                 return false;
 334         }
 335
 336         sfc_ef100_rx_debug(rxq, "RxQ got event %08x:%08x at %u (%#x)",
 337                            EFX_QWORD_FIELD(*ev, EFX_DWORD_1),
 338                            EFX_QWORD_FIELD(*ev, EFX_DWORD_0),
 339                            rxq->evq_read_ptr,
 340                            rxq->evq_read_ptr & rxq->ptr_mask);
 341
 342         rxq->evq_read_ptr++;
 343         return true;
 344 }
 345
 346 static uint16_t
 347 sfc_ef100_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 348 {
 349         struct sfc_ef100_rxq *rxq = sfc_ef100_rxq_by_dp_rxq(rx_queue);
 350         struct rte_mbuf ** const rx_pkts_end = &rx_pkts[nb_pkts];
 351         efx_qword_t rx_ev;
 352
 353         rx_pkts = sfc_ef100_rx_process_ready_pkts(rxq, rx_pkts, rx_pkts_end);
 354
 355         if (unlikely(rxq->flags &
 356                      (SFC_EF100_RXQ_NOT_RUNNING | SFC_EF100_RXQ_EXCEPTION)))
 357                 goto done;
 358
 359         while (rx_pkts != rx_pkts_end && sfc_ef100_rx_get_event(rxq, &rx_ev)) {
 360                 rxq->ready_pkts =
 361                         EFX_QWORD_FIELD(rx_ev, ESF_GZ_EV_RXPKTS_NUM_PKT);
 362                 rx_pkts = sfc_ef100_rx_process_ready_pkts(rxq, rx_pkts,
 363                                                           rx_pkts_end);
 364         }
 365
 366         /* It is not a problem if we refill in the case of exception */
 367         sfc_ef100_rx_qrefill(rxq);
 368
 369 done:
 370         return nb_pkts - (rx_pkts_end - rx_pkts);
 371 }
 372
 373 static const uint32_t *
 374 sfc_ef100_supported_ptypes_get(__rte_unused uint32_t tunnel_encaps)
 375 {
 376         static const uint32_t ef100_native_ptypes[] = {
 377                 RTE_PTYPE_UNKNOWN
 378         };
 379
 380         return ef100_native_ptypes;
 381 }
 382
 383 static sfc_dp_rx_qdesc_npending_t sfc_ef100_rx_qdesc_npending;
 384 static unsigned int
 385 sfc_ef100_rx_qdesc_npending(__rte_unused struct sfc_dp_rxq *dp_rxq)
 386 {
 387         return 0;
 388 }
 389
 390 static sfc_dp_rx_qdesc_status_t sfc_ef100_rx_qdesc_status;
 391 static int
 392 sfc_ef100_rx_qdesc_status(__rte_unused struct sfc_dp_rxq *dp_rxq,
 393                           __rte_unused uint16_t offset)
 394 {
 395         return -ENOTSUP;
 396 }
 397
 398
 399 static sfc_dp_rx_get_dev_info_t sfc_ef100_rx_get_dev_info;
 400 static void
 401 sfc_ef100_rx_get_dev_info(struct rte_eth_dev_info *dev_info)
 402 {
 403         /*
 404          * Number of descriptors just defines maximum number of pushed
 405          * descriptors (fill level).
 406          */
 407         dev_info->rx_desc_lim.nb_min = SFC_RX_REFILL_BULK;
 408         dev_info->rx_desc_lim.nb_align = SFC_RX_REFILL_BULK;
 409 }
 410
 411
 412 static sfc_dp_rx_qsize_up_rings_t sfc_ef100_rx_qsize_up_rings;
 413 static int
 414 sfc_ef100_rx_qsize_up_rings(uint16_t nb_rx_desc,
 415                            struct sfc_dp_rx_hw_limits *limits,
 416                            __rte_unused struct rte_mempool *mb_pool,
 417                            unsigned int *rxq_entries,
 418                            unsigned int *evq_entries,
 419                            unsigned int *rxq_max_fill_level)
 420 {
 421         /*
 422          * rte_ethdev API guarantees that the number meets min, max and
 423          * alignment requirements.
 424          */
 425         if (nb_rx_desc <= limits->rxq_min_entries)
 426                 *rxq_entries = limits->rxq_min_entries;
 427         else
 428                 *rxq_entries = rte_align32pow2(nb_rx_desc);
 429
 430         *evq_entries = *rxq_entries;
 431
 432         *rxq_max_fill_level = RTE_MIN(nb_rx_desc,
 433                                       SFC_EF100_RXQ_LIMIT(*evq_entries));
 434         return 0;
 435 }
 436
 437
 438 static uint64_t
 439 sfc_ef100_mk_mbuf_rearm_data(uint16_t port_id, uint16_t prefix_size)
 440 {
 441         struct rte_mbuf m;
 442
 443         memset(&m, 0, sizeof(m));
 444
 445         rte_mbuf_refcnt_set(&m, 1);
 446         m.data_off = RTE_PKTMBUF_HEADROOM + prefix_size;
 447         m.nb_segs = 1;
 448         m.port = port_id;
 449
 450         /* rearm_data covers structure members filled in above */
 451         rte_compiler_barrier();
 452         RTE_BUILD_BUG_ON(sizeof(m.rearm_data[0]) != sizeof(uint64_t));
 453         return m.rearm_data[0];
 454 }
 455
 456 static sfc_dp_rx_qcreate_t sfc_ef100_rx_qcreate;
 457 static int
 458 sfc_ef100_rx_qcreate(uint16_t port_id, uint16_t queue_id,
 459                     const struct rte_pci_addr *pci_addr, int socket_id,
 460                     const struct sfc_dp_rx_qcreate_info *info,
 461                     struct sfc_dp_rxq **dp_rxqp)
 462 {
 463         struct sfc_ef100_rxq *rxq;
 464         int rc;
 465
 466         rc = EINVAL;
 467         if (info->rxq_entries != info->evq_entries)
 468                 goto fail_rxq_args;
 469
 470         rc = ENOMEM;
 471         rxq = rte_zmalloc_socket("sfc-ef100-rxq", sizeof(*rxq),
 472                                  RTE_CACHE_LINE_SIZE, socket_id);
 473         if (rxq == NULL)
 474                 goto fail_rxq_alloc;
 475
 476         sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr);
 477
 478         rc = ENOMEM;
 479         rxq->sw_ring = rte_calloc_socket("sfc-ef100-rxq-sw_ring",
 480                                          info->rxq_entries,
 481                                          sizeof(*rxq->sw_ring),
 482                                          RTE_CACHE_LINE_SIZE, socket_id);
 483         if (rxq->sw_ring == NULL)
 484                 goto fail_desc_alloc;
 485
 486         rxq->flags |= SFC_EF100_RXQ_NOT_RUNNING;
 487         rxq->ptr_mask = info->rxq_entries - 1;
 488         rxq->evq_phase_bit_shift = rte_bsf32(info->evq_entries);
 489         rxq->evq_hw_ring = info->evq_hw_ring;
 490         rxq->max_fill_level = info->max_fill_level;
 491         rxq->refill_threshold = info->refill_threshold;
 492         rxq->rearm_data =
 493                 sfc_ef100_mk_mbuf_rearm_data(port_id, info->prefix_size);
 494         rxq->prefix_size = info->prefix_size;
 495         rxq->buf_size = info->buf_size;
 496         rxq->refill_mb_pool = info->refill_mb_pool;
 497         rxq->rxq_hw_ring = info->rxq_hw_ring;
 498         rxq->doorbell = (volatile uint8_t *)info->mem_bar +
 499                         ER_GZ_RX_RING_DOORBELL_OFST +
 500                         (info->hw_index << info->vi_window_shift);
 501
 502         sfc_ef100_rx_debug(rxq, "RxQ doorbell is %p", rxq->doorbell);
 503
 504         *dp_rxqp = &rxq->dp;
 505         return 0;
 506
 507 fail_desc_alloc:
 508         rte_free(rxq);
 509
 510 fail_rxq_alloc:
 511 fail_rxq_args:
 512         return rc;
 513 }
 514
 515 static sfc_dp_rx_qdestroy_t sfc_ef100_rx_qdestroy;
 516 static void
 517 sfc_ef100_rx_qdestroy(struct sfc_dp_rxq *dp_rxq)
 518 {
 519         struct sfc_ef100_rxq *rxq = sfc_ef100_rxq_by_dp_rxq(dp_rxq);
 520
 521         rte_free(rxq->sw_ring);
 522         rte_free(rxq);
 523 }
 524
 525 static sfc_dp_rx_qstart_t sfc_ef100_rx_qstart;
 526 static int
 527 sfc_ef100_rx_qstart(struct sfc_dp_rxq *dp_rxq, unsigned int evq_read_ptr)
 528 {
 529         struct sfc_ef100_rxq *rxq = sfc_ef100_rxq_by_dp_rxq(dp_rxq);
 530
 531         SFC_ASSERT(rxq->completed == 0);
 532         SFC_ASSERT(rxq->added == 0);
 533
 534         sfc_ef100_rx_qrefill(rxq);
 535
 536         rxq->evq_read_ptr = evq_read_ptr;
 537
 538         rxq->flags |= SFC_EF100_RXQ_STARTED;
 539         rxq->flags &= ~(SFC_EF100_RXQ_NOT_RUNNING | SFC_EF100_RXQ_EXCEPTION);
 540
 541         return 0;
 542 }
 543
 544 static sfc_dp_rx_qstop_t sfc_ef100_rx_qstop;
 545 static void
 546 sfc_ef100_rx_qstop(struct sfc_dp_rxq *dp_rxq, unsigned int *evq_read_ptr)
 547 {
 548         struct sfc_ef100_rxq *rxq = sfc_ef100_rxq_by_dp_rxq(dp_rxq);
 549
 550         rxq->flags |= SFC_EF100_RXQ_NOT_RUNNING;
 551
 552         *evq_read_ptr = rxq->evq_read_ptr;
 553 }
 554
 555 static sfc_dp_rx_qrx_ev_t sfc_ef100_rx_qrx_ev;
 556 static bool
 557 sfc_ef100_rx_qrx_ev(struct sfc_dp_rxq *dp_rxq, __rte_unused unsigned int id)
 558 {
 559         __rte_unused struct sfc_ef100_rxq *rxq = sfc_ef100_rxq_by_dp_rxq(dp_rxq);
 560
 561         SFC_ASSERT(rxq->flags & SFC_EF100_RXQ_NOT_RUNNING);
 562
 563         /*
 564          * It is safe to ignore Rx event since we free all mbufs on
 565          * queue purge anyway.
 566          */
 567
 568         return false;
 569 }
 570
 571 static sfc_dp_rx_qpurge_t sfc_ef100_rx_qpurge;
 572 static void
 573 sfc_ef100_rx_qpurge(struct sfc_dp_rxq *dp_rxq)
 574 {
 575         struct sfc_ef100_rxq *rxq = sfc_ef100_rxq_by_dp_rxq(dp_rxq);
 576         unsigned int i;
 577         struct sfc_ef100_rx_sw_desc *rxd;
 578
 579         for (i = rxq->completed; i != rxq->added; ++i) {
 580                 rxd = &rxq->sw_ring[i & rxq->ptr_mask];
 581                 rte_mbuf_raw_free(rxd->mbuf);
 582                 rxd->mbuf = NULL;
 583         }
 584
 585         rxq->completed = rxq->added = 0;
 586         rxq->ready_pkts = 0;
 587
 588         rxq->flags &= ~SFC_EF100_RXQ_STARTED;
 589 }
 590
 591 struct sfc_dp_rx sfc_ef100_rx = {
 592         .dp = {
 593                 .name           = SFC_KVARG_DATAPATH_EF100,
 594                 .type           = SFC_DP_RX,
 595                 .hw_fw_caps     = SFC_DP_HW_FW_CAP_EF100,
 596         },
 597         .features               = SFC_DP_RX_FEAT_MULTI_PROCESS,
 598         .dev_offload_capa       = 0,
 599         .queue_offload_capa     = DEV_RX_OFFLOAD_SCATTER,
 600         .get_dev_info           = sfc_ef100_rx_get_dev_info,
 601         .qsize_up_rings         = sfc_ef100_rx_qsize_up_rings,
 602         .qcreate                = sfc_ef100_rx_qcreate,
 603         .qdestroy               = sfc_ef100_rx_qdestroy,
 604         .qstart                 = sfc_ef100_rx_qstart,
 605         .qstop                  = sfc_ef100_rx_qstop,
 606         .qrx_ev                 = sfc_ef100_rx_qrx_ev,
 607         .qpurge                 = sfc_ef100_rx_qpurge,
 608         .supported_ptypes_get   = sfc_ef100_supported_ptypes_get,
 609         .qdesc_npending         = sfc_ef100_rx_qdesc_npending,
 610         .qdesc_status           = sfc_ef100_rx_qdesc_status,
 611         .pkt_burst              = sfc_ef100_recv_pkts,
 612 };