1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2018-2019 Solarflare Communications Inc.
6 * This software was jointly developed between OKTET Labs (under contract
7 * for Solarflare) and Solarflare Communications, Inc.
16 #include "efx_types.h"
18 #include "efx_regs_ef100.h"
20 #include "sfc_debug.h"
21 #include "sfc_dp_tx.h"
22 #include "sfc_tweak.h"
23 #include "sfc_kvargs.h"
24 #include "sfc_ef100.h"
27 #define sfc_ef100_tx_err(_txq, ...) \
28 SFC_DP_LOG(SFC_KVARG_DATAPATH_EF100, ERR, &(_txq)->dp.dpq, __VA_ARGS__)
30 #define sfc_ef100_tx_debug(_txq, ...) \
31 SFC_DP_LOG(SFC_KVARG_DATAPATH_EF100, DEBUG, &(_txq)->dp.dpq, \
35 /** Maximum length of the send descriptor data */
36 #define SFC_EF100_TX_SEND_DESC_LEN_MAX \
37 ((1u << ESF_GZ_TX_SEND_LEN_WIDTH) - 1)
39 /** Maximum length of the segment descriptor data */
40 #define SFC_EF100_TX_SEG_DESC_LEN_MAX \
41 ((1u << ESF_GZ_TX_SEG_LEN_WIDTH) - 1)
44 * Maximum number of descriptors/buffers in the Tx ring.
45 * It should guarantee that corresponding event queue never overfill.
46 * EF100 native datapath uses event queue of the same size as Tx queue.
47 * Maximum number of events on datapath can be estimated as number of
48 * Tx queue entries (one event per Tx buffer in the worst case) plus
49 * Tx error and flush events.
51 #define SFC_EF100_TXQ_LIMIT(_ndesc) \
52 ((_ndesc) - 1 /* head must not step on tail */ - \
53 1 /* Rx error */ - 1 /* flush */)
55 struct sfc_ef100_tx_sw_desc {
56 struct rte_mbuf *mbuf;
59 struct sfc_ef100_txq {
61 #define SFC_EF100_TXQ_STARTED 0x1
62 #define SFC_EF100_TXQ_NOT_RUNNING 0x2
63 #define SFC_EF100_TXQ_EXCEPTION 0x4
65 unsigned int ptr_mask;
67 unsigned int completed;
68 unsigned int max_fill_level;
69 unsigned int free_thresh;
70 struct sfc_ef100_tx_sw_desc *sw_ring;
71 efx_oword_t *txq_hw_ring;
72 volatile void *doorbell;
75 unsigned int evq_read_ptr;
76 unsigned int evq_phase_bit_shift;
77 volatile efx_qword_t *evq_hw_ring;
79 /* Datapath transmit queue anchor */
83 static inline struct sfc_ef100_txq *
84 sfc_ef100_txq_by_dp_txq(struct sfc_dp_txq *dp_txq)
86 return container_of(dp_txq, struct sfc_ef100_txq, dp);
90 sfc_ef100_tx_prepare_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
93 struct sfc_ef100_txq * const txq = sfc_ef100_txq_by_dp_txq(tx_queue);
96 for (i = 0; i < nb_pkts; i++) {
97 struct rte_mbuf *m = tx_pkts[i];
100 ret = sfc_dp_tx_prepare_pkt(m, 0, txq->max_fill_level, 0, 0);
101 if (unlikely(ret != 0)) {
106 if (m->nb_segs > EFX_MASK32(ESF_GZ_TX_SEND_NUM_SEGS)) {
116 sfc_ef100_tx_get_event(struct sfc_ef100_txq *txq, efx_qword_t *ev)
118 volatile efx_qword_t *evq_hw_ring = txq->evq_hw_ring;
121 * Exception flag is set when reap is done.
122 * It is never done twice per packet burst get, and absence of
123 * the flag is checked on burst get entry.
125 SFC_ASSERT((txq->flags & SFC_EF100_TXQ_EXCEPTION) == 0);
127 *ev = evq_hw_ring[txq->evq_read_ptr & txq->ptr_mask];
129 if (!sfc_ef100_ev_present(ev,
130 (txq->evq_read_ptr >> txq->evq_phase_bit_shift) & 1))
133 if (unlikely(!sfc_ef100_ev_type_is(ev,
134 ESE_GZ_EF100_EV_TX_COMPLETION))) {
136 * Do not move read_ptr to keep the event for exception
137 * handling by the control path.
139 txq->flags |= SFC_EF100_TXQ_EXCEPTION;
140 sfc_ef100_tx_err(txq,
141 "TxQ exception at EvQ ptr %u(%#x), event %08x:%08x",
142 txq->evq_read_ptr, txq->evq_read_ptr & txq->ptr_mask,
143 EFX_QWORD_FIELD(*ev, EFX_DWORD_1),
144 EFX_QWORD_FIELD(*ev, EFX_DWORD_0));
148 sfc_ef100_tx_debug(txq, "TxQ got event %08x:%08x at %u (%#x)",
149 EFX_QWORD_FIELD(*ev, EFX_DWORD_1),
150 EFX_QWORD_FIELD(*ev, EFX_DWORD_0),
152 txq->evq_read_ptr & txq->ptr_mask);
159 sfc_ef100_tx_process_events(struct sfc_ef100_txq *txq)
161 unsigned int num_descs = 0;
164 while (sfc_ef100_tx_get_event(txq, &tx_ev))
165 num_descs += EFX_QWORD_FIELD(tx_ev, ESF_GZ_EV_TXCMPL_NUM_DESC);
171 sfc_ef100_tx_reap_num_descs(struct sfc_ef100_txq *txq, unsigned int num_descs)
174 unsigned int completed = txq->completed;
175 unsigned int pending = completed + num_descs;
176 struct rte_mbuf *bulk[SFC_TX_REAP_BULK_SIZE];
180 struct sfc_ef100_tx_sw_desc *txd;
183 txd = &txq->sw_ring[completed & txq->ptr_mask];
184 if (txd->mbuf == NULL)
187 m = rte_pktmbuf_prefree_seg(txd->mbuf);
193 if (nb == RTE_DIM(bulk) ||
194 (nb != 0 && m->pool != bulk[0]->pool)) {
195 rte_mempool_put_bulk(bulk[0]->pool,
201 } while (++completed != pending);
204 rte_mempool_put_bulk(bulk[0]->pool, (void *)bulk, nb);
206 txq->completed = completed;
211 sfc_ef100_tx_reap(struct sfc_ef100_txq *txq)
213 sfc_ef100_tx_reap_num_descs(txq, sfc_ef100_tx_process_events(txq));
217 sfc_ef100_tx_qdesc_send_create(const struct rte_mbuf *m, efx_oword_t *tx_desc)
222 outer_l3 = (m->ol_flags & PKT_TX_IP_CKSUM);
223 outer_l4 = (m->ol_flags & PKT_TX_L4_MASK);
225 EFX_POPULATE_OWORD_6(*tx_desc,
226 ESF_GZ_TX_SEND_ADDR, rte_mbuf_data_iova(m),
227 ESF_GZ_TX_SEND_LEN, rte_pktmbuf_data_len(m),
228 ESF_GZ_TX_SEND_NUM_SEGS, m->nb_segs,
229 ESF_GZ_TX_SEND_CSO_OUTER_L3, outer_l3,
230 ESF_GZ_TX_SEND_CSO_OUTER_L4, outer_l4,
231 ESF_GZ_TX_DESC_TYPE, ESE_GZ_TX_DESC_TYPE_SEND);
235 sfc_ef100_tx_qdesc_seg_create(rte_iova_t addr, uint16_t len,
236 efx_oword_t *tx_desc)
238 EFX_POPULATE_OWORD_3(*tx_desc,
239 ESF_GZ_TX_SEG_ADDR, addr,
240 ESF_GZ_TX_SEG_LEN, len,
241 ESF_GZ_TX_DESC_TYPE, ESE_GZ_TX_DESC_TYPE_SEG);
245 sfc_ef100_tx_qpush(struct sfc_ef100_txq *txq, unsigned int added)
249 EFX_POPULATE_DWORD_1(dword, ERF_GZ_TX_RING_PIDX, added & txq->ptr_mask);
251 /* DMA sync to device is not required */
254 * rte_write32() has rte_io_wmb() which guarantees that the STORE
255 * operations (i.e. Rx and event descriptor updates) that precede
256 * the rte_io_wmb() call are visible to NIC before the STORE
257 * operations that follow it (i.e. doorbell write).
259 rte_write32(dword.ed_u32[0], txq->doorbell);
261 sfc_ef100_tx_debug(txq, "TxQ pushed doorbell at pidx %u (added=%u)",
262 EFX_DWORD_FIELD(dword, ERF_GZ_TX_RING_PIDX),
267 sfc_ef100_tx_pkt_descs_max(const struct rte_mbuf *m)
269 /** Maximum length of an mbuf segment data */
270 #define SFC_MBUF_SEG_LEN_MAX UINT16_MAX
271 RTE_BUILD_BUG_ON(sizeof(m->data_len) != 2);
274 * mbuf segment cannot be bigger than maximum segment length and
275 * maximum packet length since TSO is not supported yet.
276 * Make sure that the first segment does not need fragmentation
277 * (split into many Tx descriptors).
279 RTE_BUILD_BUG_ON(SFC_EF100_TX_SEND_DESC_LEN_MAX <
280 RTE_MIN((unsigned int)EFX_MAC_PDU_MAX, SFC_MBUF_SEG_LEN_MAX));
283 * Any segment of scattered packet cannot be bigger than maximum
284 * segment length and maximum packet length since TSO is not
286 * Make sure that subsequent segments do not need fragmentation (split
287 * into many Tx descriptors).
289 RTE_BUILD_BUG_ON(SFC_EF100_TX_SEG_DESC_LEN_MAX <
290 RTE_MIN((unsigned int)EFX_MAC_PDU_MAX, SFC_MBUF_SEG_LEN_MAX));
296 sfc_ef100_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
298 struct sfc_ef100_txq * const txq = sfc_ef100_txq_by_dp_txq(tx_queue);
300 unsigned int dma_desc_space;
302 struct rte_mbuf **pktp;
303 struct rte_mbuf **pktp_end;
305 if (unlikely(txq->flags &
306 (SFC_EF100_TXQ_NOT_RUNNING | SFC_EF100_TXQ_EXCEPTION)))
310 dma_desc_space = txq->max_fill_level - (added - txq->completed);
312 reap_done = (dma_desc_space < txq->free_thresh);
314 sfc_ef100_tx_reap(txq);
315 dma_desc_space = txq->max_fill_level - (added - txq->completed);
318 for (pktp = &tx_pkts[0], pktp_end = &tx_pkts[nb_pkts];
321 struct rte_mbuf *m_seg = *pktp;
322 unsigned int pkt_start = added;
325 if (likely(pktp + 1 != pktp_end))
326 rte_mbuf_prefetch_part1(pktp[1]);
328 if (sfc_ef100_tx_pkt_descs_max(m_seg) > dma_desc_space) {
332 /* Push already prepared descriptors before polling */
333 if (added != txq->added) {
334 sfc_ef100_tx_qpush(txq, added);
338 sfc_ef100_tx_reap(txq);
340 dma_desc_space = txq->max_fill_level -
341 (added - txq->completed);
342 if (sfc_ef100_tx_pkt_descs_max(m_seg) > dma_desc_space)
346 id = added++ & txq->ptr_mask;
347 sfc_ef100_tx_qdesc_send_create(m_seg, &txq->txq_hw_ring[id]);
350 * rte_pktmbuf_free() is commonly used in DPDK for
351 * recycling packets - the function checks every
352 * segment's reference counter and returns the
353 * buffer to its pool whenever possible;
354 * nevertheless, freeing mbuf segments one by one
355 * may entail some performance decline;
356 * from this point, sfc_efx_tx_reap() does the same job
357 * on its own and frees buffers in bulks (all mbufs
358 * within a bulk belong to the same pool);
359 * from this perspective, individual segment pointers
360 * must be associated with the corresponding SW
361 * descriptors independently so that only one loop
362 * is sufficient on reap to inspect all the buffers
364 txq->sw_ring[id].mbuf = m_seg;
366 while ((m_seg = m_seg->next) != NULL) {
367 RTE_BUILD_BUG_ON(SFC_MBUF_SEG_LEN_MAX >
368 SFC_EF100_TX_SEG_DESC_LEN_MAX);
370 id = added++ & txq->ptr_mask;
371 sfc_ef100_tx_qdesc_seg_create(rte_mbuf_data_iova(m_seg),
372 rte_pktmbuf_data_len(m_seg),
373 &txq->txq_hw_ring[id]);
374 txq->sw_ring[id].mbuf = m_seg;
377 dma_desc_space -= (added - pkt_start);
380 if (likely(added != txq->added)) {
381 sfc_ef100_tx_qpush(txq, added);
385 #if SFC_TX_XMIT_PKTS_REAP_AT_LEAST_ONCE
387 sfc_ef100_tx_reap(txq);
390 return pktp - &tx_pkts[0];
393 static sfc_dp_tx_get_dev_info_t sfc_ef100_get_dev_info;
395 sfc_ef100_get_dev_info(struct rte_eth_dev_info *dev_info)
398 * Number of descriptors just defines maximum number of pushed
399 * descriptors (fill level).
401 dev_info->tx_desc_lim.nb_min = 1;
402 dev_info->tx_desc_lim.nb_align = 1;
405 static sfc_dp_tx_qsize_up_rings_t sfc_ef100_tx_qsize_up_rings;
407 sfc_ef100_tx_qsize_up_rings(uint16_t nb_tx_desc,
408 struct sfc_dp_tx_hw_limits *limits,
409 unsigned int *txq_entries,
410 unsigned int *evq_entries,
411 unsigned int *txq_max_fill_level)
414 * rte_ethdev API guarantees that the number meets min, max and
415 * alignment requirements.
417 if (nb_tx_desc <= limits->txq_min_entries)
418 *txq_entries = limits->txq_min_entries;
420 *txq_entries = rte_align32pow2(nb_tx_desc);
422 *evq_entries = *txq_entries;
424 *txq_max_fill_level = RTE_MIN(nb_tx_desc,
425 SFC_EF100_TXQ_LIMIT(*evq_entries));
429 static sfc_dp_tx_qcreate_t sfc_ef100_tx_qcreate;
431 sfc_ef100_tx_qcreate(uint16_t port_id, uint16_t queue_id,
432 const struct rte_pci_addr *pci_addr, int socket_id,
433 const struct sfc_dp_tx_qcreate_info *info,
434 struct sfc_dp_txq **dp_txqp)
436 struct sfc_ef100_txq *txq;
440 if (info->txq_entries != info->evq_entries)
444 txq = rte_zmalloc_socket("sfc-ef100-txq", sizeof(*txq),
445 RTE_CACHE_LINE_SIZE, socket_id);
449 sfc_dp_queue_init(&txq->dp.dpq, port_id, queue_id, pci_addr);
452 txq->sw_ring = rte_calloc_socket("sfc-ef100-txq-sw_ring",
454 sizeof(*txq->sw_ring),
455 RTE_CACHE_LINE_SIZE, socket_id);
456 if (txq->sw_ring == NULL)
457 goto fail_sw_ring_alloc;
459 txq->flags = SFC_EF100_TXQ_NOT_RUNNING;
460 txq->ptr_mask = info->txq_entries - 1;
461 txq->max_fill_level = info->max_fill_level;
462 txq->free_thresh = info->free_thresh;
463 txq->evq_phase_bit_shift = rte_bsf32(info->evq_entries);
464 txq->txq_hw_ring = info->txq_hw_ring;
465 txq->doorbell = (volatile uint8_t *)info->mem_bar +
466 ER_GZ_TX_RING_DOORBELL_OFST +
467 (info->hw_index << info->vi_window_shift);
468 txq->evq_hw_ring = info->evq_hw_ring;
470 sfc_ef100_tx_debug(txq, "TxQ doorbell is %p", txq->doorbell);
483 static sfc_dp_tx_qdestroy_t sfc_ef100_tx_qdestroy;
485 sfc_ef100_tx_qdestroy(struct sfc_dp_txq *dp_txq)
487 struct sfc_ef100_txq *txq = sfc_ef100_txq_by_dp_txq(dp_txq);
489 rte_free(txq->sw_ring);
493 static sfc_dp_tx_qstart_t sfc_ef100_tx_qstart;
495 sfc_ef100_tx_qstart(struct sfc_dp_txq *dp_txq, unsigned int evq_read_ptr,
496 unsigned int txq_desc_index)
498 struct sfc_ef100_txq *txq = sfc_ef100_txq_by_dp_txq(dp_txq);
500 txq->evq_read_ptr = evq_read_ptr;
501 txq->added = txq->completed = txq_desc_index;
503 txq->flags |= SFC_EF100_TXQ_STARTED;
504 txq->flags &= ~(SFC_EF100_TXQ_NOT_RUNNING | SFC_EF100_TXQ_EXCEPTION);
509 static sfc_dp_tx_qstop_t sfc_ef100_tx_qstop;
511 sfc_ef100_tx_qstop(struct sfc_dp_txq *dp_txq, unsigned int *evq_read_ptr)
513 struct sfc_ef100_txq *txq = sfc_ef100_txq_by_dp_txq(dp_txq);
515 txq->flags |= SFC_EF100_TXQ_NOT_RUNNING;
517 *evq_read_ptr = txq->evq_read_ptr;
520 static sfc_dp_tx_qtx_ev_t sfc_ef100_tx_qtx_ev;
522 sfc_ef100_tx_qtx_ev(struct sfc_dp_txq *dp_txq, unsigned int num_descs)
524 struct sfc_ef100_txq *txq = sfc_ef100_txq_by_dp_txq(dp_txq);
526 SFC_ASSERT(txq->flags & SFC_EF100_TXQ_NOT_RUNNING);
528 sfc_ef100_tx_reap_num_descs(txq, num_descs);
533 static sfc_dp_tx_qreap_t sfc_ef100_tx_qreap;
535 sfc_ef100_tx_qreap(struct sfc_dp_txq *dp_txq)
537 struct sfc_ef100_txq *txq = sfc_ef100_txq_by_dp_txq(dp_txq);
538 unsigned int completed;
540 for (completed = txq->completed; completed != txq->added; ++completed) {
541 struct sfc_ef100_tx_sw_desc *txd;
543 txd = &txq->sw_ring[completed & txq->ptr_mask];
544 if (txd->mbuf != NULL) {
545 rte_pktmbuf_free_seg(txd->mbuf);
550 txq->flags &= ~SFC_EF100_TXQ_STARTED;
554 sfc_ef100_tx_qdesc_npending(struct sfc_ef100_txq *txq)
556 const unsigned int evq_old_read_ptr = txq->evq_read_ptr;
557 unsigned int npending = 0;
560 if (unlikely(txq->flags &
561 (SFC_EF100_TXQ_NOT_RUNNING | SFC_EF100_TXQ_EXCEPTION)))
564 while (sfc_ef100_tx_get_event(txq, &tx_ev))
565 npending += EFX_QWORD_FIELD(tx_ev, ESF_GZ_EV_TXCMPL_NUM_DESC);
568 * The function does not process events, so return event queue read
569 * pointer to the original position to allow the events that were
570 * read to be processed later
572 txq->evq_read_ptr = evq_old_read_ptr;
577 static sfc_dp_tx_qdesc_status_t sfc_ef100_tx_qdesc_status;
579 sfc_ef100_tx_qdesc_status(struct sfc_dp_txq *dp_txq, uint16_t offset)
581 struct sfc_ef100_txq *txq = sfc_ef100_txq_by_dp_txq(dp_txq);
582 unsigned int pushed = txq->added - txq->completed;
584 if (unlikely(offset > txq->ptr_mask))
587 if (unlikely(offset >= txq->max_fill_level))
588 return RTE_ETH_TX_DESC_UNAVAIL;
590 return (offset >= pushed ||
591 offset < sfc_ef100_tx_qdesc_npending(txq)) ?
592 RTE_ETH_TX_DESC_DONE : RTE_ETH_TX_DESC_FULL;
595 struct sfc_dp_tx sfc_ef100_tx = {
597 .name = SFC_KVARG_DATAPATH_EF100,
599 .hw_fw_caps = SFC_DP_HW_FW_CAP_EF100,
601 .features = SFC_DP_TX_FEAT_MULTI_PROCESS,
602 .dev_offload_capa = 0,
603 .queue_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
604 DEV_TX_OFFLOAD_UDP_CKSUM |
605 DEV_TX_OFFLOAD_TCP_CKSUM |
606 DEV_TX_OFFLOAD_MULTI_SEGS,
607 .get_dev_info = sfc_ef100_get_dev_info,
608 .qsize_up_rings = sfc_ef100_tx_qsize_up_rings,
609 .qcreate = sfc_ef100_tx_qcreate,
610 .qdestroy = sfc_ef100_tx_qdestroy,
611 .qstart = sfc_ef100_tx_qstart,
612 .qtx_ev = sfc_ef100_tx_qtx_ev,
613 .qstop = sfc_ef100_tx_qstop,
614 .qreap = sfc_ef100_tx_qreap,
615 .qdesc_status = sfc_ef100_tx_qdesc_status,
616 .pkt_prepare = sfc_ef100_tx_prepare_pkts,
617 .pkt_burst = sfc_ef100_xmit_pkts,