1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2018-2019 Solarflare Communications Inc.
6 * This software was jointly developed between OKTET Labs (under contract
7 * for Solarflare) and Solarflare Communications, Inc.
17 #include "efx_types.h"
19 #include "efx_regs_ef100.h"
21 #include "sfc_debug.h"
22 #include "sfc_dp_tx.h"
23 #include "sfc_tweak.h"
24 #include "sfc_kvargs.h"
25 #include "sfc_ef100.h"
28 #define sfc_ef100_tx_err(_txq, ...) \
29 SFC_DP_LOG(SFC_KVARG_DATAPATH_EF100, ERR, &(_txq)->dp.dpq, __VA_ARGS__)
31 #define sfc_ef100_tx_debug(_txq, ...) \
32 SFC_DP_LOG(SFC_KVARG_DATAPATH_EF100, DEBUG, &(_txq)->dp.dpq, \
36 /** Maximum length of the send descriptor data */
37 #define SFC_EF100_TX_SEND_DESC_LEN_MAX \
38 ((1u << ESF_GZ_TX_SEND_LEN_WIDTH) - 1)
40 /** Maximum length of the segment descriptor data */
41 #define SFC_EF100_TX_SEG_DESC_LEN_MAX \
42 ((1u << ESF_GZ_TX_SEG_LEN_WIDTH) - 1)
45 * Maximum number of descriptors/buffers in the Tx ring.
46 * It should guarantee that corresponding event queue never overfill.
47 * EF100 native datapath uses event queue of the same size as Tx queue.
48 * Maximum number of events on datapath can be estimated as number of
49 * Tx queue entries (one event per Tx buffer in the worst case) plus
50 * Tx error and flush events.
52 #define SFC_EF100_TXQ_LIMIT(_ndesc) \
53 ((_ndesc) - 1 /* head must not step on tail */ - \
54 1 /* Rx error */ - 1 /* flush */)
56 struct sfc_ef100_tx_sw_desc {
57 struct rte_mbuf *mbuf;
60 struct sfc_ef100_txq {
62 #define SFC_EF100_TXQ_STARTED 0x1
63 #define SFC_EF100_TXQ_NOT_RUNNING 0x2
64 #define SFC_EF100_TXQ_EXCEPTION 0x4
66 unsigned int ptr_mask;
68 unsigned int completed;
69 unsigned int max_fill_level;
70 unsigned int free_thresh;
71 struct sfc_ef100_tx_sw_desc *sw_ring;
72 efx_oword_t *txq_hw_ring;
73 volatile void *doorbell;
76 unsigned int evq_read_ptr;
77 unsigned int evq_phase_bit_shift;
78 volatile efx_qword_t *evq_hw_ring;
80 uint16_t tso_tcp_header_offset_limit;
81 uint16_t tso_max_nb_header_descs;
82 uint16_t tso_max_header_len;
83 uint16_t tso_max_nb_payload_descs;
84 uint32_t tso_max_payload_len;
85 uint32_t tso_max_nb_outgoing_frames;
87 /* Datapath transmit queue anchor */
91 static inline struct sfc_ef100_txq *
92 sfc_ef100_txq_by_dp_txq(struct sfc_dp_txq *dp_txq)
94 return container_of(dp_txq, struct sfc_ef100_txq, dp);
98 sfc_ef100_tx_prepare_pkt_tso(struct sfc_ef100_txq * const txq,
101 size_t header_len = ((m->ol_flags & PKT_TX_TUNNEL_MASK) ?
102 m->outer_l2_len + m->outer_l3_len : 0) +
103 m->l2_len + m->l3_len + m->l4_len;
104 size_t payload_len = m->pkt_len - header_len;
105 unsigned long mss_conformant_max_payload_len;
106 unsigned int nb_payload_descs;
108 #ifdef RTE_LIBRTE_SFC_EFX_DEBUG
109 switch (m->ol_flags & PKT_TX_TUNNEL_MASK) {
112 case PKT_TX_TUNNEL_VXLAN:
114 case PKT_TX_TUNNEL_GENEVE:
121 mss_conformant_max_payload_len =
122 m->tso_segsz * txq->tso_max_nb_outgoing_frames;
125 * Don't really want to know exact number of payload segments.
126 * Just use total number of segments as upper limit. Practically
127 * maximum number of payload segments is significantly bigger
128 * than maximum number header segments, so we can neglect header
129 * segments excluded total number of segments to estimate number
130 * of payload segments required.
132 nb_payload_descs = m->nb_segs;
135 * Carry out multiple independent checks using bitwise OR
136 * to avoid unnecessary conditional branching.
138 if (unlikely((header_len > txq->tso_max_header_len) |
139 (nb_payload_descs > txq->tso_max_nb_payload_descs) |
140 (payload_len > txq->tso_max_payload_len) |
141 (payload_len > mss_conformant_max_payload_len) |
142 (m->pkt_len == header_len)))
149 sfc_ef100_tx_prepare_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
152 struct sfc_ef100_txq * const txq = sfc_ef100_txq_by_dp_txq(tx_queue);
155 for (i = 0; i < nb_pkts; i++) {
156 struct rte_mbuf *m = tx_pkts[i];
157 unsigned int max_nb_header_segs = 0;
158 bool calc_phdr_cksum = false;
162 * Partial checksum offload is used in the case of
163 * inner TCP/UDP checksum offload. It requires
164 * pseudo-header checksum which is calculated below,
165 * but requires contiguous packet headers.
167 if ((m->ol_flags & PKT_TX_TUNNEL_MASK) &&
168 (m->ol_flags & PKT_TX_L4_MASK)) {
169 calc_phdr_cksum = true;
170 max_nb_header_segs = 1;
171 } else if (m->ol_flags & PKT_TX_TCP_SEG) {
172 max_nb_header_segs = txq->tso_max_nb_header_descs;
175 ret = sfc_dp_tx_prepare_pkt(m, max_nb_header_segs, 0,
176 txq->tso_tcp_header_offset_limit,
177 txq->max_fill_level, 1, 0);
178 if (unlikely(ret != 0)) {
183 if (m->ol_flags & PKT_TX_TCP_SEG) {
184 ret = sfc_ef100_tx_prepare_pkt_tso(txq, m);
185 if (unlikely(ret != 0)) {
189 } else if (m->nb_segs > EFX_MASK32(ESF_GZ_TX_SEND_NUM_SEGS)) {
194 if (calc_phdr_cksum) {
196 * Full checksum offload does IPv4 header checksum
197 * and does not require any assistance.
199 ret = rte_net_intel_cksum_flags_prepare(m,
200 m->ol_flags & ~PKT_TX_IP_CKSUM);
201 if (unlikely(ret != 0)) {
212 sfc_ef100_tx_get_event(struct sfc_ef100_txq *txq, efx_qword_t *ev)
214 volatile efx_qword_t *evq_hw_ring = txq->evq_hw_ring;
217 * Exception flag is set when reap is done.
218 * It is never done twice per packet burst get, and absence of
219 * the flag is checked on burst get entry.
221 SFC_ASSERT((txq->flags & SFC_EF100_TXQ_EXCEPTION) == 0);
223 *ev = evq_hw_ring[txq->evq_read_ptr & txq->ptr_mask];
225 if (!sfc_ef100_ev_present(ev,
226 (txq->evq_read_ptr >> txq->evq_phase_bit_shift) & 1))
229 if (unlikely(!sfc_ef100_ev_type_is(ev,
230 ESE_GZ_EF100_EV_TX_COMPLETION))) {
232 * Do not move read_ptr to keep the event for exception
233 * handling by the control path.
235 txq->flags |= SFC_EF100_TXQ_EXCEPTION;
236 sfc_ef100_tx_err(txq,
237 "TxQ exception at EvQ ptr %u(%#x), event %08x:%08x",
238 txq->evq_read_ptr, txq->evq_read_ptr & txq->ptr_mask,
239 EFX_QWORD_FIELD(*ev, EFX_DWORD_1),
240 EFX_QWORD_FIELD(*ev, EFX_DWORD_0));
244 sfc_ef100_tx_debug(txq, "TxQ got event %08x:%08x at %u (%#x)",
245 EFX_QWORD_FIELD(*ev, EFX_DWORD_1),
246 EFX_QWORD_FIELD(*ev, EFX_DWORD_0),
248 txq->evq_read_ptr & txq->ptr_mask);
255 sfc_ef100_tx_process_events(struct sfc_ef100_txq *txq)
257 unsigned int num_descs = 0;
260 while (sfc_ef100_tx_get_event(txq, &tx_ev))
261 num_descs += EFX_QWORD_FIELD(tx_ev, ESF_GZ_EV_TXCMPL_NUM_DESC);
267 sfc_ef100_tx_reap_num_descs(struct sfc_ef100_txq *txq, unsigned int num_descs)
270 unsigned int completed = txq->completed;
271 unsigned int pending = completed + num_descs;
272 struct rte_mbuf *bulk[SFC_TX_REAP_BULK_SIZE];
276 struct sfc_ef100_tx_sw_desc *txd;
279 txd = &txq->sw_ring[completed & txq->ptr_mask];
280 if (txd->mbuf == NULL)
283 m = rte_pktmbuf_prefree_seg(txd->mbuf);
289 if (nb == RTE_DIM(bulk) ||
290 (nb != 0 && m->pool != bulk[0]->pool)) {
291 rte_mempool_put_bulk(bulk[0]->pool,
297 } while (++completed != pending);
300 rte_mempool_put_bulk(bulk[0]->pool, (void *)bulk, nb);
302 txq->completed = completed;
307 sfc_ef100_tx_reap(struct sfc_ef100_txq *txq)
309 sfc_ef100_tx_reap_num_descs(txq, sfc_ef100_tx_process_events(txq));
313 sfc_ef100_tx_qdesc_cso_inner_l3(uint64_t tx_tunnel)
318 case PKT_TX_TUNNEL_VXLAN:
319 inner_l3 = ESE_GZ_TX_DESC_CS_INNER_L3_VXLAN;
321 case PKT_TX_TUNNEL_GENEVE:
322 inner_l3 = ESE_GZ_TX_DESC_CS_INNER_L3_GENEVE;
325 inner_l3 = ESE_GZ_TX_DESC_CS_INNER_L3_OFF;
332 sfc_ef100_tx_qdesc_send_create(const struct rte_mbuf *m, efx_oword_t *tx_desc)
338 uint16_t part_cksum_w;
339 uint16_t l4_offset_w;
341 if ((m->ol_flags & PKT_TX_TUNNEL_MASK) == 0) {
342 outer_l3 = (m->ol_flags & PKT_TX_IP_CKSUM);
343 outer_l4 = (m->ol_flags & PKT_TX_L4_MASK);
344 inner_l3 = ESE_GZ_TX_DESC_CS_INNER_L3_OFF;
345 partial_en = ESE_GZ_TX_DESC_CSO_PARTIAL_EN_OFF;
349 outer_l3 = (m->ol_flags & PKT_TX_OUTER_IP_CKSUM);
350 outer_l4 = (m->ol_flags & PKT_TX_OUTER_UDP_CKSUM);
351 inner_l3 = sfc_ef100_tx_qdesc_cso_inner_l3(m->ol_flags &
354 switch (m->ol_flags & PKT_TX_L4_MASK) {
355 case PKT_TX_TCP_CKSUM:
356 partial_en = ESE_GZ_TX_DESC_CSO_PARTIAL_EN_TCP;
357 part_cksum_w = offsetof(struct rte_tcp_hdr, cksum) >> 1;
359 case PKT_TX_UDP_CKSUM:
360 partial_en = ESE_GZ_TX_DESC_CSO_PARTIAL_EN_UDP;
361 part_cksum_w = offsetof(struct rte_udp_hdr,
365 partial_en = ESE_GZ_TX_DESC_CSO_PARTIAL_EN_OFF;
369 l4_offset_w = (m->outer_l2_len + m->outer_l3_len +
370 m->l2_len + m->l3_len) >> 1;
373 EFX_POPULATE_OWORD_10(*tx_desc,
374 ESF_GZ_TX_SEND_ADDR, rte_mbuf_data_iova(m),
375 ESF_GZ_TX_SEND_LEN, rte_pktmbuf_data_len(m),
376 ESF_GZ_TX_SEND_NUM_SEGS, m->nb_segs,
377 ESF_GZ_TX_SEND_CSO_PARTIAL_START_W, l4_offset_w,
378 ESF_GZ_TX_SEND_CSO_PARTIAL_CSUM_W, part_cksum_w,
379 ESF_GZ_TX_SEND_CSO_PARTIAL_EN, partial_en,
380 ESF_GZ_TX_SEND_CSO_INNER_L3, inner_l3,
381 ESF_GZ_TX_SEND_CSO_OUTER_L3, outer_l3,
382 ESF_GZ_TX_SEND_CSO_OUTER_L4, outer_l4,
383 ESF_GZ_TX_DESC_TYPE, ESE_GZ_TX_DESC_TYPE_SEND);
387 sfc_ef100_tx_qdesc_seg_create(rte_iova_t addr, uint16_t len,
388 efx_oword_t *tx_desc)
390 EFX_POPULATE_OWORD_3(*tx_desc,
391 ESF_GZ_TX_SEG_ADDR, addr,
392 ESF_GZ_TX_SEG_LEN, len,
393 ESF_GZ_TX_DESC_TYPE, ESE_GZ_TX_DESC_TYPE_SEG);
397 sfc_ef100_tx_qdesc_tso_create(const struct rte_mbuf *m,
398 uint16_t nb_header_descs,
399 uint16_t nb_payload_descs,
400 size_t header_len, size_t payload_len,
401 size_t outer_iph_off, size_t outer_udph_off,
402 size_t iph_off, size_t tcph_off,
403 efx_oword_t *tx_desc)
405 efx_oword_t tx_desc_extra_fields;
406 int ed_outer_udp_len = (outer_udph_off != 0) ? 1 : 0;
407 int ed_outer_ip_len = (outer_iph_off != 0) ? 1 : 0;
408 int ed_outer_ip_id = (outer_iph_off != 0) ?
409 ESE_GZ_TX_DESC_IP4_ID_INC_MOD16 : 0;
411 * If no tunnel encapsulation is present, then the ED_INNER
412 * fields should be used.
414 int ed_inner_ip_id = ESE_GZ_TX_DESC_IP4_ID_INC_MOD16;
415 uint8_t inner_l3 = sfc_ef100_tx_qdesc_cso_inner_l3(
416 m->ol_flags & PKT_TX_TUNNEL_MASK);
418 EFX_POPULATE_OWORD_10(*tx_desc,
419 ESF_GZ_TX_TSO_MSS, m->tso_segsz,
420 ESF_GZ_TX_TSO_HDR_NUM_SEGS, nb_header_descs,
421 ESF_GZ_TX_TSO_PAYLOAD_NUM_SEGS, nb_payload_descs,
422 ESF_GZ_TX_TSO_ED_OUTER_IP4_ID, ed_outer_ip_id,
423 ESF_GZ_TX_TSO_ED_INNER_IP4_ID, ed_inner_ip_id,
424 ESF_GZ_TX_TSO_ED_OUTER_IP_LEN, ed_outer_ip_len,
425 ESF_GZ_TX_TSO_ED_INNER_IP_LEN, 1,
426 ESF_GZ_TX_TSO_ED_OUTER_UDP_LEN, ed_outer_udp_len,
427 ESF_GZ_TX_TSO_HDR_LEN_W, header_len >> 1,
428 ESF_GZ_TX_TSO_PAYLOAD_LEN, payload_len);
430 EFX_POPULATE_OWORD_9(tx_desc_extra_fields,
432 * Outer offsets are required for outer IPv4 ID
433 * and length edits in the case of tunnel TSO.
435 ESF_GZ_TX_TSO_OUTER_L3_OFF_W, outer_iph_off >> 1,
436 ESF_GZ_TX_TSO_OUTER_L4_OFF_W, outer_udph_off >> 1,
438 * Inner offsets are required for inner IPv4 ID
439 * and IP length edits and partial checksum
440 * offload in the case of tunnel TSO.
442 ESF_GZ_TX_TSO_INNER_L3_OFF_W, iph_off >> 1,
443 ESF_GZ_TX_TSO_INNER_L4_OFF_W, tcph_off >> 1,
444 ESF_GZ_TX_TSO_CSO_INNER_L4,
445 inner_l3 != ESE_GZ_TX_DESC_CS_INNER_L3_OFF,
446 ESF_GZ_TX_TSO_CSO_INNER_L3, inner_l3,
448 * Use outer full checksum offloads which do
449 * not require any extra information.
451 ESF_GZ_TX_TSO_CSO_OUTER_L3, 1,
452 ESF_GZ_TX_TSO_CSO_OUTER_L4, 1,
453 ESF_GZ_TX_DESC_TYPE, ESE_GZ_TX_DESC_TYPE_TSO);
455 EFX_OR_OWORD(*tx_desc, tx_desc_extra_fields);
459 sfc_ef100_tx_qpush(struct sfc_ef100_txq *txq, unsigned int added)
463 EFX_POPULATE_DWORD_1(dword, ERF_GZ_TX_RING_PIDX, added & txq->ptr_mask);
465 /* DMA sync to device is not required */
468 * rte_write32() has rte_io_wmb() which guarantees that the STORE
469 * operations (i.e. Rx and event descriptor updates) that precede
470 * the rte_io_wmb() call are visible to NIC before the STORE
471 * operations that follow it (i.e. doorbell write).
473 rte_write32(dword.ed_u32[0], txq->doorbell);
475 sfc_ef100_tx_debug(txq, "TxQ pushed doorbell at pidx %u (added=%u)",
476 EFX_DWORD_FIELD(dword, ERF_GZ_TX_RING_PIDX),
481 sfc_ef100_tx_pkt_descs_max(const struct rte_mbuf *m)
483 unsigned int extra_descs = 0;
485 /** Maximum length of an mbuf segment data */
486 #define SFC_MBUF_SEG_LEN_MAX UINT16_MAX
487 RTE_BUILD_BUG_ON(sizeof(m->data_len) != 2);
489 if (m->ol_flags & PKT_TX_TCP_SEG) {
490 /* Tx TSO descriptor */
493 * Extra Tx segment descriptor may be required if header
494 * ends in the middle of segment.
499 * mbuf segment cannot be bigger than maximum segment length
500 * and maximum packet length since TSO is not supported yet.
501 * Make sure that the first segment does not need fragmentation
502 * (split into many Tx descriptors).
504 RTE_BUILD_BUG_ON(SFC_EF100_TX_SEND_DESC_LEN_MAX <
505 RTE_MIN((unsigned int)EFX_MAC_PDU_MAX,
506 SFC_MBUF_SEG_LEN_MAX));
510 * Any segment of scattered packet cannot be bigger than maximum
511 * segment length. Make sure that subsequent segments do not need
512 * fragmentation (split into many Tx descriptors).
514 RTE_BUILD_BUG_ON(SFC_EF100_TX_SEG_DESC_LEN_MAX < SFC_MBUF_SEG_LEN_MAX);
516 return m->nb_segs + extra_descs;
519 static struct rte_mbuf *
520 sfc_ef100_xmit_tso_pkt(struct sfc_ef100_txq * const txq,
521 struct rte_mbuf *m, unsigned int *added)
523 struct rte_mbuf *m_seg = m;
524 unsigned int nb_hdr_descs;
525 unsigned int nb_pld_descs;
526 unsigned int seg_split = 0;
527 unsigned int tso_desc_id;
529 size_t outer_iph_off;
530 size_t outer_udph_off;
534 size_t remaining_hdr_len;
536 if (m->ol_flags & PKT_TX_TUNNEL_MASK) {
537 outer_iph_off = m->outer_l2_len;
538 outer_udph_off = outer_iph_off + m->outer_l3_len;
543 iph_off = outer_udph_off + m->l2_len;
544 tcph_off = iph_off + m->l3_len;
545 header_len = tcph_off + m->l4_len;
548 * Remember ID of the TX_TSO descriptor to be filled in.
549 * We can't fill it in right now since we need to calculate
550 * number of header and payload segments first and don't want
551 * to traverse it twice here.
553 tso_desc_id = (*added)++ & txq->ptr_mask;
555 remaining_hdr_len = header_len;
557 id = (*added)++ & txq->ptr_mask;
558 if (rte_pktmbuf_data_len(m_seg) <= remaining_hdr_len) {
559 /* The segment is fully header segment */
560 sfc_ef100_tx_qdesc_seg_create(
561 rte_mbuf_data_iova(m_seg),
562 rte_pktmbuf_data_len(m_seg),
563 &txq->txq_hw_ring[id]);
564 remaining_hdr_len -= rte_pktmbuf_data_len(m_seg);
567 * The segment must be split into header and
570 sfc_ef100_tx_qdesc_seg_create(
571 rte_mbuf_data_iova(m_seg),
573 &txq->txq_hw_ring[id]);
574 SFC_ASSERT(txq->sw_ring[id].mbuf == NULL);
576 id = (*added)++ & txq->ptr_mask;
577 sfc_ef100_tx_qdesc_seg_create(
578 rte_mbuf_data_iova(m_seg) + remaining_hdr_len,
579 rte_pktmbuf_data_len(m_seg) - remaining_hdr_len,
580 &txq->txq_hw_ring[id]);
581 remaining_hdr_len = 0;
584 txq->sw_ring[id].mbuf = m_seg;
586 } while (remaining_hdr_len > 0);
589 * If a segment is split into header and payload segments, added
590 * pointer counts it twice and we should correct it.
592 nb_hdr_descs = ((id - tso_desc_id) & txq->ptr_mask) - seg_split;
593 nb_pld_descs = m->nb_segs - nb_hdr_descs + seg_split;
595 sfc_ef100_tx_qdesc_tso_create(m, nb_hdr_descs, nb_pld_descs, header_len,
596 rte_pktmbuf_pkt_len(m) - header_len,
597 outer_iph_off, outer_udph_off,
599 &txq->txq_hw_ring[tso_desc_id]);
605 sfc_ef100_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
607 struct sfc_ef100_txq * const txq = sfc_ef100_txq_by_dp_txq(tx_queue);
609 unsigned int dma_desc_space;
611 struct rte_mbuf **pktp;
612 struct rte_mbuf **pktp_end;
614 if (unlikely(txq->flags &
615 (SFC_EF100_TXQ_NOT_RUNNING | SFC_EF100_TXQ_EXCEPTION)))
619 dma_desc_space = txq->max_fill_level - (added - txq->completed);
621 reap_done = (dma_desc_space < txq->free_thresh);
623 sfc_ef100_tx_reap(txq);
624 dma_desc_space = txq->max_fill_level - (added - txq->completed);
627 for (pktp = &tx_pkts[0], pktp_end = &tx_pkts[nb_pkts];
630 struct rte_mbuf *m_seg = *pktp;
631 unsigned int pkt_start = added;
634 if (likely(pktp + 1 != pktp_end))
635 rte_mbuf_prefetch_part1(pktp[1]);
637 if (sfc_ef100_tx_pkt_descs_max(m_seg) > dma_desc_space) {
641 /* Push already prepared descriptors before polling */
642 if (added != txq->added) {
643 sfc_ef100_tx_qpush(txq, added);
647 sfc_ef100_tx_reap(txq);
649 dma_desc_space = txq->max_fill_level -
650 (added - txq->completed);
651 if (sfc_ef100_tx_pkt_descs_max(m_seg) > dma_desc_space)
655 if (m_seg->ol_flags & PKT_TX_TCP_SEG) {
656 m_seg = sfc_ef100_xmit_tso_pkt(txq, m_seg, &added);
658 id = added++ & txq->ptr_mask;
659 sfc_ef100_tx_qdesc_send_create(m_seg,
660 &txq->txq_hw_ring[id]);
663 * rte_pktmbuf_free() is commonly used in DPDK for
664 * recycling packets - the function checks every
665 * segment's reference counter and returns the
666 * buffer to its pool whenever possible;
667 * nevertheless, freeing mbuf segments one by one
668 * may entail some performance decline;
669 * from this point, sfc_efx_tx_reap() does the same job
670 * on its own and frees buffers in bulks (all mbufs
671 * within a bulk belong to the same pool);
672 * from this perspective, individual segment pointers
673 * must be associated with the corresponding SW
674 * descriptors independently so that only one loop
675 * is sufficient on reap to inspect all the buffers
677 txq->sw_ring[id].mbuf = m_seg;
681 while (m_seg != NULL) {
682 RTE_BUILD_BUG_ON(SFC_MBUF_SEG_LEN_MAX >
683 SFC_EF100_TX_SEG_DESC_LEN_MAX);
685 id = added++ & txq->ptr_mask;
686 sfc_ef100_tx_qdesc_seg_create(rte_mbuf_data_iova(m_seg),
687 rte_pktmbuf_data_len(m_seg),
688 &txq->txq_hw_ring[id]);
689 txq->sw_ring[id].mbuf = m_seg;
693 dma_desc_space -= (added - pkt_start);
696 if (likely(added != txq->added)) {
697 sfc_ef100_tx_qpush(txq, added);
701 #if SFC_TX_XMIT_PKTS_REAP_AT_LEAST_ONCE
703 sfc_ef100_tx_reap(txq);
706 return pktp - &tx_pkts[0];
709 static sfc_dp_tx_get_dev_info_t sfc_ef100_get_dev_info;
711 sfc_ef100_get_dev_info(struct rte_eth_dev_info *dev_info)
714 * Number of descriptors just defines maximum number of pushed
715 * descriptors (fill level).
717 dev_info->tx_desc_lim.nb_min = 1;
718 dev_info->tx_desc_lim.nb_align = 1;
721 static sfc_dp_tx_qsize_up_rings_t sfc_ef100_tx_qsize_up_rings;
723 sfc_ef100_tx_qsize_up_rings(uint16_t nb_tx_desc,
724 struct sfc_dp_tx_hw_limits *limits,
725 unsigned int *txq_entries,
726 unsigned int *evq_entries,
727 unsigned int *txq_max_fill_level)
730 * rte_ethdev API guarantees that the number meets min, max and
731 * alignment requirements.
733 if (nb_tx_desc <= limits->txq_min_entries)
734 *txq_entries = limits->txq_min_entries;
736 *txq_entries = rte_align32pow2(nb_tx_desc);
738 *evq_entries = *txq_entries;
740 *txq_max_fill_level = RTE_MIN(nb_tx_desc,
741 SFC_EF100_TXQ_LIMIT(*evq_entries));
745 static sfc_dp_tx_qcreate_t sfc_ef100_tx_qcreate;
747 sfc_ef100_tx_qcreate(uint16_t port_id, uint16_t queue_id,
748 const struct rte_pci_addr *pci_addr, int socket_id,
749 const struct sfc_dp_tx_qcreate_info *info,
750 struct sfc_dp_txq **dp_txqp)
752 struct sfc_ef100_txq *txq;
756 if (info->txq_entries != info->evq_entries)
760 txq = rte_zmalloc_socket("sfc-ef100-txq", sizeof(*txq),
761 RTE_CACHE_LINE_SIZE, socket_id);
765 sfc_dp_queue_init(&txq->dp.dpq, port_id, queue_id, pci_addr);
768 txq->sw_ring = rte_calloc_socket("sfc-ef100-txq-sw_ring",
770 sizeof(*txq->sw_ring),
771 RTE_CACHE_LINE_SIZE, socket_id);
772 if (txq->sw_ring == NULL)
773 goto fail_sw_ring_alloc;
775 txq->flags = SFC_EF100_TXQ_NOT_RUNNING;
776 txq->ptr_mask = info->txq_entries - 1;
777 txq->max_fill_level = info->max_fill_level;
778 txq->free_thresh = info->free_thresh;
779 txq->evq_phase_bit_shift = rte_bsf32(info->evq_entries);
780 txq->txq_hw_ring = info->txq_hw_ring;
781 txq->doorbell = (volatile uint8_t *)info->mem_bar +
782 ER_GZ_TX_RING_DOORBELL_OFST +
783 (info->hw_index << info->vi_window_shift);
784 txq->evq_hw_ring = info->evq_hw_ring;
786 txq->tso_tcp_header_offset_limit = info->tso_tcp_header_offset_limit;
787 txq->tso_max_nb_header_descs = info->tso_max_nb_header_descs;
788 txq->tso_max_header_len = info->tso_max_header_len;
789 txq->tso_max_nb_payload_descs = info->tso_max_nb_payload_descs;
790 txq->tso_max_payload_len = info->tso_max_payload_len;
791 txq->tso_max_nb_outgoing_frames = info->tso_max_nb_outgoing_frames;
793 sfc_ef100_tx_debug(txq, "TxQ doorbell is %p", txq->doorbell);
806 static sfc_dp_tx_qdestroy_t sfc_ef100_tx_qdestroy;
808 sfc_ef100_tx_qdestroy(struct sfc_dp_txq *dp_txq)
810 struct sfc_ef100_txq *txq = sfc_ef100_txq_by_dp_txq(dp_txq);
812 rte_free(txq->sw_ring);
816 static sfc_dp_tx_qstart_t sfc_ef100_tx_qstart;
818 sfc_ef100_tx_qstart(struct sfc_dp_txq *dp_txq, unsigned int evq_read_ptr,
819 unsigned int txq_desc_index)
821 struct sfc_ef100_txq *txq = sfc_ef100_txq_by_dp_txq(dp_txq);
823 txq->evq_read_ptr = evq_read_ptr;
824 txq->added = txq->completed = txq_desc_index;
826 txq->flags |= SFC_EF100_TXQ_STARTED;
827 txq->flags &= ~(SFC_EF100_TXQ_NOT_RUNNING | SFC_EF100_TXQ_EXCEPTION);
832 static sfc_dp_tx_qstop_t sfc_ef100_tx_qstop;
834 sfc_ef100_tx_qstop(struct sfc_dp_txq *dp_txq, unsigned int *evq_read_ptr)
836 struct sfc_ef100_txq *txq = sfc_ef100_txq_by_dp_txq(dp_txq);
838 txq->flags |= SFC_EF100_TXQ_NOT_RUNNING;
840 *evq_read_ptr = txq->evq_read_ptr;
843 static sfc_dp_tx_qtx_ev_t sfc_ef100_tx_qtx_ev;
845 sfc_ef100_tx_qtx_ev(struct sfc_dp_txq *dp_txq, unsigned int num_descs)
847 struct sfc_ef100_txq *txq = sfc_ef100_txq_by_dp_txq(dp_txq);
849 SFC_ASSERT(txq->flags & SFC_EF100_TXQ_NOT_RUNNING);
851 sfc_ef100_tx_reap_num_descs(txq, num_descs);
856 static sfc_dp_tx_qreap_t sfc_ef100_tx_qreap;
858 sfc_ef100_tx_qreap(struct sfc_dp_txq *dp_txq)
860 struct sfc_ef100_txq *txq = sfc_ef100_txq_by_dp_txq(dp_txq);
861 unsigned int completed;
863 for (completed = txq->completed; completed != txq->added; ++completed) {
864 struct sfc_ef100_tx_sw_desc *txd;
866 txd = &txq->sw_ring[completed & txq->ptr_mask];
867 if (txd->mbuf != NULL) {
868 rte_pktmbuf_free_seg(txd->mbuf);
873 txq->flags &= ~SFC_EF100_TXQ_STARTED;
877 sfc_ef100_tx_qdesc_npending(struct sfc_ef100_txq *txq)
879 const unsigned int evq_old_read_ptr = txq->evq_read_ptr;
880 unsigned int npending = 0;
883 if (unlikely(txq->flags &
884 (SFC_EF100_TXQ_NOT_RUNNING | SFC_EF100_TXQ_EXCEPTION)))
887 while (sfc_ef100_tx_get_event(txq, &tx_ev))
888 npending += EFX_QWORD_FIELD(tx_ev, ESF_GZ_EV_TXCMPL_NUM_DESC);
891 * The function does not process events, so return event queue read
892 * pointer to the original position to allow the events that were
893 * read to be processed later
895 txq->evq_read_ptr = evq_old_read_ptr;
900 static sfc_dp_tx_qdesc_status_t sfc_ef100_tx_qdesc_status;
902 sfc_ef100_tx_qdesc_status(struct sfc_dp_txq *dp_txq, uint16_t offset)
904 struct sfc_ef100_txq *txq = sfc_ef100_txq_by_dp_txq(dp_txq);
905 unsigned int pushed = txq->added - txq->completed;
907 if (unlikely(offset > txq->ptr_mask))
910 if (unlikely(offset >= txq->max_fill_level))
911 return RTE_ETH_TX_DESC_UNAVAIL;
913 return (offset >= pushed ||
914 offset < sfc_ef100_tx_qdesc_npending(txq)) ?
915 RTE_ETH_TX_DESC_DONE : RTE_ETH_TX_DESC_FULL;
918 struct sfc_dp_tx sfc_ef100_tx = {
920 .name = SFC_KVARG_DATAPATH_EF100,
922 .hw_fw_caps = SFC_DP_HW_FW_CAP_EF100,
924 .features = SFC_DP_TX_FEAT_MULTI_PROCESS,
925 .dev_offload_capa = 0,
926 .queue_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
927 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
928 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM |
929 DEV_TX_OFFLOAD_UDP_CKSUM |
930 DEV_TX_OFFLOAD_TCP_CKSUM |
931 DEV_TX_OFFLOAD_MULTI_SEGS |
932 DEV_TX_OFFLOAD_TCP_TSO |
933 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
934 DEV_TX_OFFLOAD_GENEVE_TNL_TSO,
935 .get_dev_info = sfc_ef100_get_dev_info,
936 .qsize_up_rings = sfc_ef100_tx_qsize_up_rings,
937 .qcreate = sfc_ef100_tx_qcreate,
938 .qdestroy = sfc_ef100_tx_qdestroy,
939 .qstart = sfc_ef100_tx_qstart,
940 .qtx_ev = sfc_ef100_tx_qtx_ev,
941 .qstop = sfc_ef100_tx_qstop,
942 .qreap = sfc_ef100_tx_qreap,
943 .qdesc_status = sfc_ef100_tx_qdesc_status,
944 .pkt_prepare = sfc_ef100_tx_prepare_pkts,
945 .pkt_burst = sfc_ef100_xmit_pkts,