drivers/net/sfc/sfc_ef10_essb_rx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2017-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  *
   6  * This software was jointly developed between OKTET Labs (under contract
   7  * for Solarflare) and Solarflare Communications, Inc.
   8  */
   9
  10 /* EF10 equal stride packed stream receive native datapath implementation */
  11
  12 #include <stdbool.h>
  13
  14 #include <rte_byteorder.h>
  15 #include <rte_mbuf_ptype.h>
  16 #include <rte_mbuf.h>
  17 #include <rte_io.h>
  18
  19 #include "efx.h"
  20 #include "efx_types.h"
  21 #include "efx_regs.h"
  22 #include "efx_regs_ef10.h"
  23
  24 #include "sfc_tweak.h"
  25 #include "sfc_dp_rx.h"
  26 #include "sfc_kvargs.h"
  27 #include "sfc_ef10.h"
  28
  29 /* Tunnels are not supported */
  30 #define SFC_EF10_RX_EV_ENCAP_SUPPORT    0
  31 #include "sfc_ef10_rx_ev.h"
  32
  33 #define sfc_ef10_essb_rx_err(dpq, ...) \
  34         SFC_DP_LOG(SFC_KVARG_DATAPATH_EF10_ESSB, ERR, dpq, __VA_ARGS__)
  35
  36 #define sfc_ef10_essb_rx_info(dpq, ...) \
  37         SFC_DP_LOG(SFC_KVARG_DATAPATH_EF10_ESSB, INFO, dpq, __VA_ARGS__)
  38
  39 /*
  40  * Fake length for RXQ descriptors in equal stride super-buffer mode
  41  * to make hardware happy.
  42  */
  43 #define SFC_EF10_ESSB_RX_FAKE_BUF_SIZE  32
  44
  45 /**
  46  * Maximum number of descriptors/buffers in the Rx ring.
  47  * It should guarantee that corresponding event queue never overfill.
  48  */
  49 #define SFC_EF10_ESSB_RXQ_LIMIT(_nevs) \
  50         ((_nevs) - 1 /* head must not step on tail */ - \
  51          (SFC_EF10_EV_PER_CACHE_LINE - 1) /* max unused EvQ entries */ - \
  52          1 /* Rx error */ - 1 /* flush */)
  53
  54 struct sfc_ef10_essb_rx_sw_desc {
  55         struct rte_mbuf                 *first_mbuf;
  56 };
  57
  58 struct sfc_ef10_essb_rxq {
  59         /* Used on data path */
  60         unsigned int                    flags;
  61 #define SFC_EF10_ESSB_RXQ_STARTED       0x1
  62 #define SFC_EF10_ESSB_RXQ_NOT_RUNNING   0x2
  63 #define SFC_EF10_ESSB_RXQ_EXCEPTION     0x4
  64         unsigned int                    rxq_ptr_mask;
  65         unsigned int                    block_size;
  66         unsigned int                    buf_stride;
  67         unsigned int                    bufs_ptr;
  68         unsigned int                    completed;
  69         unsigned int                    pending_id;
  70         unsigned int                    bufs_pending;
  71         unsigned int                    left_in_completed;
  72         unsigned int                    left_in_pending;
  73         unsigned int                    evq_read_ptr;
  74         unsigned int                    evq_ptr_mask;
  75         efx_qword_t                     *evq_hw_ring;
  76         struct sfc_ef10_essb_rx_sw_desc *sw_ring;
  77         uint16_t                        port_id;
  78
  79         /* Used on refill */
  80         unsigned int                    added;
  81         unsigned int                    max_fill_level;
  82         unsigned int                    refill_threshold;
  83         struct rte_mempool              *refill_mb_pool;
  84         efx_qword_t                     *rxq_hw_ring;
  85         volatile void                   *doorbell;
  86
  87         /* Datapath receive queue anchor */
  88         struct sfc_dp_rxq               dp;
  89 };
  90
  91 static inline struct sfc_ef10_essb_rxq *
  92 sfc_ef10_essb_rxq_by_dp_rxq(struct sfc_dp_rxq *dp_rxq)
  93 {
  94         return container_of(dp_rxq, struct sfc_ef10_essb_rxq, dp);
  95 }
  96
  97 static struct rte_mbuf *
  98 sfc_ef10_essb_next_mbuf(const struct sfc_ef10_essb_rxq *rxq,
  99                         struct rte_mbuf *mbuf)
 100 {
 101         return (struct rte_mbuf *)((uintptr_t)mbuf + rxq->buf_stride);
 102 }
 103
 104 static struct rte_mbuf *
 105 sfc_ef10_essb_mbuf_by_index(const struct sfc_ef10_essb_rxq *rxq,
 106                             struct rte_mbuf *mbuf, unsigned int idx)
 107 {
 108         return (struct rte_mbuf *)((uintptr_t)mbuf + idx * rxq->buf_stride);
 109 }
 110
 111 static struct rte_mbuf *
 112 sfc_ef10_essb_maybe_next_completed(struct sfc_ef10_essb_rxq *rxq)
 113 {
 114         const struct sfc_ef10_essb_rx_sw_desc *rxd;
 115
 116         if (rxq->left_in_completed != 0) {
 117                 rxd = &rxq->sw_ring[rxq->completed & rxq->rxq_ptr_mask];
 118                 return sfc_ef10_essb_mbuf_by_index(rxq, rxd->first_mbuf,
 119                                 rxq->block_size - rxq->left_in_completed);
 120         } else {
 121                 rxq->completed++;
 122                 rxd = &rxq->sw_ring[rxq->completed & rxq->rxq_ptr_mask];
 123                 rxq->left_in_completed = rxq->block_size;
 124                 return rxd->first_mbuf;
 125         }
 126 }
 127
 128 static void
 129 sfc_ef10_essb_rx_qrefill(struct sfc_ef10_essb_rxq *rxq)
 130 {
 131         const unsigned int rxq_ptr_mask = rxq->rxq_ptr_mask;
 132         unsigned int free_space;
 133         unsigned int bulks;
 134         void *mbuf_blocks[SFC_EF10_RX_WPTR_ALIGN];
 135         unsigned int added = rxq->added;
 136
 137         free_space = rxq->max_fill_level - (added - rxq->completed);
 138
 139         if (free_space < rxq->refill_threshold)
 140                 return;
 141
 142         bulks = free_space / RTE_DIM(mbuf_blocks);
 143         /* refill_threshold guarantees that bulks is positive */
 144         SFC_ASSERT(bulks > 0);
 145
 146         do {
 147                 unsigned int id;
 148                 unsigned int i;
 149
 150                 if (unlikely(rte_mempool_get_contig_blocks(rxq->refill_mb_pool,
 151                                 mbuf_blocks, RTE_DIM(mbuf_blocks)) < 0)) {
 152                         struct rte_eth_dev_data *dev_data =
 153                                 rte_eth_devices[rxq->port_id].data;
 154
 155                         /*
 156                          * It is hardly a safe way to increment counter
 157                          * from different contexts, but all PMDs do it.
 158                          */
 159                         dev_data->rx_mbuf_alloc_failed += RTE_DIM(mbuf_blocks);
 160                         /* Return if we have posted nothing yet */
 161                         if (added == rxq->added)
 162                                 return;
 163                         /* Push posted */
 164                         break;
 165                 }
 166
 167                 for (i = 0, id = added & rxq_ptr_mask;
 168                      i < RTE_DIM(mbuf_blocks);
 169                      ++i, ++id) {
 170                         struct rte_mbuf *m = mbuf_blocks[i];
 171                         struct sfc_ef10_essb_rx_sw_desc *rxd;
 172
 173                         SFC_ASSERT((id & ~rxq_ptr_mask) == 0);
 174                         rxd = &rxq->sw_ring[id];
 175                         rxd->first_mbuf = m;
 176
 177                         /* RX_KER_BYTE_CNT is ignored by firmware */
 178                         EFX_POPULATE_QWORD_2(rxq->rxq_hw_ring[id],
 179                                              ESF_DZ_RX_KER_BYTE_CNT,
 180                                              SFC_EF10_ESSB_RX_FAKE_BUF_SIZE,
 181                                              ESF_DZ_RX_KER_BUF_ADDR,
 182                                              rte_mbuf_data_iova_default(m));
 183                 }
 184
 185                 added += RTE_DIM(mbuf_blocks);
 186
 187         } while (--bulks > 0);
 188
 189         SFC_ASSERT(rxq->added != added);
 190         rxq->added = added;
 191         sfc_ef10_rx_qpush(rxq->doorbell, added, rxq_ptr_mask);
 192 }
 193
 194 static bool
 195 sfc_ef10_essb_rx_event_get(struct sfc_ef10_essb_rxq *rxq, efx_qword_t *rx_ev)
 196 {
 197         *rx_ev = rxq->evq_hw_ring[rxq->evq_read_ptr & rxq->evq_ptr_mask];
 198
 199         if (!sfc_ef10_ev_present(*rx_ev))
 200                 return false;
 201
 202         if (unlikely(EFX_QWORD_FIELD(*rx_ev, FSF_AZ_EV_CODE) !=
 203                      FSE_AZ_EV_CODE_RX_EV)) {
 204                 /*
 205                  * Do not move read_ptr to keep the event for exception
 206                  * handling
 207                  */
 208                 rxq->flags |= SFC_EF10_ESSB_RXQ_EXCEPTION;
 209                 sfc_ef10_essb_rx_err(&rxq->dp.dpq,
 210                                      "RxQ exception at EvQ read ptr %#x",
 211                                      rxq->evq_read_ptr);
 212                 return false;
 213         }
 214
 215         rxq->evq_read_ptr++;
 216         return true;
 217 }
 218
 219 static void
 220 sfc_ef10_essb_rx_process_ev(struct sfc_ef10_essb_rxq *rxq, efx_qword_t rx_ev)
 221 {
 222         unsigned int ready;
 223
 224         ready = (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_DSC_PTR_LBITS) -
 225                  rxq->bufs_ptr) &
 226                 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
 227
 228         rxq->bufs_ptr += ready;
 229         rxq->bufs_pending += ready;
 230
 231         SFC_ASSERT(ready > 0);
 232         do {
 233                 const struct sfc_ef10_essb_rx_sw_desc *rxd;
 234                 struct rte_mbuf *m;
 235                 unsigned int todo_bufs;
 236                 struct rte_mbuf *m0;
 237
 238                 rxd = &rxq->sw_ring[rxq->pending_id];
 239                 m = sfc_ef10_essb_mbuf_by_index(rxq, rxd->first_mbuf,
 240                         rxq->block_size - rxq->left_in_pending);
 241
 242                 if (ready < rxq->left_in_pending) {
 243                         todo_bufs = ready;
 244                         ready = 0;
 245                         rxq->left_in_pending -= todo_bufs;
 246                 } else {
 247                         todo_bufs = rxq->left_in_pending;
 248                         ready -= todo_bufs;
 249                         rxq->left_in_pending = rxq->block_size;
 250                         if (rxq->pending_id != rxq->rxq_ptr_mask)
 251                                 rxq->pending_id++;
 252                         else
 253                                 rxq->pending_id = 0;
 254                 }
 255
 256                 SFC_ASSERT(todo_bufs > 0);
 257                 --todo_bufs;
 258
 259                 sfc_ef10_rx_ev_to_offloads(rx_ev, m, ~0ull);
 260
 261                 /* Prefetch pseudo-header */
 262                 rte_prefetch0((uint8_t *)m->buf_addr + RTE_PKTMBUF_HEADROOM);
 263
 264                 m0 = m;
 265                 while (todo_bufs-- > 0) {
 266                         m = sfc_ef10_essb_next_mbuf(rxq, m);
 267                         m->ol_flags = m0->ol_flags;
 268                         m->packet_type = m0->packet_type;
 269                         /* Prefetch pseudo-header */
 270                         rte_prefetch0((uint8_t *)m->buf_addr +
 271                                       RTE_PKTMBUF_HEADROOM);
 272                 }
 273         } while (ready > 0);
 274 }
 275
 276 static unsigned int
 277 sfc_ef10_essb_rx_get_pending(struct sfc_ef10_essb_rxq *rxq,
 278                              struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 279 {
 280         unsigned int n_rx_pkts = 0;
 281         unsigned int todo_bufs;
 282         struct rte_mbuf *m;
 283
 284         while ((todo_bufs = RTE_MIN(nb_pkts - n_rx_pkts,
 285                                     rxq->bufs_pending)) > 0) {
 286                 m = sfc_ef10_essb_maybe_next_completed(rxq);
 287
 288                 todo_bufs = RTE_MIN(todo_bufs, rxq->left_in_completed);
 289
 290                 rxq->bufs_pending -= todo_bufs;
 291                 rxq->left_in_completed -= todo_bufs;
 292
 293                 SFC_ASSERT(todo_bufs > 0);
 294                 todo_bufs--;
 295
 296                 do {
 297                         const efx_qword_t *qwordp;
 298                         uint16_t pkt_len;
 299
 300                         rx_pkts[n_rx_pkts++] = m;
 301
 302                         /* Parse pseudo-header */
 303                         qwordp = (const efx_qword_t *)
 304                                 ((uint8_t *)m->buf_addr + RTE_PKTMBUF_HEADROOM);
 305                         pkt_len =
 306                                 EFX_QWORD_FIELD(*qwordp,
 307                                                 ES_EZ_ESSB_RX_PREFIX_DATA_LEN);
 308
 309                         m->data_off = RTE_PKTMBUF_HEADROOM +
 310                                 ES_EZ_ESSB_RX_PREFIX_LEN;
 311                         m->port = rxq->port_id;
 312
 313                         rte_pktmbuf_pkt_len(m) = pkt_len;
 314                         rte_pktmbuf_data_len(m) = pkt_len;
 315
 316                         m->ol_flags |=
 317                                 (PKT_RX_RSS_HASH *
 318                                  !!EFX_TEST_QWORD_BIT(*qwordp,
 319                                         ES_EZ_ESSB_RX_PREFIX_HASH_VALID_LBN));
 320
 321                         /* EFX_QWORD_FIELD converts little-endian to CPU */
 322                         m->hash.rss =
 323                                 EFX_QWORD_FIELD(*qwordp,
 324                                                 ES_EZ_ESSB_RX_PREFIX_HASH);
 325
 326                         m = sfc_ef10_essb_next_mbuf(rxq, m);
 327                 } while (todo_bufs-- > 0);
 328         }
 329
 330         return n_rx_pkts;
 331 }
 332
 333
 334 static uint16_t
 335 sfc_ef10_essb_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 336                         uint16_t nb_pkts)
 337 {
 338         struct sfc_ef10_essb_rxq *rxq = sfc_ef10_essb_rxq_by_dp_rxq(rx_queue);
 339         const unsigned int evq_old_read_ptr = rxq->evq_read_ptr;
 340         uint16_t n_rx_pkts;
 341         efx_qword_t rx_ev;
 342
 343         if (unlikely(rxq->flags & (SFC_EF10_ESSB_RXQ_NOT_RUNNING |
 344                                    SFC_EF10_ESSB_RXQ_EXCEPTION)))
 345                 return 0;
 346
 347         n_rx_pkts = sfc_ef10_essb_rx_get_pending(rxq, rx_pkts, nb_pkts);
 348
 349         while (n_rx_pkts != nb_pkts &&
 350                sfc_ef10_essb_rx_event_get(rxq, &rx_ev)) {
 351                 /*
 352                  * DROP_EVENT is an internal to the NIC, software should
 353                  * never see it and, therefore, may ignore it.
 354                  */
 355
 356                 sfc_ef10_essb_rx_process_ev(rxq, rx_ev);
 357                 n_rx_pkts += sfc_ef10_essb_rx_get_pending(rxq,
 358                                                           rx_pkts + n_rx_pkts,
 359                                                           nb_pkts - n_rx_pkts);
 360         }
 361
 362         sfc_ef10_ev_qclear(rxq->evq_hw_ring, rxq->evq_ptr_mask,
 363                            evq_old_read_ptr, rxq->evq_read_ptr);
 364
 365         /* It is not a problem if we refill in the case of exception */
 366         sfc_ef10_essb_rx_qrefill(rxq);
 367
 368         return n_rx_pkts;
 369 }
 370
 371 static sfc_dp_rx_qdesc_npending_t sfc_ef10_essb_rx_qdesc_npending;
 372 static unsigned int
 373 sfc_ef10_essb_rx_qdesc_npending(__rte_unused struct sfc_dp_rxq *dp_rxq)
 374 {
 375         /*
 376          * Correct implementation requires EvQ polling and events
 377          * processing.
 378          */
 379         return -ENOTSUP;
 380 }
 381
 382 static sfc_dp_rx_get_dev_info_t sfc_ef10_essb_rx_get_dev_info;
 383 static void
 384 sfc_ef10_essb_rx_get_dev_info(struct rte_eth_dev_info *dev_info)
 385 {
 386         /*
 387          * Number of descriptors just defines maximum number of pushed
 388          * descriptors (fill level).
 389          */
 390         dev_info->rx_desc_lim.nb_min = SFC_RX_REFILL_BULK;
 391         dev_info->rx_desc_lim.nb_align = SFC_RX_REFILL_BULK;
 392 }
 393
 394 static sfc_dp_rx_pool_ops_supported_t sfc_ef10_essb_rx_pool_ops_supported;
 395 static int
 396 sfc_ef10_essb_rx_pool_ops_supported(const char *pool)
 397 {
 398         SFC_ASSERT(pool != NULL);
 399
 400         if (strcmp(pool, "bucket") == 0)
 401                 return 0;
 402
 403         return -ENOTSUP;
 404 }
 405
 406 static sfc_dp_rx_qsize_up_rings_t sfc_ef10_essb_rx_qsize_up_rings;
 407 static int
 408 sfc_ef10_essb_rx_qsize_up_rings(uint16_t nb_rx_desc,
 409                                 struct rte_mempool *mb_pool,
 410                                 unsigned int *rxq_entries,
 411                                 unsigned int *evq_entries,
 412                                 unsigned int *rxq_max_fill_level)
 413 {
 414         int rc;
 415         struct rte_mempool_info mp_info;
 416         unsigned int nb_hw_rx_desc;
 417         unsigned int max_events;
 418
 419         rc = rte_mempool_ops_get_info(mb_pool, &mp_info);
 420         if (rc != 0)
 421                 return -rc;
 422         if (mp_info.contig_block_size == 0)
 423                 return EINVAL;
 424
 425         /*
 426          * Calculate required number of hardware Rx descriptors each
 427          * carrying contig block size Rx buffers.
 428          * It cannot be less than Rx write pointer alignment plus 1
 429          * in order to avoid cases when the ring is guaranteed to be
 430          * empty.
 431          */
 432         nb_hw_rx_desc = RTE_MAX(SFC_DIV_ROUND_UP(nb_rx_desc,
 433                                                  mp_info.contig_block_size),
 434                                 SFC_EF10_RX_WPTR_ALIGN + 1);
 435         if (nb_hw_rx_desc <= EFX_RXQ_MINNDESCS) {
 436                 *rxq_entries = EFX_RXQ_MINNDESCS;
 437         } else {
 438                 *rxq_entries = rte_align32pow2(nb_hw_rx_desc);
 439                 if (*rxq_entries > EFX_RXQ_MAXNDESCS)
 440                         return EINVAL;
 441         }
 442
 443         max_events = RTE_ALIGN_FLOOR(nb_hw_rx_desc, SFC_EF10_RX_WPTR_ALIGN) *
 444                 mp_info.contig_block_size +
 445                 (SFC_EF10_EV_PER_CACHE_LINE - 1) /* max unused EvQ entries */ +
 446                 1 /* Rx error */ + 1 /* flush */ + 1 /* head-tail space */;
 447
 448         *evq_entries = rte_align32pow2(max_events);
 449         *evq_entries = RTE_MAX(*evq_entries, (unsigned int)EFX_EVQ_MINNEVS);
 450         *evq_entries = RTE_MIN(*evq_entries, (unsigned int)EFX_EVQ_MAXNEVS);
 451
 452         /*
 453          * May be even maximum event queue size is insufficient to handle
 454          * so many Rx descriptors. If so, we should limit Rx queue fill level.
 455          */
 456         *rxq_max_fill_level = RTE_MIN(nb_rx_desc,
 457                                       SFC_EF10_ESSB_RXQ_LIMIT(*evq_entries));
 458         return 0;
 459 }
 460
 461 static sfc_dp_rx_qcreate_t sfc_ef10_essb_rx_qcreate;
 462 static int
 463 sfc_ef10_essb_rx_qcreate(uint16_t port_id, uint16_t queue_id,
 464                          const struct rte_pci_addr *pci_addr, int socket_id,
 465                          const struct sfc_dp_rx_qcreate_info *info,
 466                          struct sfc_dp_rxq **dp_rxqp)
 467 {
 468         struct rte_mempool * const mp = info->refill_mb_pool;
 469         struct rte_mempool_info mp_info;
 470         struct sfc_ef10_essb_rxq *rxq;
 471         int rc;
 472
 473         rc = rte_mempool_ops_get_info(mp, &mp_info);
 474         if (rc != 0) {
 475                 /* Positive errno is used in the driver */
 476                 rc = -rc;
 477                 goto fail_get_contig_block_size;
 478         }
 479
 480         /* Check if the mempool provides block dequeue */
 481         rc = EINVAL;
 482         if (mp_info.contig_block_size == 0)
 483                 goto fail_no_block_dequeue;
 484
 485         rc = ENOMEM;
 486         rxq = rte_zmalloc_socket("sfc-ef10-rxq", sizeof(*rxq),
 487                                  RTE_CACHE_LINE_SIZE, socket_id);
 488         if (rxq == NULL)
 489                 goto fail_rxq_alloc;
 490
 491         sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr);
 492
 493         rc = ENOMEM;
 494         rxq->sw_ring = rte_calloc_socket("sfc-ef10-rxq-sw_ring",
 495                                          info->rxq_entries,
 496                                          sizeof(*rxq->sw_ring),
 497                                          RTE_CACHE_LINE_SIZE, socket_id);
 498         if (rxq->sw_ring == NULL)
 499                 goto fail_desc_alloc;
 500
 501         rxq->block_size = mp_info.contig_block_size;
 502         rxq->buf_stride = mp->header_size + mp->elt_size + mp->trailer_size;
 503         rxq->rxq_ptr_mask = info->rxq_entries - 1;
 504         rxq->evq_ptr_mask = info->evq_entries - 1;
 505         rxq->evq_hw_ring = info->evq_hw_ring;
 506         rxq->port_id = port_id;
 507
 508         rxq->max_fill_level = info->max_fill_level / mp_info.contig_block_size;
 509         rxq->refill_threshold =
 510                 RTE_MAX(info->refill_threshold / mp_info.contig_block_size,
 511                         SFC_EF10_RX_WPTR_ALIGN);
 512         rxq->refill_mb_pool = mp;
 513         rxq->rxq_hw_ring = info->rxq_hw_ring;
 514
 515         rxq->doorbell = (volatile uint8_t *)info->mem_bar +
 516                         ER_DZ_RX_DESC_UPD_REG_OFST +
 517                         (info->hw_index << info->vi_window_shift);
 518
 519         sfc_ef10_essb_rx_info(&rxq->dp.dpq,
 520                               "block size is %u, buf stride is %u",
 521                               rxq->block_size, rxq->buf_stride);
 522         sfc_ef10_essb_rx_info(&rxq->dp.dpq,
 523                               "max fill level is %u descs (%u bufs), "
 524                               "refill threashold %u descs (%u bufs)",
 525                               rxq->max_fill_level,
 526                               rxq->max_fill_level * rxq->block_size,
 527                               rxq->refill_threshold,
 528                               rxq->refill_threshold * rxq->block_size);
 529
 530         *dp_rxqp = &rxq->dp;
 531         return 0;
 532
 533 fail_desc_alloc:
 534         rte_free(rxq);
 535
 536 fail_rxq_alloc:
 537 fail_no_block_dequeue:
 538 fail_get_contig_block_size:
 539         return rc;
 540 }
 541
 542 static sfc_dp_rx_qdestroy_t sfc_ef10_essb_rx_qdestroy;
 543 static void
 544 sfc_ef10_essb_rx_qdestroy(struct sfc_dp_rxq *dp_rxq)
 545 {
 546         struct sfc_ef10_essb_rxq *rxq = sfc_ef10_essb_rxq_by_dp_rxq(dp_rxq);
 547
 548         rte_free(rxq->sw_ring);
 549         rte_free(rxq);
 550 }
 551
 552 static sfc_dp_rx_qstart_t sfc_ef10_essb_rx_qstart;
 553 static int
 554 sfc_ef10_essb_rx_qstart(struct sfc_dp_rxq *dp_rxq, unsigned int evq_read_ptr)
 555 {
 556         struct sfc_ef10_essb_rxq *rxq = sfc_ef10_essb_rxq_by_dp_rxq(dp_rxq);
 557
 558         rxq->evq_read_ptr = evq_read_ptr;
 559
 560         /* Initialize before refill */
 561         rxq->completed = rxq->pending_id = rxq->added = 0;
 562         rxq->left_in_completed = rxq->left_in_pending = rxq->block_size;
 563         rxq->bufs_ptr = UINT_MAX;
 564         rxq->bufs_pending = 0;
 565
 566         sfc_ef10_essb_rx_qrefill(rxq);
 567
 568         rxq->flags |= SFC_EF10_ESSB_RXQ_STARTED;
 569         rxq->flags &=
 570                 ~(SFC_EF10_ESSB_RXQ_NOT_RUNNING | SFC_EF10_ESSB_RXQ_EXCEPTION);
 571
 572         return 0;
 573 }
 574
 575 static sfc_dp_rx_qstop_t sfc_ef10_essb_rx_qstop;
 576 static void
 577 sfc_ef10_essb_rx_qstop(struct sfc_dp_rxq *dp_rxq, unsigned int *evq_read_ptr)
 578 {
 579         struct sfc_ef10_essb_rxq *rxq = sfc_ef10_essb_rxq_by_dp_rxq(dp_rxq);
 580
 581         rxq->flags |= SFC_EF10_ESSB_RXQ_NOT_RUNNING;
 582
 583         *evq_read_ptr = rxq->evq_read_ptr;
 584 }
 585
 586 static sfc_dp_rx_qrx_ev_t sfc_ef10_essb_rx_qrx_ev;
 587 static bool
 588 sfc_ef10_essb_rx_qrx_ev(struct sfc_dp_rxq *dp_rxq, __rte_unused unsigned int id)
 589 {
 590         __rte_unused struct sfc_ef10_essb_rxq *rxq;
 591
 592         rxq = sfc_ef10_essb_rxq_by_dp_rxq(dp_rxq);
 593         SFC_ASSERT(rxq->flags & SFC_EF10_ESSB_RXQ_NOT_RUNNING);
 594
 595         /*
 596          * It is safe to ignore Rx event since we free all mbufs on
 597          * queue purge anyway.
 598          */
 599
 600         return false;
 601 }
 602
 603 static sfc_dp_rx_qpurge_t sfc_ef10_essb_rx_qpurge;
 604 static void
 605 sfc_ef10_essb_rx_qpurge(struct sfc_dp_rxq *dp_rxq)
 606 {
 607         struct sfc_ef10_essb_rxq *rxq = sfc_ef10_essb_rxq_by_dp_rxq(dp_rxq);
 608         unsigned int i, j;
 609         const struct sfc_ef10_essb_rx_sw_desc *rxd;
 610         struct rte_mbuf *m;
 611
 612         if (rxq->completed != rxq->added && rxq->left_in_completed > 0) {
 613                 rxd = &rxq->sw_ring[rxq->completed & rxq->rxq_ptr_mask];
 614                 m = sfc_ef10_essb_mbuf_by_index(rxq, rxd->first_mbuf,
 615                                 rxq->block_size - rxq->left_in_completed);
 616                 do {
 617                         rxq->left_in_completed--;
 618                         rte_mempool_put(rxq->refill_mb_pool, m);
 619                         m = sfc_ef10_essb_next_mbuf(rxq, m);
 620                 } while (rxq->left_in_completed > 0);
 621                 rxq->completed++;
 622         }
 623
 624         for (i = rxq->completed; i != rxq->added; ++i) {
 625                 rxd = &rxq->sw_ring[i & rxq->rxq_ptr_mask];
 626                 m = rxd->first_mbuf;
 627                 for (j = 0; j < rxq->block_size; ++j) {
 628                         rte_mempool_put(rxq->refill_mb_pool, m);
 629                         m = sfc_ef10_essb_next_mbuf(rxq, m);
 630                 }
 631         }
 632
 633         rxq->flags &= ~SFC_EF10_ESSB_RXQ_STARTED;
 634 }
 635
 636 struct sfc_dp_rx sfc_ef10_essb_rx = {
 637         .dp = {
 638                 .name           = SFC_KVARG_DATAPATH_EF10_ESSB,
 639                 .type           = SFC_DP_RX,
 640                 .hw_fw_caps     = SFC_DP_HW_FW_CAP_EF10 |
 641                                   SFC_DP_HW_FW_CAP_RX_ES_SUPER_BUFFER,
 642         },
 643         .features               = 0,
 644         .get_dev_info           = sfc_ef10_essb_rx_get_dev_info,
 645         .pool_ops_supported     = sfc_ef10_essb_rx_pool_ops_supported,
 646         .qsize_up_rings         = sfc_ef10_essb_rx_qsize_up_rings,
 647         .qcreate                = sfc_ef10_essb_rx_qcreate,
 648         .qdestroy               = sfc_ef10_essb_rx_qdestroy,
 649         .qstart                 = sfc_ef10_essb_rx_qstart,
 650         .qstop                  = sfc_ef10_essb_rx_qstop,
 651         .qrx_ev                 = sfc_ef10_essb_rx_qrx_ev,
 652         .qpurge                 = sfc_ef10_essb_rx_qpurge,
 653         .supported_ptypes_get   = sfc_ef10_supported_ptypes_get,
 654         .qdesc_npending         = sfc_ef10_essb_rx_qdesc_npending,
 655         .pkt_burst              = sfc_ef10_essb_recv_pkts,
 656 };