1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016-2018 Solarflare Communications Inc.
6 * This software was jointly developed between OKTET Labs (under contract
7 * for Solarflare) and Solarflare Communications, Inc.
10 /* EF10 native datapath implementation */
14 #include <rte_byteorder.h>
15 #include <rte_mbuf_ptype.h>
20 #include "efx_types.h"
22 #include "efx_regs_ef10.h"
24 #include "sfc_tweak.h"
25 #include "sfc_dp_rx.h"
26 #include "sfc_kvargs.h"
29 #define SFC_EF10_RX_EV_ENCAP_SUPPORT 1
30 #include "sfc_ef10_rx_ev.h"
32 #define sfc_ef10_rx_err(dpq, ...) \
33 SFC_DP_LOG(SFC_KVARG_DATAPATH_EF10, ERR, dpq, __VA_ARGS__)
36 * Maximum number of descriptors/buffers in the Rx ring.
37 * It should guarantee that corresponding event queue never overfill.
38 * EF10 native datapath uses event queue of the same size as Rx queue.
39 * Maximum number of events on datapath can be estimated as number of
40 * Rx queue entries (one event per Rx buffer in the worst case) plus
41 * Rx error and flush events.
43 #define SFC_EF10_RXQ_LIMIT(_ndesc) \
44 ((_ndesc) - 1 /* head must not step on tail */ - \
45 (SFC_EF10_EV_PER_CACHE_LINE - 1) /* max unused EvQ entries */ - \
46 1 /* Rx error */ - 1 /* flush */)
48 struct sfc_ef10_rx_sw_desc {
49 struct rte_mbuf *mbuf;
53 /* Used on data path */
55 #define SFC_EF10_RXQ_STARTED 0x1
56 #define SFC_EF10_RXQ_NOT_RUNNING 0x2
57 #define SFC_EF10_RXQ_EXCEPTION 0x4
58 #define SFC_EF10_RXQ_RSS_HASH 0x8
59 unsigned int ptr_mask;
60 unsigned int prepared;
61 unsigned int completed;
62 unsigned int evq_read_ptr;
63 efx_qword_t *evq_hw_ring;
64 struct sfc_ef10_rx_sw_desc *sw_ring;
71 unsigned int max_fill_level;
72 unsigned int refill_threshold;
73 struct rte_mempool *refill_mb_pool;
74 efx_qword_t *rxq_hw_ring;
75 volatile void *doorbell;
77 /* Datapath receive queue anchor */
81 static inline struct sfc_ef10_rxq *
82 sfc_ef10_rxq_by_dp_rxq(struct sfc_dp_rxq *dp_rxq)
84 return container_of(dp_rxq, struct sfc_ef10_rxq, dp);
88 sfc_ef10_rx_qrefill(struct sfc_ef10_rxq *rxq)
90 const unsigned int ptr_mask = rxq->ptr_mask;
91 const uint32_t buf_size = rxq->buf_size;
92 unsigned int free_space;
94 void *objs[SFC_RX_REFILL_BULK];
95 unsigned int added = rxq->added;
97 RTE_BUILD_BUG_ON(SFC_RX_REFILL_BULK % SFC_EF10_RX_WPTR_ALIGN != 0);
99 free_space = rxq->max_fill_level - (added - rxq->completed);
101 if (free_space < rxq->refill_threshold)
104 bulks = free_space / RTE_DIM(objs);
105 /* refill_threshold guarantees that bulks is positive */
106 SFC_ASSERT(bulks > 0);
112 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs,
113 RTE_DIM(objs)) < 0)) {
114 struct rte_eth_dev_data *dev_data =
115 rte_eth_devices[rxq->dp.dpq.port_id].data;
118 * It is hardly a safe way to increment counter
119 * from different contexts, but all PMDs do it.
121 dev_data->rx_mbuf_alloc_failed += RTE_DIM(objs);
122 /* Return if we have posted nothing yet */
123 if (added == rxq->added)
129 for (i = 0, id = added & ptr_mask;
132 struct rte_mbuf *m = objs[i];
133 struct sfc_ef10_rx_sw_desc *rxd;
134 rte_iova_t phys_addr;
136 SFC_ASSERT((id & ~ptr_mask) == 0);
137 rxd = &rxq->sw_ring[id];
141 * Avoid writing to mbuf. It is cheaper to do it
142 * when we receive packet and fill in nearby
146 phys_addr = rte_mbuf_data_iova_default(m);
147 EFX_POPULATE_QWORD_2(rxq->rxq_hw_ring[id],
148 ESF_DZ_RX_KER_BYTE_CNT, buf_size,
149 ESF_DZ_RX_KER_BUF_ADDR, phys_addr);
152 added += RTE_DIM(objs);
153 } while (--bulks > 0);
155 SFC_ASSERT(rxq->added != added);
157 sfc_ef10_rx_qpush(rxq->doorbell, added, ptr_mask);
161 sfc_ef10_rx_prefetch_next(struct sfc_ef10_rxq *rxq, unsigned int next_id)
163 struct rte_mbuf *next_mbuf;
165 /* Prefetch next bunch of software descriptors */
166 if ((next_id % (RTE_CACHE_LINE_SIZE / sizeof(rxq->sw_ring[0]))) == 0)
167 rte_prefetch0(&rxq->sw_ring[next_id]);
170 * It looks strange to prefetch depending on previous prefetch
171 * data, but measurements show that it is really efficient and
172 * increases packet rate.
174 next_mbuf = rxq->sw_ring[next_id].mbuf;
175 if (likely(next_mbuf != NULL)) {
176 /* Prefetch the next mbuf structure */
177 rte_mbuf_prefetch_part1(next_mbuf);
179 /* Prefetch pseudo header of the next packet */
180 /* data_off is not filled in yet */
181 /* Yes, data could be not ready yet, but we hope */
182 rte_prefetch0((uint8_t *)next_mbuf->buf_addr +
183 RTE_PKTMBUF_HEADROOM);
188 sfc_ef10_rx_prepared(struct sfc_ef10_rxq *rxq, struct rte_mbuf **rx_pkts,
191 uint16_t n_rx_pkts = RTE_MIN(nb_pkts, rxq->prepared);
192 unsigned int completed = rxq->completed;
195 rxq->prepared -= n_rx_pkts;
196 rxq->completed = completed + n_rx_pkts;
198 for (i = 0; i < n_rx_pkts; ++i, ++completed)
199 rx_pkts[i] = rxq->sw_ring[completed & rxq->ptr_mask].mbuf;
205 sfc_ef10_rx_pseudo_hdr_get_len(const uint8_t *pseudo_hdr)
207 return rte_le_to_cpu_16(*(const uint16_t *)&pseudo_hdr[8]);
211 sfc_ef10_rx_pseudo_hdr_get_hash(const uint8_t *pseudo_hdr)
213 return rte_le_to_cpu_32(*(const uint32_t *)pseudo_hdr);
217 sfc_ef10_rx_process_event(struct sfc_ef10_rxq *rxq, efx_qword_t rx_ev,
218 struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
220 const unsigned int ptr_mask = rxq->ptr_mask;
221 unsigned int completed = rxq->completed;
223 struct sfc_ef10_rx_sw_desc *rxd;
227 const uint8_t *pseudo_hdr;
230 ready = (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_DSC_PTR_LBITS) - completed) &
231 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
232 SFC_ASSERT(ready > 0);
234 if (rx_ev.eq_u64[0] &
235 rte_cpu_to_le_64((1ull << ESF_DZ_RX_ECC_ERR_LBN) |
236 (1ull << ESF_DZ_RX_ECRC_ERR_LBN))) {
237 SFC_ASSERT(rxq->prepared == 0);
238 rxq->completed += ready;
239 while (ready-- > 0) {
240 rxd = &rxq->sw_ring[completed++ & ptr_mask];
241 rte_mempool_put(rxq->refill_mb_pool, rxd->mbuf);
246 n_rx_pkts = RTE_MIN(ready, nb_pkts);
247 rxq->prepared = ready - n_rx_pkts;
248 rxq->completed += n_rx_pkts;
250 rxd = &rxq->sw_ring[completed++ & ptr_mask];
252 sfc_ef10_rx_prefetch_next(rxq, completed & ptr_mask);
258 RTE_BUILD_BUG_ON(sizeof(m->rearm_data[0]) != sizeof(rxq->rearm_data));
259 m->rearm_data[0] = rxq->rearm_data;
261 /* Classify packet based on Rx event */
262 /* Mask RSS hash offload flag if RSS is not enabled */
263 sfc_ef10_rx_ev_to_offloads(rx_ev, m,
264 (rxq->flags & SFC_EF10_RXQ_RSS_HASH) ?
265 ~0ull : ~PKT_RX_RSS_HASH);
267 /* data_off already moved past pseudo header */
268 pseudo_hdr = (uint8_t *)m->buf_addr + RTE_PKTMBUF_HEADROOM;
271 * Always get RSS hash from pseudo header to avoid
272 * condition/branching. If it is valid or not depends on
273 * PKT_RX_RSS_HASH in m->ol_flags.
275 m->hash.rss = sfc_ef10_rx_pseudo_hdr_get_hash(pseudo_hdr);
278 pkt_len = EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_BYTES) -
281 pkt_len = sfc_ef10_rx_pseudo_hdr_get_len(pseudo_hdr);
282 SFC_ASSERT(pkt_len > 0);
283 rte_pktmbuf_data_len(m) = pkt_len;
284 rte_pktmbuf_pkt_len(m) = pkt_len;
286 SFC_ASSERT(m->next == NULL);
288 /* Remember mbuf to copy offload flags and packet type from */
290 for (--ready; ready > 0; --ready) {
291 rxd = &rxq->sw_ring[completed++ & ptr_mask];
293 sfc_ef10_rx_prefetch_next(rxq, completed & ptr_mask);
297 if (ready > rxq->prepared)
300 RTE_BUILD_BUG_ON(sizeof(m->rearm_data[0]) !=
301 sizeof(rxq->rearm_data));
302 m->rearm_data[0] = rxq->rearm_data;
304 /* Event-dependent information is the same */
305 m->ol_flags = m0->ol_flags;
306 m->packet_type = m0->packet_type;
308 /* data_off already moved past pseudo header */
309 pseudo_hdr = (uint8_t *)m->buf_addr + RTE_PKTMBUF_HEADROOM;
312 * Always get RSS hash from pseudo header to avoid
313 * condition/branching. If it is valid or not depends on
314 * PKT_RX_RSS_HASH in m->ol_flags.
316 m->hash.rss = sfc_ef10_rx_pseudo_hdr_get_hash(pseudo_hdr);
318 pkt_len = sfc_ef10_rx_pseudo_hdr_get_len(pseudo_hdr);
319 SFC_ASSERT(pkt_len > 0);
320 rte_pktmbuf_data_len(m) = pkt_len;
321 rte_pktmbuf_pkt_len(m) = pkt_len;
323 SFC_ASSERT(m->next == NULL);
330 sfc_ef10_rx_get_event(struct sfc_ef10_rxq *rxq, efx_qword_t *rx_ev)
332 *rx_ev = rxq->evq_hw_ring[rxq->evq_read_ptr & rxq->ptr_mask];
334 if (!sfc_ef10_ev_present(*rx_ev))
337 if (unlikely(EFX_QWORD_FIELD(*rx_ev, FSF_AZ_EV_CODE) !=
338 FSE_AZ_EV_CODE_RX_EV)) {
340 * Do not move read_ptr to keep the event for exception
341 * handling by the control path.
343 rxq->flags |= SFC_EF10_RXQ_EXCEPTION;
344 sfc_ef10_rx_err(&rxq->dp.dpq,
345 "RxQ exception at EvQ read ptr %#x",
355 sfc_ef10_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
357 struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(rx_queue);
358 unsigned int evq_old_read_ptr;
362 if (unlikely(rxq->flags &
363 (SFC_EF10_RXQ_NOT_RUNNING | SFC_EF10_RXQ_EXCEPTION)))
366 n_rx_pkts = sfc_ef10_rx_prepared(rxq, rx_pkts, nb_pkts);
368 evq_old_read_ptr = rxq->evq_read_ptr;
369 while (n_rx_pkts != nb_pkts && sfc_ef10_rx_get_event(rxq, &rx_ev)) {
371 * DROP_EVENT is an internal to the NIC, software should
372 * never see it and, therefore, may ignore it.
375 n_rx_pkts += sfc_ef10_rx_process_event(rxq, rx_ev,
377 nb_pkts - n_rx_pkts);
380 sfc_ef10_ev_qclear(rxq->evq_hw_ring, rxq->ptr_mask, evq_old_read_ptr,
383 /* It is not a problem if we refill in the case of exception */
384 sfc_ef10_rx_qrefill(rxq);
390 sfc_ef10_supported_ptypes_get(uint32_t tunnel_encaps)
392 static const uint32_t ef10_native_ptypes[] = {
394 RTE_PTYPE_L2_ETHER_ARP,
395 RTE_PTYPE_L2_ETHER_VLAN,
396 RTE_PTYPE_L2_ETHER_QINQ,
397 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
398 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
404 static const uint32_t ef10_overlay_ptypes[] = {
406 RTE_PTYPE_L2_ETHER_ARP,
407 RTE_PTYPE_L2_ETHER_VLAN,
408 RTE_PTYPE_L2_ETHER_QINQ,
409 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
410 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
414 RTE_PTYPE_TUNNEL_VXLAN,
415 RTE_PTYPE_TUNNEL_NVGRE,
416 RTE_PTYPE_INNER_L2_ETHER,
417 RTE_PTYPE_INNER_L2_ETHER_VLAN,
418 RTE_PTYPE_INNER_L2_ETHER_QINQ,
419 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
420 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
421 RTE_PTYPE_INNER_L4_FRAG,
422 RTE_PTYPE_INNER_L4_TCP,
423 RTE_PTYPE_INNER_L4_UDP,
428 * The function returns static set of supported packet types,
429 * so we can't build it dynamically based on supported tunnel
430 * encapsulations and should limit to known sets.
432 switch (tunnel_encaps) {
433 case (1u << EFX_TUNNEL_PROTOCOL_VXLAN |
434 1u << EFX_TUNNEL_PROTOCOL_GENEVE |
435 1u << EFX_TUNNEL_PROTOCOL_NVGRE):
436 return ef10_overlay_ptypes;
439 "Unexpected set of supported tunnel encapsulations: %#x",
443 return ef10_native_ptypes;
447 static sfc_dp_rx_qdesc_npending_t sfc_ef10_rx_qdesc_npending;
449 sfc_ef10_rx_qdesc_npending(__rte_unused struct sfc_dp_rxq *dp_rxq)
452 * Correct implementation requires EvQ polling and events
453 * processing (keeping all ready mbufs in prepared).
458 static sfc_dp_rx_qdesc_status_t sfc_ef10_rx_qdesc_status;
460 sfc_ef10_rx_qdesc_status(__rte_unused struct sfc_dp_rxq *dp_rxq,
461 __rte_unused uint16_t offset)
467 static sfc_dp_rx_get_dev_info_t sfc_ef10_rx_get_dev_info;
469 sfc_ef10_rx_get_dev_info(struct rte_eth_dev_info *dev_info)
472 * Number of descriptors just defines maximum number of pushed
473 * descriptors (fill level).
475 dev_info->rx_desc_lim.nb_min = SFC_RX_REFILL_BULK;
476 dev_info->rx_desc_lim.nb_align = SFC_RX_REFILL_BULK;
480 static sfc_dp_rx_qsize_up_rings_t sfc_ef10_rx_qsize_up_rings;
482 sfc_ef10_rx_qsize_up_rings(uint16_t nb_rx_desc,
483 __rte_unused struct rte_mempool *mb_pool,
484 unsigned int *rxq_entries,
485 unsigned int *evq_entries,
486 unsigned int *rxq_max_fill_level)
489 * rte_ethdev API guarantees that the number meets min, max and
490 * alignment requirements.
492 if (nb_rx_desc <= EFX_RXQ_MINNDESCS)
493 *rxq_entries = EFX_RXQ_MINNDESCS;
495 *rxq_entries = rte_align32pow2(nb_rx_desc);
497 *evq_entries = *rxq_entries;
499 *rxq_max_fill_level = RTE_MIN(nb_rx_desc,
500 SFC_EF10_RXQ_LIMIT(*evq_entries));
506 sfc_ef10_mk_mbuf_rearm_data(uint16_t port_id, uint16_t prefix_size)
510 memset(&m, 0, sizeof(m));
512 rte_mbuf_refcnt_set(&m, 1);
513 m.data_off = RTE_PKTMBUF_HEADROOM + prefix_size;
517 /* rearm_data covers structure members filled in above */
518 rte_compiler_barrier();
519 RTE_BUILD_BUG_ON(sizeof(m.rearm_data[0]) != sizeof(uint64_t));
520 return m.rearm_data[0];
523 static sfc_dp_rx_qcreate_t sfc_ef10_rx_qcreate;
525 sfc_ef10_rx_qcreate(uint16_t port_id, uint16_t queue_id,
526 const struct rte_pci_addr *pci_addr, int socket_id,
527 const struct sfc_dp_rx_qcreate_info *info,
528 struct sfc_dp_rxq **dp_rxqp)
530 struct sfc_ef10_rxq *rxq;
534 if (info->rxq_entries != info->evq_entries)
538 rxq = rte_zmalloc_socket("sfc-ef10-rxq", sizeof(*rxq),
539 RTE_CACHE_LINE_SIZE, socket_id);
543 sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr);
546 rxq->sw_ring = rte_calloc_socket("sfc-ef10-rxq-sw_ring",
548 sizeof(*rxq->sw_ring),
549 RTE_CACHE_LINE_SIZE, socket_id);
550 if (rxq->sw_ring == NULL)
551 goto fail_desc_alloc;
553 rxq->flags |= SFC_EF10_RXQ_NOT_RUNNING;
554 if (info->flags & SFC_RXQ_FLAG_RSS_HASH)
555 rxq->flags |= SFC_EF10_RXQ_RSS_HASH;
556 rxq->ptr_mask = info->rxq_entries - 1;
557 rxq->evq_hw_ring = info->evq_hw_ring;
558 rxq->max_fill_level = info->max_fill_level;
559 rxq->refill_threshold = info->refill_threshold;
561 sfc_ef10_mk_mbuf_rearm_data(port_id, info->prefix_size);
562 rxq->prefix_size = info->prefix_size;
563 rxq->buf_size = info->buf_size;
564 rxq->refill_mb_pool = info->refill_mb_pool;
565 rxq->rxq_hw_ring = info->rxq_hw_ring;
566 rxq->doorbell = (volatile uint8_t *)info->mem_bar +
567 ER_DZ_RX_DESC_UPD_REG_OFST +
568 (info->hw_index << info->vi_window_shift);
581 static sfc_dp_rx_qdestroy_t sfc_ef10_rx_qdestroy;
583 sfc_ef10_rx_qdestroy(struct sfc_dp_rxq *dp_rxq)
585 struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
587 rte_free(rxq->sw_ring);
591 static sfc_dp_rx_qstart_t sfc_ef10_rx_qstart;
593 sfc_ef10_rx_qstart(struct sfc_dp_rxq *dp_rxq, unsigned int evq_read_ptr)
595 struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
598 rxq->completed = rxq->added = 0;
600 sfc_ef10_rx_qrefill(rxq);
602 rxq->evq_read_ptr = evq_read_ptr;
604 rxq->flags |= SFC_EF10_RXQ_STARTED;
605 rxq->flags &= ~(SFC_EF10_RXQ_NOT_RUNNING | SFC_EF10_RXQ_EXCEPTION);
610 static sfc_dp_rx_qstop_t sfc_ef10_rx_qstop;
612 sfc_ef10_rx_qstop(struct sfc_dp_rxq *dp_rxq, unsigned int *evq_read_ptr)
614 struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
616 rxq->flags |= SFC_EF10_RXQ_NOT_RUNNING;
618 *evq_read_ptr = rxq->evq_read_ptr;
621 static sfc_dp_rx_qrx_ev_t sfc_ef10_rx_qrx_ev;
623 sfc_ef10_rx_qrx_ev(struct sfc_dp_rxq *dp_rxq, __rte_unused unsigned int id)
625 __rte_unused struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
627 SFC_ASSERT(rxq->flags & SFC_EF10_RXQ_NOT_RUNNING);
630 * It is safe to ignore Rx event since we free all mbufs on
631 * queue purge anyway.
637 static sfc_dp_rx_qpurge_t sfc_ef10_rx_qpurge;
639 sfc_ef10_rx_qpurge(struct sfc_dp_rxq *dp_rxq)
641 struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
643 struct sfc_ef10_rx_sw_desc *rxd;
645 for (i = rxq->completed; i != rxq->added; ++i) {
646 rxd = &rxq->sw_ring[i & rxq->ptr_mask];
647 rte_mempool_put(rxq->refill_mb_pool, rxd->mbuf);
651 rxq->flags &= ~SFC_EF10_RXQ_STARTED;
654 struct sfc_dp_rx sfc_ef10_rx = {
656 .name = SFC_KVARG_DATAPATH_EF10,
658 .hw_fw_caps = SFC_DP_HW_FW_CAP_EF10,
660 .features = SFC_DP_RX_FEAT_MULTI_PROCESS |
661 SFC_DP_RX_FEAT_TUNNELS,
662 .get_dev_info = sfc_ef10_rx_get_dev_info,
663 .qsize_up_rings = sfc_ef10_rx_qsize_up_rings,
664 .qcreate = sfc_ef10_rx_qcreate,
665 .qdestroy = sfc_ef10_rx_qdestroy,
666 .qstart = sfc_ef10_rx_qstart,
667 .qstop = sfc_ef10_rx_qstop,
668 .qrx_ev = sfc_ef10_rx_qrx_ev,
669 .qpurge = sfc_ef10_rx_qpurge,
670 .supported_ptypes_get = sfc_ef10_supported_ptypes_get,
671 .qdesc_npending = sfc_ef10_rx_qdesc_npending,
672 .qdesc_status = sfc_ef10_rx_qdesc_status,
673 .pkt_burst = sfc_ef10_recv_pkts,