drivers/net/sfc/sfc_ef10_rx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2016-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  *
   6  * This software was jointly developed between OKTET Labs (under contract
   7  * for Solarflare) and Solarflare Communications, Inc.
   8  */
   9
  10 /* EF10 native datapath implementation */
  11
  12 #include <stdbool.h>
  13
  14 #include <rte_byteorder.h>
  15 #include <rte_mbuf_ptype.h>
  16 #include <rte_mbuf.h>
  17 #include <rte_io.h>
  18
  19 #include "efx.h"
  20 #include "efx_types.h"
  21 #include "efx_regs.h"
  22 #include "efx_regs_ef10.h"
  23
  24 #include "sfc_tweak.h"
  25 #include "sfc_dp_rx.h"
  26 #include "sfc_kvargs.h"
  27 #include "sfc_ef10.h"
  28
  29 #define sfc_ef10_rx_err(dpq, ...) \
  30         SFC_DP_LOG(SFC_KVARG_DATAPATH_EF10, ERR, dpq, __VA_ARGS__)
  31
  32 /**
  33  * Maximum number of descriptors/buffers in the Rx ring.
  34  * It should guarantee that corresponding event queue never overfill.
  35  * EF10 native datapath uses event queue of the same size as Rx queue.
  36  * Maximum number of events on datapath can be estimated as number of
  37  * Rx queue entries (one event per Rx buffer in the worst case) plus
  38  * Rx error and flush events.
  39  */
  40 #define SFC_EF10_RXQ_LIMIT(_ndesc) \
  41         ((_ndesc) - 1 /* head must not step on tail */ - \
  42          (SFC_EF10_EV_PER_CACHE_LINE - 1) /* max unused EvQ entries */ - \
  43          1 /* Rx error */ - 1 /* flush */)
  44
  45 struct sfc_ef10_rx_sw_desc {
  46         struct rte_mbuf                 *mbuf;
  47 };
  48
  49 struct sfc_ef10_rxq {
  50         /* Used on data path */
  51         unsigned int                    flags;
  52 #define SFC_EF10_RXQ_STARTED            0x1
  53 #define SFC_EF10_RXQ_NOT_RUNNING        0x2
  54 #define SFC_EF10_RXQ_EXCEPTION          0x4
  55 #define SFC_EF10_RXQ_RSS_HASH           0x8
  56         unsigned int                    ptr_mask;
  57         unsigned int                    prepared;
  58         unsigned int                    completed;
  59         unsigned int                    evq_read_ptr;
  60         efx_qword_t                     *evq_hw_ring;
  61         struct sfc_ef10_rx_sw_desc      *sw_ring;
  62         uint64_t                        rearm_data;
  63         uint16_t                        prefix_size;
  64
  65         /* Used on refill */
  66         uint16_t                        buf_size;
  67         unsigned int                    added;
  68         unsigned int                    max_fill_level;
  69         unsigned int                    refill_threshold;
  70         struct rte_mempool              *refill_mb_pool;
  71         efx_qword_t                     *rxq_hw_ring;
  72         volatile void                   *doorbell;
  73
  74         /* Datapath receive queue anchor */
  75         struct sfc_dp_rxq               dp;
  76 };
  77
  78 static inline struct sfc_ef10_rxq *
  79 sfc_ef10_rxq_by_dp_rxq(struct sfc_dp_rxq *dp_rxq)
  80 {
  81         return container_of(dp_rxq, struct sfc_ef10_rxq, dp);
  82 }
  83
  84 static void
  85 sfc_ef10_rx_qrefill(struct sfc_ef10_rxq *rxq)
  86 {
  87         const unsigned int ptr_mask = rxq->ptr_mask;
  88         const uint32_t buf_size = rxq->buf_size;
  89         unsigned int free_space;
  90         unsigned int bulks;
  91         void *objs[SFC_RX_REFILL_BULK];
  92         unsigned int added = rxq->added;
  93
  94         RTE_BUILD_BUG_ON(SFC_RX_REFILL_BULK % SFC_EF10_RX_WPTR_ALIGN != 0);
  95
  96         free_space = rxq->max_fill_level - (added - rxq->completed);
  97
  98         if (free_space < rxq->refill_threshold)
  99                 return;
 100
 101         bulks = free_space / RTE_DIM(objs);
 102         /* refill_threshold guarantees that bulks is positive */
 103         SFC_ASSERT(bulks > 0);
 104
 105         do {
 106                 unsigned int id;
 107                 unsigned int i;
 108
 109                 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs,
 110                                                   RTE_DIM(objs)) < 0)) {
 111                         struct rte_eth_dev_data *dev_data =
 112                                 rte_eth_devices[rxq->dp.dpq.port_id].data;
 113
 114                         /*
 115                          * It is hardly a safe way to increment counter
 116                          * from different contexts, but all PMDs do it.
 117                          */
 118                         dev_data->rx_mbuf_alloc_failed += RTE_DIM(objs);
 119                         /* Return if we have posted nothing yet */
 120                         if (added == rxq->added)
 121                                 return;
 122                         /* Push posted */
 123                         break;
 124                 }
 125
 126                 for (i = 0, id = added & ptr_mask;
 127                      i < RTE_DIM(objs);
 128                      ++i, ++id) {
 129                         struct rte_mbuf *m = objs[i];
 130                         struct sfc_ef10_rx_sw_desc *rxd;
 131                         rte_iova_t phys_addr;
 132
 133                         SFC_ASSERT((id & ~ptr_mask) == 0);
 134                         rxd = &rxq->sw_ring[id];
 135                         rxd->mbuf = m;
 136
 137                         /*
 138                          * Avoid writing to mbuf. It is cheaper to do it
 139                          * when we receive packet and fill in nearby
 140                          * structure members.
 141                          */
 142
 143                         phys_addr = rte_mbuf_data_iova_default(m);
 144                         EFX_POPULATE_QWORD_2(rxq->rxq_hw_ring[id],
 145                             ESF_DZ_RX_KER_BYTE_CNT, buf_size,
 146                             ESF_DZ_RX_KER_BUF_ADDR, phys_addr);
 147                 }
 148
 149                 added += RTE_DIM(objs);
 150         } while (--bulks > 0);
 151
 152         SFC_ASSERT(rxq->added != added);
 153         rxq->added = added;
 154         sfc_ef10_rx_qpush(rxq->doorbell, added, ptr_mask);
 155 }
 156
 157 static void
 158 sfc_ef10_rx_prefetch_next(struct sfc_ef10_rxq *rxq, unsigned int next_id)
 159 {
 160         struct rte_mbuf *next_mbuf;
 161
 162         /* Prefetch next bunch of software descriptors */
 163         if ((next_id % (RTE_CACHE_LINE_SIZE / sizeof(rxq->sw_ring[0]))) == 0)
 164                 rte_prefetch0(&rxq->sw_ring[next_id]);
 165
 166         /*
 167          * It looks strange to prefetch depending on previous prefetch
 168          * data, but measurements show that it is really efficient and
 169          * increases packet rate.
 170          */
 171         next_mbuf = rxq->sw_ring[next_id].mbuf;
 172         if (likely(next_mbuf != NULL)) {
 173                 /* Prefetch the next mbuf structure */
 174                 rte_mbuf_prefetch_part1(next_mbuf);
 175
 176                 /* Prefetch pseudo header of the next packet */
 177                 /* data_off is not filled in yet */
 178                 /* Yes, data could be not ready yet, but we hope */
 179                 rte_prefetch0((uint8_t *)next_mbuf->buf_addr +
 180                               RTE_PKTMBUF_HEADROOM);
 181         }
 182 }
 183
 184 static uint16_t
 185 sfc_ef10_rx_prepared(struct sfc_ef10_rxq *rxq, struct rte_mbuf **rx_pkts,
 186                      uint16_t nb_pkts)
 187 {
 188         uint16_t n_rx_pkts = RTE_MIN(nb_pkts, rxq->prepared);
 189         unsigned int completed = rxq->completed;
 190         unsigned int i;
 191
 192         rxq->prepared -= n_rx_pkts;
 193         rxq->completed = completed + n_rx_pkts;
 194
 195         for (i = 0; i < n_rx_pkts; ++i, ++completed)
 196                 rx_pkts[i] = rxq->sw_ring[completed & rxq->ptr_mask].mbuf;
 197
 198         return n_rx_pkts;
 199 }
 200
 201 static void
 202 sfc_ef10_rx_ev_to_offloads(struct sfc_ef10_rxq *rxq, const efx_qword_t rx_ev,
 203                            struct rte_mbuf *m)
 204 {
 205         uint32_t tun_ptype = 0;
 206         /* Which event bit is mapped to PKT_RX_IP_CKSUM_* */
 207         int8_t ip_csum_err_bit;
 208         /* Which event bit is mapped to PKT_RX_L4_CKSUM_* */
 209         int8_t l4_csum_err_bit;
 210         uint32_t l2_ptype = 0;
 211         uint32_t l3_ptype = 0;
 212         uint32_t l4_ptype = 0;
 213         uint64_t ol_flags = 0;
 214
 215         if (unlikely(EFX_TEST_QWORD_BIT(rx_ev, ESF_DZ_RX_PARSE_INCOMPLETE_LBN)))
 216                 goto done;
 217
 218         switch (EFX_QWORD_FIELD(rx_ev, ESF_EZ_RX_ENCAP_HDR)) {
 219         default:
 220                 /* Unexpected encapsulation tag class */
 221                 SFC_ASSERT(false);
 222                 /* FALLTHROUGH */
 223         case ESE_EZ_ENCAP_HDR_NONE:
 224                 break;
 225         case ESE_EZ_ENCAP_HDR_VXLAN:
 226                 /*
 227                  * It is definitely UDP, but we have no information
 228                  * about IPv4 vs IPv6 and VLAN tagging.
 229                  */
 230                 tun_ptype = RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L4_UDP;
 231                 break;
 232         case ESE_EZ_ENCAP_HDR_GRE:
 233                 /*
 234                  * We have no information about IPv4 vs IPv6 and VLAN tagging.
 235                  */
 236                 tun_ptype = RTE_PTYPE_TUNNEL_NVGRE;
 237                 break;
 238         }
 239
 240         if (tun_ptype == 0) {
 241                 ip_csum_err_bit = ESF_DZ_RX_IPCKSUM_ERR_LBN;
 242                 l4_csum_err_bit = ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN;
 243         } else {
 244                 ip_csum_err_bit = ESF_EZ_RX_IP_INNER_CHKSUM_ERR_LBN;
 245                 l4_csum_err_bit = ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_LBN;
 246                 if (unlikely(EFX_TEST_QWORD_BIT(rx_ev,
 247                                                 ESF_DZ_RX_IPCKSUM_ERR_LBN)))
 248                         ol_flags |= PKT_RX_EIP_CKSUM_BAD;
 249         }
 250
 251         switch (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_ETH_TAG_CLASS)) {
 252         case ESE_DZ_ETH_TAG_CLASS_NONE:
 253                 l2_ptype = (tun_ptype == 0) ? RTE_PTYPE_L2_ETHER :
 254                         RTE_PTYPE_INNER_L2_ETHER;
 255                 break;
 256         case ESE_DZ_ETH_TAG_CLASS_VLAN1:
 257                 l2_ptype = (tun_ptype == 0) ? RTE_PTYPE_L2_ETHER_VLAN :
 258                         RTE_PTYPE_INNER_L2_ETHER_VLAN;
 259                 break;
 260         case ESE_DZ_ETH_TAG_CLASS_VLAN2:
 261                 l2_ptype = (tun_ptype == 0) ? RTE_PTYPE_L2_ETHER_QINQ :
 262                         RTE_PTYPE_INNER_L2_ETHER_QINQ;
 263                 break;
 264         default:
 265                 /* Unexpected Eth tag class */
 266                 SFC_ASSERT(false);
 267         }
 268
 269         switch (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_L3_CLASS)) {
 270         case ESE_DZ_L3_CLASS_IP4_FRAG:
 271                 l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_FRAG :
 272                         RTE_PTYPE_INNER_L4_FRAG;
 273                 /* FALLTHROUGH */
 274         case ESE_DZ_L3_CLASS_IP4:
 275                 l3_ptype = (tun_ptype == 0) ? RTE_PTYPE_L3_IPV4_EXT_UNKNOWN :
 276                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
 277                 ol_flags |= PKT_RX_RSS_HASH |
 278                         ((EFX_TEST_QWORD_BIT(rx_ev, ip_csum_err_bit)) ?
 279                          PKT_RX_IP_CKSUM_BAD : PKT_RX_IP_CKSUM_GOOD);
 280                 break;
 281         case ESE_DZ_L3_CLASS_IP6_FRAG:
 282                 l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_FRAG :
 283                         RTE_PTYPE_INNER_L4_FRAG;
 284                 /* FALLTHROUGH */
 285         case ESE_DZ_L3_CLASS_IP6:
 286                 l3_ptype = (tun_ptype == 0) ? RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
 287                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
 288                 ol_flags |= PKT_RX_RSS_HASH;
 289                 break;
 290         case ESE_DZ_L3_CLASS_ARP:
 291                 /* Override Layer 2 packet type */
 292                 /* There is no ARP classification for inner packets */
 293                 if (tun_ptype == 0)
 294                         l2_ptype = RTE_PTYPE_L2_ETHER_ARP;
 295                 break;
 296         default:
 297                 /* Unexpected Layer 3 class */
 298                 SFC_ASSERT(false);
 299         }
 300
 301         /*
 302          * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is only
 303          * 2 bits wide on Medford2. Check it is safe to use the Medford2 field
 304          * and values for all EF10 controllers.
 305          */
 306         RTE_BUILD_BUG_ON(ESF_FZ_RX_L4_CLASS_LBN != ESF_DE_RX_L4_CLASS_LBN);
 307         switch (EFX_QWORD_FIELD(rx_ev, ESF_FZ_RX_L4_CLASS)) {
 308         case ESE_FZ_L4_CLASS_TCP:
 309                  RTE_BUILD_BUG_ON(ESE_FZ_L4_CLASS_TCP != ESE_DE_L4_CLASS_TCP);
 310                 l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_TCP :
 311                         RTE_PTYPE_INNER_L4_TCP;
 312                 ol_flags |=
 313                         (EFX_TEST_QWORD_BIT(rx_ev, l4_csum_err_bit)) ?
 314                         PKT_RX_L4_CKSUM_BAD : PKT_RX_L4_CKSUM_GOOD;
 315                 break;
 316         case ESE_FZ_L4_CLASS_UDP:
 317                  RTE_BUILD_BUG_ON(ESE_FZ_L4_CLASS_UDP != ESE_DE_L4_CLASS_UDP);
 318                 l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_UDP :
 319                         RTE_PTYPE_INNER_L4_UDP;
 320                 ol_flags |=
 321                         (EFX_TEST_QWORD_BIT(rx_ev, l4_csum_err_bit)) ?
 322                         PKT_RX_L4_CKSUM_BAD : PKT_RX_L4_CKSUM_GOOD;
 323                 break;
 324         case ESE_FZ_L4_CLASS_UNKNOWN:
 325                  RTE_BUILD_BUG_ON(ESE_FZ_L4_CLASS_UNKNOWN !=
 326                                   ESE_DE_L4_CLASS_UNKNOWN);
 327                 break;
 328         default:
 329                 /* Unexpected Layer 4 class */
 330                 SFC_ASSERT(false);
 331         }
 332
 333         /* Remove RSS hash offload flag if RSS is not enabled */
 334         if (~rxq->flags & SFC_EF10_RXQ_RSS_HASH)
 335                 ol_flags &= ~PKT_RX_RSS_HASH;
 336
 337 done:
 338         m->ol_flags = ol_flags;
 339         m->packet_type = tun_ptype | l2_ptype | l3_ptype | l4_ptype;
 340 }
 341
 342 static uint16_t
 343 sfc_ef10_rx_pseudo_hdr_get_len(const uint8_t *pseudo_hdr)
 344 {
 345         return rte_le_to_cpu_16(*(const uint16_t *)&pseudo_hdr[8]);
 346 }
 347
 348 static uint32_t
 349 sfc_ef10_rx_pseudo_hdr_get_hash(const uint8_t *pseudo_hdr)
 350 {
 351         return rte_le_to_cpu_32(*(const uint32_t *)pseudo_hdr);
 352 }
 353
 354 static uint16_t
 355 sfc_ef10_rx_process_event(struct sfc_ef10_rxq *rxq, efx_qword_t rx_ev,
 356                           struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 357 {
 358         const unsigned int ptr_mask = rxq->ptr_mask;
 359         unsigned int completed = rxq->completed;
 360         unsigned int ready;
 361         struct sfc_ef10_rx_sw_desc *rxd;
 362         struct rte_mbuf *m;
 363         struct rte_mbuf *m0;
 364         uint16_t n_rx_pkts;
 365         const uint8_t *pseudo_hdr;
 366         uint16_t pkt_len;
 367
 368         ready = (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_DSC_PTR_LBITS) - completed) &
 369                 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
 370         SFC_ASSERT(ready > 0);
 371
 372         if (rx_ev.eq_u64[0] &
 373             rte_cpu_to_le_64((1ull << ESF_DZ_RX_ECC_ERR_LBN) |
 374                              (1ull << ESF_DZ_RX_ECRC_ERR_LBN))) {
 375                 SFC_ASSERT(rxq->prepared == 0);
 376                 rxq->completed += ready;
 377                 while (ready-- > 0) {
 378                         rxd = &rxq->sw_ring[completed++ & ptr_mask];
 379                         rte_mempool_put(rxq->refill_mb_pool, rxd->mbuf);
 380                 }
 381                 return 0;
 382         }
 383
 384         n_rx_pkts = RTE_MIN(ready, nb_pkts);
 385         rxq->prepared = ready - n_rx_pkts;
 386         rxq->completed += n_rx_pkts;
 387
 388         rxd = &rxq->sw_ring[completed++ & ptr_mask];
 389
 390         sfc_ef10_rx_prefetch_next(rxq, completed & ptr_mask);
 391
 392         m = rxd->mbuf;
 393
 394         *rx_pkts++ = m;
 395
 396         RTE_BUILD_BUG_ON(sizeof(m->rearm_data[0]) != sizeof(rxq->rearm_data));
 397         m->rearm_data[0] = rxq->rearm_data;
 398
 399         /* Classify packet based on Rx event */
 400         sfc_ef10_rx_ev_to_offloads(rxq, rx_ev, m);
 401
 402         /* data_off already moved past pseudo header */
 403         pseudo_hdr = (uint8_t *)m->buf_addr + RTE_PKTMBUF_HEADROOM;
 404
 405         /*
 406          * Always get RSS hash from pseudo header to avoid
 407          * condition/branching. If it is valid or not depends on
 408          * PKT_RX_RSS_HASH in m->ol_flags.
 409          */
 410         m->hash.rss = sfc_ef10_rx_pseudo_hdr_get_hash(pseudo_hdr);
 411
 412         if (ready == 1)
 413                 pkt_len = EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_BYTES) -
 414                         rxq->prefix_size;
 415         else
 416                 pkt_len = sfc_ef10_rx_pseudo_hdr_get_len(pseudo_hdr);
 417         SFC_ASSERT(pkt_len > 0);
 418         rte_pktmbuf_data_len(m) = pkt_len;
 419         rte_pktmbuf_pkt_len(m) = pkt_len;
 420
 421         SFC_ASSERT(m->next == NULL);
 422
 423         /* Remember mbuf to copy offload flags and packet type from */
 424         m0 = m;
 425         for (--ready; ready > 0; --ready) {
 426                 rxd = &rxq->sw_ring[completed++ & ptr_mask];
 427
 428                 sfc_ef10_rx_prefetch_next(rxq, completed & ptr_mask);
 429
 430                 m = rxd->mbuf;
 431
 432                 if (ready > rxq->prepared)
 433                         *rx_pkts++ = m;
 434
 435                 RTE_BUILD_BUG_ON(sizeof(m->rearm_data[0]) !=
 436                                  sizeof(rxq->rearm_data));
 437                 m->rearm_data[0] = rxq->rearm_data;
 438
 439                 /* Event-dependent information is the same */
 440                 m->ol_flags = m0->ol_flags;
 441                 m->packet_type = m0->packet_type;
 442
 443                 /* data_off already moved past pseudo header */
 444                 pseudo_hdr = (uint8_t *)m->buf_addr + RTE_PKTMBUF_HEADROOM;
 445
 446                 /*
 447                  * Always get RSS hash from pseudo header to avoid
 448                  * condition/branching. If it is valid or not depends on
 449                  * PKT_RX_RSS_HASH in m->ol_flags.
 450                  */
 451                 m->hash.rss = sfc_ef10_rx_pseudo_hdr_get_hash(pseudo_hdr);
 452
 453                 pkt_len = sfc_ef10_rx_pseudo_hdr_get_len(pseudo_hdr);
 454                 SFC_ASSERT(pkt_len > 0);
 455                 rte_pktmbuf_data_len(m) = pkt_len;
 456                 rte_pktmbuf_pkt_len(m) = pkt_len;
 457
 458                 SFC_ASSERT(m->next == NULL);
 459         }
 460
 461         return n_rx_pkts;
 462 }
 463
 464 static bool
 465 sfc_ef10_rx_get_event(struct sfc_ef10_rxq *rxq, efx_qword_t *rx_ev)
 466 {
 467         *rx_ev = rxq->evq_hw_ring[rxq->evq_read_ptr & rxq->ptr_mask];
 468
 469         if (!sfc_ef10_ev_present(*rx_ev))
 470                 return false;
 471
 472         if (unlikely(EFX_QWORD_FIELD(*rx_ev, FSF_AZ_EV_CODE) !=
 473                      FSE_AZ_EV_CODE_RX_EV)) {
 474                 /*
 475                  * Do not move read_ptr to keep the event for exception
 476                  * handling by the control path.
 477                  */
 478                 rxq->flags |= SFC_EF10_RXQ_EXCEPTION;
 479                 sfc_ef10_rx_err(&rxq->dp.dpq,
 480                                 "RxQ exception at EvQ read ptr %#x",
 481                                 rxq->evq_read_ptr);
 482                 return false;
 483         }
 484
 485         rxq->evq_read_ptr++;
 486         return true;
 487 }
 488
 489 static uint16_t
 490 sfc_ef10_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 491 {
 492         struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(rx_queue);
 493         unsigned int evq_old_read_ptr;
 494         uint16_t n_rx_pkts;
 495         efx_qword_t rx_ev;
 496
 497         if (unlikely(rxq->flags &
 498                      (SFC_EF10_RXQ_NOT_RUNNING | SFC_EF10_RXQ_EXCEPTION)))
 499                 return 0;
 500
 501         n_rx_pkts = sfc_ef10_rx_prepared(rxq, rx_pkts, nb_pkts);
 502
 503         evq_old_read_ptr = rxq->evq_read_ptr;
 504         while (n_rx_pkts != nb_pkts && sfc_ef10_rx_get_event(rxq, &rx_ev)) {
 505                 /*
 506                  * DROP_EVENT is an internal to the NIC, software should
 507                  * never see it and, therefore, may ignore it.
 508                  */
 509
 510                 n_rx_pkts += sfc_ef10_rx_process_event(rxq, rx_ev,
 511                                                        rx_pkts + n_rx_pkts,
 512                                                        nb_pkts - n_rx_pkts);
 513         }
 514
 515         sfc_ef10_ev_qclear(rxq->evq_hw_ring, rxq->ptr_mask, evq_old_read_ptr,
 516                            rxq->evq_read_ptr);
 517
 518         /* It is not a problem if we refill in the case of exception */
 519         sfc_ef10_rx_qrefill(rxq);
 520
 521         return n_rx_pkts;
 522 }
 523
 524 static const uint32_t *
 525 sfc_ef10_supported_ptypes_get(uint32_t tunnel_encaps)
 526 {
 527         static const uint32_t ef10_native_ptypes[] = {
 528                 RTE_PTYPE_L2_ETHER,
 529                 RTE_PTYPE_L2_ETHER_ARP,
 530                 RTE_PTYPE_L2_ETHER_VLAN,
 531                 RTE_PTYPE_L2_ETHER_QINQ,
 532                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 533                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 534                 RTE_PTYPE_L4_FRAG,
 535                 RTE_PTYPE_L4_TCP,
 536                 RTE_PTYPE_L4_UDP,
 537                 RTE_PTYPE_UNKNOWN
 538         };
 539         static const uint32_t ef10_overlay_ptypes[] = {
 540                 RTE_PTYPE_L2_ETHER,
 541                 RTE_PTYPE_L2_ETHER_ARP,
 542                 RTE_PTYPE_L2_ETHER_VLAN,
 543                 RTE_PTYPE_L2_ETHER_QINQ,
 544                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 545                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 546                 RTE_PTYPE_L4_FRAG,
 547                 RTE_PTYPE_L4_TCP,
 548                 RTE_PTYPE_L4_UDP,
 549                 RTE_PTYPE_TUNNEL_VXLAN,
 550                 RTE_PTYPE_TUNNEL_NVGRE,
 551                 RTE_PTYPE_INNER_L2_ETHER,
 552                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
 553                 RTE_PTYPE_INNER_L2_ETHER_QINQ,
 554                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
 555                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
 556                 RTE_PTYPE_INNER_L4_FRAG,
 557                 RTE_PTYPE_INNER_L4_TCP,
 558                 RTE_PTYPE_INNER_L4_UDP,
 559                 RTE_PTYPE_UNKNOWN
 560         };
 561
 562         /*
 563          * The function returns static set of supported packet types,
 564          * so we can't build it dynamically based on supported tunnel
 565          * encapsulations and should limit to known sets.
 566          */
 567         switch (tunnel_encaps) {
 568         case (1u << EFX_TUNNEL_PROTOCOL_VXLAN |
 569               1u << EFX_TUNNEL_PROTOCOL_GENEVE |
 570               1u << EFX_TUNNEL_PROTOCOL_NVGRE):
 571                 return ef10_overlay_ptypes;
 572         default:
 573                 SFC_GENERIC_LOG(ERR,
 574                         "Unexpected set of supported tunnel encapsulations: %#x",
 575                         tunnel_encaps);
 576                 /* FALLTHROUGH */
 577         case 0:
 578                 return ef10_native_ptypes;
 579         }
 580 }
 581
 582 static sfc_dp_rx_qdesc_npending_t sfc_ef10_rx_qdesc_npending;
 583 static unsigned int
 584 sfc_ef10_rx_qdesc_npending(__rte_unused struct sfc_dp_rxq *dp_rxq)
 585 {
 586         /*
 587          * Correct implementation requires EvQ polling and events
 588          * processing (keeping all ready mbufs in prepared).
 589          */
 590         return -ENOTSUP;
 591 }
 592
 593 static sfc_dp_rx_qdesc_status_t sfc_ef10_rx_qdesc_status;
 594 static int
 595 sfc_ef10_rx_qdesc_status(__rte_unused struct sfc_dp_rxq *dp_rxq,
 596                          __rte_unused uint16_t offset)
 597 {
 598         return -ENOTSUP;
 599 }
 600
 601
 602 static sfc_dp_rx_get_dev_info_t sfc_ef10_rx_get_dev_info;
 603 static void
 604 sfc_ef10_rx_get_dev_info(struct rte_eth_dev_info *dev_info)
 605 {
 606         /*
 607          * Number of descriptors just defines maximum number of pushed
 608          * descriptors (fill level).
 609          */
 610         dev_info->rx_desc_lim.nb_min = SFC_RX_REFILL_BULK;
 611         dev_info->rx_desc_lim.nb_align = SFC_RX_REFILL_BULK;
 612 }
 613
 614
 615 static sfc_dp_rx_qsize_up_rings_t sfc_ef10_rx_qsize_up_rings;
 616 static int
 617 sfc_ef10_rx_qsize_up_rings(uint16_t nb_rx_desc,
 618                            unsigned int *rxq_entries,
 619                            unsigned int *evq_entries,
 620                            unsigned int *rxq_max_fill_level)
 621 {
 622         /*
 623          * rte_ethdev API guarantees that the number meets min, max and
 624          * alignment requirements.
 625          */
 626         if (nb_rx_desc <= EFX_RXQ_MINNDESCS)
 627                 *rxq_entries = EFX_RXQ_MINNDESCS;
 628         else
 629                 *rxq_entries = rte_align32pow2(nb_rx_desc);
 630
 631         *evq_entries = *rxq_entries;
 632
 633         *rxq_max_fill_level = RTE_MIN(nb_rx_desc,
 634                                       SFC_EF10_RXQ_LIMIT(*evq_entries));
 635         return 0;
 636 }
 637
 638
 639 static uint64_t
 640 sfc_ef10_mk_mbuf_rearm_data(uint16_t port_id, uint16_t prefix_size)
 641 {
 642         struct rte_mbuf m;
 643
 644         memset(&m, 0, sizeof(m));
 645
 646         rte_mbuf_refcnt_set(&m, 1);
 647         m.data_off = RTE_PKTMBUF_HEADROOM + prefix_size;
 648         m.nb_segs = 1;
 649         m.port = port_id;
 650
 651         /* rearm_data covers structure members filled in above */
 652         rte_compiler_barrier();
 653         RTE_BUILD_BUG_ON(sizeof(m.rearm_data[0]) != sizeof(uint64_t));
 654         return m.rearm_data[0];
 655 }
 656
 657 static sfc_dp_rx_qcreate_t sfc_ef10_rx_qcreate;
 658 static int
 659 sfc_ef10_rx_qcreate(uint16_t port_id, uint16_t queue_id,
 660                     const struct rte_pci_addr *pci_addr, int socket_id,
 661                     const struct sfc_dp_rx_qcreate_info *info,
 662                     struct sfc_dp_rxq **dp_rxqp)
 663 {
 664         struct sfc_ef10_rxq *rxq;
 665         int rc;
 666
 667         rc = EINVAL;
 668         if (info->rxq_entries != info->evq_entries)
 669                 goto fail_rxq_args;
 670
 671         rc = ENOMEM;
 672         rxq = rte_zmalloc_socket("sfc-ef10-rxq", sizeof(*rxq),
 673                                  RTE_CACHE_LINE_SIZE, socket_id);
 674         if (rxq == NULL)
 675                 goto fail_rxq_alloc;
 676
 677         sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr);
 678
 679         rc = ENOMEM;
 680         rxq->sw_ring = rte_calloc_socket("sfc-ef10-rxq-sw_ring",
 681                                          info->rxq_entries,
 682                                          sizeof(*rxq->sw_ring),
 683                                          RTE_CACHE_LINE_SIZE, socket_id);
 684         if (rxq->sw_ring == NULL)
 685                 goto fail_desc_alloc;
 686
 687         rxq->flags |= SFC_EF10_RXQ_NOT_RUNNING;
 688         if (info->flags & SFC_RXQ_FLAG_RSS_HASH)
 689                 rxq->flags |= SFC_EF10_RXQ_RSS_HASH;
 690         rxq->ptr_mask = info->rxq_entries - 1;
 691         rxq->evq_hw_ring = info->evq_hw_ring;
 692         rxq->max_fill_level = info->max_fill_level;
 693         rxq->refill_threshold = info->refill_threshold;
 694         rxq->rearm_data =
 695                 sfc_ef10_mk_mbuf_rearm_data(port_id, info->prefix_size);
 696         rxq->prefix_size = info->prefix_size;
 697         rxq->buf_size = info->buf_size;
 698         rxq->refill_mb_pool = info->refill_mb_pool;
 699         rxq->rxq_hw_ring = info->rxq_hw_ring;
 700         rxq->doorbell = (volatile uint8_t *)info->mem_bar +
 701                         ER_DZ_RX_DESC_UPD_REG_OFST +
 702                         (info->hw_index << info->vi_window_shift);
 703
 704         *dp_rxqp = &rxq->dp;
 705         return 0;
 706
 707 fail_desc_alloc:
 708         rte_free(rxq);
 709
 710 fail_rxq_alloc:
 711 fail_rxq_args:
 712         return rc;
 713 }
 714
 715 static sfc_dp_rx_qdestroy_t sfc_ef10_rx_qdestroy;
 716 static void
 717 sfc_ef10_rx_qdestroy(struct sfc_dp_rxq *dp_rxq)
 718 {
 719         struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
 720
 721         rte_free(rxq->sw_ring);
 722         rte_free(rxq);
 723 }
 724
 725 static sfc_dp_rx_qstart_t sfc_ef10_rx_qstart;
 726 static int
 727 sfc_ef10_rx_qstart(struct sfc_dp_rxq *dp_rxq, unsigned int evq_read_ptr)
 728 {
 729         struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
 730
 731         rxq->prepared = 0;
 732         rxq->completed = rxq->added = 0;
 733
 734         sfc_ef10_rx_qrefill(rxq);
 735
 736         rxq->evq_read_ptr = evq_read_ptr;
 737
 738         rxq->flags |= SFC_EF10_RXQ_STARTED;
 739         rxq->flags &= ~(SFC_EF10_RXQ_NOT_RUNNING | SFC_EF10_RXQ_EXCEPTION);
 740
 741         return 0;
 742 }
 743
 744 static sfc_dp_rx_qstop_t sfc_ef10_rx_qstop;
 745 static void
 746 sfc_ef10_rx_qstop(struct sfc_dp_rxq *dp_rxq, unsigned int *evq_read_ptr)
 747 {
 748         struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
 749
 750         rxq->flags |= SFC_EF10_RXQ_NOT_RUNNING;
 751
 752         *evq_read_ptr = rxq->evq_read_ptr;
 753 }
 754
 755 static sfc_dp_rx_qrx_ev_t sfc_ef10_rx_qrx_ev;
 756 static bool
 757 sfc_ef10_rx_qrx_ev(struct sfc_dp_rxq *dp_rxq, __rte_unused unsigned int id)
 758 {
 759         __rte_unused struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
 760
 761         SFC_ASSERT(rxq->flags & SFC_EF10_RXQ_NOT_RUNNING);
 762
 763         /*
 764          * It is safe to ignore Rx event since we free all mbufs on
 765          * queue purge anyway.
 766          */
 767
 768         return false;
 769 }
 770
 771 static sfc_dp_rx_qpurge_t sfc_ef10_rx_qpurge;
 772 static void
 773 sfc_ef10_rx_qpurge(struct sfc_dp_rxq *dp_rxq)
 774 {
 775         struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
 776         unsigned int i;
 777         struct sfc_ef10_rx_sw_desc *rxd;
 778
 779         for (i = rxq->completed; i != rxq->added; ++i) {
 780                 rxd = &rxq->sw_ring[i & rxq->ptr_mask];
 781                 rte_mempool_put(rxq->refill_mb_pool, rxd->mbuf);
 782                 rxd->mbuf = NULL;
 783         }
 784
 785         rxq->flags &= ~SFC_EF10_RXQ_STARTED;
 786 }
 787
 788 struct sfc_dp_rx sfc_ef10_rx = {
 789         .dp = {
 790                 .name           = SFC_KVARG_DATAPATH_EF10,
 791                 .type           = SFC_DP_RX,
 792                 .hw_fw_caps     = SFC_DP_HW_FW_CAP_EF10,
 793         },
 794         .features               = SFC_DP_RX_FEAT_MULTI_PROCESS |
 795                                   SFC_DP_RX_FEAT_TUNNELS,
 796         .get_dev_info           = sfc_ef10_rx_get_dev_info,
 797         .qsize_up_rings         = sfc_ef10_rx_qsize_up_rings,
 798         .qcreate                = sfc_ef10_rx_qcreate,
 799         .qdestroy               = sfc_ef10_rx_qdestroy,
 800         .qstart                 = sfc_ef10_rx_qstart,
 801         .qstop                  = sfc_ef10_rx_qstop,
 802         .qrx_ev                 = sfc_ef10_rx_qrx_ev,
 803         .qpurge                 = sfc_ef10_rx_qpurge,
 804         .supported_ptypes_get   = sfc_ef10_supported_ptypes_get,
 805         .qdesc_npending         = sfc_ef10_rx_qdesc_npending,
 806         .qdesc_status           = sfc_ef10_rx_qdesc_status,
 807         .pkt_burst              = sfc_ef10_recv_pkts,
 808 };