2 * Copyright (c) 2016 Solarflare Communications Inc.
5 * This software was jointly developed between OKTET Labs (under contract
6 * for Solarflare) and Solarflare Communications, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
11 * 1. Redistributions of source code must retain the above copyright notice,
12 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright notice,
14 * this list of conditions and the following disclaimer in the documentation
15 * and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
19 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
21 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
23 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
24 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
25 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
26 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
27 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #include <rte_mempool.h>
35 #include "sfc_debug.h"
39 #include "sfc_tweak.h"
42 * Maximum number of Rx queue flush attempt in the case of failure or
45 #define SFC_RX_QFLUSH_ATTEMPTS (3)
48 * Time to wait between event queue polling attempts when waiting for Rx
49 * queue flush done or failed events.
51 #define SFC_RX_QFLUSH_POLL_WAIT_MS (1)
54 * Maximum number of event queue polling attempts when waiting for Rx queue
55 * flush done or failed events. It defines Rx queue flush attempt timeout
56 * together with SFC_RX_QFLUSH_POLL_WAIT_MS.
58 #define SFC_RX_QFLUSH_POLL_ATTEMPTS (2000)
61 sfc_rx_qflush_done(struct sfc_rxq *rxq)
63 rxq->state |= SFC_RXQ_FLUSHED;
64 rxq->state &= ~SFC_RXQ_FLUSHING;
68 sfc_rx_qflush_failed(struct sfc_rxq *rxq)
70 rxq->state |= SFC_RXQ_FLUSH_FAILED;
71 rxq->state &= ~SFC_RXQ_FLUSHING;
75 sfc_rx_qrefill(struct sfc_rxq *rxq)
77 unsigned int free_space;
79 void *objs[SFC_RX_REFILL_BULK];
80 efsys_dma_addr_t addr[RTE_DIM(objs)];
81 unsigned int added = rxq->added;
84 struct sfc_rx_sw_desc *rxd;
86 uint8_t port_id = rxq->port_id;
88 free_space = EFX_RXQ_LIMIT(rxq->ptr_mask + 1) -
89 (added - rxq->completed);
91 if (free_space < rxq->refill_threshold)
94 bulks = free_space / RTE_DIM(objs);
96 id = added & rxq->ptr_mask;
98 if (rte_mempool_get_bulk(rxq->refill_mb_pool, objs,
101 * It is hardly a safe way to increment counter
102 * from different contexts, but all PMDs do it.
104 rxq->evq->sa->eth_dev->data->rx_mbuf_alloc_failed +=
109 for (i = 0; i < RTE_DIM(objs);
110 ++i, id = (id + 1) & rxq->ptr_mask) {
113 rxd = &rxq->sw_desc[id];
116 rte_mbuf_refcnt_set(m, 1);
117 m->data_off = RTE_PKTMBUF_HEADROOM;
122 addr[i] = rte_pktmbuf_mtophys(m);
125 efx_rx_qpost(rxq->common, addr, rxq->buf_size,
126 RTE_DIM(objs), rxq->completed, added);
127 added += RTE_DIM(objs);
130 /* Push doorbell if something is posted */
131 if (rxq->added != added) {
133 efx_rx_qpush(rxq->common, added, &rxq->pushed);
138 sfc_rx_desc_flags_to_offload_flags(const unsigned int desc_flags)
140 uint64_t mbuf_flags = 0;
142 switch (desc_flags & (EFX_PKT_IPV4 | EFX_CKSUM_IPV4)) {
143 case (EFX_PKT_IPV4 | EFX_CKSUM_IPV4):
144 mbuf_flags |= PKT_RX_IP_CKSUM_GOOD;
147 mbuf_flags |= PKT_RX_IP_CKSUM_BAD;
150 RTE_BUILD_BUG_ON(PKT_RX_IP_CKSUM_UNKNOWN != 0);
151 SFC_ASSERT((mbuf_flags & PKT_RX_IP_CKSUM_MASK) ==
152 PKT_RX_IP_CKSUM_UNKNOWN);
156 switch ((desc_flags &
157 (EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP))) {
158 case (EFX_PKT_TCP | EFX_CKSUM_TCPUDP):
159 case (EFX_PKT_UDP | EFX_CKSUM_TCPUDP):
160 mbuf_flags |= PKT_RX_L4_CKSUM_GOOD;
164 mbuf_flags |= PKT_RX_L4_CKSUM_BAD;
167 RTE_BUILD_BUG_ON(PKT_RX_L4_CKSUM_UNKNOWN != 0);
168 SFC_ASSERT((mbuf_flags & PKT_RX_L4_CKSUM_MASK) ==
169 PKT_RX_L4_CKSUM_UNKNOWN);
177 sfc_rx_desc_flags_to_packet_type(const unsigned int desc_flags)
179 return RTE_PTYPE_L2_ETHER |
180 ((desc_flags & EFX_PKT_IPV4) ?
181 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN : 0) |
182 ((desc_flags & EFX_PKT_IPV6) ?
183 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN : 0) |
184 ((desc_flags & EFX_PKT_TCP) ? RTE_PTYPE_L4_TCP : 0) |
185 ((desc_flags & EFX_PKT_UDP) ? RTE_PTYPE_L4_UDP : 0);
189 sfc_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
191 struct sfc_rxq *rxq = rx_queue;
192 unsigned int completed;
193 unsigned int prefix_size = rxq->prefix_size;
194 unsigned int done_pkts = 0;
195 boolean_t discard_next = B_FALSE;
197 if (unlikely((rxq->state & SFC_RXQ_RUNNING) == 0))
200 sfc_ev_qpoll(rxq->evq);
202 completed = rxq->completed;
203 while (completed != rxq->pending && done_pkts < nb_pkts) {
205 struct sfc_rx_sw_desc *rxd;
207 unsigned int seg_len;
208 unsigned int desc_flags;
210 id = completed++ & rxq->ptr_mask;
211 rxd = &rxq->sw_desc[id];
213 desc_flags = rxd->flags;
218 if (desc_flags & (EFX_ADDR_MISMATCH | EFX_DISCARD))
221 if (desc_flags & EFX_PKT_CONT)
224 if (desc_flags & EFX_PKT_PREFIX_LEN) {
228 rc = efx_pseudo_hdr_pkt_length_get(rxq->common,
229 rte_pktmbuf_mtod(m, uint8_t *), &tmp_size);
233 seg_len = rxd->size - prefix_size;
236 m->data_off += prefix_size;
237 rte_pktmbuf_data_len(m) = seg_len;
238 rte_pktmbuf_pkt_len(m) = seg_len;
240 m->ol_flags = sfc_rx_desc_flags_to_offload_flags(desc_flags);
241 m->packet_type = sfc_rx_desc_flags_to_packet_type(desc_flags);
248 discard_next = ((desc_flags & EFX_PKT_CONT) != 0);
249 rte_mempool_put(rxq->refill_mb_pool, m);
253 rxq->completed = completed;
261 sfc_rx_qpurge(struct sfc_rxq *rxq)
264 struct sfc_rx_sw_desc *rxd;
266 for (i = rxq->completed; i != rxq->added; ++i) {
267 rxd = &rxq->sw_desc[i & rxq->ptr_mask];
268 rte_mempool_put(rxq->refill_mb_pool, rxd->mbuf);
274 sfc_rx_qflush(struct sfc_adapter *sa, unsigned int sw_index)
277 unsigned int retry_count;
278 unsigned int wait_count;
280 rxq = sa->rxq_info[sw_index].rxq;
281 SFC_ASSERT(rxq->state & SFC_RXQ_STARTED);
284 * Retry Rx queue flushing in the case of flush failed or
285 * timeout. In the worst case it can delay for 6 seconds.
287 for (retry_count = 0;
288 ((rxq->state & SFC_RXQ_FLUSHED) == 0) &&
289 (retry_count < SFC_RX_QFLUSH_ATTEMPTS);
291 if (efx_rx_qflush(rxq->common) != 0) {
292 rxq->state |= SFC_RXQ_FLUSH_FAILED;
295 rxq->state &= ~SFC_RXQ_FLUSH_FAILED;
296 rxq->state |= SFC_RXQ_FLUSHING;
299 * Wait for Rx queue flush done or failed event at least
300 * SFC_RX_QFLUSH_POLL_WAIT_MS milliseconds and not more
301 * than 2 seconds (SFC_RX_QFLUSH_POLL_WAIT_MS multiplied
302 * by SFC_RX_QFLUSH_POLL_ATTEMPTS).
306 rte_delay_ms(SFC_RX_QFLUSH_POLL_WAIT_MS);
307 sfc_ev_qpoll(rxq->evq);
308 } while ((rxq->state & SFC_RXQ_FLUSHING) &&
309 (wait_count++ < SFC_RX_QFLUSH_POLL_ATTEMPTS));
311 if (rxq->state & SFC_RXQ_FLUSHING)
312 sfc_err(sa, "RxQ %u flush timed out", sw_index);
314 if (rxq->state & SFC_RXQ_FLUSH_FAILED)
315 sfc_err(sa, "RxQ %u flush failed", sw_index);
317 if (rxq->state & SFC_RXQ_FLUSHED)
318 sfc_info(sa, "RxQ %u flushed", sw_index);
325 sfc_rx_qstart(struct sfc_adapter *sa, unsigned int sw_index)
327 struct sfc_rxq_info *rxq_info;
332 sfc_log_init(sa, "sw_index=%u", sw_index);
334 SFC_ASSERT(sw_index < sa->rxq_count);
336 rxq_info = &sa->rxq_info[sw_index];
338 SFC_ASSERT(rxq->state == SFC_RXQ_INITIALIZED);
342 rc = sfc_ev_qstart(sa, evq->evq_index);
346 rc = efx_rx_qcreate(sa->nic, rxq->hw_index, 0, rxq_info->type,
347 &rxq->mem, rxq_info->entries,
348 0 /* not used on EF10 */, evq->common,
351 goto fail_rx_qcreate;
353 efx_rx_qenable(rxq->common);
355 rxq->pending = rxq->completed = rxq->added = rxq->pushed = 0;
357 rxq->state |= (SFC_RXQ_STARTED | SFC_RXQ_RUNNING);
362 rc = efx_mac_filter_default_rxq_set(sa->nic, rxq->common,
365 goto fail_mac_filter_default_rxq_set;
368 /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
369 sa->eth_dev->data->rx_queue_state[sw_index] =
370 RTE_ETH_QUEUE_STATE_STARTED;
374 fail_mac_filter_default_rxq_set:
375 sfc_rx_qflush(sa, sw_index);
378 sfc_ev_qstop(sa, evq->evq_index);
385 sfc_rx_qstop(struct sfc_adapter *sa, unsigned int sw_index)
387 struct sfc_rxq_info *rxq_info;
390 sfc_log_init(sa, "sw_index=%u", sw_index);
392 SFC_ASSERT(sw_index < sa->rxq_count);
394 rxq_info = &sa->rxq_info[sw_index];
396 SFC_ASSERT(rxq->state & SFC_RXQ_STARTED);
398 /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
399 sa->eth_dev->data->rx_queue_state[sw_index] =
400 RTE_ETH_QUEUE_STATE_STOPPED;
402 rxq->state &= ~SFC_RXQ_RUNNING;
405 efx_mac_filter_default_rxq_clear(sa->nic);
407 sfc_rx_qflush(sa, sw_index);
409 rxq->state = SFC_RXQ_INITIALIZED;
411 efx_rx_qdestroy(rxq->common);
413 sfc_ev_qstop(sa, rxq->evq->evq_index);
417 sfc_rx_qcheck_conf(struct sfc_adapter *sa, uint16_t nb_rx_desc,
418 const struct rte_eth_rxconf *rx_conf)
420 const uint16_t rx_free_thresh_max = EFX_RXQ_LIMIT(nb_rx_desc);
423 if (rx_conf->rx_thresh.pthresh != 0 ||
424 rx_conf->rx_thresh.hthresh != 0 ||
425 rx_conf->rx_thresh.wthresh != 0) {
427 "RxQ prefetch/host/writeback thresholds are not supported");
431 if (rx_conf->rx_free_thresh > rx_free_thresh_max) {
433 "RxQ free threshold too large: %u vs maximum %u",
434 rx_conf->rx_free_thresh, rx_free_thresh_max);
438 if (rx_conf->rx_drop_en == 0) {
439 sfc_err(sa, "RxQ drop disable is not supported");
443 if (rx_conf->rx_deferred_start != 0) {
444 sfc_err(sa, "RxQ deferred start is not supported");
452 sfc_rx_mbuf_data_alignment(struct rte_mempool *mb_pool)
457 /* The mbuf object itself is always cache line aligned */
458 order = rte_bsf32(RTE_CACHE_LINE_SIZE);
460 /* Data offset from mbuf object start */
461 data_off = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(mb_pool) +
462 RTE_PKTMBUF_HEADROOM;
464 order = MIN(order, rte_bsf32(data_off));
466 return 1u << (order - 1);
470 sfc_rx_mb_pool_buf_size(struct sfc_adapter *sa, struct rte_mempool *mb_pool)
472 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
473 const uint32_t nic_align_start = MAX(1, encp->enc_rx_buf_align_start);
474 const uint32_t nic_align_end = MAX(1, encp->enc_rx_buf_align_end);
476 unsigned int buf_aligned;
477 unsigned int start_alignment;
478 unsigned int end_padding_alignment;
480 /* Below it is assumed that both alignments are power of 2 */
481 SFC_ASSERT(rte_is_power_of_2(nic_align_start));
482 SFC_ASSERT(rte_is_power_of_2(nic_align_end));
485 * mbuf is always cache line aligned, double-check
486 * that it meets rx buffer start alignment requirements.
489 /* Start from mbuf pool data room size */
490 buf_size = rte_pktmbuf_data_room_size(mb_pool);
492 /* Remove headroom */
493 if (buf_size <= RTE_PKTMBUF_HEADROOM) {
495 "RxQ mbuf pool %s object data room size %u is smaller than headroom %u",
496 mb_pool->name, buf_size, RTE_PKTMBUF_HEADROOM);
499 buf_size -= RTE_PKTMBUF_HEADROOM;
501 /* Calculate guaranteed data start alignment */
502 buf_aligned = sfc_rx_mbuf_data_alignment(mb_pool);
504 /* Reserve space for start alignment */
505 if (buf_aligned < nic_align_start) {
506 start_alignment = nic_align_start - buf_aligned;
507 if (buf_size <= start_alignment) {
509 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u and buffer start alignment %u required by NIC",
511 rte_pktmbuf_data_room_size(mb_pool),
512 RTE_PKTMBUF_HEADROOM, start_alignment);
515 buf_aligned = nic_align_start;
516 buf_size -= start_alignment;
521 /* Make sure that end padding does not write beyond the buffer */
522 if (buf_aligned < nic_align_end) {
524 * Estimate space which can be lost. If guarnteed buffer
525 * size is odd, lost space is (nic_align_end - 1). More
526 * accurate formula is below.
528 end_padding_alignment = nic_align_end -
529 MIN(buf_aligned, 1u << (rte_bsf32(buf_size) - 1));
530 if (buf_size <= end_padding_alignment) {
532 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u, buffer start alignment %u and end padding alignment %u required by NIC",
534 rte_pktmbuf_data_room_size(mb_pool),
535 RTE_PKTMBUF_HEADROOM, start_alignment,
536 end_padding_alignment);
539 buf_size -= end_padding_alignment;
542 * Start is aligned the same or better than end,
545 buf_size = P2ALIGN(buf_size, nic_align_end);
552 sfc_rx_qinit(struct sfc_adapter *sa, unsigned int sw_index,
553 uint16_t nb_rx_desc, unsigned int socket_id,
554 const struct rte_eth_rxconf *rx_conf,
555 struct rte_mempool *mb_pool)
557 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
560 struct sfc_rxq_info *rxq_info;
561 unsigned int evq_index;
565 rc = sfc_rx_qcheck_conf(sa, nb_rx_desc, rx_conf);
569 buf_size = sfc_rx_mb_pool_buf_size(sa, mb_pool);
571 sfc_err(sa, "RxQ %u mbuf pool object size is too small",
577 if ((buf_size < sa->port.pdu + encp->enc_rx_prefix_size) &&
578 !sa->eth_dev->data->dev_conf.rxmode.enable_scatter) {
579 sfc_err(sa, "Rx scatter is disabled and RxQ %u mbuf pool "
580 "object size is too small", sw_index);
581 sfc_err(sa, "RxQ %u calculated Rx buffer size is %u vs "
582 "PDU size %u plus Rx prefix %u bytes",
583 sw_index, buf_size, (unsigned int)sa->port.pdu,
584 encp->enc_rx_prefix_size);
589 SFC_ASSERT(sw_index < sa->rxq_count);
590 rxq_info = &sa->rxq_info[sw_index];
592 SFC_ASSERT(nb_rx_desc <= rxq_info->max_entries);
593 rxq_info->entries = nb_rx_desc;
594 rxq_info->type = EFX_RXQ_TYPE_DEFAULT;
596 evq_index = sfc_evq_index_by_rxq_sw_index(sa, sw_index);
598 rc = sfc_ev_qinit(sa, evq_index, rxq_info->entries, socket_id);
602 evq = sa->evq_info[evq_index].evq;
605 rxq = rte_zmalloc_socket("sfc-rxq", sizeof(*rxq), RTE_CACHE_LINE_SIZE,
610 rc = sfc_dma_alloc(sa, "rxq", sw_index, EFX_RXQ_SIZE(rxq_info->entries),
611 socket_id, &rxq->mem);
616 rxq->sw_desc = rte_calloc_socket("sfc-rxq-sw_desc", rxq_info->entries,
617 sizeof(*rxq->sw_desc),
618 RTE_CACHE_LINE_SIZE, socket_id);
619 if (rxq->sw_desc == NULL)
620 goto fail_desc_alloc;
624 rxq->ptr_mask = rxq_info->entries - 1;
625 rxq->refill_threshold = rx_conf->rx_free_thresh;
626 rxq->refill_mb_pool = mb_pool;
627 rxq->buf_size = buf_size;
628 rxq->hw_index = sw_index;
629 rxq->port_id = sa->eth_dev->data->port_id;
631 /* Cache limits required on datapath in RxQ structure */
632 rxq->batch_max = encp->enc_rx_batch_max;
633 rxq->prefix_size = encp->enc_rx_prefix_size;
635 rxq->state = SFC_RXQ_INITIALIZED;
642 sfc_dma_free(sa, &rxq->mem);
648 sfc_ev_qfini(sa, evq_index);
651 rxq_info->entries = 0;
654 sfc_log_init(sa, "failed %d", rc);
659 sfc_rx_qfini(struct sfc_adapter *sa, unsigned int sw_index)
661 struct sfc_rxq_info *rxq_info;
664 SFC_ASSERT(sw_index < sa->rxq_count);
666 rxq_info = &sa->rxq_info[sw_index];
669 SFC_ASSERT(rxq->state == SFC_RXQ_INITIALIZED);
671 rxq_info->rxq = NULL;
672 rxq_info->entries = 0;
674 rte_free(rxq->sw_desc);
675 sfc_dma_free(sa, &rxq->mem);
680 sfc_rx_start(struct sfc_adapter *sa)
682 unsigned int sw_index;
685 sfc_log_init(sa, "rxq_count=%u", sa->rxq_count);
687 rc = efx_rx_init(sa->nic);
691 for (sw_index = 0; sw_index < sa->rxq_count; ++sw_index) {
692 rc = sfc_rx_qstart(sa, sw_index);
700 while (sw_index-- > 0)
701 sfc_rx_qstop(sa, sw_index);
703 efx_rx_fini(sa->nic);
706 sfc_log_init(sa, "failed %d", rc);
711 sfc_rx_stop(struct sfc_adapter *sa)
713 unsigned int sw_index;
715 sfc_log_init(sa, "rxq_count=%u", sa->rxq_count);
717 sw_index = sa->rxq_count;
718 while (sw_index-- > 0) {
719 if (sa->rxq_info[sw_index].rxq != NULL)
720 sfc_rx_qstop(sa, sw_index);
723 efx_rx_fini(sa->nic);
727 sfc_rx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index)
729 struct sfc_rxq_info *rxq_info = &sa->rxq_info[sw_index];
730 unsigned int max_entries;
732 max_entries = EFX_RXQ_MAXNDESCS;
733 SFC_ASSERT(rte_is_power_of_2(max_entries));
735 rxq_info->max_entries = max_entries;
741 sfc_rx_check_mode(struct sfc_adapter *sa, struct rte_eth_rxmode *rxmode)
745 switch (rxmode->mq_mode) {
747 /* No special checks are required */
750 sfc_err(sa, "Rx multi-queue mode %u not supported",
755 if (rxmode->header_split) {
756 sfc_err(sa, "Header split on Rx not supported");
760 if (rxmode->hw_vlan_filter) {
761 sfc_err(sa, "HW VLAN filtering not supported");
765 if (rxmode->hw_vlan_strip) {
766 sfc_err(sa, "HW VLAN stripping not supported");
770 if (rxmode->hw_vlan_extend) {
772 "Q-in-Q HW VLAN stripping not supported");
776 if (!rxmode->hw_strip_crc) {
778 "FCS stripping control not supported - always stripped");
779 rxmode->hw_strip_crc = 1;
782 if (rxmode->enable_scatter) {
783 sfc_err(sa, "Scatter on Rx not supported");
787 if (rxmode->enable_lro) {
788 sfc_err(sa, "LRO not supported");
796 * Initialize Rx subsystem.
798 * Called at device configuration stage when number of receive queues is
799 * specified together with other device level receive configuration.
801 * It should be used to allocate NUMA-unaware resources.
804 sfc_rx_init(struct sfc_adapter *sa)
806 struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
807 unsigned int sw_index;
810 rc = sfc_rx_check_mode(sa, &dev_conf->rxmode);
812 goto fail_check_mode;
814 sa->rxq_count = sa->eth_dev->data->nb_rx_queues;
817 sa->rxq_info = rte_calloc_socket("sfc-rxqs", sa->rxq_count,
818 sizeof(struct sfc_rxq_info), 0,
820 if (sa->rxq_info == NULL)
821 goto fail_rxqs_alloc;
823 for (sw_index = 0; sw_index < sa->rxq_count; ++sw_index) {
824 rc = sfc_rx_qinit_info(sa, sw_index);
826 goto fail_rx_qinit_info;
832 rte_free(sa->rxq_info);
838 sfc_log_init(sa, "failed %d", rc);
843 * Shutdown Rx subsystem.
845 * Called at device close stage, for example, before device
846 * reconfiguration or shutdown.
849 sfc_rx_fini(struct sfc_adapter *sa)
851 unsigned int sw_index;
853 sw_index = sa->rxq_count;
854 while (sw_index-- > 0) {
855 if (sa->rxq_info[sw_index].rxq != NULL)
856 sfc_rx_qfini(sa, sw_index);
859 rte_free(sa->rxq_info);