drivers/net/sfc/sfc_rx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2016-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  *
   6  * This software was jointly developed between OKTET Labs (under contract
   7  * for Solarflare) and Solarflare Communications, Inc.
   8  */
   9
  10 #include <rte_mempool.h>
  11
  12 #include "efx.h"
  13
  14 #include "sfc.h"
  15 #include "sfc_debug.h"
  16 #include "sfc_log.h"
  17 #include "sfc_ev.h"
  18 #include "sfc_rx.h"
  19 #include "sfc_kvargs.h"
  20 #include "sfc_tweak.h"
  21
  22 /*
  23  * Maximum number of Rx queue flush attempt in the case of failure or
  24  * flush timeout
  25  */
  26 #define SFC_RX_QFLUSH_ATTEMPTS          (3)
  27
  28 /*
  29  * Time to wait between event queue polling attempts when waiting for Rx
  30  * queue flush done or failed events.
  31  */
  32 #define SFC_RX_QFLUSH_POLL_WAIT_MS      (1)
  33
  34 /*
  35  * Maximum number of event queue polling attempts when waiting for Rx queue
  36  * flush done or failed events. It defines Rx queue flush attempt timeout
  37  * together with SFC_RX_QFLUSH_POLL_WAIT_MS.
  38  */
  39 #define SFC_RX_QFLUSH_POLL_ATTEMPTS     (2000)
  40
  41 void
  42 sfc_rx_qflush_done(struct sfc_rxq_info *rxq_info)
  43 {
  44         rxq_info->state |= SFC_RXQ_FLUSHED;
  45         rxq_info->state &= ~SFC_RXQ_FLUSHING;
  46 }
  47
  48 void
  49 sfc_rx_qflush_failed(struct sfc_rxq_info *rxq_info)
  50 {
  51         rxq_info->state |= SFC_RXQ_FLUSH_FAILED;
  52         rxq_info->state &= ~SFC_RXQ_FLUSHING;
  53 }
  54
  55 static void
  56 sfc_efx_rx_qrefill(struct sfc_efx_rxq *rxq)
  57 {
  58         unsigned int free_space;
  59         unsigned int bulks;
  60         void *objs[SFC_RX_REFILL_BULK];
  61         efsys_dma_addr_t addr[RTE_DIM(objs)];
  62         unsigned int added = rxq->added;
  63         unsigned int id;
  64         unsigned int i;
  65         struct sfc_efx_rx_sw_desc *rxd;
  66         struct rte_mbuf *m;
  67         uint16_t port_id = rxq->dp.dpq.port_id;
  68
  69         free_space = rxq->max_fill_level - (added - rxq->completed);
  70
  71         if (free_space < rxq->refill_threshold)
  72                 return;
  73
  74         bulks = free_space / RTE_DIM(objs);
  75         /* refill_threshold guarantees that bulks is positive */
  76         SFC_ASSERT(bulks > 0);
  77
  78         id = added & rxq->ptr_mask;
  79         do {
  80                 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs,
  81                                                   RTE_DIM(objs)) < 0)) {
  82                         /*
  83                          * It is hardly a safe way to increment counter
  84                          * from different contexts, but all PMDs do it.
  85                          */
  86                         rxq->evq->sa->eth_dev->data->rx_mbuf_alloc_failed +=
  87                                 RTE_DIM(objs);
  88                         /* Return if we have posted nothing yet */
  89                         if (added == rxq->added)
  90                                 return;
  91                         /* Push posted */
  92                         break;
  93                 }
  94
  95                 for (i = 0; i < RTE_DIM(objs);
  96                      ++i, id = (id + 1) & rxq->ptr_mask) {
  97                         m = objs[i];
  98
  99                         MBUF_RAW_ALLOC_CHECK(m);
 100
 101                         rxd = &rxq->sw_desc[id];
 102                         rxd->mbuf = m;
 103
 104                         m->data_off = RTE_PKTMBUF_HEADROOM;
 105                         m->port = port_id;
 106
 107                         addr[i] = rte_pktmbuf_iova(m);
 108                 }
 109
 110                 efx_rx_qpost(rxq->common, addr, rxq->buf_size,
 111                              RTE_DIM(objs), rxq->completed, added);
 112                 added += RTE_DIM(objs);
 113         } while (--bulks > 0);
 114
 115         SFC_ASSERT(added != rxq->added);
 116         rxq->added = added;
 117         efx_rx_qpush(rxq->common, added, &rxq->pushed);
 118 }
 119
 120 static uint64_t
 121 sfc_efx_rx_desc_flags_to_offload_flags(const unsigned int desc_flags)
 122 {
 123         uint64_t mbuf_flags = 0;
 124
 125         switch (desc_flags & (EFX_PKT_IPV4 | EFX_CKSUM_IPV4)) {
 126         case (EFX_PKT_IPV4 | EFX_CKSUM_IPV4):
 127                 mbuf_flags |= PKT_RX_IP_CKSUM_GOOD;
 128                 break;
 129         case EFX_PKT_IPV4:
 130                 mbuf_flags |= PKT_RX_IP_CKSUM_BAD;
 131                 break;
 132         default:
 133                 RTE_BUILD_BUG_ON(PKT_RX_IP_CKSUM_UNKNOWN != 0);
 134                 SFC_ASSERT((mbuf_flags & PKT_RX_IP_CKSUM_MASK) ==
 135                            PKT_RX_IP_CKSUM_UNKNOWN);
 136                 break;
 137         }
 138
 139         switch ((desc_flags &
 140                  (EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP))) {
 141         case (EFX_PKT_TCP | EFX_CKSUM_TCPUDP):
 142         case (EFX_PKT_UDP | EFX_CKSUM_TCPUDP):
 143                 mbuf_flags |= PKT_RX_L4_CKSUM_GOOD;
 144                 break;
 145         case EFX_PKT_TCP:
 146         case EFX_PKT_UDP:
 147                 mbuf_flags |= PKT_RX_L4_CKSUM_BAD;
 148                 break;
 149         default:
 150                 RTE_BUILD_BUG_ON(PKT_RX_L4_CKSUM_UNKNOWN != 0);
 151                 SFC_ASSERT((mbuf_flags & PKT_RX_L4_CKSUM_MASK) ==
 152                            PKT_RX_L4_CKSUM_UNKNOWN);
 153                 break;
 154         }
 155
 156         return mbuf_flags;
 157 }
 158
 159 static uint32_t
 160 sfc_efx_rx_desc_flags_to_packet_type(const unsigned int desc_flags)
 161 {
 162         return RTE_PTYPE_L2_ETHER |
 163                 ((desc_flags & EFX_PKT_IPV4) ?
 164                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN : 0) |
 165                 ((desc_flags & EFX_PKT_IPV6) ?
 166                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN : 0) |
 167                 ((desc_flags & EFX_PKT_TCP) ? RTE_PTYPE_L4_TCP : 0) |
 168                 ((desc_flags & EFX_PKT_UDP) ? RTE_PTYPE_L4_UDP : 0);
 169 }
 170
 171 static const uint32_t *
 172 sfc_efx_supported_ptypes_get(__rte_unused uint32_t tunnel_encaps)
 173 {
 174         static const uint32_t ptypes[] = {
 175                 RTE_PTYPE_L2_ETHER,
 176                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 177                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 178                 RTE_PTYPE_L4_TCP,
 179                 RTE_PTYPE_L4_UDP,
 180                 RTE_PTYPE_UNKNOWN
 181         };
 182
 183         return ptypes;
 184 }
 185
 186 static void
 187 sfc_efx_rx_set_rss_hash(struct sfc_efx_rxq *rxq, unsigned int flags,
 188                         struct rte_mbuf *m)
 189 {
 190         uint8_t *mbuf_data;
 191
 192
 193         if ((rxq->flags & SFC_EFX_RXQ_FLAG_RSS_HASH) == 0)
 194                 return;
 195
 196         mbuf_data = rte_pktmbuf_mtod(m, uint8_t *);
 197
 198         if (flags & (EFX_PKT_IPV4 | EFX_PKT_IPV6)) {
 199                 m->hash.rss = efx_pseudo_hdr_hash_get(rxq->common,
 200                                                       EFX_RX_HASHALG_TOEPLITZ,
 201                                                       mbuf_data);
 202
 203                 m->ol_flags |= PKT_RX_RSS_HASH;
 204         }
 205 }
 206
 207 static uint16_t
 208 sfc_efx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 209 {
 210         struct sfc_dp_rxq *dp_rxq = rx_queue;
 211         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 212         unsigned int completed;
 213         unsigned int prefix_size = rxq->prefix_size;
 214         unsigned int done_pkts = 0;
 215         boolean_t discard_next = B_FALSE;
 216         struct rte_mbuf *scatter_pkt = NULL;
 217
 218         if (unlikely((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0))
 219                 return 0;
 220
 221         sfc_ev_qpoll(rxq->evq);
 222
 223         completed = rxq->completed;
 224         while (completed != rxq->pending && done_pkts < nb_pkts) {
 225                 unsigned int id;
 226                 struct sfc_efx_rx_sw_desc *rxd;
 227                 struct rte_mbuf *m;
 228                 unsigned int seg_len;
 229                 unsigned int desc_flags;
 230
 231                 id = completed++ & rxq->ptr_mask;
 232                 rxd = &rxq->sw_desc[id];
 233                 m = rxd->mbuf;
 234                 desc_flags = rxd->flags;
 235
 236                 if (discard_next)
 237                         goto discard;
 238
 239                 if (desc_flags & (EFX_ADDR_MISMATCH | EFX_DISCARD))
 240                         goto discard;
 241
 242                 if (desc_flags & EFX_PKT_PREFIX_LEN) {
 243                         uint16_t tmp_size;
 244                         int rc __rte_unused;
 245
 246                         rc = efx_pseudo_hdr_pkt_length_get(rxq->common,
 247                                 rte_pktmbuf_mtod(m, uint8_t *), &tmp_size);
 248                         SFC_ASSERT(rc == 0);
 249                         seg_len = tmp_size;
 250                 } else {
 251                         seg_len = rxd->size - prefix_size;
 252                 }
 253
 254                 rte_pktmbuf_data_len(m) = seg_len;
 255                 rte_pktmbuf_pkt_len(m) = seg_len;
 256
 257                 if (scatter_pkt != NULL) {
 258                         if (rte_pktmbuf_chain(scatter_pkt, m) != 0) {
 259                                 rte_pktmbuf_free(scatter_pkt);
 260                                 goto discard;
 261                         }
 262                         /* The packet to deliver */
 263                         m = scatter_pkt;
 264                 }
 265
 266                 if (desc_flags & EFX_PKT_CONT) {
 267                         /* The packet is scattered, more fragments to come */
 268                         scatter_pkt = m;
 269                         /* Further fragments have no prefix */
 270                         prefix_size = 0;
 271                         continue;
 272                 }
 273
 274                 /* Scattered packet is done */
 275                 scatter_pkt = NULL;
 276                 /* The first fragment of the packet has prefix */
 277                 prefix_size = rxq->prefix_size;
 278
 279                 m->ol_flags =
 280                         sfc_efx_rx_desc_flags_to_offload_flags(desc_flags);
 281                 m->packet_type =
 282                         sfc_efx_rx_desc_flags_to_packet_type(desc_flags);
 283
 284                 /*
 285                  * Extract RSS hash from the packet prefix and
 286                  * set the corresponding field (if needed and possible)
 287                  */
 288                 sfc_efx_rx_set_rss_hash(rxq, desc_flags, m);
 289
 290                 m->data_off += prefix_size;
 291
 292                 *rx_pkts++ = m;
 293                 done_pkts++;
 294                 continue;
 295
 296 discard:
 297                 discard_next = ((desc_flags & EFX_PKT_CONT) != 0);
 298                 rte_mbuf_raw_free(m);
 299                 rxd->mbuf = NULL;
 300         }
 301
 302         /* pending is only moved when entire packet is received */
 303         SFC_ASSERT(scatter_pkt == NULL);
 304
 305         rxq->completed = completed;
 306
 307         sfc_efx_rx_qrefill(rxq);
 308
 309         return done_pkts;
 310 }
 311
 312 static sfc_dp_rx_qdesc_npending_t sfc_efx_rx_qdesc_npending;
 313 static unsigned int
 314 sfc_efx_rx_qdesc_npending(struct sfc_dp_rxq *dp_rxq)
 315 {
 316         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 317
 318         if ((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0)
 319                 return 0;
 320
 321         sfc_ev_qpoll(rxq->evq);
 322
 323         return rxq->pending - rxq->completed;
 324 }
 325
 326 static sfc_dp_rx_qdesc_status_t sfc_efx_rx_qdesc_status;
 327 static int
 328 sfc_efx_rx_qdesc_status(struct sfc_dp_rxq *dp_rxq, uint16_t offset)
 329 {
 330         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 331
 332         if (unlikely(offset > rxq->ptr_mask))
 333                 return -EINVAL;
 334
 335         /*
 336          * Poll EvQ to derive up-to-date 'rxq->pending' figure;
 337          * it is required for the queue to be running, but the
 338          * check is omitted because API design assumes that it
 339          * is the duty of the caller to satisfy all conditions
 340          */
 341         SFC_ASSERT((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) ==
 342                    SFC_EFX_RXQ_FLAG_RUNNING);
 343         sfc_ev_qpoll(rxq->evq);
 344
 345         /*
 346          * There is a handful of reserved entries in the ring,
 347          * but an explicit check whether the offset points to
 348          * a reserved entry is neglected since the two checks
 349          * below rely on the figures which take the HW limits
 350          * into account and thus if an entry is reserved, the
 351          * checks will fail and UNAVAIL code will be returned
 352          */
 353
 354         if (offset < (rxq->pending - rxq->completed))
 355                 return RTE_ETH_RX_DESC_DONE;
 356
 357         if (offset < (rxq->added - rxq->completed))
 358                 return RTE_ETH_RX_DESC_AVAIL;
 359
 360         return RTE_ETH_RX_DESC_UNAVAIL;
 361 }
 362
 363 boolean_t
 364 sfc_rx_check_scatter(size_t pdu, size_t rx_buf_size, uint32_t rx_prefix_size,
 365                      boolean_t rx_scatter_enabled, const char **error)
 366 {
 367         if ((rx_buf_size < pdu + rx_prefix_size) && !rx_scatter_enabled) {
 368                 *error = "Rx scatter is disabled and RxQ mbuf pool object size is too small";
 369                 return B_FALSE;
 370         }
 371
 372         return B_TRUE;
 373 }
 374
 375 /** Get Rx datapath ops by the datapath RxQ handle */
 376 const struct sfc_dp_rx *
 377 sfc_dp_rx_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
 378 {
 379         const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
 380         struct rte_eth_dev *eth_dev;
 381         struct sfc_adapter_priv *sap;
 382
 383         SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
 384         eth_dev = &rte_eth_devices[dpq->port_id];
 385
 386         sap = sfc_adapter_priv_by_eth_dev(eth_dev);
 387
 388         return sap->dp_rx;
 389 }
 390
 391 struct sfc_rxq_info *
 392 sfc_rxq_info_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
 393 {
 394         const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
 395         struct rte_eth_dev *eth_dev;
 396         struct sfc_adapter_shared *sas;
 397
 398         SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
 399         eth_dev = &rte_eth_devices[dpq->port_id];
 400
 401         sas = sfc_adapter_shared_by_eth_dev(eth_dev);
 402
 403         SFC_ASSERT(dpq->queue_id < sas->rxq_count);
 404         return &sas->rxq_info[dpq->queue_id];
 405 }
 406
 407 struct sfc_rxq *
 408 sfc_rxq_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
 409 {
 410         const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
 411         struct rte_eth_dev *eth_dev;
 412         struct sfc_adapter *sa;
 413
 414         SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
 415         eth_dev = &rte_eth_devices[dpq->port_id];
 416
 417         sa = sfc_adapter_by_eth_dev(eth_dev);
 418
 419         SFC_ASSERT(dpq->queue_id < sfc_sa2shared(sa)->rxq_count);
 420         return &sa->rxq_ctrl[dpq->queue_id];
 421 }
 422
 423 static sfc_dp_rx_qsize_up_rings_t sfc_efx_rx_qsize_up_rings;
 424 static int
 425 sfc_efx_rx_qsize_up_rings(uint16_t nb_rx_desc,
 426                           __rte_unused struct sfc_dp_rx_hw_limits *limits,
 427                           __rte_unused struct rte_mempool *mb_pool,
 428                           unsigned int *rxq_entries,
 429                           unsigned int *evq_entries,
 430                           unsigned int *rxq_max_fill_level)
 431 {
 432         *rxq_entries = nb_rx_desc;
 433         *evq_entries = nb_rx_desc;
 434         *rxq_max_fill_level = EFX_RXQ_LIMIT(*rxq_entries);
 435         return 0;
 436 }
 437
 438 static sfc_dp_rx_qcreate_t sfc_efx_rx_qcreate;
 439 static int
 440 sfc_efx_rx_qcreate(uint16_t port_id, uint16_t queue_id,
 441                    const struct rte_pci_addr *pci_addr, int socket_id,
 442                    const struct sfc_dp_rx_qcreate_info *info,
 443                    struct sfc_dp_rxq **dp_rxqp)
 444 {
 445         struct sfc_efx_rxq *rxq;
 446         int rc;
 447
 448         rc = ENOMEM;
 449         rxq = rte_zmalloc_socket("sfc-efx-rxq", sizeof(*rxq),
 450                                  RTE_CACHE_LINE_SIZE, socket_id);
 451         if (rxq == NULL)
 452                 goto fail_rxq_alloc;
 453
 454         sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr);
 455
 456         rc = ENOMEM;
 457         rxq->sw_desc = rte_calloc_socket("sfc-efx-rxq-sw_desc",
 458                                          info->rxq_entries,
 459                                          sizeof(*rxq->sw_desc),
 460                                          RTE_CACHE_LINE_SIZE, socket_id);
 461         if (rxq->sw_desc == NULL)
 462                 goto fail_desc_alloc;
 463
 464         /* efx datapath is bound to efx control path */
 465         rxq->evq = sfc_rxq_by_dp_rxq(&rxq->dp)->evq;
 466         if (info->flags & SFC_RXQ_FLAG_RSS_HASH)
 467                 rxq->flags |= SFC_EFX_RXQ_FLAG_RSS_HASH;
 468         rxq->ptr_mask = info->rxq_entries - 1;
 469         rxq->batch_max = info->batch_max;
 470         rxq->prefix_size = info->prefix_size;
 471         rxq->max_fill_level = info->max_fill_level;
 472         rxq->refill_threshold = info->refill_threshold;
 473         rxq->buf_size = info->buf_size;
 474         rxq->refill_mb_pool = info->refill_mb_pool;
 475
 476         *dp_rxqp = &rxq->dp;
 477         return 0;
 478
 479 fail_desc_alloc:
 480         rte_free(rxq);
 481
 482 fail_rxq_alloc:
 483         return rc;
 484 }
 485
 486 static sfc_dp_rx_qdestroy_t sfc_efx_rx_qdestroy;
 487 static void
 488 sfc_efx_rx_qdestroy(struct sfc_dp_rxq *dp_rxq)
 489 {
 490         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 491
 492         rte_free(rxq->sw_desc);
 493         rte_free(rxq);
 494 }
 495
 496 static sfc_dp_rx_qstart_t sfc_efx_rx_qstart;
 497 static int
 498 sfc_efx_rx_qstart(struct sfc_dp_rxq *dp_rxq,
 499                   __rte_unused unsigned int evq_read_ptr)
 500 {
 501         /* libefx-based datapath is specific to libefx-based PMD */
 502         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 503         struct sfc_rxq *crxq = sfc_rxq_by_dp_rxq(dp_rxq);
 504
 505         rxq->common = crxq->common;
 506
 507         rxq->pending = rxq->completed = rxq->added = rxq->pushed = 0;
 508
 509         sfc_efx_rx_qrefill(rxq);
 510
 511         rxq->flags |= (SFC_EFX_RXQ_FLAG_STARTED | SFC_EFX_RXQ_FLAG_RUNNING);
 512
 513         return 0;
 514 }
 515
 516 static sfc_dp_rx_qstop_t sfc_efx_rx_qstop;
 517 static void
 518 sfc_efx_rx_qstop(struct sfc_dp_rxq *dp_rxq,
 519                  __rte_unused unsigned int *evq_read_ptr)
 520 {
 521         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 522
 523         rxq->flags &= ~SFC_EFX_RXQ_FLAG_RUNNING;
 524
 525         /* libefx-based datapath is bound to libefx-based PMD and uses
 526          * event queue structure directly. So, there is no necessity to
 527          * return EvQ read pointer.
 528          */
 529 }
 530
 531 static sfc_dp_rx_qpurge_t sfc_efx_rx_qpurge;
 532 static void
 533 sfc_efx_rx_qpurge(struct sfc_dp_rxq *dp_rxq)
 534 {
 535         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 536         unsigned int i;
 537         struct sfc_efx_rx_sw_desc *rxd;
 538
 539         for (i = rxq->completed; i != rxq->added; ++i) {
 540                 rxd = &rxq->sw_desc[i & rxq->ptr_mask];
 541                 rte_mbuf_raw_free(rxd->mbuf);
 542                 rxd->mbuf = NULL;
 543                 /* Packed stream relies on 0 in inactive SW desc.
 544                  * Rx queue stop is not performance critical, so
 545                  * there is no harm to do it always.
 546                  */
 547                 rxd->flags = 0;
 548                 rxd->size = 0;
 549         }
 550
 551         rxq->flags &= ~SFC_EFX_RXQ_FLAG_STARTED;
 552 }
 553
 554 struct sfc_dp_rx sfc_efx_rx = {
 555         .dp = {
 556                 .name           = SFC_KVARG_DATAPATH_EFX,
 557                 .type           = SFC_DP_RX,
 558                 .hw_fw_caps     = 0,
 559         },
 560         .features               = 0,
 561         .dev_offload_capa       = DEV_RX_OFFLOAD_CHECKSUM,
 562         .queue_offload_capa     = DEV_RX_OFFLOAD_SCATTER,
 563         .qsize_up_rings         = sfc_efx_rx_qsize_up_rings,
 564         .qcreate                = sfc_efx_rx_qcreate,
 565         .qdestroy               = sfc_efx_rx_qdestroy,
 566         .qstart                 = sfc_efx_rx_qstart,
 567         .qstop                  = sfc_efx_rx_qstop,
 568         .qpurge                 = sfc_efx_rx_qpurge,
 569         .supported_ptypes_get   = sfc_efx_supported_ptypes_get,
 570         .qdesc_npending         = sfc_efx_rx_qdesc_npending,
 571         .qdesc_status           = sfc_efx_rx_qdesc_status,
 572         .pkt_burst              = sfc_efx_recv_pkts,
 573 };
 574
 575 static void
 576 sfc_rx_qflush(struct sfc_adapter *sa, unsigned int sw_index)
 577 {
 578         struct sfc_rxq_info *rxq_info;
 579         struct sfc_rxq *rxq;
 580         unsigned int retry_count;
 581         unsigned int wait_count;
 582         int rc;
 583
 584         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
 585         SFC_ASSERT(rxq_info->state & SFC_RXQ_STARTED);
 586
 587         rxq = &sa->rxq_ctrl[sw_index];
 588
 589         /*
 590          * Retry Rx queue flushing in the case of flush failed or
 591          * timeout. In the worst case it can delay for 6 seconds.
 592          */
 593         for (retry_count = 0;
 594              ((rxq_info->state & SFC_RXQ_FLUSHED) == 0) &&
 595              (retry_count < SFC_RX_QFLUSH_ATTEMPTS);
 596              ++retry_count) {
 597                 rc = efx_rx_qflush(rxq->common);
 598                 if (rc != 0) {
 599                         rxq_info->state |= (rc == EALREADY) ?
 600                                 SFC_RXQ_FLUSHED : SFC_RXQ_FLUSH_FAILED;
 601                         break;
 602                 }
 603                 rxq_info->state &= ~SFC_RXQ_FLUSH_FAILED;
 604                 rxq_info->state |= SFC_RXQ_FLUSHING;
 605
 606                 /*
 607                  * Wait for Rx queue flush done or failed event at least
 608                  * SFC_RX_QFLUSH_POLL_WAIT_MS milliseconds and not more
 609                  * than 2 seconds (SFC_RX_QFLUSH_POLL_WAIT_MS multiplied
 610                  * by SFC_RX_QFLUSH_POLL_ATTEMPTS).
 611                  */
 612                 wait_count = 0;
 613                 do {
 614                         rte_delay_ms(SFC_RX_QFLUSH_POLL_WAIT_MS);
 615                         sfc_ev_qpoll(rxq->evq);
 616                 } while ((rxq_info->state & SFC_RXQ_FLUSHING) &&
 617                          (wait_count++ < SFC_RX_QFLUSH_POLL_ATTEMPTS));
 618
 619                 if (rxq_info->state & SFC_RXQ_FLUSHING)
 620                         sfc_err(sa, "RxQ %u flush timed out", sw_index);
 621
 622                 if (rxq_info->state & SFC_RXQ_FLUSH_FAILED)
 623                         sfc_err(sa, "RxQ %u flush failed", sw_index);
 624
 625                 if (rxq_info->state & SFC_RXQ_FLUSHED)
 626                         sfc_notice(sa, "RxQ %u flushed", sw_index);
 627         }
 628
 629         sa->priv.dp_rx->qpurge(rxq_info->dp);
 630 }
 631
 632 static int
 633 sfc_rx_default_rxq_set_filter(struct sfc_adapter *sa, struct sfc_rxq *rxq)
 634 {
 635         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
 636         boolean_t need_rss = (rss->channels > 0) ? B_TRUE : B_FALSE;
 637         struct sfc_port *port = &sa->port;
 638         int rc;
 639
 640         /*
 641          * If promiscuous or all-multicast mode has been requested, setting
 642          * filter for the default Rx queue might fail, in particular, while
 643          * running over PCI function which is not a member of corresponding
 644          * privilege groups; if this occurs, few iterations will be made to
 645          * repeat this step without promiscuous and all-multicast flags set
 646          */
 647 retry:
 648         rc = efx_mac_filter_default_rxq_set(sa->nic, rxq->common, need_rss);
 649         if (rc == 0)
 650                 return 0;
 651         else if (rc != EOPNOTSUPP)
 652                 return rc;
 653
 654         if (port->promisc) {
 655                 sfc_warn(sa, "promiscuous mode has been requested, "
 656                              "but the HW rejects it");
 657                 sfc_warn(sa, "promiscuous mode will be disabled");
 658
 659                 port->promisc = B_FALSE;
 660                 rc = sfc_set_rx_mode(sa);
 661                 if (rc != 0)
 662                         return rc;
 663
 664                 goto retry;
 665         }
 666
 667         if (port->allmulti) {
 668                 sfc_warn(sa, "all-multicast mode has been requested, "
 669                              "but the HW rejects it");
 670                 sfc_warn(sa, "all-multicast mode will be disabled");
 671
 672                 port->allmulti = B_FALSE;
 673                 rc = sfc_set_rx_mode(sa);
 674                 if (rc != 0)
 675                         return rc;
 676
 677                 goto retry;
 678         }
 679
 680         return rc;
 681 }
 682
 683 int
 684 sfc_rx_qstart(struct sfc_adapter *sa, unsigned int sw_index)
 685 {
 686         struct sfc_rxq_info *rxq_info;
 687         struct sfc_rxq *rxq;
 688         struct sfc_evq *evq;
 689         int rc;
 690
 691         sfc_log_init(sa, "sw_index=%u", sw_index);
 692
 693         SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
 694
 695         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
 696         SFC_ASSERT(rxq_info->state == SFC_RXQ_INITIALIZED);
 697
 698         rxq = &sa->rxq_ctrl[sw_index];
 699         evq = rxq->evq;
 700
 701         rc = sfc_ev_qstart(evq, sfc_evq_index_by_rxq_sw_index(sa, sw_index));
 702         if (rc != 0)
 703                 goto fail_ev_qstart;
 704
 705         switch (rxq_info->type) {
 706         case EFX_RXQ_TYPE_DEFAULT:
 707                 rc = efx_rx_qcreate(sa->nic, rxq->hw_index, 0, rxq_info->type,
 708                         rxq->buf_size,
 709                         &rxq->mem, rxq_info->entries, 0 /* not used on EF10 */,
 710                         rxq_info->type_flags, evq->common, &rxq->common);
 711                 break;
 712         case EFX_RXQ_TYPE_ES_SUPER_BUFFER: {
 713                 struct rte_mempool *mp = rxq_info->refill_mb_pool;
 714                 struct rte_mempool_info mp_info;
 715
 716                 rc = rte_mempool_ops_get_info(mp, &mp_info);
 717                 if (rc != 0) {
 718                         /* Positive errno is used in the driver */
 719                         rc = -rc;
 720                         goto fail_mp_get_info;
 721                 }
 722                 if (mp_info.contig_block_size <= 0) {
 723                         rc = EINVAL;
 724                         goto fail_bad_contig_block_size;
 725                 }
 726                 rc = efx_rx_qcreate_es_super_buffer(sa->nic, rxq->hw_index, 0,
 727                         mp_info.contig_block_size, rxq->buf_size,
 728                         mp->header_size + mp->elt_size + mp->trailer_size,
 729                         sa->rxd_wait_timeout_ns,
 730                         &rxq->mem, rxq_info->entries, rxq_info->type_flags,
 731                         evq->common, &rxq->common);
 732                 break;
 733         }
 734         default:
 735                 rc = ENOTSUP;
 736         }
 737         if (rc != 0)
 738                 goto fail_rx_qcreate;
 739
 740         efx_rx_qenable(rxq->common);
 741
 742         rc = sa->priv.dp_rx->qstart(rxq_info->dp, evq->read_ptr);
 743         if (rc != 0)
 744                 goto fail_dp_qstart;
 745
 746         rxq_info->state |= SFC_RXQ_STARTED;
 747
 748         if (sw_index == 0 && !sfc_sa2shared(sa)->isolated) {
 749                 rc = sfc_rx_default_rxq_set_filter(sa, rxq);
 750                 if (rc != 0)
 751                         goto fail_mac_filter_default_rxq_set;
 752         }
 753
 754         /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
 755         sa->eth_dev->data->rx_queue_state[sw_index] =
 756                 RTE_ETH_QUEUE_STATE_STARTED;
 757
 758         return 0;
 759
 760 fail_mac_filter_default_rxq_set:
 761         sa->priv.dp_rx->qstop(rxq_info->dp, &rxq->evq->read_ptr);
 762
 763 fail_dp_qstart:
 764         sfc_rx_qflush(sa, sw_index);
 765
 766 fail_rx_qcreate:
 767 fail_bad_contig_block_size:
 768 fail_mp_get_info:
 769         sfc_ev_qstop(evq);
 770
 771 fail_ev_qstart:
 772         return rc;
 773 }
 774
 775 void
 776 sfc_rx_qstop(struct sfc_adapter *sa, unsigned int sw_index)
 777 {
 778         struct sfc_rxq_info *rxq_info;
 779         struct sfc_rxq *rxq;
 780
 781         sfc_log_init(sa, "sw_index=%u", sw_index);
 782
 783         SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
 784
 785         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
 786
 787         if (rxq_info->state == SFC_RXQ_INITIALIZED)
 788                 return;
 789         SFC_ASSERT(rxq_info->state & SFC_RXQ_STARTED);
 790
 791         /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
 792         sa->eth_dev->data->rx_queue_state[sw_index] =
 793                 RTE_ETH_QUEUE_STATE_STOPPED;
 794
 795         rxq = &sa->rxq_ctrl[sw_index];
 796         sa->priv.dp_rx->qstop(rxq_info->dp, &rxq->evq->read_ptr);
 797
 798         if (sw_index == 0)
 799                 efx_mac_filter_default_rxq_clear(sa->nic);
 800
 801         sfc_rx_qflush(sa, sw_index);
 802
 803         rxq_info->state = SFC_RXQ_INITIALIZED;
 804
 805         efx_rx_qdestroy(rxq->common);
 806
 807         sfc_ev_qstop(rxq->evq);
 808 }
 809
 810 static uint64_t
 811 sfc_rx_get_offload_mask(struct sfc_adapter *sa)
 812 {
 813         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
 814         uint64_t no_caps = 0;
 815
 816         if (encp->enc_tunnel_encapsulations_supported == 0)
 817                 no_caps |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
 818
 819         return ~no_caps;
 820 }
 821
 822 uint64_t
 823 sfc_rx_get_dev_offload_caps(struct sfc_adapter *sa)
 824 {
 825         uint64_t caps = sa->priv.dp_rx->dev_offload_capa;
 826
 827         caps |= DEV_RX_OFFLOAD_JUMBO_FRAME;
 828
 829         return caps & sfc_rx_get_offload_mask(sa);
 830 }
 831
 832 uint64_t
 833 sfc_rx_get_queue_offload_caps(struct sfc_adapter *sa)
 834 {
 835         return sa->priv.dp_rx->queue_offload_capa & sfc_rx_get_offload_mask(sa);
 836 }
 837
 838 static int
 839 sfc_rx_qcheck_conf(struct sfc_adapter *sa, unsigned int rxq_max_fill_level,
 840                    const struct rte_eth_rxconf *rx_conf,
 841                    __rte_unused uint64_t offloads)
 842 {
 843         int rc = 0;
 844
 845         if (rx_conf->rx_thresh.pthresh != 0 ||
 846             rx_conf->rx_thresh.hthresh != 0 ||
 847             rx_conf->rx_thresh.wthresh != 0) {
 848                 sfc_warn(sa,
 849                         "RxQ prefetch/host/writeback thresholds are not supported");
 850         }
 851
 852         if (rx_conf->rx_free_thresh > rxq_max_fill_level) {
 853                 sfc_err(sa,
 854                         "RxQ free threshold too large: %u vs maximum %u",
 855                         rx_conf->rx_free_thresh, rxq_max_fill_level);
 856                 rc = EINVAL;
 857         }
 858
 859         if (rx_conf->rx_drop_en == 0) {
 860                 sfc_err(sa, "RxQ drop disable is not supported");
 861                 rc = EINVAL;
 862         }
 863
 864         return rc;
 865 }
 866
 867 static unsigned int
 868 sfc_rx_mbuf_data_alignment(struct rte_mempool *mb_pool)
 869 {
 870         uint32_t data_off;
 871         uint32_t order;
 872
 873         /* The mbuf object itself is always cache line aligned */
 874         order = rte_bsf32(RTE_CACHE_LINE_SIZE);
 875
 876         /* Data offset from mbuf object start */
 877         data_off = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(mb_pool) +
 878                 RTE_PKTMBUF_HEADROOM;
 879
 880         order = MIN(order, rte_bsf32(data_off));
 881
 882         return 1u << order;
 883 }
 884
 885 static uint16_t
 886 sfc_rx_mb_pool_buf_size(struct sfc_adapter *sa, struct rte_mempool *mb_pool)
 887 {
 888         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
 889         const uint32_t nic_align_start = MAX(1, encp->enc_rx_buf_align_start);
 890         const uint32_t nic_align_end = MAX(1, encp->enc_rx_buf_align_end);
 891         uint16_t buf_size;
 892         unsigned int buf_aligned;
 893         unsigned int start_alignment;
 894         unsigned int end_padding_alignment;
 895
 896         /* Below it is assumed that both alignments are power of 2 */
 897         SFC_ASSERT(rte_is_power_of_2(nic_align_start));
 898         SFC_ASSERT(rte_is_power_of_2(nic_align_end));
 899
 900         /*
 901          * mbuf is always cache line aligned, double-check
 902          * that it meets rx buffer start alignment requirements.
 903          */
 904
 905         /* Start from mbuf pool data room size */
 906         buf_size = rte_pktmbuf_data_room_size(mb_pool);
 907
 908         /* Remove headroom */
 909         if (buf_size <= RTE_PKTMBUF_HEADROOM) {
 910                 sfc_err(sa,
 911                         "RxQ mbuf pool %s object data room size %u is smaller than headroom %u",
 912                         mb_pool->name, buf_size, RTE_PKTMBUF_HEADROOM);
 913                 return 0;
 914         }
 915         buf_size -= RTE_PKTMBUF_HEADROOM;
 916
 917         /* Calculate guaranteed data start alignment */
 918         buf_aligned = sfc_rx_mbuf_data_alignment(mb_pool);
 919
 920         /* Reserve space for start alignment */
 921         if (buf_aligned < nic_align_start) {
 922                 start_alignment = nic_align_start - buf_aligned;
 923                 if (buf_size <= start_alignment) {
 924                         sfc_err(sa,
 925                                 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u and buffer start alignment %u required by NIC",
 926                                 mb_pool->name,
 927                                 rte_pktmbuf_data_room_size(mb_pool),
 928                                 RTE_PKTMBUF_HEADROOM, start_alignment);
 929                         return 0;
 930                 }
 931                 buf_aligned = nic_align_start;
 932                 buf_size -= start_alignment;
 933         } else {
 934                 start_alignment = 0;
 935         }
 936
 937         /* Make sure that end padding does not write beyond the buffer */
 938         if (buf_aligned < nic_align_end) {
 939                 /*
 940                  * Estimate space which can be lost. If guarnteed buffer
 941                  * size is odd, lost space is (nic_align_end - 1). More
 942                  * accurate formula is below.
 943                  */
 944                 end_padding_alignment = nic_align_end -
 945                         MIN(buf_aligned, 1u << (rte_bsf32(buf_size) - 1));
 946                 if (buf_size <= end_padding_alignment) {
 947                         sfc_err(sa,
 948                                 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u, buffer start alignment %u and end padding alignment %u required by NIC",
 949                                 mb_pool->name,
 950                                 rte_pktmbuf_data_room_size(mb_pool),
 951                                 RTE_PKTMBUF_HEADROOM, start_alignment,
 952                                 end_padding_alignment);
 953                         return 0;
 954                 }
 955                 buf_size -= end_padding_alignment;
 956         } else {
 957                 /*
 958                  * Start is aligned the same or better than end,
 959                  * just align length.
 960                  */
 961                 buf_size = P2ALIGN(buf_size, nic_align_end);
 962         }
 963
 964         return buf_size;
 965 }
 966
 967 int
 968 sfc_rx_qinit(struct sfc_adapter *sa, unsigned int sw_index,
 969              uint16_t nb_rx_desc, unsigned int socket_id,
 970              const struct rte_eth_rxconf *rx_conf,
 971              struct rte_mempool *mb_pool)
 972 {
 973         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
 974         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
 975         int rc;
 976         unsigned int rxq_entries;
 977         unsigned int evq_entries;
 978         unsigned int rxq_max_fill_level;
 979         uint64_t offloads;
 980         uint16_t buf_size;
 981         struct sfc_rxq_info *rxq_info;
 982         struct sfc_evq *evq;
 983         struct sfc_rxq *rxq;
 984         struct sfc_dp_rx_qcreate_info info;
 985         struct sfc_dp_rx_hw_limits hw_limits;
 986         uint16_t rx_free_thresh;
 987         const char *error;
 988
 989         memset(&hw_limits, 0, sizeof(hw_limits));
 990         hw_limits.rxq_max_entries = sa->rxq_max_entries;
 991         hw_limits.rxq_min_entries = sa->rxq_min_entries;
 992         hw_limits.evq_max_entries = sa->evq_max_entries;
 993         hw_limits.evq_min_entries = sa->evq_min_entries;
 994
 995         rc = sa->priv.dp_rx->qsize_up_rings(nb_rx_desc, &hw_limits, mb_pool,
 996                                             &rxq_entries, &evq_entries,
 997                                             &rxq_max_fill_level);
 998         if (rc != 0)
 999                 goto fail_size_up_rings;
1000         SFC_ASSERT(rxq_entries >= sa->rxq_min_entries);
1001         SFC_ASSERT(rxq_entries <= sa->rxq_max_entries);
1002         SFC_ASSERT(rxq_max_fill_level <= nb_rx_desc);
1003
1004         offloads = rx_conf->offloads |
1005                 sa->eth_dev->data->dev_conf.rxmode.offloads;
1006         rc = sfc_rx_qcheck_conf(sa, rxq_max_fill_level, rx_conf, offloads);
1007         if (rc != 0)
1008                 goto fail_bad_conf;
1009
1010         buf_size = sfc_rx_mb_pool_buf_size(sa, mb_pool);
1011         if (buf_size == 0) {
1012                 sfc_err(sa, "RxQ %u mbuf pool object size is too small",
1013                         sw_index);
1014                 rc = EINVAL;
1015                 goto fail_bad_conf;
1016         }
1017
1018         if (!sfc_rx_check_scatter(sa->port.pdu, buf_size,
1019                                   encp->enc_rx_prefix_size,
1020                                   (offloads & DEV_RX_OFFLOAD_SCATTER),
1021                                   &error)) {
1022                 sfc_err(sa, "RxQ %u MTU check failed: %s", sw_index, error);
1023                 sfc_err(sa, "RxQ %u calculated Rx buffer size is %u vs "
1024                         "PDU size %u plus Rx prefix %u bytes",
1025                         sw_index, buf_size, (unsigned int)sa->port.pdu,
1026                         encp->enc_rx_prefix_size);
1027                 rc = EINVAL;
1028                 goto fail_bad_conf;
1029         }
1030
1031         SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
1032         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
1033
1034         SFC_ASSERT(rxq_entries <= rxq_info->max_entries);
1035         rxq_info->entries = rxq_entries;
1036
1037         if (sa->priv.dp_rx->dp.hw_fw_caps & SFC_DP_HW_FW_CAP_RX_ES_SUPER_BUFFER)
1038                 rxq_info->type = EFX_RXQ_TYPE_ES_SUPER_BUFFER;
1039         else
1040                 rxq_info->type = EFX_RXQ_TYPE_DEFAULT;
1041
1042         rxq_info->type_flags =
1043                 (offloads & DEV_RX_OFFLOAD_SCATTER) ?
1044                 EFX_RXQ_FLAG_SCATTER : EFX_RXQ_FLAG_NONE;
1045
1046         if ((encp->enc_tunnel_encapsulations_supported != 0) &&
1047             (sfc_dp_rx_offload_capa(sa->priv.dp_rx) &
1048              DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) != 0)
1049                 rxq_info->type_flags |= EFX_RXQ_FLAG_INNER_CLASSES;
1050
1051         rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_RX, sw_index,
1052                           evq_entries, socket_id, &evq);
1053         if (rc != 0)
1054                 goto fail_ev_qinit;
1055
1056         rxq = &sa->rxq_ctrl[sw_index];
1057         rxq->evq = evq;
1058         rxq->hw_index = sw_index;
1059         /*
1060          * If Rx refill threshold is specified (its value is non zero) in
1061          * Rx configuration, use specified value. Otherwise use 1/8 of
1062          * the Rx descriptors number as the default. It allows to keep
1063          * Rx ring full-enough and does not refill too aggressive if
1064          * packet rate is high.
1065          *
1066          * Since PMD refills in bulks waiting for full bulk may be
1067          * refilled (basically round down), it is better to round up
1068          * here to mitigate it a bit.
1069          */
1070         rx_free_thresh = (rx_conf->rx_free_thresh != 0) ?
1071                 rx_conf->rx_free_thresh : EFX_DIV_ROUND_UP(nb_rx_desc, 8);
1072         /* Rx refill threshold cannot be smaller than refill bulk */
1073         rxq_info->refill_threshold =
1074                 RTE_MAX(rx_free_thresh, SFC_RX_REFILL_BULK);
1075         rxq_info->refill_mb_pool = mb_pool;
1076         rxq->buf_size = buf_size;
1077
1078         rc = sfc_dma_alloc(sa, "rxq", sw_index,
1079                            efx_rxq_size(sa->nic, rxq_info->entries),
1080                            socket_id, &rxq->mem);
1081         if (rc != 0)
1082                 goto fail_dma_alloc;
1083
1084         memset(&info, 0, sizeof(info));
1085         info.refill_mb_pool = rxq_info->refill_mb_pool;
1086         info.max_fill_level = rxq_max_fill_level;
1087         info.refill_threshold = rxq_info->refill_threshold;
1088         info.buf_size = buf_size;
1089         info.batch_max = encp->enc_rx_batch_max;
1090         info.prefix_size = encp->enc_rx_prefix_size;
1091
1092         if (rss->hash_support == EFX_RX_HASH_AVAILABLE && rss->channels > 0)
1093                 info.flags |= SFC_RXQ_FLAG_RSS_HASH;
1094
1095         info.rxq_entries = rxq_info->entries;
1096         info.rxq_hw_ring = rxq->mem.esm_base;
1097         info.evq_entries = evq_entries;
1098         info.evq_hw_ring = evq->mem.esm_base;
1099         info.hw_index = rxq->hw_index;
1100         info.mem_bar = sa->mem_bar.esb_base;
1101         info.vi_window_shift = encp->enc_vi_window_shift;
1102
1103         rc = sa->priv.dp_rx->qcreate(sa->eth_dev->data->port_id, sw_index,
1104                                      &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr,
1105                                      socket_id, &info, &rxq_info->dp);
1106         if (rc != 0)
1107                 goto fail_dp_rx_qcreate;
1108
1109         evq->dp_rxq = rxq_info->dp;
1110
1111         rxq_info->state = SFC_RXQ_INITIALIZED;
1112
1113         rxq_info->deferred_start = (rx_conf->rx_deferred_start != 0);
1114
1115         return 0;
1116
1117 fail_dp_rx_qcreate:
1118         sfc_dma_free(sa, &rxq->mem);
1119
1120 fail_dma_alloc:
1121         sfc_ev_qfini(evq);
1122
1123 fail_ev_qinit:
1124         rxq_info->entries = 0;
1125
1126 fail_bad_conf:
1127 fail_size_up_rings:
1128         sfc_log_init(sa, "failed %d", rc);
1129         return rc;
1130 }
1131
1132 void
1133 sfc_rx_qfini(struct sfc_adapter *sa, unsigned int sw_index)
1134 {
1135         struct sfc_rxq_info *rxq_info;
1136         struct sfc_rxq *rxq;
1137
1138         SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
1139         sa->eth_dev->data->rx_queues[sw_index] = NULL;
1140
1141         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
1142
1143         SFC_ASSERT(rxq_info->state == SFC_RXQ_INITIALIZED);
1144
1145         sa->priv.dp_rx->qdestroy(rxq_info->dp);
1146         rxq_info->dp = NULL;
1147
1148         rxq_info->state &= ~SFC_RXQ_INITIALIZED;
1149         rxq_info->entries = 0;
1150
1151         rxq = &sa->rxq_ctrl[sw_index];
1152
1153         sfc_dma_free(sa, &rxq->mem);
1154
1155         sfc_ev_qfini(rxq->evq);
1156         rxq->evq = NULL;
1157 }
1158
1159 /*
1160  * Mapping between RTE RSS hash functions and their EFX counterparts.
1161  */
1162 static const struct sfc_rss_hf_rte_to_efx sfc_rss_hf_map[] = {
1163         { ETH_RSS_NONFRAG_IPV4_TCP,
1164           EFX_RX_HASH(IPV4_TCP, 4TUPLE) },
1165         { ETH_RSS_NONFRAG_IPV4_UDP,
1166           EFX_RX_HASH(IPV4_UDP, 4TUPLE) },
1167         { ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_IPV6_TCP_EX,
1168           EFX_RX_HASH(IPV6_TCP, 4TUPLE) },
1169         { ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_UDP_EX,
1170           EFX_RX_HASH(IPV6_UDP, 4TUPLE) },
1171         { ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_OTHER,
1172           EFX_RX_HASH(IPV4_TCP, 2TUPLE) | EFX_RX_HASH(IPV4_UDP, 2TUPLE) |
1173           EFX_RX_HASH(IPV4, 2TUPLE) },
1174         { ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_OTHER |
1175           ETH_RSS_IPV6_EX,
1176           EFX_RX_HASH(IPV6_TCP, 2TUPLE) | EFX_RX_HASH(IPV6_UDP, 2TUPLE) |
1177           EFX_RX_HASH(IPV6, 2TUPLE) }
1178 };
1179
1180 static efx_rx_hash_type_t
1181 sfc_rx_hash_types_mask_supp(efx_rx_hash_type_t hash_type,
1182                             unsigned int *hash_type_flags_supported,
1183                             unsigned int nb_hash_type_flags_supported)
1184 {
1185         efx_rx_hash_type_t hash_type_masked = 0;
1186         unsigned int i, j;
1187
1188         for (i = 0; i < nb_hash_type_flags_supported; ++i) {
1189                 unsigned int class_tuple_lbn[] = {
1190                         EFX_RX_CLASS_IPV4_TCP_LBN,
1191                         EFX_RX_CLASS_IPV4_UDP_LBN,
1192                         EFX_RX_CLASS_IPV4_LBN,
1193                         EFX_RX_CLASS_IPV6_TCP_LBN,
1194                         EFX_RX_CLASS_IPV6_UDP_LBN,
1195                         EFX_RX_CLASS_IPV6_LBN
1196                 };
1197
1198                 for (j = 0; j < RTE_DIM(class_tuple_lbn); ++j) {
1199                         unsigned int tuple_mask = EFX_RX_CLASS_HASH_4TUPLE;
1200                         unsigned int flag;
1201
1202                         tuple_mask <<= class_tuple_lbn[j];
1203                         flag = hash_type & tuple_mask;
1204
1205                         if (flag == hash_type_flags_supported[i])
1206                                 hash_type_masked |= flag;
1207                 }
1208         }
1209
1210         return hash_type_masked;
1211 }
1212
1213 int
1214 sfc_rx_hash_init(struct sfc_adapter *sa)
1215 {
1216         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1217         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1218         uint32_t alg_mask = encp->enc_rx_scale_hash_alg_mask;
1219         efx_rx_hash_alg_t alg;
1220         unsigned int flags_supp[EFX_RX_HASH_NFLAGS];
1221         unsigned int nb_flags_supp;
1222         struct sfc_rss_hf_rte_to_efx *hf_map;
1223         struct sfc_rss_hf_rte_to_efx *entry;
1224         efx_rx_hash_type_t efx_hash_types;
1225         unsigned int i;
1226         int rc;
1227
1228         if (alg_mask & (1U << EFX_RX_HASHALG_TOEPLITZ))
1229                 alg = EFX_RX_HASHALG_TOEPLITZ;
1230         else if (alg_mask & (1U << EFX_RX_HASHALG_PACKED_STREAM))
1231                 alg = EFX_RX_HASHALG_PACKED_STREAM;
1232         else
1233                 return EINVAL;
1234
1235         rc = efx_rx_scale_hash_flags_get(sa->nic, alg, flags_supp,
1236                                          RTE_DIM(flags_supp), &nb_flags_supp);
1237         if (rc != 0)
1238                 return rc;
1239
1240         hf_map = rte_calloc_socket("sfc-rss-hf-map",
1241                                    RTE_DIM(sfc_rss_hf_map),
1242                                    sizeof(*hf_map), 0, sa->socket_id);
1243         if (hf_map == NULL)
1244                 return ENOMEM;
1245
1246         entry = hf_map;
1247         efx_hash_types = 0;
1248         for (i = 0; i < RTE_DIM(sfc_rss_hf_map); ++i) {
1249                 efx_rx_hash_type_t ht;
1250
1251                 ht = sfc_rx_hash_types_mask_supp(sfc_rss_hf_map[i].efx,
1252                                                  flags_supp, nb_flags_supp);
1253                 if (ht != 0) {
1254                         entry->rte = sfc_rss_hf_map[i].rte;
1255                         entry->efx = ht;
1256                         efx_hash_types |= ht;
1257                         ++entry;
1258                 }
1259         }
1260
1261         rss->hash_alg = alg;
1262         rss->hf_map_nb_entries = (unsigned int)(entry - hf_map);
1263         rss->hf_map = hf_map;
1264         rss->hash_types = efx_hash_types;
1265
1266         return 0;
1267 }
1268
1269 void
1270 sfc_rx_hash_fini(struct sfc_adapter *sa)
1271 {
1272         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1273
1274         rte_free(rss->hf_map);
1275 }
1276
1277 int
1278 sfc_rx_hf_rte_to_efx(struct sfc_adapter *sa, uint64_t rte,
1279                      efx_rx_hash_type_t *efx)
1280 {
1281         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1282         efx_rx_hash_type_t hash_types = 0;
1283         unsigned int i;
1284
1285         for (i = 0; i < rss->hf_map_nb_entries; ++i) {
1286                 uint64_t rte_mask = rss->hf_map[i].rte;
1287
1288                 if ((rte & rte_mask) != 0) {
1289                         rte &= ~rte_mask;
1290                         hash_types |= rss->hf_map[i].efx;
1291                 }
1292         }
1293
1294         if (rte != 0) {
1295                 sfc_err(sa, "unsupported hash functions requested");
1296                 return EINVAL;
1297         }
1298
1299         *efx = hash_types;
1300
1301         return 0;
1302 }
1303
1304 uint64_t
1305 sfc_rx_hf_efx_to_rte(struct sfc_rss *rss, efx_rx_hash_type_t efx)
1306 {
1307         uint64_t rte = 0;
1308         unsigned int i;
1309
1310         for (i = 0; i < rss->hf_map_nb_entries; ++i) {
1311                 efx_rx_hash_type_t hash_type = rss->hf_map[i].efx;
1312
1313                 if ((efx & hash_type) == hash_type)
1314                         rte |= rss->hf_map[i].rte;
1315         }
1316
1317         return rte;
1318 }
1319
1320 static int
1321 sfc_rx_process_adv_conf_rss(struct sfc_adapter *sa,
1322                             struct rte_eth_rss_conf *conf)
1323 {
1324         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1325         efx_rx_hash_type_t efx_hash_types = rss->hash_types;
1326         uint64_t rss_hf = sfc_rx_hf_efx_to_rte(rss, efx_hash_types);
1327         int rc;
1328
1329         if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) {
1330                 if ((conf->rss_hf != 0 && conf->rss_hf != rss_hf) ||
1331                     conf->rss_key != NULL)
1332                         return EINVAL;
1333         }
1334
1335         if (conf->rss_hf != 0) {
1336                 rc = sfc_rx_hf_rte_to_efx(sa, conf->rss_hf, &efx_hash_types);
1337                 if (rc != 0)
1338                         return rc;
1339         }
1340
1341         if (conf->rss_key != NULL) {
1342                 if (conf->rss_key_len != sizeof(rss->key)) {
1343                         sfc_err(sa, "RSS key size is wrong (should be %lu)",
1344                                 sizeof(rss->key));
1345                         return EINVAL;
1346                 }
1347                 rte_memcpy(rss->key, conf->rss_key, sizeof(rss->key));
1348         }
1349
1350         rss->hash_types = efx_hash_types;
1351
1352         return 0;
1353 }
1354
1355 static int
1356 sfc_rx_rss_config(struct sfc_adapter *sa)
1357 {
1358         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1359         int rc = 0;
1360
1361         if (rss->channels > 0) {
1362                 rc = efx_rx_scale_mode_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1363                                            rss->hash_alg, rss->hash_types,
1364                                            B_TRUE);
1365                 if (rc != 0)
1366                         goto finish;
1367
1368                 rc = efx_rx_scale_key_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1369                                           rss->key, sizeof(rss->key));
1370                 if (rc != 0)
1371                         goto finish;
1372
1373                 rc = efx_rx_scale_tbl_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1374                                           rss->tbl, RTE_DIM(rss->tbl));
1375         }
1376
1377 finish:
1378         return rc;
1379 }
1380
1381 int
1382 sfc_rx_start(struct sfc_adapter *sa)
1383 {
1384         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1385         unsigned int sw_index;
1386         int rc;
1387
1388         sfc_log_init(sa, "rxq_count=%u", sas->rxq_count);
1389
1390         rc = efx_rx_init(sa->nic);
1391         if (rc != 0)
1392                 goto fail_rx_init;
1393
1394         rc = sfc_rx_rss_config(sa);
1395         if (rc != 0)
1396                 goto fail_rss_config;
1397
1398         for (sw_index = 0; sw_index < sas->rxq_count; ++sw_index) {
1399                 if (sas->rxq_info[sw_index].state == SFC_RXQ_INITIALIZED &&
1400                     (!sas->rxq_info[sw_index].deferred_start ||
1401                      sas->rxq_info[sw_index].deferred_started)) {
1402                         rc = sfc_rx_qstart(sa, sw_index);
1403                         if (rc != 0)
1404                                 goto fail_rx_qstart;
1405                 }
1406         }
1407
1408         return 0;
1409
1410 fail_rx_qstart:
1411         while (sw_index-- > 0)
1412                 sfc_rx_qstop(sa, sw_index);
1413
1414 fail_rss_config:
1415         efx_rx_fini(sa->nic);
1416
1417 fail_rx_init:
1418         sfc_log_init(sa, "failed %d", rc);
1419         return rc;
1420 }
1421
1422 void
1423 sfc_rx_stop(struct sfc_adapter *sa)
1424 {
1425         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1426         unsigned int sw_index;
1427
1428         sfc_log_init(sa, "rxq_count=%u", sas->rxq_count);
1429
1430         sw_index = sas->rxq_count;
1431         while (sw_index-- > 0) {
1432                 if (sas->rxq_info[sw_index].state & SFC_RXQ_STARTED)
1433                         sfc_rx_qstop(sa, sw_index);
1434         }
1435
1436         efx_rx_fini(sa->nic);
1437 }
1438
1439 static int
1440 sfc_rx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index)
1441 {
1442         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1443         struct sfc_rxq_info *rxq_info = &sas->rxq_info[sw_index];
1444         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1445         unsigned int max_entries;
1446
1447         max_entries = encp->enc_rxq_max_ndescs;
1448         SFC_ASSERT(rte_is_power_of_2(max_entries));
1449
1450         rxq_info->max_entries = max_entries;
1451
1452         return 0;
1453 }
1454
1455 static int
1456 sfc_rx_check_mode(struct sfc_adapter *sa, struct rte_eth_rxmode *rxmode)
1457 {
1458         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1459         uint64_t offloads_supported = sfc_rx_get_dev_offload_caps(sa) |
1460                                       sfc_rx_get_queue_offload_caps(sa);
1461         struct sfc_rss *rss = &sas->rss;
1462         int rc = 0;
1463
1464         switch (rxmode->mq_mode) {
1465         case ETH_MQ_RX_NONE:
1466                 /* No special checks are required */
1467                 break;
1468         case ETH_MQ_RX_RSS:
1469                 if (rss->context_type == EFX_RX_SCALE_UNAVAILABLE) {
1470                         sfc_err(sa, "RSS is not available");
1471                         rc = EINVAL;
1472                 }
1473                 break;
1474         default:
1475                 sfc_err(sa, "Rx multi-queue mode %u not supported",
1476                         rxmode->mq_mode);
1477                 rc = EINVAL;
1478         }
1479
1480         /*
1481          * Requested offloads are validated against supported by ethdev,
1482          * so unsupported offloads cannot be added as the result of
1483          * below check.
1484          */
1485         if ((rxmode->offloads & DEV_RX_OFFLOAD_CHECKSUM) !=
1486             (offloads_supported & DEV_RX_OFFLOAD_CHECKSUM)) {
1487                 sfc_warn(sa, "Rx checksum offloads cannot be disabled - always on (IPv4/TCP/UDP)");
1488                 rxmode->offloads |= DEV_RX_OFFLOAD_CHECKSUM;
1489         }
1490
1491         if ((offloads_supported & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) &&
1492             (~rxmode->offloads & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM)) {
1493                 sfc_warn(sa, "Rx outer IPv4 checksum offload cannot be disabled - always on");
1494                 rxmode->offloads |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
1495         }
1496
1497         return rc;
1498 }
1499
1500 /**
1501  * Destroy excess queues that are no longer needed after reconfiguration
1502  * or complete close.
1503  */
1504 static void
1505 sfc_rx_fini_queues(struct sfc_adapter *sa, unsigned int nb_rx_queues)
1506 {
1507         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1508         int sw_index;
1509
1510         SFC_ASSERT(nb_rx_queues <= sas->rxq_count);
1511
1512         sw_index = sas->rxq_count;
1513         while (--sw_index >= (int)nb_rx_queues) {
1514                 if (sas->rxq_info[sw_index].state & SFC_RXQ_INITIALIZED)
1515                         sfc_rx_qfini(sa, sw_index);
1516         }
1517
1518         sas->rxq_count = nb_rx_queues;
1519 }
1520
1521 /**
1522  * Initialize Rx subsystem.
1523  *
1524  * Called at device (re)configuration stage when number of receive queues is
1525  * specified together with other device level receive configuration.
1526  *
1527  * It should be used to allocate NUMA-unaware resources.
1528  */
1529 int
1530 sfc_rx_configure(struct sfc_adapter *sa)
1531 {
1532         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1533         struct sfc_rss *rss = &sas->rss;
1534         struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
1535         const unsigned int nb_rx_queues = sa->eth_dev->data->nb_rx_queues;
1536         int rc;
1537
1538         sfc_log_init(sa, "nb_rx_queues=%u (old %u)",
1539                      nb_rx_queues, sas->rxq_count);
1540
1541         rc = sfc_rx_check_mode(sa, &dev_conf->rxmode);
1542         if (rc != 0)
1543                 goto fail_check_mode;
1544
1545         if (nb_rx_queues == sas->rxq_count)
1546                 goto configure_rss;
1547
1548         if (sas->rxq_info == NULL) {
1549                 rc = ENOMEM;
1550                 sas->rxq_info = rte_calloc_socket("sfc-rxqs", nb_rx_queues,
1551                                                   sizeof(sas->rxq_info[0]), 0,
1552                                                   sa->socket_id);
1553                 if (sas->rxq_info == NULL)
1554                         goto fail_rxqs_alloc;
1555
1556                 /*
1557                  * Allocate primary process only RxQ control from heap
1558                  * since it should not be shared.
1559                  */
1560                 rc = ENOMEM;
1561                 sa->rxq_ctrl = calloc(nb_rx_queues, sizeof(sa->rxq_ctrl[0]));
1562                 if (sa->rxq_ctrl == NULL)
1563                         goto fail_rxqs_ctrl_alloc;
1564         } else {
1565                 struct sfc_rxq_info *new_rxq_info;
1566                 struct sfc_rxq *new_rxq_ctrl;
1567
1568                 if (nb_rx_queues < sas->rxq_count)
1569                         sfc_rx_fini_queues(sa, nb_rx_queues);
1570
1571                 rc = ENOMEM;
1572                 new_rxq_info =
1573                         rte_realloc(sas->rxq_info,
1574                                     nb_rx_queues * sizeof(sas->rxq_info[0]), 0);
1575                 if (new_rxq_info == NULL && nb_rx_queues > 0)
1576                         goto fail_rxqs_realloc;
1577
1578                 rc = ENOMEM;
1579                 new_rxq_ctrl = realloc(sa->rxq_ctrl,
1580                                        nb_rx_queues * sizeof(sa->rxq_ctrl[0]));
1581                 if (new_rxq_ctrl == NULL && nb_rx_queues > 0)
1582                         goto fail_rxqs_ctrl_realloc;
1583
1584                 sas->rxq_info = new_rxq_info;
1585                 sa->rxq_ctrl = new_rxq_ctrl;
1586                 if (nb_rx_queues > sas->rxq_count) {
1587                         memset(&sas->rxq_info[sas->rxq_count], 0,
1588                                (nb_rx_queues - sas->rxq_count) *
1589                                sizeof(sas->rxq_info[0]));
1590                         memset(&sa->rxq_ctrl[sas->rxq_count], 0,
1591                                (nb_rx_queues - sas->rxq_count) *
1592                                sizeof(sa->rxq_ctrl[0]));
1593                 }
1594         }
1595
1596         while (sas->rxq_count < nb_rx_queues) {
1597                 rc = sfc_rx_qinit_info(sa, sas->rxq_count);
1598                 if (rc != 0)
1599                         goto fail_rx_qinit_info;
1600
1601                 sas->rxq_count++;
1602         }
1603
1604 configure_rss:
1605         rss->channels = (dev_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) ?
1606                          MIN(sas->rxq_count, EFX_MAXRSS) : 0;
1607
1608         if (rss->channels > 0) {
1609                 struct rte_eth_rss_conf *adv_conf_rss;
1610                 unsigned int sw_index;
1611
1612                 for (sw_index = 0; sw_index < EFX_RSS_TBL_SIZE; ++sw_index)
1613                         rss->tbl[sw_index] = sw_index % rss->channels;
1614
1615                 adv_conf_rss = &dev_conf->rx_adv_conf.rss_conf;
1616                 rc = sfc_rx_process_adv_conf_rss(sa, adv_conf_rss);
1617                 if (rc != 0)
1618                         goto fail_rx_process_adv_conf_rss;
1619         }
1620
1621         return 0;
1622
1623 fail_rx_process_adv_conf_rss:
1624 fail_rx_qinit_info:
1625 fail_rxqs_ctrl_realloc:
1626 fail_rxqs_realloc:
1627 fail_rxqs_ctrl_alloc:
1628 fail_rxqs_alloc:
1629         sfc_rx_close(sa);
1630
1631 fail_check_mode:
1632         sfc_log_init(sa, "failed %d", rc);
1633         return rc;
1634 }
1635
1636 /**
1637  * Shutdown Rx subsystem.
1638  *
1639  * Called at device close stage, for example, before device shutdown.
1640  */
1641 void
1642 sfc_rx_close(struct sfc_adapter *sa)
1643 {
1644         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1645
1646         sfc_rx_fini_queues(sa, 0);
1647
1648         rss->channels = 0;
1649
1650         free(sa->rxq_ctrl);
1651         sa->rxq_ctrl = NULL;
1652
1653         rte_free(sfc_sa2shared(sa)->rxq_info);
1654         sfc_sa2shared(sa)->rxq_info = NULL;
1655 }