drivers/net/sfc/sfc_rx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2016-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  *
   6  * This software was jointly developed between OKTET Labs (under contract
   7  * for Solarflare) and Solarflare Communications, Inc.
   8  */
   9
  10 #include <rte_mempool.h>
  11
  12 #include "efx.h"
  13
  14 #include "sfc.h"
  15 #include "sfc_debug.h"
  16 #include "sfc_log.h"
  17 #include "sfc_ev.h"
  18 #include "sfc_rx.h"
  19 #include "sfc_kvargs.h"
  20 #include "sfc_tweak.h"
  21
  22 /*
  23  * Maximum number of Rx queue flush attempt in the case of failure or
  24  * flush timeout
  25  */
  26 #define SFC_RX_QFLUSH_ATTEMPTS          (3)
  27
  28 /*
  29  * Time to wait between event queue polling attempts when waiting for Rx
  30  * queue flush done or failed events.
  31  */
  32 #define SFC_RX_QFLUSH_POLL_WAIT_MS      (1)
  33
  34 /*
  35  * Maximum number of event queue polling attempts when waiting for Rx queue
  36  * flush done or failed events. It defines Rx queue flush attempt timeout
  37  * together with SFC_RX_QFLUSH_POLL_WAIT_MS.
  38  */
  39 #define SFC_RX_QFLUSH_POLL_ATTEMPTS     (2000)
  40
  41 void
  42 sfc_rx_qflush_done(struct sfc_rxq *rxq)
  43 {
  44         rxq->state |= SFC_RXQ_FLUSHED;
  45         rxq->state &= ~SFC_RXQ_FLUSHING;
  46 }
  47
  48 void
  49 sfc_rx_qflush_failed(struct sfc_rxq *rxq)
  50 {
  51         rxq->state |= SFC_RXQ_FLUSH_FAILED;
  52         rxq->state &= ~SFC_RXQ_FLUSHING;
  53 }
  54
  55 static void
  56 sfc_efx_rx_qrefill(struct sfc_efx_rxq *rxq)
  57 {
  58         unsigned int free_space;
  59         unsigned int bulks;
  60         void *objs[SFC_RX_REFILL_BULK];
  61         efsys_dma_addr_t addr[RTE_DIM(objs)];
  62         unsigned int added = rxq->added;
  63         unsigned int id;
  64         unsigned int i;
  65         struct sfc_efx_rx_sw_desc *rxd;
  66         struct rte_mbuf *m;
  67         uint16_t port_id = rxq->dp.dpq.port_id;
  68
  69         free_space = rxq->max_fill_level - (added - rxq->completed);
  70
  71         if (free_space < rxq->refill_threshold)
  72                 return;
  73
  74         bulks = free_space / RTE_DIM(objs);
  75         /* refill_threshold guarantees that bulks is positive */
  76         SFC_ASSERT(bulks > 0);
  77
  78         id = added & rxq->ptr_mask;
  79         do {
  80                 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs,
  81                                                   RTE_DIM(objs)) < 0)) {
  82                         /*
  83                          * It is hardly a safe way to increment counter
  84                          * from different contexts, but all PMDs do it.
  85                          */
  86                         rxq->evq->sa->eth_dev->data->rx_mbuf_alloc_failed +=
  87                                 RTE_DIM(objs);
  88                         /* Return if we have posted nothing yet */
  89                         if (added == rxq->added)
  90                                 return;
  91                         /* Push posted */
  92                         break;
  93                 }
  94
  95                 for (i = 0; i < RTE_DIM(objs);
  96                      ++i, id = (id + 1) & rxq->ptr_mask) {
  97                         m = objs[i];
  98
  99                         rxd = &rxq->sw_desc[id];
 100                         rxd->mbuf = m;
 101
 102                         SFC_ASSERT(rte_mbuf_refcnt_read(m) == 1);
 103                         m->data_off = RTE_PKTMBUF_HEADROOM;
 104                         SFC_ASSERT(m->next == NULL);
 105                         SFC_ASSERT(m->nb_segs == 1);
 106                         m->port = port_id;
 107
 108                         addr[i] = rte_pktmbuf_iova(m);
 109                 }
 110
 111                 efx_rx_qpost(rxq->common, addr, rxq->buf_size,
 112                              RTE_DIM(objs), rxq->completed, added);
 113                 added += RTE_DIM(objs);
 114         } while (--bulks > 0);
 115
 116         SFC_ASSERT(added != rxq->added);
 117         rxq->added = added;
 118         efx_rx_qpush(rxq->common, added, &rxq->pushed);
 119 }
 120
 121 static uint64_t
 122 sfc_efx_rx_desc_flags_to_offload_flags(const unsigned int desc_flags)
 123 {
 124         uint64_t mbuf_flags = 0;
 125
 126         switch (desc_flags & (EFX_PKT_IPV4 | EFX_CKSUM_IPV4)) {
 127         case (EFX_PKT_IPV4 | EFX_CKSUM_IPV4):
 128                 mbuf_flags |= PKT_RX_IP_CKSUM_GOOD;
 129                 break;
 130         case EFX_PKT_IPV4:
 131                 mbuf_flags |= PKT_RX_IP_CKSUM_BAD;
 132                 break;
 133         default:
 134                 RTE_BUILD_BUG_ON(PKT_RX_IP_CKSUM_UNKNOWN != 0);
 135                 SFC_ASSERT((mbuf_flags & PKT_RX_IP_CKSUM_MASK) ==
 136                            PKT_RX_IP_CKSUM_UNKNOWN);
 137                 break;
 138         }
 139
 140         switch ((desc_flags &
 141                  (EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP))) {
 142         case (EFX_PKT_TCP | EFX_CKSUM_TCPUDP):
 143         case (EFX_PKT_UDP | EFX_CKSUM_TCPUDP):
 144                 mbuf_flags |= PKT_RX_L4_CKSUM_GOOD;
 145                 break;
 146         case EFX_PKT_TCP:
 147         case EFX_PKT_UDP:
 148                 mbuf_flags |= PKT_RX_L4_CKSUM_BAD;
 149                 break;
 150         default:
 151                 RTE_BUILD_BUG_ON(PKT_RX_L4_CKSUM_UNKNOWN != 0);
 152                 SFC_ASSERT((mbuf_flags & PKT_RX_L4_CKSUM_MASK) ==
 153                            PKT_RX_L4_CKSUM_UNKNOWN);
 154                 break;
 155         }
 156
 157         return mbuf_flags;
 158 }
 159
 160 static uint32_t
 161 sfc_efx_rx_desc_flags_to_packet_type(const unsigned int desc_flags)
 162 {
 163         return RTE_PTYPE_L2_ETHER |
 164                 ((desc_flags & EFX_PKT_IPV4) ?
 165                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN : 0) |
 166                 ((desc_flags & EFX_PKT_IPV6) ?
 167                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN : 0) |
 168                 ((desc_flags & EFX_PKT_TCP) ? RTE_PTYPE_L4_TCP : 0) |
 169                 ((desc_flags & EFX_PKT_UDP) ? RTE_PTYPE_L4_UDP : 0);
 170 }
 171
 172 static const uint32_t *
 173 sfc_efx_supported_ptypes_get(__rte_unused uint32_t tunnel_encaps)
 174 {
 175         static const uint32_t ptypes[] = {
 176                 RTE_PTYPE_L2_ETHER,
 177                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 178                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 179                 RTE_PTYPE_L4_TCP,
 180                 RTE_PTYPE_L4_UDP,
 181                 RTE_PTYPE_UNKNOWN
 182         };
 183
 184         return ptypes;
 185 }
 186
 187 static void
 188 sfc_efx_rx_set_rss_hash(struct sfc_efx_rxq *rxq, unsigned int flags,
 189                         struct rte_mbuf *m)
 190 {
 191         uint8_t *mbuf_data;
 192
 193
 194         if ((rxq->flags & SFC_EFX_RXQ_FLAG_RSS_HASH) == 0)
 195                 return;
 196
 197         mbuf_data = rte_pktmbuf_mtod(m, uint8_t *);
 198
 199         if (flags & (EFX_PKT_IPV4 | EFX_PKT_IPV6)) {
 200                 m->hash.rss = efx_pseudo_hdr_hash_get(rxq->common,
 201                                                       EFX_RX_HASHALG_TOEPLITZ,
 202                                                       mbuf_data);
 203
 204                 m->ol_flags |= PKT_RX_RSS_HASH;
 205         }
 206 }
 207
 208 static uint16_t
 209 sfc_efx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 210 {
 211         struct sfc_dp_rxq *dp_rxq = rx_queue;
 212         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 213         unsigned int completed;
 214         unsigned int prefix_size = rxq->prefix_size;
 215         unsigned int done_pkts = 0;
 216         boolean_t discard_next = B_FALSE;
 217         struct rte_mbuf *scatter_pkt = NULL;
 218
 219         if (unlikely((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0))
 220                 return 0;
 221
 222         sfc_ev_qpoll(rxq->evq);
 223
 224         completed = rxq->completed;
 225         while (completed != rxq->pending && done_pkts < nb_pkts) {
 226                 unsigned int id;
 227                 struct sfc_efx_rx_sw_desc *rxd;
 228                 struct rte_mbuf *m;
 229                 unsigned int seg_len;
 230                 unsigned int desc_flags;
 231
 232                 id = completed++ & rxq->ptr_mask;
 233                 rxd = &rxq->sw_desc[id];
 234                 m = rxd->mbuf;
 235                 desc_flags = rxd->flags;
 236
 237                 if (discard_next)
 238                         goto discard;
 239
 240                 if (desc_flags & (EFX_ADDR_MISMATCH | EFX_DISCARD))
 241                         goto discard;
 242
 243                 if (desc_flags & EFX_PKT_PREFIX_LEN) {
 244                         uint16_t tmp_size;
 245                         int rc __rte_unused;
 246
 247                         rc = efx_pseudo_hdr_pkt_length_get(rxq->common,
 248                                 rte_pktmbuf_mtod(m, uint8_t *), &tmp_size);
 249                         SFC_ASSERT(rc == 0);
 250                         seg_len = tmp_size;
 251                 } else {
 252                         seg_len = rxd->size - prefix_size;
 253                 }
 254
 255                 rte_pktmbuf_data_len(m) = seg_len;
 256                 rte_pktmbuf_pkt_len(m) = seg_len;
 257
 258                 if (scatter_pkt != NULL) {
 259                         if (rte_pktmbuf_chain(scatter_pkt, m) != 0) {
 260                                 rte_pktmbuf_free(scatter_pkt);
 261                                 goto discard;
 262                         }
 263                         /* The packet to deliver */
 264                         m = scatter_pkt;
 265                 }
 266
 267                 if (desc_flags & EFX_PKT_CONT) {
 268                         /* The packet is scattered, more fragments to come */
 269                         scatter_pkt = m;
 270                         /* Further fragments have no prefix */
 271                         prefix_size = 0;
 272                         continue;
 273                 }
 274
 275                 /* Scattered packet is done */
 276                 scatter_pkt = NULL;
 277                 /* The first fragment of the packet has prefix */
 278                 prefix_size = rxq->prefix_size;
 279
 280                 m->ol_flags =
 281                         sfc_efx_rx_desc_flags_to_offload_flags(desc_flags);
 282                 m->packet_type =
 283                         sfc_efx_rx_desc_flags_to_packet_type(desc_flags);
 284
 285                 /*
 286                  * Extract RSS hash from the packet prefix and
 287                  * set the corresponding field (if needed and possible)
 288                  */
 289                 sfc_efx_rx_set_rss_hash(rxq, desc_flags, m);
 290
 291                 m->data_off += prefix_size;
 292
 293                 *rx_pkts++ = m;
 294                 done_pkts++;
 295                 continue;
 296
 297 discard:
 298                 discard_next = ((desc_flags & EFX_PKT_CONT) != 0);
 299                 rte_mempool_put(rxq->refill_mb_pool, m);
 300                 rxd->mbuf = NULL;
 301         }
 302
 303         /* pending is only moved when entire packet is received */
 304         SFC_ASSERT(scatter_pkt == NULL);
 305
 306         rxq->completed = completed;
 307
 308         sfc_efx_rx_qrefill(rxq);
 309
 310         return done_pkts;
 311 }
 312
 313 static sfc_dp_rx_qdesc_npending_t sfc_efx_rx_qdesc_npending;
 314 static unsigned int
 315 sfc_efx_rx_qdesc_npending(struct sfc_dp_rxq *dp_rxq)
 316 {
 317         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 318
 319         if ((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0)
 320                 return 0;
 321
 322         sfc_ev_qpoll(rxq->evq);
 323
 324         return rxq->pending - rxq->completed;
 325 }
 326
 327 static sfc_dp_rx_qdesc_status_t sfc_efx_rx_qdesc_status;
 328 static int
 329 sfc_efx_rx_qdesc_status(struct sfc_dp_rxq *dp_rxq, uint16_t offset)
 330 {
 331         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 332
 333         if (unlikely(offset > rxq->ptr_mask))
 334                 return -EINVAL;
 335
 336         /*
 337          * Poll EvQ to derive up-to-date 'rxq->pending' figure;
 338          * it is required for the queue to be running, but the
 339          * check is omitted because API design assumes that it
 340          * is the duty of the caller to satisfy all conditions
 341          */
 342         SFC_ASSERT((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) ==
 343                    SFC_EFX_RXQ_FLAG_RUNNING);
 344         sfc_ev_qpoll(rxq->evq);
 345
 346         /*
 347          * There is a handful of reserved entries in the ring,
 348          * but an explicit check whether the offset points to
 349          * a reserved entry is neglected since the two checks
 350          * below rely on the figures which take the HW limits
 351          * into account and thus if an entry is reserved, the
 352          * checks will fail and UNAVAIL code will be returned
 353          */
 354
 355         if (offset < (rxq->pending - rxq->completed))
 356                 return RTE_ETH_RX_DESC_DONE;
 357
 358         if (offset < (rxq->added - rxq->completed))
 359                 return RTE_ETH_RX_DESC_AVAIL;
 360
 361         return RTE_ETH_RX_DESC_UNAVAIL;
 362 }
 363
 364 struct sfc_rxq *
 365 sfc_rxq_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
 366 {
 367         const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
 368         struct rte_eth_dev *eth_dev;
 369         struct sfc_adapter *sa;
 370         struct sfc_rxq *rxq;
 371
 372         SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
 373         eth_dev = &rte_eth_devices[dpq->port_id];
 374
 375         sa = eth_dev->data->dev_private;
 376
 377         SFC_ASSERT(dpq->queue_id < sa->rxq_count);
 378         rxq = sa->rxq_info[dpq->queue_id].rxq;
 379
 380         SFC_ASSERT(rxq != NULL);
 381         return rxq;
 382 }
 383
 384 static sfc_dp_rx_qsize_up_rings_t sfc_efx_rx_qsize_up_rings;
 385 static int
 386 sfc_efx_rx_qsize_up_rings(uint16_t nb_rx_desc,
 387                           __rte_unused struct rte_mempool *mb_pool,
 388                           unsigned int *rxq_entries,
 389                           unsigned int *evq_entries,
 390                           unsigned int *rxq_max_fill_level)
 391 {
 392         *rxq_entries = nb_rx_desc;
 393         *evq_entries = nb_rx_desc;
 394         *rxq_max_fill_level = EFX_RXQ_LIMIT(*rxq_entries);
 395         return 0;
 396 }
 397
 398 static sfc_dp_rx_qcreate_t sfc_efx_rx_qcreate;
 399 static int
 400 sfc_efx_rx_qcreate(uint16_t port_id, uint16_t queue_id,
 401                    const struct rte_pci_addr *pci_addr, int socket_id,
 402                    const struct sfc_dp_rx_qcreate_info *info,
 403                    struct sfc_dp_rxq **dp_rxqp)
 404 {
 405         struct sfc_efx_rxq *rxq;
 406         int rc;
 407
 408         rc = ENOMEM;
 409         rxq = rte_zmalloc_socket("sfc-efx-rxq", sizeof(*rxq),
 410                                  RTE_CACHE_LINE_SIZE, socket_id);
 411         if (rxq == NULL)
 412                 goto fail_rxq_alloc;
 413
 414         sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr);
 415
 416         rc = ENOMEM;
 417         rxq->sw_desc = rte_calloc_socket("sfc-efx-rxq-sw_desc",
 418                                          info->rxq_entries,
 419                                          sizeof(*rxq->sw_desc),
 420                                          RTE_CACHE_LINE_SIZE, socket_id);
 421         if (rxq->sw_desc == NULL)
 422                 goto fail_desc_alloc;
 423
 424         /* efx datapath is bound to efx control path */
 425         rxq->evq = sfc_rxq_by_dp_rxq(&rxq->dp)->evq;
 426         if (info->flags & SFC_RXQ_FLAG_RSS_HASH)
 427                 rxq->flags |= SFC_EFX_RXQ_FLAG_RSS_HASH;
 428         rxq->ptr_mask = info->rxq_entries - 1;
 429         rxq->batch_max = info->batch_max;
 430         rxq->prefix_size = info->prefix_size;
 431         rxq->max_fill_level = info->max_fill_level;
 432         rxq->refill_threshold = info->refill_threshold;
 433         rxq->buf_size = info->buf_size;
 434         rxq->refill_mb_pool = info->refill_mb_pool;
 435
 436         *dp_rxqp = &rxq->dp;
 437         return 0;
 438
 439 fail_desc_alloc:
 440         rte_free(rxq);
 441
 442 fail_rxq_alloc:
 443         return rc;
 444 }
 445
 446 static sfc_dp_rx_qdestroy_t sfc_efx_rx_qdestroy;
 447 static void
 448 sfc_efx_rx_qdestroy(struct sfc_dp_rxq *dp_rxq)
 449 {
 450         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 451
 452         rte_free(rxq->sw_desc);
 453         rte_free(rxq);
 454 }
 455
 456 static sfc_dp_rx_qstart_t sfc_efx_rx_qstart;
 457 static int
 458 sfc_efx_rx_qstart(struct sfc_dp_rxq *dp_rxq,
 459                   __rte_unused unsigned int evq_read_ptr)
 460 {
 461         /* libefx-based datapath is specific to libefx-based PMD */
 462         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 463         struct sfc_rxq *crxq = sfc_rxq_by_dp_rxq(dp_rxq);
 464
 465         rxq->common = crxq->common;
 466
 467         rxq->pending = rxq->completed = rxq->added = rxq->pushed = 0;
 468
 469         sfc_efx_rx_qrefill(rxq);
 470
 471         rxq->flags |= (SFC_EFX_RXQ_FLAG_STARTED | SFC_EFX_RXQ_FLAG_RUNNING);
 472
 473         return 0;
 474 }
 475
 476 static sfc_dp_rx_qstop_t sfc_efx_rx_qstop;
 477 static void
 478 sfc_efx_rx_qstop(struct sfc_dp_rxq *dp_rxq,
 479                  __rte_unused unsigned int *evq_read_ptr)
 480 {
 481         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 482
 483         rxq->flags &= ~SFC_EFX_RXQ_FLAG_RUNNING;
 484
 485         /* libefx-based datapath is bound to libefx-based PMD and uses
 486          * event queue structure directly. So, there is no necessity to
 487          * return EvQ read pointer.
 488          */
 489 }
 490
 491 static sfc_dp_rx_qpurge_t sfc_efx_rx_qpurge;
 492 static void
 493 sfc_efx_rx_qpurge(struct sfc_dp_rxq *dp_rxq)
 494 {
 495         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 496         unsigned int i;
 497         struct sfc_efx_rx_sw_desc *rxd;
 498
 499         for (i = rxq->completed; i != rxq->added; ++i) {
 500                 rxd = &rxq->sw_desc[i & rxq->ptr_mask];
 501                 rte_mempool_put(rxq->refill_mb_pool, rxd->mbuf);
 502                 rxd->mbuf = NULL;
 503                 /* Packed stream relies on 0 in inactive SW desc.
 504                  * Rx queue stop is not performance critical, so
 505                  * there is no harm to do it always.
 506                  */
 507                 rxd->flags = 0;
 508                 rxd->size = 0;
 509         }
 510
 511         rxq->flags &= ~SFC_EFX_RXQ_FLAG_STARTED;
 512 }
 513
 514 struct sfc_dp_rx sfc_efx_rx = {
 515         .dp = {
 516                 .name           = SFC_KVARG_DATAPATH_EFX,
 517                 .type           = SFC_DP_RX,
 518                 .hw_fw_caps     = 0,
 519         },
 520         .features               = SFC_DP_RX_FEAT_SCATTER,
 521         .qsize_up_rings         = sfc_efx_rx_qsize_up_rings,
 522         .qcreate                = sfc_efx_rx_qcreate,
 523         .qdestroy               = sfc_efx_rx_qdestroy,
 524         .qstart                 = sfc_efx_rx_qstart,
 525         .qstop                  = sfc_efx_rx_qstop,
 526         .qpurge                 = sfc_efx_rx_qpurge,
 527         .supported_ptypes_get   = sfc_efx_supported_ptypes_get,
 528         .qdesc_npending         = sfc_efx_rx_qdesc_npending,
 529         .qdesc_status           = sfc_efx_rx_qdesc_status,
 530         .pkt_burst              = sfc_efx_recv_pkts,
 531 };
 532
 533 unsigned int
 534 sfc_rx_qdesc_npending(struct sfc_adapter *sa, unsigned int sw_index)
 535 {
 536         struct sfc_rxq *rxq;
 537
 538         SFC_ASSERT(sw_index < sa->rxq_count);
 539         rxq = sa->rxq_info[sw_index].rxq;
 540
 541         if (rxq == NULL || (rxq->state & SFC_RXQ_STARTED) == 0)
 542                 return 0;
 543
 544         return sa->dp_rx->qdesc_npending(rxq->dp);
 545 }
 546
 547 int
 548 sfc_rx_qdesc_done(struct sfc_dp_rxq *dp_rxq, unsigned int offset)
 549 {
 550         struct sfc_rxq *rxq = sfc_rxq_by_dp_rxq(dp_rxq);
 551
 552         return offset < rxq->evq->sa->dp_rx->qdesc_npending(dp_rxq);
 553 }
 554
 555 static void
 556 sfc_rx_qflush(struct sfc_adapter *sa, unsigned int sw_index)
 557 {
 558         struct sfc_rxq *rxq;
 559         unsigned int retry_count;
 560         unsigned int wait_count;
 561         int rc;
 562
 563         rxq = sa->rxq_info[sw_index].rxq;
 564         SFC_ASSERT(rxq->state & SFC_RXQ_STARTED);
 565
 566         /*
 567          * Retry Rx queue flushing in the case of flush failed or
 568          * timeout. In the worst case it can delay for 6 seconds.
 569          */
 570         for (retry_count = 0;
 571              ((rxq->state & SFC_RXQ_FLUSHED) == 0) &&
 572              (retry_count < SFC_RX_QFLUSH_ATTEMPTS);
 573              ++retry_count) {
 574                 rc = efx_rx_qflush(rxq->common);
 575                 if (rc != 0) {
 576                         rxq->state |= (rc == EALREADY) ?
 577                                 SFC_RXQ_FLUSHED : SFC_RXQ_FLUSH_FAILED;
 578                         break;
 579                 }
 580                 rxq->state &= ~SFC_RXQ_FLUSH_FAILED;
 581                 rxq->state |= SFC_RXQ_FLUSHING;
 582
 583                 /*
 584                  * Wait for Rx queue flush done or failed event at least
 585                  * SFC_RX_QFLUSH_POLL_WAIT_MS milliseconds and not more
 586                  * than 2 seconds (SFC_RX_QFLUSH_POLL_WAIT_MS multiplied
 587                  * by SFC_RX_QFLUSH_POLL_ATTEMPTS).
 588                  */
 589                 wait_count = 0;
 590                 do {
 591                         rte_delay_ms(SFC_RX_QFLUSH_POLL_WAIT_MS);
 592                         sfc_ev_qpoll(rxq->evq);
 593                 } while ((rxq->state & SFC_RXQ_FLUSHING) &&
 594                          (wait_count++ < SFC_RX_QFLUSH_POLL_ATTEMPTS));
 595
 596                 if (rxq->state & SFC_RXQ_FLUSHING)
 597                         sfc_err(sa, "RxQ %u flush timed out", sw_index);
 598
 599                 if (rxq->state & SFC_RXQ_FLUSH_FAILED)
 600                         sfc_err(sa, "RxQ %u flush failed", sw_index);
 601
 602                 if (rxq->state & SFC_RXQ_FLUSHED)
 603                         sfc_notice(sa, "RxQ %u flushed", sw_index);
 604         }
 605
 606         sa->dp_rx->qpurge(rxq->dp);
 607 }
 608
 609 static int
 610 sfc_rx_default_rxq_set_filter(struct sfc_adapter *sa, struct sfc_rxq *rxq)
 611 {
 612         struct sfc_rss *rss = &sa->rss;
 613         boolean_t need_rss = (rss->channels > 0) ? B_TRUE : B_FALSE;
 614         struct sfc_port *port = &sa->port;
 615         int rc;
 616
 617         /*
 618          * If promiscuous or all-multicast mode has been requested, setting
 619          * filter for the default Rx queue might fail, in particular, while
 620          * running over PCI function which is not a member of corresponding
 621          * privilege groups; if this occurs, few iterations will be made to
 622          * repeat this step without promiscuous and all-multicast flags set
 623          */
 624 retry:
 625         rc = efx_mac_filter_default_rxq_set(sa->nic, rxq->common, need_rss);
 626         if (rc == 0)
 627                 return 0;
 628         else if (rc != EOPNOTSUPP)
 629                 return rc;
 630
 631         if (port->promisc) {
 632                 sfc_warn(sa, "promiscuous mode has been requested, "
 633                              "but the HW rejects it");
 634                 sfc_warn(sa, "promiscuous mode will be disabled");
 635
 636                 port->promisc = B_FALSE;
 637                 rc = sfc_set_rx_mode(sa);
 638                 if (rc != 0)
 639                         return rc;
 640
 641                 goto retry;
 642         }
 643
 644         if (port->allmulti) {
 645                 sfc_warn(sa, "all-multicast mode has been requested, "
 646                              "but the HW rejects it");
 647                 sfc_warn(sa, "all-multicast mode will be disabled");
 648
 649                 port->allmulti = B_FALSE;
 650                 rc = sfc_set_rx_mode(sa);
 651                 if (rc != 0)
 652                         return rc;
 653
 654                 goto retry;
 655         }
 656
 657         return rc;
 658 }
 659
 660 int
 661 sfc_rx_qstart(struct sfc_adapter *sa, unsigned int sw_index)
 662 {
 663         struct sfc_port *port = &sa->port;
 664         struct sfc_rxq_info *rxq_info;
 665         struct sfc_rxq *rxq;
 666         struct sfc_evq *evq;
 667         int rc;
 668
 669         sfc_log_init(sa, "sw_index=%u", sw_index);
 670
 671         SFC_ASSERT(sw_index < sa->rxq_count);
 672
 673         rxq_info = &sa->rxq_info[sw_index];
 674         rxq = rxq_info->rxq;
 675         SFC_ASSERT(rxq->state == SFC_RXQ_INITIALIZED);
 676
 677         evq = rxq->evq;
 678
 679         rc = sfc_ev_qstart(evq, sfc_evq_index_by_rxq_sw_index(sa, sw_index));
 680         if (rc != 0)
 681                 goto fail_ev_qstart;
 682
 683         rc = efx_rx_qcreate(sa->nic, rxq->hw_index, 0, rxq_info->type,
 684                             &rxq->mem, rxq_info->entries,
 685                             0 /* not used on EF10 */, rxq_info->type_flags,
 686                             evq->common, &rxq->common);
 687         if (rc != 0)
 688                 goto fail_rx_qcreate;
 689
 690         efx_rx_qenable(rxq->common);
 691
 692         rc = sa->dp_rx->qstart(rxq->dp, evq->read_ptr);
 693         if (rc != 0)
 694                 goto fail_dp_qstart;
 695
 696         rxq->state |= SFC_RXQ_STARTED;
 697
 698         if ((sw_index == 0) && !port->isolated) {
 699                 rc = sfc_rx_default_rxq_set_filter(sa, rxq);
 700                 if (rc != 0)
 701                         goto fail_mac_filter_default_rxq_set;
 702         }
 703
 704         /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
 705         sa->eth_dev->data->rx_queue_state[sw_index] =
 706                 RTE_ETH_QUEUE_STATE_STARTED;
 707
 708         return 0;
 709
 710 fail_mac_filter_default_rxq_set:
 711         sa->dp_rx->qstop(rxq->dp, &rxq->evq->read_ptr);
 712
 713 fail_dp_qstart:
 714         sfc_rx_qflush(sa, sw_index);
 715
 716 fail_rx_qcreate:
 717         sfc_ev_qstop(evq);
 718
 719 fail_ev_qstart:
 720         return rc;
 721 }
 722
 723 void
 724 sfc_rx_qstop(struct sfc_adapter *sa, unsigned int sw_index)
 725 {
 726         struct sfc_rxq_info *rxq_info;
 727         struct sfc_rxq *rxq;
 728
 729         sfc_log_init(sa, "sw_index=%u", sw_index);
 730
 731         SFC_ASSERT(sw_index < sa->rxq_count);
 732
 733         rxq_info = &sa->rxq_info[sw_index];
 734         rxq = rxq_info->rxq;
 735
 736         if (rxq->state == SFC_RXQ_INITIALIZED)
 737                 return;
 738         SFC_ASSERT(rxq->state & SFC_RXQ_STARTED);
 739
 740         /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
 741         sa->eth_dev->data->rx_queue_state[sw_index] =
 742                 RTE_ETH_QUEUE_STATE_STOPPED;
 743
 744         sa->dp_rx->qstop(rxq->dp, &rxq->evq->read_ptr);
 745
 746         if (sw_index == 0)
 747                 efx_mac_filter_default_rxq_clear(sa->nic);
 748
 749         sfc_rx_qflush(sa, sw_index);
 750
 751         rxq->state = SFC_RXQ_INITIALIZED;
 752
 753         efx_rx_qdestroy(rxq->common);
 754
 755         sfc_ev_qstop(rxq->evq);
 756 }
 757
 758 uint64_t
 759 sfc_rx_get_dev_offload_caps(struct sfc_adapter *sa)
 760 {
 761         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
 762         uint64_t caps = 0;
 763
 764         caps |= DEV_RX_OFFLOAD_JUMBO_FRAME;
 765         caps |= DEV_RX_OFFLOAD_CRC_STRIP;
 766         caps |= DEV_RX_OFFLOAD_IPV4_CKSUM;
 767         caps |= DEV_RX_OFFLOAD_UDP_CKSUM;
 768         caps |= DEV_RX_OFFLOAD_TCP_CKSUM;
 769
 770         if (encp->enc_tunnel_encapsulations_supported &&
 771             (sa->dp_rx->features & SFC_DP_RX_FEAT_TUNNELS))
 772                 caps |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
 773
 774         return caps;
 775 }
 776
 777 uint64_t
 778 sfc_rx_get_queue_offload_caps(struct sfc_adapter *sa)
 779 {
 780         uint64_t caps = 0;
 781
 782         if (sa->dp_rx->features & SFC_DP_RX_FEAT_SCATTER)
 783                 caps |= DEV_RX_OFFLOAD_SCATTER;
 784
 785         return caps;
 786 }
 787
 788 static void
 789 sfc_rx_log_offloads(struct sfc_adapter *sa, const char *offload_group,
 790                     const char *verdict, uint64_t offloads)
 791 {
 792         unsigned long long bit;
 793
 794         while ((bit = __builtin_ffsll(offloads)) != 0) {
 795                 uint64_t flag = (1ULL << --bit);
 796
 797                 sfc_err(sa, "Rx %s offload %s %s", offload_group,
 798                         rte_eth_dev_rx_offload_name(flag), verdict);
 799
 800                 offloads &= ~flag;
 801         }
 802 }
 803
 804 static boolean_t
 805 sfc_rx_queue_offloads_mismatch(struct sfc_adapter *sa, uint64_t requested)
 806 {
 807         uint64_t mandatory = sa->eth_dev->data->dev_conf.rxmode.offloads;
 808         uint64_t supported = sfc_rx_get_dev_offload_caps(sa) |
 809                              sfc_rx_get_queue_offload_caps(sa);
 810         uint64_t rejected = requested & ~supported;
 811         uint64_t missing = (requested & mandatory) ^ mandatory;
 812         boolean_t mismatch = B_FALSE;
 813
 814         if (rejected) {
 815                 sfc_rx_log_offloads(sa, "queue", "is unsupported", rejected);
 816                 mismatch = B_TRUE;
 817         }
 818
 819         if (missing) {
 820                 sfc_rx_log_offloads(sa, "queue", "must be set", missing);
 821                 mismatch = B_TRUE;
 822         }
 823
 824         return mismatch;
 825 }
 826
 827 static int
 828 sfc_rx_qcheck_conf(struct sfc_adapter *sa, unsigned int rxq_max_fill_level,
 829                    const struct rte_eth_rxconf *rx_conf)
 830 {
 831         uint64_t offloads_supported = sfc_rx_get_dev_offload_caps(sa) |
 832                                       sfc_rx_get_queue_offload_caps(sa);
 833         int rc = 0;
 834
 835         if (rx_conf->rx_thresh.pthresh != 0 ||
 836             rx_conf->rx_thresh.hthresh != 0 ||
 837             rx_conf->rx_thresh.wthresh != 0) {
 838                 sfc_warn(sa,
 839                         "RxQ prefetch/host/writeback thresholds are not supported");
 840         }
 841
 842         if (rx_conf->rx_free_thresh > rxq_max_fill_level) {
 843                 sfc_err(sa,
 844                         "RxQ free threshold too large: %u vs maximum %u",
 845                         rx_conf->rx_free_thresh, rxq_max_fill_level);
 846                 rc = EINVAL;
 847         }
 848
 849         if (rx_conf->rx_drop_en == 0) {
 850                 sfc_err(sa, "RxQ drop disable is not supported");
 851                 rc = EINVAL;
 852         }
 853
 854         if ((rx_conf->offloads & DEV_RX_OFFLOAD_CHECKSUM) !=
 855             DEV_RX_OFFLOAD_CHECKSUM)
 856                 sfc_warn(sa, "Rx checksum offloads cannot be disabled - always on (IPv4/TCP/UDP)");
 857
 858         if ((offloads_supported & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) &&
 859             (~rx_conf->offloads & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM))
 860                 sfc_warn(sa, "Rx outer IPv4 checksum offload cannot be disabled - always on");
 861
 862         if (sfc_rx_queue_offloads_mismatch(sa, rx_conf->offloads))
 863                 rc = EINVAL;
 864
 865         return rc;
 866 }
 867
 868 static unsigned int
 869 sfc_rx_mbuf_data_alignment(struct rte_mempool *mb_pool)
 870 {
 871         uint32_t data_off;
 872         uint32_t order;
 873
 874         /* The mbuf object itself is always cache line aligned */
 875         order = rte_bsf32(RTE_CACHE_LINE_SIZE);
 876
 877         /* Data offset from mbuf object start */
 878         data_off = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(mb_pool) +
 879                 RTE_PKTMBUF_HEADROOM;
 880
 881         order = MIN(order, rte_bsf32(data_off));
 882
 883         return 1u << order;
 884 }
 885
 886 static uint16_t
 887 sfc_rx_mb_pool_buf_size(struct sfc_adapter *sa, struct rte_mempool *mb_pool)
 888 {
 889         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
 890         const uint32_t nic_align_start = MAX(1, encp->enc_rx_buf_align_start);
 891         const uint32_t nic_align_end = MAX(1, encp->enc_rx_buf_align_end);
 892         uint16_t buf_size;
 893         unsigned int buf_aligned;
 894         unsigned int start_alignment;
 895         unsigned int end_padding_alignment;
 896
 897         /* Below it is assumed that both alignments are power of 2 */
 898         SFC_ASSERT(rte_is_power_of_2(nic_align_start));
 899         SFC_ASSERT(rte_is_power_of_2(nic_align_end));
 900
 901         /*
 902          * mbuf is always cache line aligned, double-check
 903          * that it meets rx buffer start alignment requirements.
 904          */
 905
 906         /* Start from mbuf pool data room size */
 907         buf_size = rte_pktmbuf_data_room_size(mb_pool);
 908
 909         /* Remove headroom */
 910         if (buf_size <= RTE_PKTMBUF_HEADROOM) {
 911                 sfc_err(sa,
 912                         "RxQ mbuf pool %s object data room size %u is smaller than headroom %u",
 913                         mb_pool->name, buf_size, RTE_PKTMBUF_HEADROOM);
 914                 return 0;
 915         }
 916         buf_size -= RTE_PKTMBUF_HEADROOM;
 917
 918         /* Calculate guaranteed data start alignment */
 919         buf_aligned = sfc_rx_mbuf_data_alignment(mb_pool);
 920
 921         /* Reserve space for start alignment */
 922         if (buf_aligned < nic_align_start) {
 923                 start_alignment = nic_align_start - buf_aligned;
 924                 if (buf_size <= start_alignment) {
 925                         sfc_err(sa,
 926                                 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u and buffer start alignment %u required by NIC",
 927                                 mb_pool->name,
 928                                 rte_pktmbuf_data_room_size(mb_pool),
 929                                 RTE_PKTMBUF_HEADROOM, start_alignment);
 930                         return 0;
 931                 }
 932                 buf_aligned = nic_align_start;
 933                 buf_size -= start_alignment;
 934         } else {
 935                 start_alignment = 0;
 936         }
 937
 938         /* Make sure that end padding does not write beyond the buffer */
 939         if (buf_aligned < nic_align_end) {
 940                 /*
 941                  * Estimate space which can be lost. If guarnteed buffer
 942                  * size is odd, lost space is (nic_align_end - 1). More
 943                  * accurate formula is below.
 944                  */
 945                 end_padding_alignment = nic_align_end -
 946                         MIN(buf_aligned, 1u << (rte_bsf32(buf_size) - 1));
 947                 if (buf_size <= end_padding_alignment) {
 948                         sfc_err(sa,
 949                                 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u, buffer start alignment %u and end padding alignment %u required by NIC",
 950                                 mb_pool->name,
 951                                 rte_pktmbuf_data_room_size(mb_pool),
 952                                 RTE_PKTMBUF_HEADROOM, start_alignment,
 953                                 end_padding_alignment);
 954                         return 0;
 955                 }
 956                 buf_size -= end_padding_alignment;
 957         } else {
 958                 /*
 959                  * Start is aligned the same or better than end,
 960                  * just align length.
 961                  */
 962                 buf_size = P2ALIGN(buf_size, nic_align_end);
 963         }
 964
 965         return buf_size;
 966 }
 967
 968 int
 969 sfc_rx_qinit(struct sfc_adapter *sa, unsigned int sw_index,
 970              uint16_t nb_rx_desc, unsigned int socket_id,
 971              const struct rte_eth_rxconf *rx_conf,
 972              struct rte_mempool *mb_pool)
 973 {
 974         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
 975         struct sfc_rss *rss = &sa->rss;
 976         int rc;
 977         unsigned int rxq_entries;
 978         unsigned int evq_entries;
 979         unsigned int rxq_max_fill_level;
 980         uint16_t buf_size;
 981         struct sfc_rxq_info *rxq_info;
 982         struct sfc_evq *evq;
 983         struct sfc_rxq *rxq;
 984         struct sfc_dp_rx_qcreate_info info;
 985
 986         rc = sa->dp_rx->qsize_up_rings(nb_rx_desc, mb_pool, &rxq_entries,
 987                                        &evq_entries, &rxq_max_fill_level);
 988         if (rc != 0)
 989                 goto fail_size_up_rings;
 990         SFC_ASSERT(rxq_entries >= EFX_RXQ_MINNDESCS);
 991         SFC_ASSERT(rxq_entries <= EFX_RXQ_MAXNDESCS);
 992         SFC_ASSERT(rxq_max_fill_level <= nb_rx_desc);
 993
 994         rc = sfc_rx_qcheck_conf(sa, rxq_max_fill_level, rx_conf);
 995         if (rc != 0)
 996                 goto fail_bad_conf;
 997
 998         buf_size = sfc_rx_mb_pool_buf_size(sa, mb_pool);
 999         if (buf_size == 0) {
1000                 sfc_err(sa, "RxQ %u mbuf pool object size is too small",
1001                         sw_index);
1002                 rc = EINVAL;
1003                 goto fail_bad_conf;
1004         }
1005
1006         if ((buf_size < sa->port.pdu + encp->enc_rx_prefix_size) &&
1007             (~rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER)) {
1008                 sfc_err(sa, "Rx scatter is disabled and RxQ %u mbuf pool "
1009                         "object size is too small", sw_index);
1010                 sfc_err(sa, "RxQ %u calculated Rx buffer size is %u vs "
1011                         "PDU size %u plus Rx prefix %u bytes",
1012                         sw_index, buf_size, (unsigned int)sa->port.pdu,
1013                         encp->enc_rx_prefix_size);
1014                 rc = EINVAL;
1015                 goto fail_bad_conf;
1016         }
1017
1018         SFC_ASSERT(sw_index < sa->rxq_count);
1019         rxq_info = &sa->rxq_info[sw_index];
1020
1021         SFC_ASSERT(rxq_entries <= rxq_info->max_entries);
1022         rxq_info->entries = rxq_entries;
1023         rxq_info->type = EFX_RXQ_TYPE_DEFAULT;
1024         rxq_info->type_flags =
1025                 (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) ?
1026                 EFX_RXQ_FLAG_SCATTER : EFX_RXQ_FLAG_NONE;
1027
1028         if ((encp->enc_tunnel_encapsulations_supported != 0) &&
1029             (sa->dp_rx->features & SFC_DP_RX_FEAT_TUNNELS))
1030                 rxq_info->type_flags |= EFX_RXQ_FLAG_INNER_CLASSES;
1031
1032         rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_RX, sw_index,
1033                           evq_entries, socket_id, &evq);
1034         if (rc != 0)
1035                 goto fail_ev_qinit;
1036
1037         rc = ENOMEM;
1038         rxq = rte_zmalloc_socket("sfc-rxq", sizeof(*rxq), RTE_CACHE_LINE_SIZE,
1039                                  socket_id);
1040         if (rxq == NULL)
1041                 goto fail_rxq_alloc;
1042
1043         rxq_info->rxq = rxq;
1044
1045         rxq->evq = evq;
1046         rxq->hw_index = sw_index;
1047         rxq->refill_threshold =
1048                 RTE_MAX(rx_conf->rx_free_thresh, SFC_RX_REFILL_BULK);
1049         rxq->refill_mb_pool = mb_pool;
1050
1051         rc = sfc_dma_alloc(sa, "rxq", sw_index, EFX_RXQ_SIZE(rxq_info->entries),
1052                            socket_id, &rxq->mem);
1053         if (rc != 0)
1054                 goto fail_dma_alloc;
1055
1056         memset(&info, 0, sizeof(info));
1057         info.refill_mb_pool = rxq->refill_mb_pool;
1058         info.max_fill_level = rxq_max_fill_level;
1059         info.refill_threshold = rxq->refill_threshold;
1060         info.buf_size = buf_size;
1061         info.batch_max = encp->enc_rx_batch_max;
1062         info.prefix_size = encp->enc_rx_prefix_size;
1063
1064         if (rss->hash_support == EFX_RX_HASH_AVAILABLE && rss->channels > 0)
1065                 info.flags |= SFC_RXQ_FLAG_RSS_HASH;
1066
1067         info.rxq_entries = rxq_info->entries;
1068         info.rxq_hw_ring = rxq->mem.esm_base;
1069         info.evq_entries = evq_entries;
1070         info.evq_hw_ring = evq->mem.esm_base;
1071         info.hw_index = rxq->hw_index;
1072         info.mem_bar = sa->mem_bar.esb_base;
1073         info.vi_window_shift = encp->enc_vi_window_shift;
1074
1075         rc = sa->dp_rx->qcreate(sa->eth_dev->data->port_id, sw_index,
1076                                 &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr,
1077                                 socket_id, &info, &rxq->dp);
1078         if (rc != 0)
1079                 goto fail_dp_rx_qcreate;
1080
1081         evq->dp_rxq = rxq->dp;
1082
1083         rxq->state = SFC_RXQ_INITIALIZED;
1084
1085         rxq_info->deferred_start = (rx_conf->rx_deferred_start != 0);
1086
1087         return 0;
1088
1089 fail_dp_rx_qcreate:
1090         sfc_dma_free(sa, &rxq->mem);
1091
1092 fail_dma_alloc:
1093         rxq_info->rxq = NULL;
1094         rte_free(rxq);
1095
1096 fail_rxq_alloc:
1097         sfc_ev_qfini(evq);
1098
1099 fail_ev_qinit:
1100         rxq_info->entries = 0;
1101
1102 fail_bad_conf:
1103 fail_size_up_rings:
1104         sfc_log_init(sa, "failed %d", rc);
1105         return rc;
1106 }
1107
1108 void
1109 sfc_rx_qfini(struct sfc_adapter *sa, unsigned int sw_index)
1110 {
1111         struct sfc_rxq_info *rxq_info;
1112         struct sfc_rxq *rxq;
1113
1114         SFC_ASSERT(sw_index < sa->rxq_count);
1115
1116         rxq_info = &sa->rxq_info[sw_index];
1117
1118         rxq = rxq_info->rxq;
1119         SFC_ASSERT(rxq->state == SFC_RXQ_INITIALIZED);
1120
1121         sa->dp_rx->qdestroy(rxq->dp);
1122         rxq->dp = NULL;
1123
1124         rxq_info->rxq = NULL;
1125         rxq_info->entries = 0;
1126
1127         sfc_dma_free(sa, &rxq->mem);
1128
1129         sfc_ev_qfini(rxq->evq);
1130         rxq->evq = NULL;
1131
1132         rte_free(rxq);
1133 }
1134
1135 /*
1136  * Mapping between RTE RSS hash functions and their EFX counterparts.
1137  */
1138 struct sfc_rss_hf_rte_to_efx sfc_rss_hf_map[] = {
1139         { ETH_RSS_NONFRAG_IPV4_TCP,
1140           EFX_RX_HASH(IPV4_TCP, 4TUPLE) },
1141         { ETH_RSS_NONFRAG_IPV4_UDP,
1142           EFX_RX_HASH(IPV4_UDP, 4TUPLE) },
1143         { ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_IPV6_TCP_EX,
1144           EFX_RX_HASH(IPV6_TCP, 4TUPLE) },
1145         { ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_UDP_EX,
1146           EFX_RX_HASH(IPV6_UDP, 4TUPLE) },
1147         { ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_OTHER,
1148           EFX_RX_HASH(IPV4_TCP, 2TUPLE) | EFX_RX_HASH(IPV4_UDP, 2TUPLE) |
1149           EFX_RX_HASH(IPV4, 2TUPLE) },
1150         { ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_OTHER |
1151           ETH_RSS_IPV6_EX,
1152           EFX_RX_HASH(IPV6_TCP, 2TUPLE) | EFX_RX_HASH(IPV6_UDP, 2TUPLE) |
1153           EFX_RX_HASH(IPV6, 2TUPLE) }
1154 };
1155
1156 static efx_rx_hash_type_t
1157 sfc_rx_hash_types_mask_supp(efx_rx_hash_type_t hash_type,
1158                             unsigned int *hash_type_flags_supported,
1159                             unsigned int nb_hash_type_flags_supported)
1160 {
1161         efx_rx_hash_type_t hash_type_masked = 0;
1162         unsigned int i, j;
1163
1164         for (i = 0; i < nb_hash_type_flags_supported; ++i) {
1165                 unsigned int class_tuple_lbn[] = {
1166                         EFX_RX_CLASS_IPV4_TCP_LBN,
1167                         EFX_RX_CLASS_IPV4_UDP_LBN,
1168                         EFX_RX_CLASS_IPV4_LBN,
1169                         EFX_RX_CLASS_IPV6_TCP_LBN,
1170                         EFX_RX_CLASS_IPV6_UDP_LBN,
1171                         EFX_RX_CLASS_IPV6_LBN
1172                 };
1173
1174                 for (j = 0; j < RTE_DIM(class_tuple_lbn); ++j) {
1175                         unsigned int tuple_mask = EFX_RX_CLASS_HASH_4TUPLE;
1176                         unsigned int flag;
1177
1178                         tuple_mask <<= class_tuple_lbn[j];
1179                         flag = hash_type & tuple_mask;
1180
1181                         if (flag == hash_type_flags_supported[i])
1182                                 hash_type_masked |= flag;
1183                 }
1184         }
1185
1186         return hash_type_masked;
1187 }
1188
1189 int
1190 sfc_rx_hash_init(struct sfc_adapter *sa)
1191 {
1192         struct sfc_rss *rss = &sa->rss;
1193         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1194         uint32_t alg_mask = encp->enc_rx_scale_hash_alg_mask;
1195         efx_rx_hash_alg_t alg;
1196         unsigned int flags_supp[EFX_RX_HASH_NFLAGS];
1197         unsigned int nb_flags_supp;
1198         struct sfc_rss_hf_rte_to_efx *hf_map;
1199         struct sfc_rss_hf_rte_to_efx *entry;
1200         efx_rx_hash_type_t efx_hash_types;
1201         unsigned int i;
1202         int rc;
1203
1204         if (alg_mask & (1U << EFX_RX_HASHALG_TOEPLITZ))
1205                 alg = EFX_RX_HASHALG_TOEPLITZ;
1206         else if (alg_mask & (1U << EFX_RX_HASHALG_PACKED_STREAM))
1207                 alg = EFX_RX_HASHALG_PACKED_STREAM;
1208         else
1209                 return EINVAL;
1210
1211         rc = efx_rx_scale_hash_flags_get(sa->nic, alg, flags_supp,
1212                                          &nb_flags_supp);
1213         if (rc != 0)
1214                 return rc;
1215
1216         hf_map = rte_calloc_socket("sfc-rss-hf-map",
1217                                    RTE_DIM(sfc_rss_hf_map),
1218                                    sizeof(*hf_map), 0, sa->socket_id);
1219         if (hf_map == NULL)
1220                 return ENOMEM;
1221
1222         entry = hf_map;
1223         efx_hash_types = 0;
1224         for (i = 0; i < RTE_DIM(sfc_rss_hf_map); ++i) {
1225                 efx_rx_hash_type_t ht;
1226
1227                 ht = sfc_rx_hash_types_mask_supp(sfc_rss_hf_map[i].efx,
1228                                                  flags_supp, nb_flags_supp);
1229                 if (ht != 0) {
1230                         entry->rte = sfc_rss_hf_map[i].rte;
1231                         entry->efx = ht;
1232                         efx_hash_types |= ht;
1233                         ++entry;
1234                 }
1235         }
1236
1237         rss->hash_alg = alg;
1238         rss->hf_map_nb_entries = (unsigned int)(entry - hf_map);
1239         rss->hf_map = hf_map;
1240         rss->hash_types = efx_hash_types;
1241
1242         return 0;
1243 }
1244
1245 void
1246 sfc_rx_hash_fini(struct sfc_adapter *sa)
1247 {
1248         struct sfc_rss *rss = &sa->rss;
1249
1250         rte_free(rss->hf_map);
1251 }
1252
1253 int
1254 sfc_rx_hf_rte_to_efx(struct sfc_adapter *sa, uint64_t rte,
1255                      efx_rx_hash_type_t *efx)
1256 {
1257         struct sfc_rss *rss = &sa->rss;
1258         efx_rx_hash_type_t hash_types = 0;
1259         unsigned int i;
1260
1261         for (i = 0; i < rss->hf_map_nb_entries; ++i) {
1262                 uint64_t rte_mask = rss->hf_map[i].rte;
1263
1264                 if ((rte & rte_mask) != 0) {
1265                         rte &= ~rte_mask;
1266                         hash_types |= rss->hf_map[i].efx;
1267                 }
1268         }
1269
1270         if (rte != 0) {
1271                 sfc_err(sa, "unsupported hash functions requested");
1272                 return EINVAL;
1273         }
1274
1275         *efx = hash_types;
1276
1277         return 0;
1278 }
1279
1280 uint64_t
1281 sfc_rx_hf_efx_to_rte(struct sfc_adapter *sa, efx_rx_hash_type_t efx)
1282 {
1283         struct sfc_rss *rss = &sa->rss;
1284         uint64_t rte = 0;
1285         unsigned int i;
1286
1287         for (i = 0; i < rss->hf_map_nb_entries; ++i) {
1288                 efx_rx_hash_type_t hash_type = rss->hf_map[i].efx;
1289
1290                 if ((efx & hash_type) == hash_type)
1291                         rte |= rss->hf_map[i].rte;
1292         }
1293
1294         return rte;
1295 }
1296
1297 static int
1298 sfc_rx_process_adv_conf_rss(struct sfc_adapter *sa,
1299                             struct rte_eth_rss_conf *conf)
1300 {
1301         struct sfc_rss *rss = &sa->rss;
1302         efx_rx_hash_type_t efx_hash_types = rss->hash_types;
1303         uint64_t rss_hf = sfc_rx_hf_efx_to_rte(sa, efx_hash_types);
1304         int rc;
1305
1306         if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) {
1307                 if ((conf->rss_hf != 0 && conf->rss_hf != rss_hf) ||
1308                     conf->rss_key != NULL)
1309                         return EINVAL;
1310         }
1311
1312         if (conf->rss_hf != 0) {
1313                 rc = sfc_rx_hf_rte_to_efx(sa, conf->rss_hf, &efx_hash_types);
1314                 if (rc != 0)
1315                         return rc;
1316         }
1317
1318         if (conf->rss_key != NULL) {
1319                 if (conf->rss_key_len != sizeof(rss->key)) {
1320                         sfc_err(sa, "RSS key size is wrong (should be %lu)",
1321                                 sizeof(rss->key));
1322                         return EINVAL;
1323                 }
1324                 rte_memcpy(rss->key, conf->rss_key, sizeof(rss->key));
1325         }
1326
1327         rss->hash_types = efx_hash_types;
1328
1329         return 0;
1330 }
1331
1332 static int
1333 sfc_rx_rss_config(struct sfc_adapter *sa)
1334 {
1335         struct sfc_rss *rss = &sa->rss;
1336         int rc = 0;
1337
1338         if (rss->channels > 0) {
1339                 rc = efx_rx_scale_mode_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1340                                            rss->hash_alg, rss->hash_types,
1341                                            B_TRUE);
1342                 if (rc != 0)
1343                         goto finish;
1344
1345                 rc = efx_rx_scale_key_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1346                                           rss->key, sizeof(rss->key));
1347                 if (rc != 0)
1348                         goto finish;
1349
1350                 rc = efx_rx_scale_tbl_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1351                                           rss->tbl, RTE_DIM(rss->tbl));
1352         }
1353
1354 finish:
1355         return rc;
1356 }
1357
1358 int
1359 sfc_rx_start(struct sfc_adapter *sa)
1360 {
1361         unsigned int sw_index;
1362         int rc;
1363
1364         sfc_log_init(sa, "rxq_count=%u", sa->rxq_count);
1365
1366         rc = efx_rx_init(sa->nic);
1367         if (rc != 0)
1368                 goto fail_rx_init;
1369
1370         rc = sfc_rx_rss_config(sa);
1371         if (rc != 0)
1372                 goto fail_rss_config;
1373
1374         for (sw_index = 0; sw_index < sa->rxq_count; ++sw_index) {
1375                 if ((!sa->rxq_info[sw_index].deferred_start ||
1376                      sa->rxq_info[sw_index].deferred_started)) {
1377                         rc = sfc_rx_qstart(sa, sw_index);
1378                         if (rc != 0)
1379                                 goto fail_rx_qstart;
1380                 }
1381         }
1382
1383         return 0;
1384
1385 fail_rx_qstart:
1386         while (sw_index-- > 0)
1387                 sfc_rx_qstop(sa, sw_index);
1388
1389 fail_rss_config:
1390         efx_rx_fini(sa->nic);
1391
1392 fail_rx_init:
1393         sfc_log_init(sa, "failed %d", rc);
1394         return rc;
1395 }
1396
1397 void
1398 sfc_rx_stop(struct sfc_adapter *sa)
1399 {
1400         unsigned int sw_index;
1401
1402         sfc_log_init(sa, "rxq_count=%u", sa->rxq_count);
1403
1404         sw_index = sa->rxq_count;
1405         while (sw_index-- > 0) {
1406                 if (sa->rxq_info[sw_index].rxq != NULL)
1407                         sfc_rx_qstop(sa, sw_index);
1408         }
1409
1410         efx_rx_fini(sa->nic);
1411 }
1412
1413 static int
1414 sfc_rx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index)
1415 {
1416         struct sfc_rxq_info *rxq_info = &sa->rxq_info[sw_index];
1417         unsigned int max_entries;
1418
1419         max_entries = EFX_RXQ_MAXNDESCS;
1420         SFC_ASSERT(rte_is_power_of_2(max_entries));
1421
1422         rxq_info->max_entries = max_entries;
1423
1424         return 0;
1425 }
1426
1427 static int
1428 sfc_rx_check_mode(struct sfc_adapter *sa, struct rte_eth_rxmode *rxmode)
1429 {
1430         struct sfc_rss *rss = &sa->rss;
1431         uint64_t offloads_supported = sfc_rx_get_dev_offload_caps(sa) |
1432                                       sfc_rx_get_queue_offload_caps(sa);
1433         uint64_t offloads_rejected = rxmode->offloads & ~offloads_supported;
1434         int rc = 0;
1435
1436         switch (rxmode->mq_mode) {
1437         case ETH_MQ_RX_NONE:
1438                 /* No special checks are required */
1439                 break;
1440         case ETH_MQ_RX_RSS:
1441                 if (rss->context_type == EFX_RX_SCALE_UNAVAILABLE) {
1442                         sfc_err(sa, "RSS is not available");
1443                         rc = EINVAL;
1444                 }
1445                 break;
1446         default:
1447                 sfc_err(sa, "Rx multi-queue mode %u not supported",
1448                         rxmode->mq_mode);
1449                 rc = EINVAL;
1450         }
1451
1452         if (offloads_rejected) {
1453                 sfc_rx_log_offloads(sa, "device", "is unsupported",
1454                                     offloads_rejected);
1455                 rc = EINVAL;
1456         }
1457
1458         if (~rxmode->offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
1459                 sfc_warn(sa, "FCS stripping cannot be disabled - always on");
1460                 rxmode->offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
1461                 rxmode->hw_strip_crc = 1;
1462         }
1463
1464         return rc;
1465 }
1466
1467 /**
1468  * Destroy excess queues that are no longer needed after reconfiguration
1469  * or complete close.
1470  */
1471 static void
1472 sfc_rx_fini_queues(struct sfc_adapter *sa, unsigned int nb_rx_queues)
1473 {
1474         int sw_index;
1475
1476         SFC_ASSERT(nb_rx_queues <= sa->rxq_count);
1477
1478         sw_index = sa->rxq_count;
1479         while (--sw_index >= (int)nb_rx_queues) {
1480                 if (sa->rxq_info[sw_index].rxq != NULL)
1481                         sfc_rx_qfini(sa, sw_index);
1482         }
1483
1484         sa->rxq_count = nb_rx_queues;
1485 }
1486
1487 /**
1488  * Initialize Rx subsystem.
1489  *
1490  * Called at device (re)configuration stage when number of receive queues is
1491  * specified together with other device level receive configuration.
1492  *
1493  * It should be used to allocate NUMA-unaware resources.
1494  */
1495 int
1496 sfc_rx_configure(struct sfc_adapter *sa)
1497 {
1498         struct sfc_rss *rss = &sa->rss;
1499         struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
1500         const unsigned int nb_rx_queues = sa->eth_dev->data->nb_rx_queues;
1501         int rc;
1502
1503         sfc_log_init(sa, "nb_rx_queues=%u (old %u)",
1504                      nb_rx_queues, sa->rxq_count);
1505
1506         rc = sfc_rx_check_mode(sa, &dev_conf->rxmode);
1507         if (rc != 0)
1508                 goto fail_check_mode;
1509
1510         if (nb_rx_queues == sa->rxq_count)
1511                 goto done;
1512
1513         if (sa->rxq_info == NULL) {
1514                 rc = ENOMEM;
1515                 sa->rxq_info = rte_calloc_socket("sfc-rxqs", nb_rx_queues,
1516                                                  sizeof(sa->rxq_info[0]), 0,
1517                                                  sa->socket_id);
1518                 if (sa->rxq_info == NULL)
1519                         goto fail_rxqs_alloc;
1520         } else {
1521                 struct sfc_rxq_info *new_rxq_info;
1522
1523                 if (nb_rx_queues < sa->rxq_count)
1524                         sfc_rx_fini_queues(sa, nb_rx_queues);
1525
1526                 rc = ENOMEM;
1527                 new_rxq_info =
1528                         rte_realloc(sa->rxq_info,
1529                                     nb_rx_queues * sizeof(sa->rxq_info[0]), 0);
1530                 if (new_rxq_info == NULL && nb_rx_queues > 0)
1531                         goto fail_rxqs_realloc;
1532
1533                 sa->rxq_info = new_rxq_info;
1534                 if (nb_rx_queues > sa->rxq_count)
1535                         memset(&sa->rxq_info[sa->rxq_count], 0,
1536                                (nb_rx_queues - sa->rxq_count) *
1537                                sizeof(sa->rxq_info[0]));
1538         }
1539
1540         while (sa->rxq_count < nb_rx_queues) {
1541                 rc = sfc_rx_qinit_info(sa, sa->rxq_count);
1542                 if (rc != 0)
1543                         goto fail_rx_qinit_info;
1544
1545                 sa->rxq_count++;
1546         }
1547
1548         rss->channels = (dev_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) ?
1549                          MIN(sa->rxq_count, EFX_MAXRSS) : 0;
1550
1551         if (rss->channels > 0) {
1552                 struct rte_eth_rss_conf *adv_conf_rss;
1553                 unsigned int sw_index;
1554
1555                 for (sw_index = 0; sw_index < EFX_RSS_TBL_SIZE; ++sw_index)
1556                         rss->tbl[sw_index] = sw_index % rss->channels;
1557
1558                 adv_conf_rss = &dev_conf->rx_adv_conf.rss_conf;
1559                 rc = sfc_rx_process_adv_conf_rss(sa, adv_conf_rss);
1560                 if (rc != 0)
1561                         goto fail_rx_process_adv_conf_rss;
1562         }
1563
1564 done:
1565         return 0;
1566
1567 fail_rx_process_adv_conf_rss:
1568 fail_rx_qinit_info:
1569 fail_rxqs_realloc:
1570 fail_rxqs_alloc:
1571         sfc_rx_close(sa);
1572
1573 fail_check_mode:
1574         sfc_log_init(sa, "failed %d", rc);
1575         return rc;
1576 }
1577
1578 /**
1579  * Shutdown Rx subsystem.
1580  *
1581  * Called at device close stage, for example, before device shutdown.
1582  */
1583 void
1584 sfc_rx_close(struct sfc_adapter *sa)
1585 {
1586         struct sfc_rss *rss = &sa->rss;
1587
1588         sfc_rx_fini_queues(sa, 0);
1589
1590         rss->channels = 0;
1591
1592         rte_free(sa->rxq_info);
1593         sa->rxq_info = NULL;
1594 }