drivers/net/sfc/sfc_rx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2016-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  *
   6  * This software was jointly developed between OKTET Labs (under contract
   7  * for Solarflare) and Solarflare Communications, Inc.
   8  */
   9
  10 #include <rte_mempool.h>
  11
  12 #include "efx.h"
  13
  14 #include "sfc.h"
  15 #include "sfc_debug.h"
  16 #include "sfc_log.h"
  17 #include "sfc_ev.h"
  18 #include "sfc_rx.h"
  19 #include "sfc_kvargs.h"
  20 #include "sfc_tweak.h"
  21
  22 /*
  23  * Maximum number of Rx queue flush attempt in the case of failure or
  24  * flush timeout
  25  */
  26 #define SFC_RX_QFLUSH_ATTEMPTS          (3)
  27
  28 /*
  29  * Time to wait between event queue polling attempts when waiting for Rx
  30  * queue flush done or failed events.
  31  */
  32 #define SFC_RX_QFLUSH_POLL_WAIT_MS      (1)
  33
  34 /*
  35  * Maximum number of event queue polling attempts when waiting for Rx queue
  36  * flush done or failed events. It defines Rx queue flush attempt timeout
  37  * together with SFC_RX_QFLUSH_POLL_WAIT_MS.
  38  */
  39 #define SFC_RX_QFLUSH_POLL_ATTEMPTS     (2000)
  40
  41 void
  42 sfc_rx_qflush_done(struct sfc_rxq_info *rxq_info)
  43 {
  44         rxq_info->state |= SFC_RXQ_FLUSHED;
  45         rxq_info->state &= ~SFC_RXQ_FLUSHING;
  46 }
  47
  48 void
  49 sfc_rx_qflush_failed(struct sfc_rxq_info *rxq_info)
  50 {
  51         rxq_info->state |= SFC_RXQ_FLUSH_FAILED;
  52         rxq_info->state &= ~SFC_RXQ_FLUSHING;
  53 }
  54
  55 static void
  56 sfc_efx_rx_qrefill(struct sfc_efx_rxq *rxq)
  57 {
  58         unsigned int free_space;
  59         unsigned int bulks;
  60         void *objs[SFC_RX_REFILL_BULK];
  61         efsys_dma_addr_t addr[RTE_DIM(objs)];
  62         unsigned int added = rxq->added;
  63         unsigned int id;
  64         unsigned int i;
  65         struct sfc_efx_rx_sw_desc *rxd;
  66         struct rte_mbuf *m;
  67         uint16_t port_id = rxq->dp.dpq.port_id;
  68
  69         free_space = rxq->max_fill_level - (added - rxq->completed);
  70
  71         if (free_space < rxq->refill_threshold)
  72                 return;
  73
  74         bulks = free_space / RTE_DIM(objs);
  75         /* refill_threshold guarantees that bulks is positive */
  76         SFC_ASSERT(bulks > 0);
  77
  78         id = added & rxq->ptr_mask;
  79         do {
  80                 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs,
  81                                                   RTE_DIM(objs)) < 0)) {
  82                         /*
  83                          * It is hardly a safe way to increment counter
  84                          * from different contexts, but all PMDs do it.
  85                          */
  86                         rxq->evq->sa->eth_dev->data->rx_mbuf_alloc_failed +=
  87                                 RTE_DIM(objs);
  88                         /* Return if we have posted nothing yet */
  89                         if (added == rxq->added)
  90                                 return;
  91                         /* Push posted */
  92                         break;
  93                 }
  94
  95                 for (i = 0; i < RTE_DIM(objs);
  96                      ++i, id = (id + 1) & rxq->ptr_mask) {
  97                         m = objs[i];
  98
  99                         MBUF_RAW_ALLOC_CHECK(m);
 100
 101                         rxd = &rxq->sw_desc[id];
 102                         rxd->mbuf = m;
 103
 104                         m->data_off = RTE_PKTMBUF_HEADROOM;
 105                         m->port = port_id;
 106
 107                         addr[i] = rte_pktmbuf_iova(m);
 108                 }
 109
 110                 efx_rx_qpost(rxq->common, addr, rxq->buf_size,
 111                              RTE_DIM(objs), rxq->completed, added);
 112                 added += RTE_DIM(objs);
 113         } while (--bulks > 0);
 114
 115         SFC_ASSERT(added != rxq->added);
 116         rxq->added = added;
 117         efx_rx_qpush(rxq->common, added, &rxq->pushed);
 118 }
 119
 120 static uint64_t
 121 sfc_efx_rx_desc_flags_to_offload_flags(const unsigned int desc_flags)
 122 {
 123         uint64_t mbuf_flags = 0;
 124
 125         switch (desc_flags & (EFX_PKT_IPV4 | EFX_CKSUM_IPV4)) {
 126         case (EFX_PKT_IPV4 | EFX_CKSUM_IPV4):
 127                 mbuf_flags |= PKT_RX_IP_CKSUM_GOOD;
 128                 break;
 129         case EFX_PKT_IPV4:
 130                 mbuf_flags |= PKT_RX_IP_CKSUM_BAD;
 131                 break;
 132         default:
 133                 RTE_BUILD_BUG_ON(PKT_RX_IP_CKSUM_UNKNOWN != 0);
 134                 SFC_ASSERT((mbuf_flags & PKT_RX_IP_CKSUM_MASK) ==
 135                            PKT_RX_IP_CKSUM_UNKNOWN);
 136                 break;
 137         }
 138
 139         switch ((desc_flags &
 140                  (EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP))) {
 141         case (EFX_PKT_TCP | EFX_CKSUM_TCPUDP):
 142         case (EFX_PKT_UDP | EFX_CKSUM_TCPUDP):
 143                 mbuf_flags |= PKT_RX_L4_CKSUM_GOOD;
 144                 break;
 145         case EFX_PKT_TCP:
 146         case EFX_PKT_UDP:
 147                 mbuf_flags |= PKT_RX_L4_CKSUM_BAD;
 148                 break;
 149         default:
 150                 RTE_BUILD_BUG_ON(PKT_RX_L4_CKSUM_UNKNOWN != 0);
 151                 SFC_ASSERT((mbuf_flags & PKT_RX_L4_CKSUM_MASK) ==
 152                            PKT_RX_L4_CKSUM_UNKNOWN);
 153                 break;
 154         }
 155
 156         return mbuf_flags;
 157 }
 158
 159 static uint32_t
 160 sfc_efx_rx_desc_flags_to_packet_type(const unsigned int desc_flags)
 161 {
 162         return RTE_PTYPE_L2_ETHER |
 163                 ((desc_flags & EFX_PKT_IPV4) ?
 164                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN : 0) |
 165                 ((desc_flags & EFX_PKT_IPV6) ?
 166                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN : 0) |
 167                 ((desc_flags & EFX_PKT_TCP) ? RTE_PTYPE_L4_TCP : 0) |
 168                 ((desc_flags & EFX_PKT_UDP) ? RTE_PTYPE_L4_UDP : 0);
 169 }
 170
 171 static const uint32_t *
 172 sfc_efx_supported_ptypes_get(__rte_unused uint32_t tunnel_encaps)
 173 {
 174         static const uint32_t ptypes[] = {
 175                 RTE_PTYPE_L2_ETHER,
 176                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 177                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 178                 RTE_PTYPE_L4_TCP,
 179                 RTE_PTYPE_L4_UDP,
 180                 RTE_PTYPE_UNKNOWN
 181         };
 182
 183         return ptypes;
 184 }
 185
 186 static void
 187 sfc_efx_rx_set_rss_hash(struct sfc_efx_rxq *rxq, unsigned int flags,
 188                         struct rte_mbuf *m)
 189 {
 190         uint8_t *mbuf_data;
 191
 192
 193         if ((rxq->flags & SFC_EFX_RXQ_FLAG_RSS_HASH) == 0)
 194                 return;
 195
 196         mbuf_data = rte_pktmbuf_mtod(m, uint8_t *);
 197
 198         if (flags & (EFX_PKT_IPV4 | EFX_PKT_IPV6)) {
 199                 m->hash.rss = efx_pseudo_hdr_hash_get(rxq->common,
 200                                                       EFX_RX_HASHALG_TOEPLITZ,
 201                                                       mbuf_data);
 202
 203                 m->ol_flags |= PKT_RX_RSS_HASH;
 204         }
 205 }
 206
 207 static uint16_t
 208 sfc_efx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 209 {
 210         struct sfc_dp_rxq *dp_rxq = rx_queue;
 211         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 212         unsigned int completed;
 213         unsigned int prefix_size = rxq->prefix_size;
 214         unsigned int done_pkts = 0;
 215         boolean_t discard_next = B_FALSE;
 216         struct rte_mbuf *scatter_pkt = NULL;
 217
 218         if (unlikely((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0))
 219                 return 0;
 220
 221         sfc_ev_qpoll(rxq->evq);
 222
 223         completed = rxq->completed;
 224         while (completed != rxq->pending && done_pkts < nb_pkts) {
 225                 unsigned int id;
 226                 struct sfc_efx_rx_sw_desc *rxd;
 227                 struct rte_mbuf *m;
 228                 unsigned int seg_len;
 229                 unsigned int desc_flags;
 230
 231                 id = completed++ & rxq->ptr_mask;
 232                 rxd = &rxq->sw_desc[id];
 233                 m = rxd->mbuf;
 234                 desc_flags = rxd->flags;
 235
 236                 if (discard_next)
 237                         goto discard;
 238
 239                 if (desc_flags & (EFX_ADDR_MISMATCH | EFX_DISCARD))
 240                         goto discard;
 241
 242                 if (desc_flags & EFX_PKT_PREFIX_LEN) {
 243                         uint16_t tmp_size;
 244                         int rc __rte_unused;
 245
 246                         rc = efx_pseudo_hdr_pkt_length_get(rxq->common,
 247                                 rte_pktmbuf_mtod(m, uint8_t *), &tmp_size);
 248                         SFC_ASSERT(rc == 0);
 249                         seg_len = tmp_size;
 250                 } else {
 251                         seg_len = rxd->size - prefix_size;
 252                 }
 253
 254                 rte_pktmbuf_data_len(m) = seg_len;
 255                 rte_pktmbuf_pkt_len(m) = seg_len;
 256
 257                 if (scatter_pkt != NULL) {
 258                         if (rte_pktmbuf_chain(scatter_pkt, m) != 0) {
 259                                 rte_pktmbuf_free(scatter_pkt);
 260                                 goto discard;
 261                         }
 262                         /* The packet to deliver */
 263                         m = scatter_pkt;
 264                 }
 265
 266                 if (desc_flags & EFX_PKT_CONT) {
 267                         /* The packet is scattered, more fragments to come */
 268                         scatter_pkt = m;
 269                         /* Further fragments have no prefix */
 270                         prefix_size = 0;
 271                         continue;
 272                 }
 273
 274                 /* Scattered packet is done */
 275                 scatter_pkt = NULL;
 276                 /* The first fragment of the packet has prefix */
 277                 prefix_size = rxq->prefix_size;
 278
 279                 m->ol_flags =
 280                         sfc_efx_rx_desc_flags_to_offload_flags(desc_flags);
 281                 m->packet_type =
 282                         sfc_efx_rx_desc_flags_to_packet_type(desc_flags);
 283
 284                 /*
 285                  * Extract RSS hash from the packet prefix and
 286                  * set the corresponding field (if needed and possible)
 287                  */
 288                 sfc_efx_rx_set_rss_hash(rxq, desc_flags, m);
 289
 290                 m->data_off += prefix_size;
 291
 292                 *rx_pkts++ = m;
 293                 done_pkts++;
 294                 continue;
 295
 296 discard:
 297                 discard_next = ((desc_flags & EFX_PKT_CONT) != 0);
 298                 rte_mbuf_raw_free(m);
 299                 rxd->mbuf = NULL;
 300         }
 301
 302         /* pending is only moved when entire packet is received */
 303         SFC_ASSERT(scatter_pkt == NULL);
 304
 305         rxq->completed = completed;
 306
 307         sfc_efx_rx_qrefill(rxq);
 308
 309         return done_pkts;
 310 }
 311
 312 static sfc_dp_rx_qdesc_npending_t sfc_efx_rx_qdesc_npending;
 313 static unsigned int
 314 sfc_efx_rx_qdesc_npending(struct sfc_dp_rxq *dp_rxq)
 315 {
 316         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 317
 318         if ((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0)
 319                 return 0;
 320
 321         sfc_ev_qpoll(rxq->evq);
 322
 323         return rxq->pending - rxq->completed;
 324 }
 325
 326 static sfc_dp_rx_qdesc_status_t sfc_efx_rx_qdesc_status;
 327 static int
 328 sfc_efx_rx_qdesc_status(struct sfc_dp_rxq *dp_rxq, uint16_t offset)
 329 {
 330         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 331
 332         if (unlikely(offset > rxq->ptr_mask))
 333                 return -EINVAL;
 334
 335         /*
 336          * Poll EvQ to derive up-to-date 'rxq->pending' figure;
 337          * it is required for the queue to be running, but the
 338          * check is omitted because API design assumes that it
 339          * is the duty of the caller to satisfy all conditions
 340          */
 341         SFC_ASSERT((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) ==
 342                    SFC_EFX_RXQ_FLAG_RUNNING);
 343         sfc_ev_qpoll(rxq->evq);
 344
 345         /*
 346          * There is a handful of reserved entries in the ring,
 347          * but an explicit check whether the offset points to
 348          * a reserved entry is neglected since the two checks
 349          * below rely on the figures which take the HW limits
 350          * into account and thus if an entry is reserved, the
 351          * checks will fail and UNAVAIL code will be returned
 352          */
 353
 354         if (offset < (rxq->pending - rxq->completed))
 355                 return RTE_ETH_RX_DESC_DONE;
 356
 357         if (offset < (rxq->added - rxq->completed))
 358                 return RTE_ETH_RX_DESC_AVAIL;
 359
 360         return RTE_ETH_RX_DESC_UNAVAIL;
 361 }
 362
 363 struct sfc_rxq_info *
 364 sfc_rxq_info_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
 365 {
 366         const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
 367         struct rte_eth_dev *eth_dev;
 368         struct sfc_adapter *sa;
 369
 370         SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
 371         eth_dev = &rte_eth_devices[dpq->port_id];
 372
 373         sa = eth_dev->data->dev_private;
 374
 375         SFC_ASSERT(dpq->queue_id < sa->rxq_count);
 376         return &sa->rxq_info[dpq->queue_id];
 377 }
 378
 379 struct sfc_rxq *
 380 sfc_rxq_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
 381 {
 382         struct sfc_rxq_info *rxq_info;
 383
 384         rxq_info = sfc_rxq_info_by_dp_rxq(dp_rxq);
 385
 386         SFC_ASSERT(rxq_info->rxq != NULL);
 387         return rxq_info->rxq;
 388 }
 389
 390 static sfc_dp_rx_qsize_up_rings_t sfc_efx_rx_qsize_up_rings;
 391 static int
 392 sfc_efx_rx_qsize_up_rings(uint16_t nb_rx_desc,
 393                           __rte_unused struct rte_mempool *mb_pool,
 394                           unsigned int *rxq_entries,
 395                           unsigned int *evq_entries,
 396                           unsigned int *rxq_max_fill_level)
 397 {
 398         *rxq_entries = nb_rx_desc;
 399         *evq_entries = nb_rx_desc;
 400         *rxq_max_fill_level = EFX_RXQ_LIMIT(*rxq_entries);
 401         return 0;
 402 }
 403
 404 static sfc_dp_rx_qcreate_t sfc_efx_rx_qcreate;
 405 static int
 406 sfc_efx_rx_qcreate(uint16_t port_id, uint16_t queue_id,
 407                    const struct rte_pci_addr *pci_addr, int socket_id,
 408                    const struct sfc_dp_rx_qcreate_info *info,
 409                    struct sfc_dp_rxq **dp_rxqp)
 410 {
 411         struct sfc_efx_rxq *rxq;
 412         int rc;
 413
 414         rc = ENOMEM;
 415         rxq = rte_zmalloc_socket("sfc-efx-rxq", sizeof(*rxq),
 416                                  RTE_CACHE_LINE_SIZE, socket_id);
 417         if (rxq == NULL)
 418                 goto fail_rxq_alloc;
 419
 420         sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr);
 421
 422         rc = ENOMEM;
 423         rxq->sw_desc = rte_calloc_socket("sfc-efx-rxq-sw_desc",
 424                                          info->rxq_entries,
 425                                          sizeof(*rxq->sw_desc),
 426                                          RTE_CACHE_LINE_SIZE, socket_id);
 427         if (rxq->sw_desc == NULL)
 428                 goto fail_desc_alloc;
 429
 430         /* efx datapath is bound to efx control path */
 431         rxq->evq = sfc_rxq_by_dp_rxq(&rxq->dp)->evq;
 432         if (info->flags & SFC_RXQ_FLAG_RSS_HASH)
 433                 rxq->flags |= SFC_EFX_RXQ_FLAG_RSS_HASH;
 434         rxq->ptr_mask = info->rxq_entries - 1;
 435         rxq->batch_max = info->batch_max;
 436         rxq->prefix_size = info->prefix_size;
 437         rxq->max_fill_level = info->max_fill_level;
 438         rxq->refill_threshold = info->refill_threshold;
 439         rxq->buf_size = info->buf_size;
 440         rxq->refill_mb_pool = info->refill_mb_pool;
 441
 442         *dp_rxqp = &rxq->dp;
 443         return 0;
 444
 445 fail_desc_alloc:
 446         rte_free(rxq);
 447
 448 fail_rxq_alloc:
 449         return rc;
 450 }
 451
 452 static sfc_dp_rx_qdestroy_t sfc_efx_rx_qdestroy;
 453 static void
 454 sfc_efx_rx_qdestroy(struct sfc_dp_rxq *dp_rxq)
 455 {
 456         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 457
 458         rte_free(rxq->sw_desc);
 459         rte_free(rxq);
 460 }
 461
 462 static sfc_dp_rx_qstart_t sfc_efx_rx_qstart;
 463 static int
 464 sfc_efx_rx_qstart(struct sfc_dp_rxq *dp_rxq,
 465                   __rte_unused unsigned int evq_read_ptr)
 466 {
 467         /* libefx-based datapath is specific to libefx-based PMD */
 468         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 469         struct sfc_rxq *crxq = sfc_rxq_by_dp_rxq(dp_rxq);
 470
 471         rxq->common = crxq->common;
 472
 473         rxq->pending = rxq->completed = rxq->added = rxq->pushed = 0;
 474
 475         sfc_efx_rx_qrefill(rxq);
 476
 477         rxq->flags |= (SFC_EFX_RXQ_FLAG_STARTED | SFC_EFX_RXQ_FLAG_RUNNING);
 478
 479         return 0;
 480 }
 481
 482 static sfc_dp_rx_qstop_t sfc_efx_rx_qstop;
 483 static void
 484 sfc_efx_rx_qstop(struct sfc_dp_rxq *dp_rxq,
 485                  __rte_unused unsigned int *evq_read_ptr)
 486 {
 487         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 488
 489         rxq->flags &= ~SFC_EFX_RXQ_FLAG_RUNNING;
 490
 491         /* libefx-based datapath is bound to libefx-based PMD and uses
 492          * event queue structure directly. So, there is no necessity to
 493          * return EvQ read pointer.
 494          */
 495 }
 496
 497 static sfc_dp_rx_qpurge_t sfc_efx_rx_qpurge;
 498 static void
 499 sfc_efx_rx_qpurge(struct sfc_dp_rxq *dp_rxq)
 500 {
 501         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 502         unsigned int i;
 503         struct sfc_efx_rx_sw_desc *rxd;
 504
 505         for (i = rxq->completed; i != rxq->added; ++i) {
 506                 rxd = &rxq->sw_desc[i & rxq->ptr_mask];
 507                 rte_mbuf_raw_free(rxd->mbuf);
 508                 rxd->mbuf = NULL;
 509                 /* Packed stream relies on 0 in inactive SW desc.
 510                  * Rx queue stop is not performance critical, so
 511                  * there is no harm to do it always.
 512                  */
 513                 rxd->flags = 0;
 514                 rxd->size = 0;
 515         }
 516
 517         rxq->flags &= ~SFC_EFX_RXQ_FLAG_STARTED;
 518 }
 519
 520 struct sfc_dp_rx sfc_efx_rx = {
 521         .dp = {
 522                 .name           = SFC_KVARG_DATAPATH_EFX,
 523                 .type           = SFC_DP_RX,
 524                 .hw_fw_caps     = 0,
 525         },
 526         .features               = SFC_DP_RX_FEAT_SCATTER |
 527                                   SFC_DP_RX_FEAT_CHECKSUM,
 528         .qsize_up_rings         = sfc_efx_rx_qsize_up_rings,
 529         .qcreate                = sfc_efx_rx_qcreate,
 530         .qdestroy               = sfc_efx_rx_qdestroy,
 531         .qstart                 = sfc_efx_rx_qstart,
 532         .qstop                  = sfc_efx_rx_qstop,
 533         .qpurge                 = sfc_efx_rx_qpurge,
 534         .supported_ptypes_get   = sfc_efx_supported_ptypes_get,
 535         .qdesc_npending         = sfc_efx_rx_qdesc_npending,
 536         .qdesc_status           = sfc_efx_rx_qdesc_status,
 537         .pkt_burst              = sfc_efx_recv_pkts,
 538 };
 539
 540 static void
 541 sfc_rx_qflush(struct sfc_adapter *sa, unsigned int sw_index)
 542 {
 543         struct sfc_rxq_info *rxq_info;
 544         struct sfc_rxq *rxq;
 545         unsigned int retry_count;
 546         unsigned int wait_count;
 547         int rc;
 548
 549         rxq_info = &sa->rxq_info[sw_index];
 550         rxq = rxq_info->rxq;
 551         SFC_ASSERT(rxq_info->state & SFC_RXQ_STARTED);
 552
 553         /*
 554          * Retry Rx queue flushing in the case of flush failed or
 555          * timeout. In the worst case it can delay for 6 seconds.
 556          */
 557         for (retry_count = 0;
 558              ((rxq_info->state & SFC_RXQ_FLUSHED) == 0) &&
 559              (retry_count < SFC_RX_QFLUSH_ATTEMPTS);
 560              ++retry_count) {
 561                 rc = efx_rx_qflush(rxq->common);
 562                 if (rc != 0) {
 563                         rxq_info->state |= (rc == EALREADY) ?
 564                                 SFC_RXQ_FLUSHED : SFC_RXQ_FLUSH_FAILED;
 565                         break;
 566                 }
 567                 rxq_info->state &= ~SFC_RXQ_FLUSH_FAILED;
 568                 rxq_info->state |= SFC_RXQ_FLUSHING;
 569
 570                 /*
 571                  * Wait for Rx queue flush done or failed event at least
 572                  * SFC_RX_QFLUSH_POLL_WAIT_MS milliseconds and not more
 573                  * than 2 seconds (SFC_RX_QFLUSH_POLL_WAIT_MS multiplied
 574                  * by SFC_RX_QFLUSH_POLL_ATTEMPTS).
 575                  */
 576                 wait_count = 0;
 577                 do {
 578                         rte_delay_ms(SFC_RX_QFLUSH_POLL_WAIT_MS);
 579                         sfc_ev_qpoll(rxq->evq);
 580                 } while ((rxq_info->state & SFC_RXQ_FLUSHING) &&
 581                          (wait_count++ < SFC_RX_QFLUSH_POLL_ATTEMPTS));
 582
 583                 if (rxq_info->state & SFC_RXQ_FLUSHING)
 584                         sfc_err(sa, "RxQ %u flush timed out", sw_index);
 585
 586                 if (rxq_info->state & SFC_RXQ_FLUSH_FAILED)
 587                         sfc_err(sa, "RxQ %u flush failed", sw_index);
 588
 589                 if (rxq_info->state & SFC_RXQ_FLUSHED)
 590                         sfc_notice(sa, "RxQ %u flushed", sw_index);
 591         }
 592
 593         sa->priv.dp_rx->qpurge(rxq_info->dp);
 594 }
 595
 596 static int
 597 sfc_rx_default_rxq_set_filter(struct sfc_adapter *sa, struct sfc_rxq *rxq)
 598 {
 599         struct sfc_rss *rss = &sa->rss;
 600         boolean_t need_rss = (rss->channels > 0) ? B_TRUE : B_FALSE;
 601         struct sfc_port *port = &sa->port;
 602         int rc;
 603
 604         /*
 605          * If promiscuous or all-multicast mode has been requested, setting
 606          * filter for the default Rx queue might fail, in particular, while
 607          * running over PCI function which is not a member of corresponding
 608          * privilege groups; if this occurs, few iterations will be made to
 609          * repeat this step without promiscuous and all-multicast flags set
 610          */
 611 retry:
 612         rc = efx_mac_filter_default_rxq_set(sa->nic, rxq->common, need_rss);
 613         if (rc == 0)
 614                 return 0;
 615         else if (rc != EOPNOTSUPP)
 616                 return rc;
 617
 618         if (port->promisc) {
 619                 sfc_warn(sa, "promiscuous mode has been requested, "
 620                              "but the HW rejects it");
 621                 sfc_warn(sa, "promiscuous mode will be disabled");
 622
 623                 port->promisc = B_FALSE;
 624                 rc = sfc_set_rx_mode(sa);
 625                 if (rc != 0)
 626                         return rc;
 627
 628                 goto retry;
 629         }
 630
 631         if (port->allmulti) {
 632                 sfc_warn(sa, "all-multicast mode has been requested, "
 633                              "but the HW rejects it");
 634                 sfc_warn(sa, "all-multicast mode will be disabled");
 635
 636                 port->allmulti = B_FALSE;
 637                 rc = sfc_set_rx_mode(sa);
 638                 if (rc != 0)
 639                         return rc;
 640
 641                 goto retry;
 642         }
 643
 644         return rc;
 645 }
 646
 647 int
 648 sfc_rx_qstart(struct sfc_adapter *sa, unsigned int sw_index)
 649 {
 650         struct sfc_port *port = &sa->port;
 651         struct sfc_rxq_info *rxq_info;
 652         struct sfc_rxq *rxq;
 653         struct sfc_evq *evq;
 654         int rc;
 655
 656         sfc_log_init(sa, "sw_index=%u", sw_index);
 657
 658         SFC_ASSERT(sw_index < sa->rxq_count);
 659
 660         rxq_info = &sa->rxq_info[sw_index];
 661         rxq = rxq_info->rxq;
 662         SFC_ASSERT(rxq != NULL);
 663         SFC_ASSERT(rxq_info->state == SFC_RXQ_INITIALIZED);
 664
 665         evq = rxq->evq;
 666
 667         rc = sfc_ev_qstart(evq, sfc_evq_index_by_rxq_sw_index(sa, sw_index));
 668         if (rc != 0)
 669                 goto fail_ev_qstart;
 670
 671         switch (rxq_info->type) {
 672         case EFX_RXQ_TYPE_DEFAULT:
 673                 rc = efx_rx_qcreate(sa->nic, rxq->hw_index, 0, rxq_info->type,
 674                         &rxq->mem, rxq_info->entries, 0 /* not used on EF10 */,
 675                         rxq_info->type_flags, evq->common, &rxq->common);
 676                 break;
 677         case EFX_RXQ_TYPE_ES_SUPER_BUFFER: {
 678                 struct rte_mempool *mp = rxq_info->refill_mb_pool;
 679                 struct rte_mempool_info mp_info;
 680
 681                 rc = rte_mempool_ops_get_info(mp, &mp_info);
 682                 if (rc != 0) {
 683                         /* Positive errno is used in the driver */
 684                         rc = -rc;
 685                         goto fail_mp_get_info;
 686                 }
 687                 if (mp_info.contig_block_size <= 0) {
 688                         rc = EINVAL;
 689                         goto fail_bad_contig_block_size;
 690                 }
 691                 rc = efx_rx_qcreate_es_super_buffer(sa->nic, rxq->hw_index, 0,
 692                         mp_info.contig_block_size, rxq->buf_size,
 693                         mp->header_size + mp->elt_size + mp->trailer_size,
 694                         sa->rxd_wait_timeout_ns,
 695                         &rxq->mem, rxq_info->entries, rxq_info->type_flags,
 696                         evq->common, &rxq->common);
 697                 break;
 698         }
 699         default:
 700                 rc = ENOTSUP;
 701         }
 702         if (rc != 0)
 703                 goto fail_rx_qcreate;
 704
 705         efx_rx_qenable(rxq->common);
 706
 707         rc = sa->priv.dp_rx->qstart(rxq_info->dp, evq->read_ptr);
 708         if (rc != 0)
 709                 goto fail_dp_qstart;
 710
 711         rxq_info->state |= SFC_RXQ_STARTED;
 712
 713         if ((sw_index == 0) && !port->isolated) {
 714                 rc = sfc_rx_default_rxq_set_filter(sa, rxq);
 715                 if (rc != 0)
 716                         goto fail_mac_filter_default_rxq_set;
 717         }
 718
 719         /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
 720         sa->eth_dev->data->rx_queue_state[sw_index] =
 721                 RTE_ETH_QUEUE_STATE_STARTED;
 722
 723         return 0;
 724
 725 fail_mac_filter_default_rxq_set:
 726         sa->priv.dp_rx->qstop(rxq_info->dp, &rxq->evq->read_ptr);
 727
 728 fail_dp_qstart:
 729         sfc_rx_qflush(sa, sw_index);
 730
 731 fail_rx_qcreate:
 732 fail_bad_contig_block_size:
 733 fail_mp_get_info:
 734         sfc_ev_qstop(evq);
 735
 736 fail_ev_qstart:
 737         return rc;
 738 }
 739
 740 void
 741 sfc_rx_qstop(struct sfc_adapter *sa, unsigned int sw_index)
 742 {
 743         struct sfc_rxq_info *rxq_info;
 744         struct sfc_rxq *rxq;
 745
 746         sfc_log_init(sa, "sw_index=%u", sw_index);
 747
 748         SFC_ASSERT(sw_index < sa->rxq_count);
 749
 750         rxq_info = &sa->rxq_info[sw_index];
 751         rxq = rxq_info->rxq;
 752
 753         if (rxq == NULL || rxq_info->state == SFC_RXQ_INITIALIZED)
 754                 return;
 755         SFC_ASSERT(rxq_info->state & SFC_RXQ_STARTED);
 756
 757         /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
 758         sa->eth_dev->data->rx_queue_state[sw_index] =
 759                 RTE_ETH_QUEUE_STATE_STOPPED;
 760
 761         sa->priv.dp_rx->qstop(rxq_info->dp, &rxq->evq->read_ptr);
 762
 763         if (sw_index == 0)
 764                 efx_mac_filter_default_rxq_clear(sa->nic);
 765
 766         sfc_rx_qflush(sa, sw_index);
 767
 768         rxq_info->state = SFC_RXQ_INITIALIZED;
 769
 770         efx_rx_qdestroy(rxq->common);
 771
 772         sfc_ev_qstop(rxq->evq);
 773 }
 774
 775 uint64_t
 776 sfc_rx_get_dev_offload_caps(struct sfc_adapter *sa)
 777 {
 778         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
 779         uint64_t caps = 0;
 780
 781         caps |= DEV_RX_OFFLOAD_JUMBO_FRAME;
 782
 783         if (sa->priv.dp_rx->features & SFC_DP_RX_FEAT_CHECKSUM) {
 784                 caps |= DEV_RX_OFFLOAD_IPV4_CKSUM;
 785                 caps |= DEV_RX_OFFLOAD_UDP_CKSUM;
 786                 caps |= DEV_RX_OFFLOAD_TCP_CKSUM;
 787         }
 788
 789         if (encp->enc_tunnel_encapsulations_supported &&
 790             (sa->priv.dp_rx->features & SFC_DP_RX_FEAT_TUNNELS))
 791                 caps |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
 792
 793         return caps;
 794 }
 795
 796 uint64_t
 797 sfc_rx_get_queue_offload_caps(struct sfc_adapter *sa)
 798 {
 799         uint64_t caps = 0;
 800
 801         if (sa->priv.dp_rx->features & SFC_DP_RX_FEAT_SCATTER)
 802                 caps |= DEV_RX_OFFLOAD_SCATTER;
 803
 804         return caps;
 805 }
 806
 807 static int
 808 sfc_rx_qcheck_conf(struct sfc_adapter *sa, unsigned int rxq_max_fill_level,
 809                    const struct rte_eth_rxconf *rx_conf,
 810                    __rte_unused uint64_t offloads)
 811 {
 812         int rc = 0;
 813
 814         if (rx_conf->rx_thresh.pthresh != 0 ||
 815             rx_conf->rx_thresh.hthresh != 0 ||
 816             rx_conf->rx_thresh.wthresh != 0) {
 817                 sfc_warn(sa,
 818                         "RxQ prefetch/host/writeback thresholds are not supported");
 819         }
 820
 821         if (rx_conf->rx_free_thresh > rxq_max_fill_level) {
 822                 sfc_err(sa,
 823                         "RxQ free threshold too large: %u vs maximum %u",
 824                         rx_conf->rx_free_thresh, rxq_max_fill_level);
 825                 rc = EINVAL;
 826         }
 827
 828         if (rx_conf->rx_drop_en == 0) {
 829                 sfc_err(sa, "RxQ drop disable is not supported");
 830                 rc = EINVAL;
 831         }
 832
 833         return rc;
 834 }
 835
 836 static unsigned int
 837 sfc_rx_mbuf_data_alignment(struct rte_mempool *mb_pool)
 838 {
 839         uint32_t data_off;
 840         uint32_t order;
 841
 842         /* The mbuf object itself is always cache line aligned */
 843         order = rte_bsf32(RTE_CACHE_LINE_SIZE);
 844
 845         /* Data offset from mbuf object start */
 846         data_off = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(mb_pool) +
 847                 RTE_PKTMBUF_HEADROOM;
 848
 849         order = MIN(order, rte_bsf32(data_off));
 850
 851         return 1u << order;
 852 }
 853
 854 static uint16_t
 855 sfc_rx_mb_pool_buf_size(struct sfc_adapter *sa, struct rte_mempool *mb_pool)
 856 {
 857         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
 858         const uint32_t nic_align_start = MAX(1, encp->enc_rx_buf_align_start);
 859         const uint32_t nic_align_end = MAX(1, encp->enc_rx_buf_align_end);
 860         uint16_t buf_size;
 861         unsigned int buf_aligned;
 862         unsigned int start_alignment;
 863         unsigned int end_padding_alignment;
 864
 865         /* Below it is assumed that both alignments are power of 2 */
 866         SFC_ASSERT(rte_is_power_of_2(nic_align_start));
 867         SFC_ASSERT(rte_is_power_of_2(nic_align_end));
 868
 869         /*
 870          * mbuf is always cache line aligned, double-check
 871          * that it meets rx buffer start alignment requirements.
 872          */
 873
 874         /* Start from mbuf pool data room size */
 875         buf_size = rte_pktmbuf_data_room_size(mb_pool);
 876
 877         /* Remove headroom */
 878         if (buf_size <= RTE_PKTMBUF_HEADROOM) {
 879                 sfc_err(sa,
 880                         "RxQ mbuf pool %s object data room size %u is smaller than headroom %u",
 881                         mb_pool->name, buf_size, RTE_PKTMBUF_HEADROOM);
 882                 return 0;
 883         }
 884         buf_size -= RTE_PKTMBUF_HEADROOM;
 885
 886         /* Calculate guaranteed data start alignment */
 887         buf_aligned = sfc_rx_mbuf_data_alignment(mb_pool);
 888
 889         /* Reserve space for start alignment */
 890         if (buf_aligned < nic_align_start) {
 891                 start_alignment = nic_align_start - buf_aligned;
 892                 if (buf_size <= start_alignment) {
 893                         sfc_err(sa,
 894                                 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u and buffer start alignment %u required by NIC",
 895                                 mb_pool->name,
 896                                 rte_pktmbuf_data_room_size(mb_pool),
 897                                 RTE_PKTMBUF_HEADROOM, start_alignment);
 898                         return 0;
 899                 }
 900                 buf_aligned = nic_align_start;
 901                 buf_size -= start_alignment;
 902         } else {
 903                 start_alignment = 0;
 904         }
 905
 906         /* Make sure that end padding does not write beyond the buffer */
 907         if (buf_aligned < nic_align_end) {
 908                 /*
 909                  * Estimate space which can be lost. If guarnteed buffer
 910                  * size is odd, lost space is (nic_align_end - 1). More
 911                  * accurate formula is below.
 912                  */
 913                 end_padding_alignment = nic_align_end -
 914                         MIN(buf_aligned, 1u << (rte_bsf32(buf_size) - 1));
 915                 if (buf_size <= end_padding_alignment) {
 916                         sfc_err(sa,
 917                                 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u, buffer start alignment %u and end padding alignment %u required by NIC",
 918                                 mb_pool->name,
 919                                 rte_pktmbuf_data_room_size(mb_pool),
 920                                 RTE_PKTMBUF_HEADROOM, start_alignment,
 921                                 end_padding_alignment);
 922                         return 0;
 923                 }
 924                 buf_size -= end_padding_alignment;
 925         } else {
 926                 /*
 927                  * Start is aligned the same or better than end,
 928                  * just align length.
 929                  */
 930                 buf_size = P2ALIGN(buf_size, nic_align_end);
 931         }
 932
 933         return buf_size;
 934 }
 935
 936 int
 937 sfc_rx_qinit(struct sfc_adapter *sa, unsigned int sw_index,
 938              uint16_t nb_rx_desc, unsigned int socket_id,
 939              const struct rte_eth_rxconf *rx_conf,
 940              struct rte_mempool *mb_pool)
 941 {
 942         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
 943         struct sfc_rss *rss = &sa->rss;
 944         int rc;
 945         unsigned int rxq_entries;
 946         unsigned int evq_entries;
 947         unsigned int rxq_max_fill_level;
 948         uint64_t offloads;
 949         uint16_t buf_size;
 950         struct sfc_rxq_info *rxq_info;
 951         struct sfc_evq *evq;
 952         struct sfc_rxq *rxq;
 953         struct sfc_dp_rx_qcreate_info info;
 954
 955         rc = sa->priv.dp_rx->qsize_up_rings(nb_rx_desc, mb_pool, &rxq_entries,
 956                                             &evq_entries, &rxq_max_fill_level);
 957         if (rc != 0)
 958                 goto fail_size_up_rings;
 959         SFC_ASSERT(rxq_entries >= EFX_RXQ_MINNDESCS);
 960         SFC_ASSERT(rxq_entries <= EFX_RXQ_MAXNDESCS);
 961         SFC_ASSERT(rxq_max_fill_level <= nb_rx_desc);
 962
 963         offloads = rx_conf->offloads |
 964                 sa->eth_dev->data->dev_conf.rxmode.offloads;
 965         rc = sfc_rx_qcheck_conf(sa, rxq_max_fill_level, rx_conf, offloads);
 966         if (rc != 0)
 967                 goto fail_bad_conf;
 968
 969         buf_size = sfc_rx_mb_pool_buf_size(sa, mb_pool);
 970         if (buf_size == 0) {
 971                 sfc_err(sa, "RxQ %u mbuf pool object size is too small",
 972                         sw_index);
 973                 rc = EINVAL;
 974                 goto fail_bad_conf;
 975         }
 976
 977         if ((buf_size < sa->port.pdu + encp->enc_rx_prefix_size) &&
 978             (~offloads & DEV_RX_OFFLOAD_SCATTER)) {
 979                 sfc_err(sa, "Rx scatter is disabled and RxQ %u mbuf pool "
 980                         "object size is too small", sw_index);
 981                 sfc_err(sa, "RxQ %u calculated Rx buffer size is %u vs "
 982                         "PDU size %u plus Rx prefix %u bytes",
 983                         sw_index, buf_size, (unsigned int)sa->port.pdu,
 984                         encp->enc_rx_prefix_size);
 985                 rc = EINVAL;
 986                 goto fail_bad_conf;
 987         }
 988
 989         SFC_ASSERT(sw_index < sa->rxq_count);
 990         rxq_info = &sa->rxq_info[sw_index];
 991
 992         SFC_ASSERT(rxq_entries <= rxq_info->max_entries);
 993         rxq_info->entries = rxq_entries;
 994
 995         if (sa->priv.dp_rx->dp.hw_fw_caps & SFC_DP_HW_FW_CAP_RX_ES_SUPER_BUFFER)
 996                 rxq_info->type = EFX_RXQ_TYPE_ES_SUPER_BUFFER;
 997         else
 998                 rxq_info->type = EFX_RXQ_TYPE_DEFAULT;
 999
1000         rxq_info->type_flags =
1001                 (offloads & DEV_RX_OFFLOAD_SCATTER) ?
1002                 EFX_RXQ_FLAG_SCATTER : EFX_RXQ_FLAG_NONE;
1003
1004         if ((encp->enc_tunnel_encapsulations_supported != 0) &&
1005             (sa->priv.dp_rx->features & SFC_DP_RX_FEAT_TUNNELS))
1006                 rxq_info->type_flags |= EFX_RXQ_FLAG_INNER_CLASSES;
1007
1008         rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_RX, sw_index,
1009                           evq_entries, socket_id, &evq);
1010         if (rc != 0)
1011                 goto fail_ev_qinit;
1012
1013         rc = ENOMEM;
1014         rxq = rte_zmalloc_socket("sfc-rxq", sizeof(*rxq), RTE_CACHE_LINE_SIZE,
1015                                  socket_id);
1016         if (rxq == NULL)
1017                 goto fail_rxq_alloc;
1018
1019         rxq_info->rxq = rxq;
1020
1021         rxq->evq = evq;
1022         rxq->hw_index = sw_index;
1023         rxq_info->refill_threshold =
1024                 RTE_MAX(rx_conf->rx_free_thresh, SFC_RX_REFILL_BULK);
1025         rxq_info->refill_mb_pool = mb_pool;
1026         rxq->buf_size = buf_size;
1027
1028         rc = sfc_dma_alloc(sa, "rxq", sw_index, EFX_RXQ_SIZE(rxq_info->entries),
1029                            socket_id, &rxq->mem);
1030         if (rc != 0)
1031                 goto fail_dma_alloc;
1032
1033         memset(&info, 0, sizeof(info));
1034         info.refill_mb_pool = rxq_info->refill_mb_pool;
1035         info.max_fill_level = rxq_max_fill_level;
1036         info.refill_threshold = rxq_info->refill_threshold;
1037         info.buf_size = buf_size;
1038         info.batch_max = encp->enc_rx_batch_max;
1039         info.prefix_size = encp->enc_rx_prefix_size;
1040
1041         if (rss->hash_support == EFX_RX_HASH_AVAILABLE && rss->channels > 0)
1042                 info.flags |= SFC_RXQ_FLAG_RSS_HASH;
1043
1044         info.rxq_entries = rxq_info->entries;
1045         info.rxq_hw_ring = rxq->mem.esm_base;
1046         info.evq_entries = evq_entries;
1047         info.evq_hw_ring = evq->mem.esm_base;
1048         info.hw_index = rxq->hw_index;
1049         info.mem_bar = sa->mem_bar.esb_base;
1050         info.vi_window_shift = encp->enc_vi_window_shift;
1051
1052         rc = sa->priv.dp_rx->qcreate(sa->eth_dev->data->port_id, sw_index,
1053                                      &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr,
1054                                      socket_id, &info, &rxq_info->dp);
1055         if (rc != 0)
1056                 goto fail_dp_rx_qcreate;
1057
1058         evq->dp_rxq = rxq_info->dp;
1059
1060         rxq_info->state = SFC_RXQ_INITIALIZED;
1061
1062         rxq_info->deferred_start = (rx_conf->rx_deferred_start != 0);
1063
1064         return 0;
1065
1066 fail_dp_rx_qcreate:
1067         sfc_dma_free(sa, &rxq->mem);
1068
1069 fail_dma_alloc:
1070         rxq_info->rxq = NULL;
1071         rte_free(rxq);
1072
1073 fail_rxq_alloc:
1074         sfc_ev_qfini(evq);
1075
1076 fail_ev_qinit:
1077         rxq_info->entries = 0;
1078
1079 fail_bad_conf:
1080 fail_size_up_rings:
1081         sfc_log_init(sa, "failed %d", rc);
1082         return rc;
1083 }
1084
1085 void
1086 sfc_rx_qfini(struct sfc_adapter *sa, unsigned int sw_index)
1087 {
1088         struct sfc_rxq_info *rxq_info;
1089         struct sfc_rxq *rxq;
1090
1091         SFC_ASSERT(sw_index < sa->rxq_count);
1092         sa->eth_dev->data->rx_queues[sw_index] = NULL;
1093
1094         rxq_info = &sa->rxq_info[sw_index];
1095
1096         rxq = rxq_info->rxq;
1097         SFC_ASSERT(rxq_info->state == SFC_RXQ_INITIALIZED);
1098
1099         sa->priv.dp_rx->qdestroy(rxq_info->dp);
1100         rxq_info->dp = NULL;
1101
1102         rxq_info->rxq = NULL;
1103         rxq_info->entries = 0;
1104
1105         sfc_dma_free(sa, &rxq->mem);
1106
1107         sfc_ev_qfini(rxq->evq);
1108         rxq->evq = NULL;
1109
1110         rte_free(rxq);
1111 }
1112
1113 /*
1114  * Mapping between RTE RSS hash functions and their EFX counterparts.
1115  */
1116 static const struct sfc_rss_hf_rte_to_efx sfc_rss_hf_map[] = {
1117         { ETH_RSS_NONFRAG_IPV4_TCP,
1118           EFX_RX_HASH(IPV4_TCP, 4TUPLE) },
1119         { ETH_RSS_NONFRAG_IPV4_UDP,
1120           EFX_RX_HASH(IPV4_UDP, 4TUPLE) },
1121         { ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_IPV6_TCP_EX,
1122           EFX_RX_HASH(IPV6_TCP, 4TUPLE) },
1123         { ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_UDP_EX,
1124           EFX_RX_HASH(IPV6_UDP, 4TUPLE) },
1125         { ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_OTHER,
1126           EFX_RX_HASH(IPV4_TCP, 2TUPLE) | EFX_RX_HASH(IPV4_UDP, 2TUPLE) |
1127           EFX_RX_HASH(IPV4, 2TUPLE) },
1128         { ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_OTHER |
1129           ETH_RSS_IPV6_EX,
1130           EFX_RX_HASH(IPV6_TCP, 2TUPLE) | EFX_RX_HASH(IPV6_UDP, 2TUPLE) |
1131           EFX_RX_HASH(IPV6, 2TUPLE) }
1132 };
1133
1134 static efx_rx_hash_type_t
1135 sfc_rx_hash_types_mask_supp(efx_rx_hash_type_t hash_type,
1136                             unsigned int *hash_type_flags_supported,
1137                             unsigned int nb_hash_type_flags_supported)
1138 {
1139         efx_rx_hash_type_t hash_type_masked = 0;
1140         unsigned int i, j;
1141
1142         for (i = 0; i < nb_hash_type_flags_supported; ++i) {
1143                 unsigned int class_tuple_lbn[] = {
1144                         EFX_RX_CLASS_IPV4_TCP_LBN,
1145                         EFX_RX_CLASS_IPV4_UDP_LBN,
1146                         EFX_RX_CLASS_IPV4_LBN,
1147                         EFX_RX_CLASS_IPV6_TCP_LBN,
1148                         EFX_RX_CLASS_IPV6_UDP_LBN,
1149                         EFX_RX_CLASS_IPV6_LBN
1150                 };
1151
1152                 for (j = 0; j < RTE_DIM(class_tuple_lbn); ++j) {
1153                         unsigned int tuple_mask = EFX_RX_CLASS_HASH_4TUPLE;
1154                         unsigned int flag;
1155
1156                         tuple_mask <<= class_tuple_lbn[j];
1157                         flag = hash_type & tuple_mask;
1158
1159                         if (flag == hash_type_flags_supported[i])
1160                                 hash_type_masked |= flag;
1161                 }
1162         }
1163
1164         return hash_type_masked;
1165 }
1166
1167 int
1168 sfc_rx_hash_init(struct sfc_adapter *sa)
1169 {
1170         struct sfc_rss *rss = &sa->rss;
1171         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1172         uint32_t alg_mask = encp->enc_rx_scale_hash_alg_mask;
1173         efx_rx_hash_alg_t alg;
1174         unsigned int flags_supp[EFX_RX_HASH_NFLAGS];
1175         unsigned int nb_flags_supp;
1176         struct sfc_rss_hf_rte_to_efx *hf_map;
1177         struct sfc_rss_hf_rte_to_efx *entry;
1178         efx_rx_hash_type_t efx_hash_types;
1179         unsigned int i;
1180         int rc;
1181
1182         if (alg_mask & (1U << EFX_RX_HASHALG_TOEPLITZ))
1183                 alg = EFX_RX_HASHALG_TOEPLITZ;
1184         else if (alg_mask & (1U << EFX_RX_HASHALG_PACKED_STREAM))
1185                 alg = EFX_RX_HASHALG_PACKED_STREAM;
1186         else
1187                 return EINVAL;
1188
1189         rc = efx_rx_scale_hash_flags_get(sa->nic, alg, flags_supp,
1190                                          RTE_DIM(flags_supp), &nb_flags_supp);
1191         if (rc != 0)
1192                 return rc;
1193
1194         hf_map = rte_calloc_socket("sfc-rss-hf-map",
1195                                    RTE_DIM(sfc_rss_hf_map),
1196                                    sizeof(*hf_map), 0, sa->socket_id);
1197         if (hf_map == NULL)
1198                 return ENOMEM;
1199
1200         entry = hf_map;
1201         efx_hash_types = 0;
1202         for (i = 0; i < RTE_DIM(sfc_rss_hf_map); ++i) {
1203                 efx_rx_hash_type_t ht;
1204
1205                 ht = sfc_rx_hash_types_mask_supp(sfc_rss_hf_map[i].efx,
1206                                                  flags_supp, nb_flags_supp);
1207                 if (ht != 0) {
1208                         entry->rte = sfc_rss_hf_map[i].rte;
1209                         entry->efx = ht;
1210                         efx_hash_types |= ht;
1211                         ++entry;
1212                 }
1213         }
1214
1215         rss->hash_alg = alg;
1216         rss->hf_map_nb_entries = (unsigned int)(entry - hf_map);
1217         rss->hf_map = hf_map;
1218         rss->hash_types = efx_hash_types;
1219
1220         return 0;
1221 }
1222
1223 void
1224 sfc_rx_hash_fini(struct sfc_adapter *sa)
1225 {
1226         struct sfc_rss *rss = &sa->rss;
1227
1228         rte_free(rss->hf_map);
1229 }
1230
1231 int
1232 sfc_rx_hf_rte_to_efx(struct sfc_adapter *sa, uint64_t rte,
1233                      efx_rx_hash_type_t *efx)
1234 {
1235         struct sfc_rss *rss = &sa->rss;
1236         efx_rx_hash_type_t hash_types = 0;
1237         unsigned int i;
1238
1239         for (i = 0; i < rss->hf_map_nb_entries; ++i) {
1240                 uint64_t rte_mask = rss->hf_map[i].rte;
1241
1242                 if ((rte & rte_mask) != 0) {
1243                         rte &= ~rte_mask;
1244                         hash_types |= rss->hf_map[i].efx;
1245                 }
1246         }
1247
1248         if (rte != 0) {
1249                 sfc_err(sa, "unsupported hash functions requested");
1250                 return EINVAL;
1251         }
1252
1253         *efx = hash_types;
1254
1255         return 0;
1256 }
1257
1258 uint64_t
1259 sfc_rx_hf_efx_to_rte(struct sfc_adapter *sa, efx_rx_hash_type_t efx)
1260 {
1261         struct sfc_rss *rss = &sa->rss;
1262         uint64_t rte = 0;
1263         unsigned int i;
1264
1265         for (i = 0; i < rss->hf_map_nb_entries; ++i) {
1266                 efx_rx_hash_type_t hash_type = rss->hf_map[i].efx;
1267
1268                 if ((efx & hash_type) == hash_type)
1269                         rte |= rss->hf_map[i].rte;
1270         }
1271
1272         return rte;
1273 }
1274
1275 static int
1276 sfc_rx_process_adv_conf_rss(struct sfc_adapter *sa,
1277                             struct rte_eth_rss_conf *conf)
1278 {
1279         struct sfc_rss *rss = &sa->rss;
1280         efx_rx_hash_type_t efx_hash_types = rss->hash_types;
1281         uint64_t rss_hf = sfc_rx_hf_efx_to_rte(sa, efx_hash_types);
1282         int rc;
1283
1284         if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) {
1285                 if ((conf->rss_hf != 0 && conf->rss_hf != rss_hf) ||
1286                     conf->rss_key != NULL)
1287                         return EINVAL;
1288         }
1289
1290         if (conf->rss_hf != 0) {
1291                 rc = sfc_rx_hf_rte_to_efx(sa, conf->rss_hf, &efx_hash_types);
1292                 if (rc != 0)
1293                         return rc;
1294         }
1295
1296         if (conf->rss_key != NULL) {
1297                 if (conf->rss_key_len != sizeof(rss->key)) {
1298                         sfc_err(sa, "RSS key size is wrong (should be %lu)",
1299                                 sizeof(rss->key));
1300                         return EINVAL;
1301                 }
1302                 rte_memcpy(rss->key, conf->rss_key, sizeof(rss->key));
1303         }
1304
1305         rss->hash_types = efx_hash_types;
1306
1307         return 0;
1308 }
1309
1310 static int
1311 sfc_rx_rss_config(struct sfc_adapter *sa)
1312 {
1313         struct sfc_rss *rss = &sa->rss;
1314         int rc = 0;
1315
1316         if (rss->channels > 0) {
1317                 rc = efx_rx_scale_mode_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1318                                            rss->hash_alg, rss->hash_types,
1319                                            B_TRUE);
1320                 if (rc != 0)
1321                         goto finish;
1322
1323                 rc = efx_rx_scale_key_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1324                                           rss->key, sizeof(rss->key));
1325                 if (rc != 0)
1326                         goto finish;
1327
1328                 rc = efx_rx_scale_tbl_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1329                                           rss->tbl, RTE_DIM(rss->tbl));
1330         }
1331
1332 finish:
1333         return rc;
1334 }
1335
1336 int
1337 sfc_rx_start(struct sfc_adapter *sa)
1338 {
1339         unsigned int sw_index;
1340         int rc;
1341
1342         sfc_log_init(sa, "rxq_count=%u", sa->rxq_count);
1343
1344         rc = efx_rx_init(sa->nic);
1345         if (rc != 0)
1346                 goto fail_rx_init;
1347
1348         rc = sfc_rx_rss_config(sa);
1349         if (rc != 0)
1350                 goto fail_rss_config;
1351
1352         for (sw_index = 0; sw_index < sa->rxq_count; ++sw_index) {
1353                 if (sa->rxq_info[sw_index].rxq != NULL &&
1354                     (!sa->rxq_info[sw_index].deferred_start ||
1355                      sa->rxq_info[sw_index].deferred_started)) {
1356                         rc = sfc_rx_qstart(sa, sw_index);
1357                         if (rc != 0)
1358                                 goto fail_rx_qstart;
1359                 }
1360         }
1361
1362         return 0;
1363
1364 fail_rx_qstart:
1365         while (sw_index-- > 0)
1366                 sfc_rx_qstop(sa, sw_index);
1367
1368 fail_rss_config:
1369         efx_rx_fini(sa->nic);
1370
1371 fail_rx_init:
1372         sfc_log_init(sa, "failed %d", rc);
1373         return rc;
1374 }
1375
1376 void
1377 sfc_rx_stop(struct sfc_adapter *sa)
1378 {
1379         unsigned int sw_index;
1380
1381         sfc_log_init(sa, "rxq_count=%u", sa->rxq_count);
1382
1383         sw_index = sa->rxq_count;
1384         while (sw_index-- > 0) {
1385                 if (sa->rxq_info[sw_index].rxq != NULL)
1386                         sfc_rx_qstop(sa, sw_index);
1387         }
1388
1389         efx_rx_fini(sa->nic);
1390 }
1391
1392 static int
1393 sfc_rx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index)
1394 {
1395         struct sfc_rxq_info *rxq_info = &sa->rxq_info[sw_index];
1396         unsigned int max_entries;
1397
1398         max_entries = EFX_RXQ_MAXNDESCS;
1399         SFC_ASSERT(rte_is_power_of_2(max_entries));
1400
1401         rxq_info->max_entries = max_entries;
1402
1403         return 0;
1404 }
1405
1406 static int
1407 sfc_rx_check_mode(struct sfc_adapter *sa, struct rte_eth_rxmode *rxmode)
1408 {
1409         uint64_t offloads_supported = sfc_rx_get_dev_offload_caps(sa) |
1410                                       sfc_rx_get_queue_offload_caps(sa);
1411         struct sfc_rss *rss = &sa->rss;
1412         int rc = 0;
1413
1414         switch (rxmode->mq_mode) {
1415         case ETH_MQ_RX_NONE:
1416                 /* No special checks are required */
1417                 break;
1418         case ETH_MQ_RX_RSS:
1419                 if (rss->context_type == EFX_RX_SCALE_UNAVAILABLE) {
1420                         sfc_err(sa, "RSS is not available");
1421                         rc = EINVAL;
1422                 }
1423                 break;
1424         default:
1425                 sfc_err(sa, "Rx multi-queue mode %u not supported",
1426                         rxmode->mq_mode);
1427                 rc = EINVAL;
1428         }
1429
1430         /*
1431          * Requested offloads are validated against supported by ethdev,
1432          * so unsupported offloads cannot be added as the result of
1433          * below check.
1434          */
1435         if ((rxmode->offloads & DEV_RX_OFFLOAD_CHECKSUM) !=
1436             (offloads_supported & DEV_RX_OFFLOAD_CHECKSUM)) {
1437                 sfc_warn(sa, "Rx checksum offloads cannot be disabled - always on (IPv4/TCP/UDP)");
1438                 rxmode->offloads |= DEV_RX_OFFLOAD_CHECKSUM;
1439         }
1440
1441         if ((offloads_supported & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) &&
1442             (~rxmode->offloads & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM)) {
1443                 sfc_warn(sa, "Rx outer IPv4 checksum offload cannot be disabled - always on");
1444                 rxmode->offloads |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
1445         }
1446
1447         return rc;
1448 }
1449
1450 /**
1451  * Destroy excess queues that are no longer needed after reconfiguration
1452  * or complete close.
1453  */
1454 static void
1455 sfc_rx_fini_queues(struct sfc_adapter *sa, unsigned int nb_rx_queues)
1456 {
1457         int sw_index;
1458
1459         SFC_ASSERT(nb_rx_queues <= sa->rxq_count);
1460
1461         sw_index = sa->rxq_count;
1462         while (--sw_index >= (int)nb_rx_queues) {
1463                 if (sa->rxq_info[sw_index].rxq != NULL)
1464                         sfc_rx_qfini(sa, sw_index);
1465         }
1466
1467         sa->rxq_count = nb_rx_queues;
1468 }
1469
1470 /**
1471  * Initialize Rx subsystem.
1472  *
1473  * Called at device (re)configuration stage when number of receive queues is
1474  * specified together with other device level receive configuration.
1475  *
1476  * It should be used to allocate NUMA-unaware resources.
1477  */
1478 int
1479 sfc_rx_configure(struct sfc_adapter *sa)
1480 {
1481         struct sfc_rss *rss = &sa->rss;
1482         struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
1483         const unsigned int nb_rx_queues = sa->eth_dev->data->nb_rx_queues;
1484         int rc;
1485
1486         sfc_log_init(sa, "nb_rx_queues=%u (old %u)",
1487                      nb_rx_queues, sa->rxq_count);
1488
1489         rc = sfc_rx_check_mode(sa, &dev_conf->rxmode);
1490         if (rc != 0)
1491                 goto fail_check_mode;
1492
1493         if (nb_rx_queues == sa->rxq_count)
1494                 goto configure_rss;
1495
1496         if (sa->rxq_info == NULL) {
1497                 rc = ENOMEM;
1498                 sa->rxq_info = rte_calloc_socket("sfc-rxqs", nb_rx_queues,
1499                                                  sizeof(sa->rxq_info[0]), 0,
1500                                                  sa->socket_id);
1501                 if (sa->rxq_info == NULL)
1502                         goto fail_rxqs_alloc;
1503         } else {
1504                 struct sfc_rxq_info *new_rxq_info;
1505
1506                 if (nb_rx_queues < sa->rxq_count)
1507                         sfc_rx_fini_queues(sa, nb_rx_queues);
1508
1509                 rc = ENOMEM;
1510                 new_rxq_info =
1511                         rte_realloc(sa->rxq_info,
1512                                     nb_rx_queues * sizeof(sa->rxq_info[0]), 0);
1513                 if (new_rxq_info == NULL && nb_rx_queues > 0)
1514                         goto fail_rxqs_realloc;
1515
1516                 sa->rxq_info = new_rxq_info;
1517                 if (nb_rx_queues > sa->rxq_count)
1518                         memset(&sa->rxq_info[sa->rxq_count], 0,
1519                                (nb_rx_queues - sa->rxq_count) *
1520                                sizeof(sa->rxq_info[0]));
1521         }
1522
1523         while (sa->rxq_count < nb_rx_queues) {
1524                 rc = sfc_rx_qinit_info(sa, sa->rxq_count);
1525                 if (rc != 0)
1526                         goto fail_rx_qinit_info;
1527
1528                 sa->rxq_count++;
1529         }
1530
1531 configure_rss:
1532         rss->channels = (dev_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) ?
1533                          MIN(sa->rxq_count, EFX_MAXRSS) : 0;
1534
1535         if (rss->channels > 0) {
1536                 struct rte_eth_rss_conf *adv_conf_rss;
1537                 unsigned int sw_index;
1538
1539                 for (sw_index = 0; sw_index < EFX_RSS_TBL_SIZE; ++sw_index)
1540                         rss->tbl[sw_index] = sw_index % rss->channels;
1541
1542                 adv_conf_rss = &dev_conf->rx_adv_conf.rss_conf;
1543                 rc = sfc_rx_process_adv_conf_rss(sa, adv_conf_rss);
1544                 if (rc != 0)
1545                         goto fail_rx_process_adv_conf_rss;
1546         }
1547
1548         return 0;
1549
1550 fail_rx_process_adv_conf_rss:
1551 fail_rx_qinit_info:
1552 fail_rxqs_realloc:
1553 fail_rxqs_alloc:
1554         sfc_rx_close(sa);
1555
1556 fail_check_mode:
1557         sfc_log_init(sa, "failed %d", rc);
1558         return rc;
1559 }
1560
1561 /**
1562  * Shutdown Rx subsystem.
1563  *
1564  * Called at device close stage, for example, before device shutdown.
1565  */
1566 void
1567 sfc_rx_close(struct sfc_adapter *sa)
1568 {
1569         struct sfc_rss *rss = &sa->rss;
1570
1571         sfc_rx_fini_queues(sa, 0);
1572
1573         rss->channels = 0;
1574
1575         rte_free(sa->rxq_info);
1576         sa->rxq_info = NULL;
1577 }