drivers/net/sfc/sfc_rx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2016-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  *
   6  * This software was jointly developed between OKTET Labs (under contract
   7  * for Solarflare) and Solarflare Communications, Inc.
   8  */
   9
  10 #include <rte_mempool.h>
  11
  12 #include "efx.h"
  13
  14 #include "sfc.h"
  15 #include "sfc_debug.h"
  16 #include "sfc_log.h"
  17 #include "sfc_ev.h"
  18 #include "sfc_rx.h"
  19 #include "sfc_kvargs.h"
  20 #include "sfc_tweak.h"
  21
  22 /*
  23  * Maximum number of Rx queue flush attempt in the case of failure or
  24  * flush timeout
  25  */
  26 #define SFC_RX_QFLUSH_ATTEMPTS          (3)
  27
  28 /*
  29  * Time to wait between event queue polling attempts when waiting for Rx
  30  * queue flush done or failed events.
  31  */
  32 #define SFC_RX_QFLUSH_POLL_WAIT_MS      (1)
  33
  34 /*
  35  * Maximum number of event queue polling attempts when waiting for Rx queue
  36  * flush done or failed events. It defines Rx queue flush attempt timeout
  37  * together with SFC_RX_QFLUSH_POLL_WAIT_MS.
  38  */
  39 #define SFC_RX_QFLUSH_POLL_ATTEMPTS     (2000)
  40
  41 void
  42 sfc_rx_qflush_done(struct sfc_rxq *rxq)
  43 {
  44         rxq->state |= SFC_RXQ_FLUSHED;
  45         rxq->state &= ~SFC_RXQ_FLUSHING;
  46 }
  47
  48 void
  49 sfc_rx_qflush_failed(struct sfc_rxq *rxq)
  50 {
  51         rxq->state |= SFC_RXQ_FLUSH_FAILED;
  52         rxq->state &= ~SFC_RXQ_FLUSHING;
  53 }
  54
  55 static void
  56 sfc_efx_rx_qrefill(struct sfc_efx_rxq *rxq)
  57 {
  58         unsigned int free_space;
  59         unsigned int bulks;
  60         void *objs[SFC_RX_REFILL_BULK];
  61         efsys_dma_addr_t addr[RTE_DIM(objs)];
  62         unsigned int added = rxq->added;
  63         unsigned int id;
  64         unsigned int i;
  65         struct sfc_efx_rx_sw_desc *rxd;
  66         struct rte_mbuf *m;
  67         uint16_t port_id = rxq->dp.dpq.port_id;
  68
  69         free_space = rxq->max_fill_level - (added - rxq->completed);
  70
  71         if (free_space < rxq->refill_threshold)
  72                 return;
  73
  74         bulks = free_space / RTE_DIM(objs);
  75         /* refill_threshold guarantees that bulks is positive */
  76         SFC_ASSERT(bulks > 0);
  77
  78         id = added & rxq->ptr_mask;
  79         do {
  80                 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs,
  81                                                   RTE_DIM(objs)) < 0)) {
  82                         /*
  83                          * It is hardly a safe way to increment counter
  84                          * from different contexts, but all PMDs do it.
  85                          */
  86                         rxq->evq->sa->eth_dev->data->rx_mbuf_alloc_failed +=
  87                                 RTE_DIM(objs);
  88                         /* Return if we have posted nothing yet */
  89                         if (added == rxq->added)
  90                                 return;
  91                         /* Push posted */
  92                         break;
  93                 }
  94
  95                 for (i = 0; i < RTE_DIM(objs);
  96                      ++i, id = (id + 1) & rxq->ptr_mask) {
  97                         m = objs[i];
  98
  99                         rxd = &rxq->sw_desc[id];
 100                         rxd->mbuf = m;
 101
 102                         SFC_ASSERT(rte_mbuf_refcnt_read(m) == 1);
 103                         m->data_off = RTE_PKTMBUF_HEADROOM;
 104                         SFC_ASSERT(m->next == NULL);
 105                         SFC_ASSERT(m->nb_segs == 1);
 106                         m->port = port_id;
 107
 108                         addr[i] = rte_pktmbuf_iova(m);
 109                 }
 110
 111                 efx_rx_qpost(rxq->common, addr, rxq->buf_size,
 112                              RTE_DIM(objs), rxq->completed, added);
 113                 added += RTE_DIM(objs);
 114         } while (--bulks > 0);
 115
 116         SFC_ASSERT(added != rxq->added);
 117         rxq->added = added;
 118         efx_rx_qpush(rxq->common, added, &rxq->pushed);
 119 }
 120
 121 static uint64_t
 122 sfc_efx_rx_desc_flags_to_offload_flags(const unsigned int desc_flags)
 123 {
 124         uint64_t mbuf_flags = 0;
 125
 126         switch (desc_flags & (EFX_PKT_IPV4 | EFX_CKSUM_IPV4)) {
 127         case (EFX_PKT_IPV4 | EFX_CKSUM_IPV4):
 128                 mbuf_flags |= PKT_RX_IP_CKSUM_GOOD;
 129                 break;
 130         case EFX_PKT_IPV4:
 131                 mbuf_flags |= PKT_RX_IP_CKSUM_BAD;
 132                 break;
 133         default:
 134                 RTE_BUILD_BUG_ON(PKT_RX_IP_CKSUM_UNKNOWN != 0);
 135                 SFC_ASSERT((mbuf_flags & PKT_RX_IP_CKSUM_MASK) ==
 136                            PKT_RX_IP_CKSUM_UNKNOWN);
 137                 break;
 138         }
 139
 140         switch ((desc_flags &
 141                  (EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP))) {
 142         case (EFX_PKT_TCP | EFX_CKSUM_TCPUDP):
 143         case (EFX_PKT_UDP | EFX_CKSUM_TCPUDP):
 144                 mbuf_flags |= PKT_RX_L4_CKSUM_GOOD;
 145                 break;
 146         case EFX_PKT_TCP:
 147         case EFX_PKT_UDP:
 148                 mbuf_flags |= PKT_RX_L4_CKSUM_BAD;
 149                 break;
 150         default:
 151                 RTE_BUILD_BUG_ON(PKT_RX_L4_CKSUM_UNKNOWN != 0);
 152                 SFC_ASSERT((mbuf_flags & PKT_RX_L4_CKSUM_MASK) ==
 153                            PKT_RX_L4_CKSUM_UNKNOWN);
 154                 break;
 155         }
 156
 157         return mbuf_flags;
 158 }
 159
 160 static uint32_t
 161 sfc_efx_rx_desc_flags_to_packet_type(const unsigned int desc_flags)
 162 {
 163         return RTE_PTYPE_L2_ETHER |
 164                 ((desc_flags & EFX_PKT_IPV4) ?
 165                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN : 0) |
 166                 ((desc_flags & EFX_PKT_IPV6) ?
 167                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN : 0) |
 168                 ((desc_flags & EFX_PKT_TCP) ? RTE_PTYPE_L4_TCP : 0) |
 169                 ((desc_flags & EFX_PKT_UDP) ? RTE_PTYPE_L4_UDP : 0);
 170 }
 171
 172 static const uint32_t *
 173 sfc_efx_supported_ptypes_get(__rte_unused uint32_t tunnel_encaps)
 174 {
 175         static const uint32_t ptypes[] = {
 176                 RTE_PTYPE_L2_ETHER,
 177                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 178                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 179                 RTE_PTYPE_L4_TCP,
 180                 RTE_PTYPE_L4_UDP,
 181                 RTE_PTYPE_UNKNOWN
 182         };
 183
 184         return ptypes;
 185 }
 186
 187 static void
 188 sfc_efx_rx_set_rss_hash(struct sfc_efx_rxq *rxq, unsigned int flags,
 189                         struct rte_mbuf *m)
 190 {
 191         uint8_t *mbuf_data;
 192
 193
 194         if ((rxq->flags & SFC_EFX_RXQ_FLAG_RSS_HASH) == 0)
 195                 return;
 196
 197         mbuf_data = rte_pktmbuf_mtod(m, uint8_t *);
 198
 199         if (flags & (EFX_PKT_IPV4 | EFX_PKT_IPV6)) {
 200                 m->hash.rss = efx_pseudo_hdr_hash_get(rxq->common,
 201                                                       EFX_RX_HASHALG_TOEPLITZ,
 202                                                       mbuf_data);
 203
 204                 m->ol_flags |= PKT_RX_RSS_HASH;
 205         }
 206 }
 207
 208 static uint16_t
 209 sfc_efx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 210 {
 211         struct sfc_dp_rxq *dp_rxq = rx_queue;
 212         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 213         unsigned int completed;
 214         unsigned int prefix_size = rxq->prefix_size;
 215         unsigned int done_pkts = 0;
 216         boolean_t discard_next = B_FALSE;
 217         struct rte_mbuf *scatter_pkt = NULL;
 218
 219         if (unlikely((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0))
 220                 return 0;
 221
 222         sfc_ev_qpoll(rxq->evq);
 223
 224         completed = rxq->completed;
 225         while (completed != rxq->pending && done_pkts < nb_pkts) {
 226                 unsigned int id;
 227                 struct sfc_efx_rx_sw_desc *rxd;
 228                 struct rte_mbuf *m;
 229                 unsigned int seg_len;
 230                 unsigned int desc_flags;
 231
 232                 id = completed++ & rxq->ptr_mask;
 233                 rxd = &rxq->sw_desc[id];
 234                 m = rxd->mbuf;
 235                 desc_flags = rxd->flags;
 236
 237                 if (discard_next)
 238                         goto discard;
 239
 240                 if (desc_flags & (EFX_ADDR_MISMATCH | EFX_DISCARD))
 241                         goto discard;
 242
 243                 if (desc_flags & EFX_PKT_PREFIX_LEN) {
 244                         uint16_t tmp_size;
 245                         int rc __rte_unused;
 246
 247                         rc = efx_pseudo_hdr_pkt_length_get(rxq->common,
 248                                 rte_pktmbuf_mtod(m, uint8_t *), &tmp_size);
 249                         SFC_ASSERT(rc == 0);
 250                         seg_len = tmp_size;
 251                 } else {
 252                         seg_len = rxd->size - prefix_size;
 253                 }
 254
 255                 rte_pktmbuf_data_len(m) = seg_len;
 256                 rte_pktmbuf_pkt_len(m) = seg_len;
 257
 258                 if (scatter_pkt != NULL) {
 259                         if (rte_pktmbuf_chain(scatter_pkt, m) != 0) {
 260                                 rte_pktmbuf_free(scatter_pkt);
 261                                 goto discard;
 262                         }
 263                         /* The packet to deliver */
 264                         m = scatter_pkt;
 265                 }
 266
 267                 if (desc_flags & EFX_PKT_CONT) {
 268                         /* The packet is scattered, more fragments to come */
 269                         scatter_pkt = m;
 270                         /* Further fragments have no prefix */
 271                         prefix_size = 0;
 272                         continue;
 273                 }
 274
 275                 /* Scattered packet is done */
 276                 scatter_pkt = NULL;
 277                 /* The first fragment of the packet has prefix */
 278                 prefix_size = rxq->prefix_size;
 279
 280                 m->ol_flags =
 281                         sfc_efx_rx_desc_flags_to_offload_flags(desc_flags);
 282                 m->packet_type =
 283                         sfc_efx_rx_desc_flags_to_packet_type(desc_flags);
 284
 285                 /*
 286                  * Extract RSS hash from the packet prefix and
 287                  * set the corresponding field (if needed and possible)
 288                  */
 289                 sfc_efx_rx_set_rss_hash(rxq, desc_flags, m);
 290
 291                 m->data_off += prefix_size;
 292
 293                 *rx_pkts++ = m;
 294                 done_pkts++;
 295                 continue;
 296
 297 discard:
 298                 discard_next = ((desc_flags & EFX_PKT_CONT) != 0);
 299                 rte_mempool_put(rxq->refill_mb_pool, m);
 300                 rxd->mbuf = NULL;
 301         }
 302
 303         /* pending is only moved when entire packet is received */
 304         SFC_ASSERT(scatter_pkt == NULL);
 305
 306         rxq->completed = completed;
 307
 308         sfc_efx_rx_qrefill(rxq);
 309
 310         return done_pkts;
 311 }
 312
 313 static sfc_dp_rx_qdesc_npending_t sfc_efx_rx_qdesc_npending;
 314 static unsigned int
 315 sfc_efx_rx_qdesc_npending(struct sfc_dp_rxq *dp_rxq)
 316 {
 317         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 318
 319         if ((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0)
 320                 return 0;
 321
 322         sfc_ev_qpoll(rxq->evq);
 323
 324         return rxq->pending - rxq->completed;
 325 }
 326
 327 static sfc_dp_rx_qdesc_status_t sfc_efx_rx_qdesc_status;
 328 static int
 329 sfc_efx_rx_qdesc_status(struct sfc_dp_rxq *dp_rxq, uint16_t offset)
 330 {
 331         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 332
 333         if (unlikely(offset > rxq->ptr_mask))
 334                 return -EINVAL;
 335
 336         /*
 337          * Poll EvQ to derive up-to-date 'rxq->pending' figure;
 338          * it is required for the queue to be running, but the
 339          * check is omitted because API design assumes that it
 340          * is the duty of the caller to satisfy all conditions
 341          */
 342         SFC_ASSERT((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) ==
 343                    SFC_EFX_RXQ_FLAG_RUNNING);
 344         sfc_ev_qpoll(rxq->evq);
 345
 346         /*
 347          * There is a handful of reserved entries in the ring,
 348          * but an explicit check whether the offset points to
 349          * a reserved entry is neglected since the two checks
 350          * below rely on the figures which take the HW limits
 351          * into account and thus if an entry is reserved, the
 352          * checks will fail and UNAVAIL code will be returned
 353          */
 354
 355         if (offset < (rxq->pending - rxq->completed))
 356                 return RTE_ETH_RX_DESC_DONE;
 357
 358         if (offset < (rxq->added - rxq->completed))
 359                 return RTE_ETH_RX_DESC_AVAIL;
 360
 361         return RTE_ETH_RX_DESC_UNAVAIL;
 362 }
 363
 364 struct sfc_rxq *
 365 sfc_rxq_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
 366 {
 367         const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
 368         struct rte_eth_dev *eth_dev;
 369         struct sfc_adapter *sa;
 370         struct sfc_rxq *rxq;
 371
 372         SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
 373         eth_dev = &rte_eth_devices[dpq->port_id];
 374
 375         sa = eth_dev->data->dev_private;
 376
 377         SFC_ASSERT(dpq->queue_id < sa->rxq_count);
 378         rxq = sa->rxq_info[dpq->queue_id].rxq;
 379
 380         SFC_ASSERT(rxq != NULL);
 381         return rxq;
 382 }
 383
 384 static sfc_dp_rx_qsize_up_rings_t sfc_efx_rx_qsize_up_rings;
 385 static int
 386 sfc_efx_rx_qsize_up_rings(uint16_t nb_rx_desc,
 387                           __rte_unused struct rte_mempool *mb_pool,
 388                           unsigned int *rxq_entries,
 389                           unsigned int *evq_entries,
 390                           unsigned int *rxq_max_fill_level)
 391 {
 392         *rxq_entries = nb_rx_desc;
 393         *evq_entries = nb_rx_desc;
 394         *rxq_max_fill_level = EFX_RXQ_LIMIT(*rxq_entries);
 395         return 0;
 396 }
 397
 398 static sfc_dp_rx_qcreate_t sfc_efx_rx_qcreate;
 399 static int
 400 sfc_efx_rx_qcreate(uint16_t port_id, uint16_t queue_id,
 401                    const struct rte_pci_addr *pci_addr, int socket_id,
 402                    const struct sfc_dp_rx_qcreate_info *info,
 403                    struct sfc_dp_rxq **dp_rxqp)
 404 {
 405         struct sfc_efx_rxq *rxq;
 406         int rc;
 407
 408         rc = ENOMEM;
 409         rxq = rte_zmalloc_socket("sfc-efx-rxq", sizeof(*rxq),
 410                                  RTE_CACHE_LINE_SIZE, socket_id);
 411         if (rxq == NULL)
 412                 goto fail_rxq_alloc;
 413
 414         sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr);
 415
 416         rc = ENOMEM;
 417         rxq->sw_desc = rte_calloc_socket("sfc-efx-rxq-sw_desc",
 418                                          info->rxq_entries,
 419                                          sizeof(*rxq->sw_desc),
 420                                          RTE_CACHE_LINE_SIZE, socket_id);
 421         if (rxq->sw_desc == NULL)
 422                 goto fail_desc_alloc;
 423
 424         /* efx datapath is bound to efx control path */
 425         rxq->evq = sfc_rxq_by_dp_rxq(&rxq->dp)->evq;
 426         if (info->flags & SFC_RXQ_FLAG_RSS_HASH)
 427                 rxq->flags |= SFC_EFX_RXQ_FLAG_RSS_HASH;
 428         rxq->ptr_mask = info->rxq_entries - 1;
 429         rxq->batch_max = info->batch_max;
 430         rxq->prefix_size = info->prefix_size;
 431         rxq->max_fill_level = info->max_fill_level;
 432         rxq->refill_threshold = info->refill_threshold;
 433         rxq->buf_size = info->buf_size;
 434         rxq->refill_mb_pool = info->refill_mb_pool;
 435
 436         *dp_rxqp = &rxq->dp;
 437         return 0;
 438
 439 fail_desc_alloc:
 440         rte_free(rxq);
 441
 442 fail_rxq_alloc:
 443         return rc;
 444 }
 445
 446 static sfc_dp_rx_qdestroy_t sfc_efx_rx_qdestroy;
 447 static void
 448 sfc_efx_rx_qdestroy(struct sfc_dp_rxq *dp_rxq)
 449 {
 450         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 451
 452         rte_free(rxq->sw_desc);
 453         rte_free(rxq);
 454 }
 455
 456 static sfc_dp_rx_qstart_t sfc_efx_rx_qstart;
 457 static int
 458 sfc_efx_rx_qstart(struct sfc_dp_rxq *dp_rxq,
 459                   __rte_unused unsigned int evq_read_ptr)
 460 {
 461         /* libefx-based datapath is specific to libefx-based PMD */
 462         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 463         struct sfc_rxq *crxq = sfc_rxq_by_dp_rxq(dp_rxq);
 464
 465         rxq->common = crxq->common;
 466
 467         rxq->pending = rxq->completed = rxq->added = rxq->pushed = 0;
 468
 469         sfc_efx_rx_qrefill(rxq);
 470
 471         rxq->flags |= (SFC_EFX_RXQ_FLAG_STARTED | SFC_EFX_RXQ_FLAG_RUNNING);
 472
 473         return 0;
 474 }
 475
 476 static sfc_dp_rx_qstop_t sfc_efx_rx_qstop;
 477 static void
 478 sfc_efx_rx_qstop(struct sfc_dp_rxq *dp_rxq,
 479                  __rte_unused unsigned int *evq_read_ptr)
 480 {
 481         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 482
 483         rxq->flags &= ~SFC_EFX_RXQ_FLAG_RUNNING;
 484
 485         /* libefx-based datapath is bound to libefx-based PMD and uses
 486          * event queue structure directly. So, there is no necessity to
 487          * return EvQ read pointer.
 488          */
 489 }
 490
 491 static sfc_dp_rx_qpurge_t sfc_efx_rx_qpurge;
 492 static void
 493 sfc_efx_rx_qpurge(struct sfc_dp_rxq *dp_rxq)
 494 {
 495         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 496         unsigned int i;
 497         struct sfc_efx_rx_sw_desc *rxd;
 498
 499         for (i = rxq->completed; i != rxq->added; ++i) {
 500                 rxd = &rxq->sw_desc[i & rxq->ptr_mask];
 501                 rte_mempool_put(rxq->refill_mb_pool, rxd->mbuf);
 502                 rxd->mbuf = NULL;
 503                 /* Packed stream relies on 0 in inactive SW desc.
 504                  * Rx queue stop is not performance critical, so
 505                  * there is no harm to do it always.
 506                  */
 507                 rxd->flags = 0;
 508                 rxd->size = 0;
 509         }
 510
 511         rxq->flags &= ~SFC_EFX_RXQ_FLAG_STARTED;
 512 }
 513
 514 struct sfc_dp_rx sfc_efx_rx = {
 515         .dp = {
 516                 .name           = SFC_KVARG_DATAPATH_EFX,
 517                 .type           = SFC_DP_RX,
 518                 .hw_fw_caps     = 0,
 519         },
 520         .features               = SFC_DP_RX_FEAT_SCATTER,
 521         .qsize_up_rings         = sfc_efx_rx_qsize_up_rings,
 522         .qcreate                = sfc_efx_rx_qcreate,
 523         .qdestroy               = sfc_efx_rx_qdestroy,
 524         .qstart                 = sfc_efx_rx_qstart,
 525         .qstop                  = sfc_efx_rx_qstop,
 526         .qpurge                 = sfc_efx_rx_qpurge,
 527         .supported_ptypes_get   = sfc_efx_supported_ptypes_get,
 528         .qdesc_npending         = sfc_efx_rx_qdesc_npending,
 529         .qdesc_status           = sfc_efx_rx_qdesc_status,
 530         .pkt_burst              = sfc_efx_recv_pkts,
 531 };
 532
 533 unsigned int
 534 sfc_rx_qdesc_npending(struct sfc_adapter *sa, unsigned int sw_index)
 535 {
 536         struct sfc_rxq *rxq;
 537
 538         SFC_ASSERT(sw_index < sa->rxq_count);
 539         rxq = sa->rxq_info[sw_index].rxq;
 540
 541         if (rxq == NULL || (rxq->state & SFC_RXQ_STARTED) == 0)
 542                 return 0;
 543
 544         return sa->dp_rx->qdesc_npending(rxq->dp);
 545 }
 546
 547 int
 548 sfc_rx_qdesc_done(struct sfc_dp_rxq *dp_rxq, unsigned int offset)
 549 {
 550         struct sfc_rxq *rxq = sfc_rxq_by_dp_rxq(dp_rxq);
 551
 552         return offset < rxq->evq->sa->dp_rx->qdesc_npending(dp_rxq);
 553 }
 554
 555 static void
 556 sfc_rx_qflush(struct sfc_adapter *sa, unsigned int sw_index)
 557 {
 558         struct sfc_rxq *rxq;
 559         unsigned int retry_count;
 560         unsigned int wait_count;
 561         int rc;
 562
 563         rxq = sa->rxq_info[sw_index].rxq;
 564         SFC_ASSERT(rxq->state & SFC_RXQ_STARTED);
 565
 566         /*
 567          * Retry Rx queue flushing in the case of flush failed or
 568          * timeout. In the worst case it can delay for 6 seconds.
 569          */
 570         for (retry_count = 0;
 571              ((rxq->state & SFC_RXQ_FLUSHED) == 0) &&
 572              (retry_count < SFC_RX_QFLUSH_ATTEMPTS);
 573              ++retry_count) {
 574                 rc = efx_rx_qflush(rxq->common);
 575                 if (rc != 0) {
 576                         rxq->state |= (rc == EALREADY) ?
 577                                 SFC_RXQ_FLUSHED : SFC_RXQ_FLUSH_FAILED;
 578                         break;
 579                 }
 580                 rxq->state &= ~SFC_RXQ_FLUSH_FAILED;
 581                 rxq->state |= SFC_RXQ_FLUSHING;
 582
 583                 /*
 584                  * Wait for Rx queue flush done or failed event at least
 585                  * SFC_RX_QFLUSH_POLL_WAIT_MS milliseconds and not more
 586                  * than 2 seconds (SFC_RX_QFLUSH_POLL_WAIT_MS multiplied
 587                  * by SFC_RX_QFLUSH_POLL_ATTEMPTS).
 588                  */
 589                 wait_count = 0;
 590                 do {
 591                         rte_delay_ms(SFC_RX_QFLUSH_POLL_WAIT_MS);
 592                         sfc_ev_qpoll(rxq->evq);
 593                 } while ((rxq->state & SFC_RXQ_FLUSHING) &&
 594                          (wait_count++ < SFC_RX_QFLUSH_POLL_ATTEMPTS));
 595
 596                 if (rxq->state & SFC_RXQ_FLUSHING)
 597                         sfc_err(sa, "RxQ %u flush timed out", sw_index);
 598
 599                 if (rxq->state & SFC_RXQ_FLUSH_FAILED)
 600                         sfc_err(sa, "RxQ %u flush failed", sw_index);
 601
 602                 if (rxq->state & SFC_RXQ_FLUSHED)
 603                         sfc_notice(sa, "RxQ %u flushed", sw_index);
 604         }
 605
 606         sa->dp_rx->qpurge(rxq->dp);
 607 }
 608
 609 static int
 610 sfc_rx_default_rxq_set_filter(struct sfc_adapter *sa, struct sfc_rxq *rxq)
 611 {
 612         struct sfc_rss *rss = &sa->rss;
 613         boolean_t need_rss = (rss->channels > 0) ? B_TRUE : B_FALSE;
 614         struct sfc_port *port = &sa->port;
 615         int rc;
 616
 617         /*
 618          * If promiscuous or all-multicast mode has been requested, setting
 619          * filter for the default Rx queue might fail, in particular, while
 620          * running over PCI function which is not a member of corresponding
 621          * privilege groups; if this occurs, few iterations will be made to
 622          * repeat this step without promiscuous and all-multicast flags set
 623          */
 624 retry:
 625         rc = efx_mac_filter_default_rxq_set(sa->nic, rxq->common, need_rss);
 626         if (rc == 0)
 627                 return 0;
 628         else if (rc != EOPNOTSUPP)
 629                 return rc;
 630
 631         if (port->promisc) {
 632                 sfc_warn(sa, "promiscuous mode has been requested, "
 633                              "but the HW rejects it");
 634                 sfc_warn(sa, "promiscuous mode will be disabled");
 635
 636                 port->promisc = B_FALSE;
 637                 rc = sfc_set_rx_mode(sa);
 638                 if (rc != 0)
 639                         return rc;
 640
 641                 goto retry;
 642         }
 643
 644         if (port->allmulti) {
 645                 sfc_warn(sa, "all-multicast mode has been requested, "
 646                              "but the HW rejects it");
 647                 sfc_warn(sa, "all-multicast mode will be disabled");
 648
 649                 port->allmulti = B_FALSE;
 650                 rc = sfc_set_rx_mode(sa);
 651                 if (rc != 0)
 652                         return rc;
 653
 654                 goto retry;
 655         }
 656
 657         return rc;
 658 }
 659
 660 int
 661 sfc_rx_qstart(struct sfc_adapter *sa, unsigned int sw_index)
 662 {
 663         struct sfc_port *port = &sa->port;
 664         struct sfc_rxq_info *rxq_info;
 665         struct sfc_rxq *rxq;
 666         struct sfc_evq *evq;
 667         int rc;
 668
 669         sfc_log_init(sa, "sw_index=%u", sw_index);
 670
 671         SFC_ASSERT(sw_index < sa->rxq_count);
 672
 673         rxq_info = &sa->rxq_info[sw_index];
 674         rxq = rxq_info->rxq;
 675         SFC_ASSERT(rxq->state == SFC_RXQ_INITIALIZED);
 676
 677         evq = rxq->evq;
 678
 679         rc = sfc_ev_qstart(evq, sfc_evq_index_by_rxq_sw_index(sa, sw_index));
 680         if (rc != 0)
 681                 goto fail_ev_qstart;
 682
 683         switch (rxq_info->type) {
 684         case EFX_RXQ_TYPE_DEFAULT:
 685                 rc = efx_rx_qcreate(sa->nic, rxq->hw_index, 0, rxq_info->type,
 686                         &rxq->mem, rxq_info->entries, 0 /* not used on EF10 */,
 687                         rxq_info->type_flags, evq->common, &rxq->common);
 688                 break;
 689         case EFX_RXQ_TYPE_ES_SUPER_BUFFER: {
 690                 struct rte_mempool *mp = rxq->refill_mb_pool;
 691                 struct rte_mempool_info mp_info;
 692
 693                 rc = rte_mempool_ops_get_info(mp, &mp_info);
 694                 if (rc != 0) {
 695                         /* Positive errno is used in the driver */
 696                         rc = -rc;
 697                         goto fail_mp_get_info;
 698                 }
 699                 if (mp_info.contig_block_size <= 0) {
 700                         rc = EINVAL;
 701                         goto fail_bad_contig_block_size;
 702                 }
 703                 rc = efx_rx_qcreate_es_super_buffer(sa->nic, rxq->hw_index, 0,
 704                         mp_info.contig_block_size, rxq->buf_size,
 705                         mp->header_size + mp->elt_size + mp->trailer_size,
 706                         sa->rxd_wait_timeout_ns,
 707                         &rxq->mem, rxq_info->entries, rxq_info->type_flags,
 708                         evq->common, &rxq->common);
 709                 break;
 710         }
 711         default:
 712                 rc = ENOTSUP;
 713         }
 714         if (rc != 0)
 715                 goto fail_rx_qcreate;
 716
 717         efx_rx_qenable(rxq->common);
 718
 719         rc = sa->dp_rx->qstart(rxq->dp, evq->read_ptr);
 720         if (rc != 0)
 721                 goto fail_dp_qstart;
 722
 723         rxq->state |= SFC_RXQ_STARTED;
 724
 725         if ((sw_index == 0) && !port->isolated) {
 726                 rc = sfc_rx_default_rxq_set_filter(sa, rxq);
 727                 if (rc != 0)
 728                         goto fail_mac_filter_default_rxq_set;
 729         }
 730
 731         /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
 732         sa->eth_dev->data->rx_queue_state[sw_index] =
 733                 RTE_ETH_QUEUE_STATE_STARTED;
 734
 735         return 0;
 736
 737 fail_mac_filter_default_rxq_set:
 738         sa->dp_rx->qstop(rxq->dp, &rxq->evq->read_ptr);
 739
 740 fail_dp_qstart:
 741         sfc_rx_qflush(sa, sw_index);
 742
 743 fail_rx_qcreate:
 744 fail_bad_contig_block_size:
 745 fail_mp_get_info:
 746         sfc_ev_qstop(evq);
 747
 748 fail_ev_qstart:
 749         return rc;
 750 }
 751
 752 void
 753 sfc_rx_qstop(struct sfc_adapter *sa, unsigned int sw_index)
 754 {
 755         struct sfc_rxq_info *rxq_info;
 756         struct sfc_rxq *rxq;
 757
 758         sfc_log_init(sa, "sw_index=%u", sw_index);
 759
 760         SFC_ASSERT(sw_index < sa->rxq_count);
 761
 762         rxq_info = &sa->rxq_info[sw_index];
 763         rxq = rxq_info->rxq;
 764
 765         if (rxq->state == SFC_RXQ_INITIALIZED)
 766                 return;
 767         SFC_ASSERT(rxq->state & SFC_RXQ_STARTED);
 768
 769         /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
 770         sa->eth_dev->data->rx_queue_state[sw_index] =
 771                 RTE_ETH_QUEUE_STATE_STOPPED;
 772
 773         sa->dp_rx->qstop(rxq->dp, &rxq->evq->read_ptr);
 774
 775         if (sw_index == 0)
 776                 efx_mac_filter_default_rxq_clear(sa->nic);
 777
 778         sfc_rx_qflush(sa, sw_index);
 779
 780         rxq->state = SFC_RXQ_INITIALIZED;
 781
 782         efx_rx_qdestroy(rxq->common);
 783
 784         sfc_ev_qstop(rxq->evq);
 785 }
 786
 787 uint64_t
 788 sfc_rx_get_dev_offload_caps(struct sfc_adapter *sa)
 789 {
 790         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
 791         uint64_t caps = 0;
 792
 793         caps |= DEV_RX_OFFLOAD_JUMBO_FRAME;
 794         caps |= DEV_RX_OFFLOAD_CRC_STRIP;
 795         caps |= DEV_RX_OFFLOAD_IPV4_CKSUM;
 796         caps |= DEV_RX_OFFLOAD_UDP_CKSUM;
 797         caps |= DEV_RX_OFFLOAD_TCP_CKSUM;
 798
 799         if (encp->enc_tunnel_encapsulations_supported &&
 800             (sa->dp_rx->features & SFC_DP_RX_FEAT_TUNNELS))
 801                 caps |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
 802
 803         return caps;
 804 }
 805
 806 uint64_t
 807 sfc_rx_get_queue_offload_caps(struct sfc_adapter *sa)
 808 {
 809         uint64_t caps = 0;
 810
 811         if (sa->dp_rx->features & SFC_DP_RX_FEAT_SCATTER)
 812                 caps |= DEV_RX_OFFLOAD_SCATTER;
 813
 814         return caps;
 815 }
 816
 817 static int
 818 sfc_rx_qcheck_conf(struct sfc_adapter *sa, unsigned int rxq_max_fill_level,
 819                    const struct rte_eth_rxconf *rx_conf,
 820                    __rte_unused uint64_t offloads)
 821 {
 822         int rc = 0;
 823
 824         if (rx_conf->rx_thresh.pthresh != 0 ||
 825             rx_conf->rx_thresh.hthresh != 0 ||
 826             rx_conf->rx_thresh.wthresh != 0) {
 827                 sfc_warn(sa,
 828                         "RxQ prefetch/host/writeback thresholds are not supported");
 829         }
 830
 831         if (rx_conf->rx_free_thresh > rxq_max_fill_level) {
 832                 sfc_err(sa,
 833                         "RxQ free threshold too large: %u vs maximum %u",
 834                         rx_conf->rx_free_thresh, rxq_max_fill_level);
 835                 rc = EINVAL;
 836         }
 837
 838         if (rx_conf->rx_drop_en == 0) {
 839                 sfc_err(sa, "RxQ drop disable is not supported");
 840                 rc = EINVAL;
 841         }
 842
 843         return rc;
 844 }
 845
 846 static unsigned int
 847 sfc_rx_mbuf_data_alignment(struct rte_mempool *mb_pool)
 848 {
 849         uint32_t data_off;
 850         uint32_t order;
 851
 852         /* The mbuf object itself is always cache line aligned */
 853         order = rte_bsf32(RTE_CACHE_LINE_SIZE);
 854
 855         /* Data offset from mbuf object start */
 856         data_off = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(mb_pool) +
 857                 RTE_PKTMBUF_HEADROOM;
 858
 859         order = MIN(order, rte_bsf32(data_off));
 860
 861         return 1u << order;
 862 }
 863
 864 static uint16_t
 865 sfc_rx_mb_pool_buf_size(struct sfc_adapter *sa, struct rte_mempool *mb_pool)
 866 {
 867         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
 868         const uint32_t nic_align_start = MAX(1, encp->enc_rx_buf_align_start);
 869         const uint32_t nic_align_end = MAX(1, encp->enc_rx_buf_align_end);
 870         uint16_t buf_size;
 871         unsigned int buf_aligned;
 872         unsigned int start_alignment;
 873         unsigned int end_padding_alignment;
 874
 875         /* Below it is assumed that both alignments are power of 2 */
 876         SFC_ASSERT(rte_is_power_of_2(nic_align_start));
 877         SFC_ASSERT(rte_is_power_of_2(nic_align_end));
 878
 879         /*
 880          * mbuf is always cache line aligned, double-check
 881          * that it meets rx buffer start alignment requirements.
 882          */
 883
 884         /* Start from mbuf pool data room size */
 885         buf_size = rte_pktmbuf_data_room_size(mb_pool);
 886
 887         /* Remove headroom */
 888         if (buf_size <= RTE_PKTMBUF_HEADROOM) {
 889                 sfc_err(sa,
 890                         "RxQ mbuf pool %s object data room size %u is smaller than headroom %u",
 891                         mb_pool->name, buf_size, RTE_PKTMBUF_HEADROOM);
 892                 return 0;
 893         }
 894         buf_size -= RTE_PKTMBUF_HEADROOM;
 895
 896         /* Calculate guaranteed data start alignment */
 897         buf_aligned = sfc_rx_mbuf_data_alignment(mb_pool);
 898
 899         /* Reserve space for start alignment */
 900         if (buf_aligned < nic_align_start) {
 901                 start_alignment = nic_align_start - buf_aligned;
 902                 if (buf_size <= start_alignment) {
 903                         sfc_err(sa,
 904                                 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u and buffer start alignment %u required by NIC",
 905                                 mb_pool->name,
 906                                 rte_pktmbuf_data_room_size(mb_pool),
 907                                 RTE_PKTMBUF_HEADROOM, start_alignment);
 908                         return 0;
 909                 }
 910                 buf_aligned = nic_align_start;
 911                 buf_size -= start_alignment;
 912         } else {
 913                 start_alignment = 0;
 914         }
 915
 916         /* Make sure that end padding does not write beyond the buffer */
 917         if (buf_aligned < nic_align_end) {
 918                 /*
 919                  * Estimate space which can be lost. If guarnteed buffer
 920                  * size is odd, lost space is (nic_align_end - 1). More
 921                  * accurate formula is below.
 922                  */
 923                 end_padding_alignment = nic_align_end -
 924                         MIN(buf_aligned, 1u << (rte_bsf32(buf_size) - 1));
 925                 if (buf_size <= end_padding_alignment) {
 926                         sfc_err(sa,
 927                                 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u, buffer start alignment %u and end padding alignment %u required by NIC",
 928                                 mb_pool->name,
 929                                 rte_pktmbuf_data_room_size(mb_pool),
 930                                 RTE_PKTMBUF_HEADROOM, start_alignment,
 931                                 end_padding_alignment);
 932                         return 0;
 933                 }
 934                 buf_size -= end_padding_alignment;
 935         } else {
 936                 /*
 937                  * Start is aligned the same or better than end,
 938                  * just align length.
 939                  */
 940                 buf_size = P2ALIGN(buf_size, nic_align_end);
 941         }
 942
 943         return buf_size;
 944 }
 945
 946 int
 947 sfc_rx_qinit(struct sfc_adapter *sa, unsigned int sw_index,
 948              uint16_t nb_rx_desc, unsigned int socket_id,
 949              const struct rte_eth_rxconf *rx_conf,
 950              struct rte_mempool *mb_pool)
 951 {
 952         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
 953         struct sfc_rss *rss = &sa->rss;
 954         int rc;
 955         unsigned int rxq_entries;
 956         unsigned int evq_entries;
 957         unsigned int rxq_max_fill_level;
 958         uint64_t offloads;
 959         uint16_t buf_size;
 960         struct sfc_rxq_info *rxq_info;
 961         struct sfc_evq *evq;
 962         struct sfc_rxq *rxq;
 963         struct sfc_dp_rx_qcreate_info info;
 964
 965         rc = sa->dp_rx->qsize_up_rings(nb_rx_desc, mb_pool, &rxq_entries,
 966                                        &evq_entries, &rxq_max_fill_level);
 967         if (rc != 0)
 968                 goto fail_size_up_rings;
 969         SFC_ASSERT(rxq_entries >= EFX_RXQ_MINNDESCS);
 970         SFC_ASSERT(rxq_entries <= EFX_RXQ_MAXNDESCS);
 971         SFC_ASSERT(rxq_max_fill_level <= nb_rx_desc);
 972
 973         offloads = rx_conf->offloads |
 974                 sa->eth_dev->data->dev_conf.rxmode.offloads;
 975         rc = sfc_rx_qcheck_conf(sa, rxq_max_fill_level, rx_conf, offloads);
 976         if (rc != 0)
 977                 goto fail_bad_conf;
 978
 979         buf_size = sfc_rx_mb_pool_buf_size(sa, mb_pool);
 980         if (buf_size == 0) {
 981                 sfc_err(sa, "RxQ %u mbuf pool object size is too small",
 982                         sw_index);
 983                 rc = EINVAL;
 984                 goto fail_bad_conf;
 985         }
 986
 987         if ((buf_size < sa->port.pdu + encp->enc_rx_prefix_size) &&
 988             (~offloads & DEV_RX_OFFLOAD_SCATTER)) {
 989                 sfc_err(sa, "Rx scatter is disabled and RxQ %u mbuf pool "
 990                         "object size is too small", sw_index);
 991                 sfc_err(sa, "RxQ %u calculated Rx buffer size is %u vs "
 992                         "PDU size %u plus Rx prefix %u bytes",
 993                         sw_index, buf_size, (unsigned int)sa->port.pdu,
 994                         encp->enc_rx_prefix_size);
 995                 rc = EINVAL;
 996                 goto fail_bad_conf;
 997         }
 998
 999         SFC_ASSERT(sw_index < sa->rxq_count);
1000         rxq_info = &sa->rxq_info[sw_index];
1001
1002         SFC_ASSERT(rxq_entries <= rxq_info->max_entries);
1003         rxq_info->entries = rxq_entries;
1004
1005         if (sa->dp_rx->dp.hw_fw_caps & SFC_DP_HW_FW_CAP_RX_ES_SUPER_BUFFER)
1006                 rxq_info->type = EFX_RXQ_TYPE_ES_SUPER_BUFFER;
1007         else
1008                 rxq_info->type = EFX_RXQ_TYPE_DEFAULT;
1009
1010         rxq_info->type_flags =
1011                 (offloads & DEV_RX_OFFLOAD_SCATTER) ?
1012                 EFX_RXQ_FLAG_SCATTER : EFX_RXQ_FLAG_NONE;
1013
1014         if ((encp->enc_tunnel_encapsulations_supported != 0) &&
1015             (sa->dp_rx->features & SFC_DP_RX_FEAT_TUNNELS))
1016                 rxq_info->type_flags |= EFX_RXQ_FLAG_INNER_CLASSES;
1017
1018         rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_RX, sw_index,
1019                           evq_entries, socket_id, &evq);
1020         if (rc != 0)
1021                 goto fail_ev_qinit;
1022
1023         rc = ENOMEM;
1024         rxq = rte_zmalloc_socket("sfc-rxq", sizeof(*rxq), RTE_CACHE_LINE_SIZE,
1025                                  socket_id);
1026         if (rxq == NULL)
1027                 goto fail_rxq_alloc;
1028
1029         rxq_info->rxq = rxq;
1030
1031         rxq->evq = evq;
1032         rxq->hw_index = sw_index;
1033         rxq->refill_threshold =
1034                 RTE_MAX(rx_conf->rx_free_thresh, SFC_RX_REFILL_BULK);
1035         rxq->refill_mb_pool = mb_pool;
1036         rxq->buf_size = buf_size;
1037
1038         rc = sfc_dma_alloc(sa, "rxq", sw_index, EFX_RXQ_SIZE(rxq_info->entries),
1039                            socket_id, &rxq->mem);
1040         if (rc != 0)
1041                 goto fail_dma_alloc;
1042
1043         memset(&info, 0, sizeof(info));
1044         info.refill_mb_pool = rxq->refill_mb_pool;
1045         info.max_fill_level = rxq_max_fill_level;
1046         info.refill_threshold = rxq->refill_threshold;
1047         info.buf_size = buf_size;
1048         info.batch_max = encp->enc_rx_batch_max;
1049         info.prefix_size = encp->enc_rx_prefix_size;
1050
1051         if (rss->hash_support == EFX_RX_HASH_AVAILABLE && rss->channels > 0)
1052                 info.flags |= SFC_RXQ_FLAG_RSS_HASH;
1053
1054         info.rxq_entries = rxq_info->entries;
1055         info.rxq_hw_ring = rxq->mem.esm_base;
1056         info.evq_entries = evq_entries;
1057         info.evq_hw_ring = evq->mem.esm_base;
1058         info.hw_index = rxq->hw_index;
1059         info.mem_bar = sa->mem_bar.esb_base;
1060         info.vi_window_shift = encp->enc_vi_window_shift;
1061
1062         rc = sa->dp_rx->qcreate(sa->eth_dev->data->port_id, sw_index,
1063                                 &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr,
1064                                 socket_id, &info, &rxq->dp);
1065         if (rc != 0)
1066                 goto fail_dp_rx_qcreate;
1067
1068         evq->dp_rxq = rxq->dp;
1069
1070         rxq->state = SFC_RXQ_INITIALIZED;
1071
1072         rxq_info->deferred_start = (rx_conf->rx_deferred_start != 0);
1073
1074         return 0;
1075
1076 fail_dp_rx_qcreate:
1077         sfc_dma_free(sa, &rxq->mem);
1078
1079 fail_dma_alloc:
1080         rxq_info->rxq = NULL;
1081         rte_free(rxq);
1082
1083 fail_rxq_alloc:
1084         sfc_ev_qfini(evq);
1085
1086 fail_ev_qinit:
1087         rxq_info->entries = 0;
1088
1089 fail_bad_conf:
1090 fail_size_up_rings:
1091         sfc_log_init(sa, "failed %d", rc);
1092         return rc;
1093 }
1094
1095 void
1096 sfc_rx_qfini(struct sfc_adapter *sa, unsigned int sw_index)
1097 {
1098         struct sfc_rxq_info *rxq_info;
1099         struct sfc_rxq *rxq;
1100
1101         SFC_ASSERT(sw_index < sa->rxq_count);
1102
1103         rxq_info = &sa->rxq_info[sw_index];
1104
1105         rxq = rxq_info->rxq;
1106         SFC_ASSERT(rxq->state == SFC_RXQ_INITIALIZED);
1107
1108         sa->dp_rx->qdestroy(rxq->dp);
1109         rxq->dp = NULL;
1110
1111         rxq_info->rxq = NULL;
1112         rxq_info->entries = 0;
1113
1114         sfc_dma_free(sa, &rxq->mem);
1115
1116         sfc_ev_qfini(rxq->evq);
1117         rxq->evq = NULL;
1118
1119         rte_free(rxq);
1120 }
1121
1122 /*
1123  * Mapping between RTE RSS hash functions and their EFX counterparts.
1124  */
1125 struct sfc_rss_hf_rte_to_efx sfc_rss_hf_map[] = {
1126         { ETH_RSS_NONFRAG_IPV4_TCP,
1127           EFX_RX_HASH(IPV4_TCP, 4TUPLE) },
1128         { ETH_RSS_NONFRAG_IPV4_UDP,
1129           EFX_RX_HASH(IPV4_UDP, 4TUPLE) },
1130         { ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_IPV6_TCP_EX,
1131           EFX_RX_HASH(IPV6_TCP, 4TUPLE) },
1132         { ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_UDP_EX,
1133           EFX_RX_HASH(IPV6_UDP, 4TUPLE) },
1134         { ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_OTHER,
1135           EFX_RX_HASH(IPV4_TCP, 2TUPLE) | EFX_RX_HASH(IPV4_UDP, 2TUPLE) |
1136           EFX_RX_HASH(IPV4, 2TUPLE) },
1137         { ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_OTHER |
1138           ETH_RSS_IPV6_EX,
1139           EFX_RX_HASH(IPV6_TCP, 2TUPLE) | EFX_RX_HASH(IPV6_UDP, 2TUPLE) |
1140           EFX_RX_HASH(IPV6, 2TUPLE) }
1141 };
1142
1143 static efx_rx_hash_type_t
1144 sfc_rx_hash_types_mask_supp(efx_rx_hash_type_t hash_type,
1145                             unsigned int *hash_type_flags_supported,
1146                             unsigned int nb_hash_type_flags_supported)
1147 {
1148         efx_rx_hash_type_t hash_type_masked = 0;
1149         unsigned int i, j;
1150
1151         for (i = 0; i < nb_hash_type_flags_supported; ++i) {
1152                 unsigned int class_tuple_lbn[] = {
1153                         EFX_RX_CLASS_IPV4_TCP_LBN,
1154                         EFX_RX_CLASS_IPV4_UDP_LBN,
1155                         EFX_RX_CLASS_IPV4_LBN,
1156                         EFX_RX_CLASS_IPV6_TCP_LBN,
1157                         EFX_RX_CLASS_IPV6_UDP_LBN,
1158                         EFX_RX_CLASS_IPV6_LBN
1159                 };
1160
1161                 for (j = 0; j < RTE_DIM(class_tuple_lbn); ++j) {
1162                         unsigned int tuple_mask = EFX_RX_CLASS_HASH_4TUPLE;
1163                         unsigned int flag;
1164
1165                         tuple_mask <<= class_tuple_lbn[j];
1166                         flag = hash_type & tuple_mask;
1167
1168                         if (flag == hash_type_flags_supported[i])
1169                                 hash_type_masked |= flag;
1170                 }
1171         }
1172
1173         return hash_type_masked;
1174 }
1175
1176 int
1177 sfc_rx_hash_init(struct sfc_adapter *sa)
1178 {
1179         struct sfc_rss *rss = &sa->rss;
1180         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1181         uint32_t alg_mask = encp->enc_rx_scale_hash_alg_mask;
1182         efx_rx_hash_alg_t alg;
1183         unsigned int flags_supp[EFX_RX_HASH_NFLAGS];
1184         unsigned int nb_flags_supp;
1185         struct sfc_rss_hf_rte_to_efx *hf_map;
1186         struct sfc_rss_hf_rte_to_efx *entry;
1187         efx_rx_hash_type_t efx_hash_types;
1188         unsigned int i;
1189         int rc;
1190
1191         if (alg_mask & (1U << EFX_RX_HASHALG_TOEPLITZ))
1192                 alg = EFX_RX_HASHALG_TOEPLITZ;
1193         else if (alg_mask & (1U << EFX_RX_HASHALG_PACKED_STREAM))
1194                 alg = EFX_RX_HASHALG_PACKED_STREAM;
1195         else
1196                 return EINVAL;
1197
1198         rc = efx_rx_scale_hash_flags_get(sa->nic, alg, flags_supp,
1199                                          &nb_flags_supp);
1200         if (rc != 0)
1201                 return rc;
1202
1203         hf_map = rte_calloc_socket("sfc-rss-hf-map",
1204                                    RTE_DIM(sfc_rss_hf_map),
1205                                    sizeof(*hf_map), 0, sa->socket_id);
1206         if (hf_map == NULL)
1207                 return ENOMEM;
1208
1209         entry = hf_map;
1210         efx_hash_types = 0;
1211         for (i = 0; i < RTE_DIM(sfc_rss_hf_map); ++i) {
1212                 efx_rx_hash_type_t ht;
1213
1214                 ht = sfc_rx_hash_types_mask_supp(sfc_rss_hf_map[i].efx,
1215                                                  flags_supp, nb_flags_supp);
1216                 if (ht != 0) {
1217                         entry->rte = sfc_rss_hf_map[i].rte;
1218                         entry->efx = ht;
1219                         efx_hash_types |= ht;
1220                         ++entry;
1221                 }
1222         }
1223
1224         rss->hash_alg = alg;
1225         rss->hf_map_nb_entries = (unsigned int)(entry - hf_map);
1226         rss->hf_map = hf_map;
1227         rss->hash_types = efx_hash_types;
1228
1229         return 0;
1230 }
1231
1232 void
1233 sfc_rx_hash_fini(struct sfc_adapter *sa)
1234 {
1235         struct sfc_rss *rss = &sa->rss;
1236
1237         rte_free(rss->hf_map);
1238 }
1239
1240 int
1241 sfc_rx_hf_rte_to_efx(struct sfc_adapter *sa, uint64_t rte,
1242                      efx_rx_hash_type_t *efx)
1243 {
1244         struct sfc_rss *rss = &sa->rss;
1245         efx_rx_hash_type_t hash_types = 0;
1246         unsigned int i;
1247
1248         for (i = 0; i < rss->hf_map_nb_entries; ++i) {
1249                 uint64_t rte_mask = rss->hf_map[i].rte;
1250
1251                 if ((rte & rte_mask) != 0) {
1252                         rte &= ~rte_mask;
1253                         hash_types |= rss->hf_map[i].efx;
1254                 }
1255         }
1256
1257         if (rte != 0) {
1258                 sfc_err(sa, "unsupported hash functions requested");
1259                 return EINVAL;
1260         }
1261
1262         *efx = hash_types;
1263
1264         return 0;
1265 }
1266
1267 uint64_t
1268 sfc_rx_hf_efx_to_rte(struct sfc_adapter *sa, efx_rx_hash_type_t efx)
1269 {
1270         struct sfc_rss *rss = &sa->rss;
1271         uint64_t rte = 0;
1272         unsigned int i;
1273
1274         for (i = 0; i < rss->hf_map_nb_entries; ++i) {
1275                 efx_rx_hash_type_t hash_type = rss->hf_map[i].efx;
1276
1277                 if ((efx & hash_type) == hash_type)
1278                         rte |= rss->hf_map[i].rte;
1279         }
1280
1281         return rte;
1282 }
1283
1284 static int
1285 sfc_rx_process_adv_conf_rss(struct sfc_adapter *sa,
1286                             struct rte_eth_rss_conf *conf)
1287 {
1288         struct sfc_rss *rss = &sa->rss;
1289         efx_rx_hash_type_t efx_hash_types = rss->hash_types;
1290         uint64_t rss_hf = sfc_rx_hf_efx_to_rte(sa, efx_hash_types);
1291         int rc;
1292
1293         if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) {
1294                 if ((conf->rss_hf != 0 && conf->rss_hf != rss_hf) ||
1295                     conf->rss_key != NULL)
1296                         return EINVAL;
1297         }
1298
1299         if (conf->rss_hf != 0) {
1300                 rc = sfc_rx_hf_rte_to_efx(sa, conf->rss_hf, &efx_hash_types);
1301                 if (rc != 0)
1302                         return rc;
1303         }
1304
1305         if (conf->rss_key != NULL) {
1306                 if (conf->rss_key_len != sizeof(rss->key)) {
1307                         sfc_err(sa, "RSS key size is wrong (should be %lu)",
1308                                 sizeof(rss->key));
1309                         return EINVAL;
1310                 }
1311                 rte_memcpy(rss->key, conf->rss_key, sizeof(rss->key));
1312         }
1313
1314         rss->hash_types = efx_hash_types;
1315
1316         return 0;
1317 }
1318
1319 static int
1320 sfc_rx_rss_config(struct sfc_adapter *sa)
1321 {
1322         struct sfc_rss *rss = &sa->rss;
1323         int rc = 0;
1324
1325         if (rss->channels > 0) {
1326                 rc = efx_rx_scale_mode_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1327                                            rss->hash_alg, rss->hash_types,
1328                                            B_TRUE);
1329                 if (rc != 0)
1330                         goto finish;
1331
1332                 rc = efx_rx_scale_key_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1333                                           rss->key, sizeof(rss->key));
1334                 if (rc != 0)
1335                         goto finish;
1336
1337                 rc = efx_rx_scale_tbl_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1338                                           rss->tbl, RTE_DIM(rss->tbl));
1339         }
1340
1341 finish:
1342         return rc;
1343 }
1344
1345 int
1346 sfc_rx_start(struct sfc_adapter *sa)
1347 {
1348         unsigned int sw_index;
1349         int rc;
1350
1351         sfc_log_init(sa, "rxq_count=%u", sa->rxq_count);
1352
1353         rc = efx_rx_init(sa->nic);
1354         if (rc != 0)
1355                 goto fail_rx_init;
1356
1357         rc = sfc_rx_rss_config(sa);
1358         if (rc != 0)
1359                 goto fail_rss_config;
1360
1361         for (sw_index = 0; sw_index < sa->rxq_count; ++sw_index) {
1362                 if ((!sa->rxq_info[sw_index].deferred_start ||
1363                      sa->rxq_info[sw_index].deferred_started)) {
1364                         rc = sfc_rx_qstart(sa, sw_index);
1365                         if (rc != 0)
1366                                 goto fail_rx_qstart;
1367                 }
1368         }
1369
1370         return 0;
1371
1372 fail_rx_qstart:
1373         while (sw_index-- > 0)
1374                 sfc_rx_qstop(sa, sw_index);
1375
1376 fail_rss_config:
1377         efx_rx_fini(sa->nic);
1378
1379 fail_rx_init:
1380         sfc_log_init(sa, "failed %d", rc);
1381         return rc;
1382 }
1383
1384 void
1385 sfc_rx_stop(struct sfc_adapter *sa)
1386 {
1387         unsigned int sw_index;
1388
1389         sfc_log_init(sa, "rxq_count=%u", sa->rxq_count);
1390
1391         sw_index = sa->rxq_count;
1392         while (sw_index-- > 0) {
1393                 if (sa->rxq_info[sw_index].rxq != NULL)
1394                         sfc_rx_qstop(sa, sw_index);
1395         }
1396
1397         efx_rx_fini(sa->nic);
1398 }
1399
1400 static int
1401 sfc_rx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index)
1402 {
1403         struct sfc_rxq_info *rxq_info = &sa->rxq_info[sw_index];
1404         unsigned int max_entries;
1405
1406         max_entries = EFX_RXQ_MAXNDESCS;
1407         SFC_ASSERT(rte_is_power_of_2(max_entries));
1408
1409         rxq_info->max_entries = max_entries;
1410
1411         return 0;
1412 }
1413
1414 static int
1415 sfc_rx_check_mode(struct sfc_adapter *sa, struct rte_eth_rxmode *rxmode)
1416 {
1417         uint64_t offloads_supported = sfc_rx_get_dev_offload_caps(sa) |
1418                                       sfc_rx_get_queue_offload_caps(sa);
1419         struct sfc_rss *rss = &sa->rss;
1420         int rc = 0;
1421
1422         switch (rxmode->mq_mode) {
1423         case ETH_MQ_RX_NONE:
1424                 /* No special checks are required */
1425                 break;
1426         case ETH_MQ_RX_RSS:
1427                 if (rss->context_type == EFX_RX_SCALE_UNAVAILABLE) {
1428                         sfc_err(sa, "RSS is not available");
1429                         rc = EINVAL;
1430                 }
1431                 break;
1432         default:
1433                 sfc_err(sa, "Rx multi-queue mode %u not supported",
1434                         rxmode->mq_mode);
1435                 rc = EINVAL;
1436         }
1437
1438         /* KEEP_CRC offload flag is not supported by PMD
1439          * can remove the below block when DEV_RX_OFFLOAD_CRC_STRIP removed
1440          */
1441         if (rte_eth_dev_must_keep_crc(rxmode->offloads)) {
1442                 sfc_warn(sa, "FCS stripping cannot be disabled - always on");
1443                 rxmode->offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
1444         }
1445
1446         if ((rxmode->offloads & DEV_RX_OFFLOAD_CHECKSUM) !=
1447             DEV_RX_OFFLOAD_CHECKSUM) {
1448                 sfc_warn(sa, "Rx checksum offloads cannot be disabled - always on (IPv4/TCP/UDP)");
1449                 rxmode->offloads |= DEV_RX_OFFLOAD_CHECKSUM;
1450         }
1451
1452         if ((offloads_supported & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) &&
1453             (~rxmode->offloads & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM)) {
1454                 sfc_warn(sa, "Rx outer IPv4 checksum offload cannot be disabled - always on");
1455                 rxmode->offloads |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
1456         }
1457
1458         return rc;
1459 }
1460
1461 /**
1462  * Destroy excess queues that are no longer needed after reconfiguration
1463  * or complete close.
1464  */
1465 static void
1466 sfc_rx_fini_queues(struct sfc_adapter *sa, unsigned int nb_rx_queues)
1467 {
1468         int sw_index;
1469
1470         SFC_ASSERT(nb_rx_queues <= sa->rxq_count);
1471
1472         sw_index = sa->rxq_count;
1473         while (--sw_index >= (int)nb_rx_queues) {
1474                 if (sa->rxq_info[sw_index].rxq != NULL)
1475                         sfc_rx_qfini(sa, sw_index);
1476         }
1477
1478         sa->rxq_count = nb_rx_queues;
1479 }
1480
1481 /**
1482  * Initialize Rx subsystem.
1483  *
1484  * Called at device (re)configuration stage when number of receive queues is
1485  * specified together with other device level receive configuration.
1486  *
1487  * It should be used to allocate NUMA-unaware resources.
1488  */
1489 int
1490 sfc_rx_configure(struct sfc_adapter *sa)
1491 {
1492         struct sfc_rss *rss = &sa->rss;
1493         struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
1494         const unsigned int nb_rx_queues = sa->eth_dev->data->nb_rx_queues;
1495         int rc;
1496
1497         sfc_log_init(sa, "nb_rx_queues=%u (old %u)",
1498                      nb_rx_queues, sa->rxq_count);
1499
1500         rc = sfc_rx_check_mode(sa, &dev_conf->rxmode);
1501         if (rc != 0)
1502                 goto fail_check_mode;
1503
1504         if (nb_rx_queues == sa->rxq_count)
1505                 goto done;
1506
1507         if (sa->rxq_info == NULL) {
1508                 rc = ENOMEM;
1509                 sa->rxq_info = rte_calloc_socket("sfc-rxqs", nb_rx_queues,
1510                                                  sizeof(sa->rxq_info[0]), 0,
1511                                                  sa->socket_id);
1512                 if (sa->rxq_info == NULL)
1513                         goto fail_rxqs_alloc;
1514         } else {
1515                 struct sfc_rxq_info *new_rxq_info;
1516
1517                 if (nb_rx_queues < sa->rxq_count)
1518                         sfc_rx_fini_queues(sa, nb_rx_queues);
1519
1520                 rc = ENOMEM;
1521                 new_rxq_info =
1522                         rte_realloc(sa->rxq_info,
1523                                     nb_rx_queues * sizeof(sa->rxq_info[0]), 0);
1524                 if (new_rxq_info == NULL && nb_rx_queues > 0)
1525                         goto fail_rxqs_realloc;
1526
1527                 sa->rxq_info = new_rxq_info;
1528                 if (nb_rx_queues > sa->rxq_count)
1529                         memset(&sa->rxq_info[sa->rxq_count], 0,
1530                                (nb_rx_queues - sa->rxq_count) *
1531                                sizeof(sa->rxq_info[0]));
1532         }
1533
1534         while (sa->rxq_count < nb_rx_queues) {
1535                 rc = sfc_rx_qinit_info(sa, sa->rxq_count);
1536                 if (rc != 0)
1537                         goto fail_rx_qinit_info;
1538
1539                 sa->rxq_count++;
1540         }
1541
1542         rss->channels = (dev_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) ?
1543                          MIN(sa->rxq_count, EFX_MAXRSS) : 0;
1544
1545         if (rss->channels > 0) {
1546                 struct rte_eth_rss_conf *adv_conf_rss;
1547                 unsigned int sw_index;
1548
1549                 for (sw_index = 0; sw_index < EFX_RSS_TBL_SIZE; ++sw_index)
1550                         rss->tbl[sw_index] = sw_index % rss->channels;
1551
1552                 adv_conf_rss = &dev_conf->rx_adv_conf.rss_conf;
1553                 rc = sfc_rx_process_adv_conf_rss(sa, adv_conf_rss);
1554                 if (rc != 0)
1555                         goto fail_rx_process_adv_conf_rss;
1556         }
1557
1558 done:
1559         return 0;
1560
1561 fail_rx_process_adv_conf_rss:
1562 fail_rx_qinit_info:
1563 fail_rxqs_realloc:
1564 fail_rxqs_alloc:
1565         sfc_rx_close(sa);
1566
1567 fail_check_mode:
1568         sfc_log_init(sa, "failed %d", rc);
1569         return rc;
1570 }
1571
1572 /**
1573  * Shutdown Rx subsystem.
1574  *
1575  * Called at device close stage, for example, before device shutdown.
1576  */
1577 void
1578 sfc_rx_close(struct sfc_adapter *sa)
1579 {
1580         struct sfc_rss *rss = &sa->rss;
1581
1582         sfc_rx_fini_queues(sa, 0);
1583
1584         rss->channels = 0;
1585
1586         rte_free(sa->rxq_info);
1587         sa->rxq_info = NULL;
1588 }