1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016-2018 Solarflare Communications Inc.
6 * This software was jointly developed between OKTET Labs (under contract
7 * for Solarflare) and Solarflare Communications, Inc.
11 #include "sfc_debug.h"
15 #include "sfc_tweak.h"
16 #include "sfc_kvargs.h"
19 * Maximum number of TX queue flush attempts in case of
20 * failure or flush timeout
22 #define SFC_TX_QFLUSH_ATTEMPTS (3)
25 * Time to wait between event queue polling attempts when waiting for TX
26 * queue flush done or flush failed events
28 #define SFC_TX_QFLUSH_POLL_WAIT_MS (1)
31 * Maximum number of event queue polling attempts when waiting for TX queue
32 * flush done or flush failed events; it defines TX queue flush attempt timeout
33 * together with SFC_TX_QFLUSH_POLL_WAIT_MS
35 #define SFC_TX_QFLUSH_POLL_ATTEMPTS (2000)
38 sfc_tx_get_dev_offload_caps(struct sfc_adapter *sa)
40 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
43 if ((sa->priv.dp_tx->features & SFC_DP_TX_FEAT_VLAN_INSERT) &&
44 encp->enc_hw_tx_insert_vlan_enabled)
45 caps |= DEV_TX_OFFLOAD_VLAN_INSERT;
47 if (sa->priv.dp_tx->features & SFC_DP_TX_FEAT_MULTI_SEG)
48 caps |= DEV_TX_OFFLOAD_MULTI_SEGS;
50 if ((~sa->priv.dp_tx->features & SFC_DP_TX_FEAT_MULTI_POOL) &&
51 (~sa->priv.dp_tx->features & SFC_DP_TX_FEAT_REFCNT))
52 caps |= DEV_TX_OFFLOAD_MBUF_FAST_FREE;
58 sfc_tx_get_queue_offload_caps(struct sfc_adapter *sa)
60 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
63 caps |= DEV_TX_OFFLOAD_IPV4_CKSUM;
64 caps |= DEV_TX_OFFLOAD_UDP_CKSUM;
65 caps |= DEV_TX_OFFLOAD_TCP_CKSUM;
67 if (encp->enc_tunnel_encapsulations_supported)
68 caps |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
71 caps |= DEV_TX_OFFLOAD_TCP_TSO;
77 sfc_tx_qcheck_conf(struct sfc_adapter *sa, unsigned int txq_max_fill_level,
78 const struct rte_eth_txconf *tx_conf,
83 if (tx_conf->tx_rs_thresh != 0) {
84 sfc_err(sa, "RS bit in transmit descriptor is not supported");
88 if (tx_conf->tx_free_thresh > txq_max_fill_level) {
90 "TxQ free threshold too large: %u vs maximum %u",
91 tx_conf->tx_free_thresh, txq_max_fill_level);
95 if (tx_conf->tx_thresh.pthresh != 0 ||
96 tx_conf->tx_thresh.hthresh != 0 ||
97 tx_conf->tx_thresh.wthresh != 0) {
99 "prefetch/host/writeback thresholds are not supported");
102 /* We either perform both TCP and UDP offload, or no offload at all */
103 if (((offloads & DEV_TX_OFFLOAD_TCP_CKSUM) == 0) !=
104 ((offloads & DEV_TX_OFFLOAD_UDP_CKSUM) == 0)) {
105 sfc_err(sa, "TCP and UDP offloads can't be set independently");
113 sfc_tx_qflush_done(struct sfc_txq_info *txq_info)
115 txq_info->state |= SFC_TXQ_FLUSHED;
116 txq_info->state &= ~SFC_TXQ_FLUSHING;
120 sfc_tx_qinit(struct sfc_adapter *sa, unsigned int sw_index,
121 uint16_t nb_tx_desc, unsigned int socket_id,
122 const struct rte_eth_txconf *tx_conf)
124 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
125 unsigned int txq_entries;
126 unsigned int evq_entries;
127 unsigned int txq_max_fill_level;
128 struct sfc_txq_info *txq_info;
132 struct sfc_dp_tx_qcreate_info info;
134 struct sfc_dp_tx_hw_limits hw_limits;
136 sfc_log_init(sa, "TxQ = %u", sw_index);
138 memset(&hw_limits, 0, sizeof(hw_limits));
139 hw_limits.txq_max_entries = sa->txq_max_entries;
140 hw_limits.txq_min_entries = sa->txq_min_entries;
142 rc = sa->priv.dp_tx->qsize_up_rings(nb_tx_desc, &hw_limits,
143 &txq_entries, &evq_entries,
144 &txq_max_fill_level);
146 goto fail_size_up_rings;
147 SFC_ASSERT(txq_entries >= sa->txq_min_entries);
148 SFC_ASSERT(txq_entries <= sa->txq_max_entries);
149 SFC_ASSERT(txq_entries >= nb_tx_desc);
150 SFC_ASSERT(txq_max_fill_level <= nb_tx_desc);
152 offloads = tx_conf->offloads |
153 sa->eth_dev->data->dev_conf.txmode.offloads;
154 rc = sfc_tx_qcheck_conf(sa, txq_max_fill_level, tx_conf, offloads);
158 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->txq_count);
159 txq_info = &sfc_sa2shared(sa)->txq_info[sw_index];
161 txq_info->entries = txq_entries;
163 rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_TX, sw_index,
164 evq_entries, socket_id, &evq);
168 txq = &sa->txq_ctrl[sw_index];
169 txq->hw_index = sw_index;
171 txq_info->free_thresh =
172 (tx_conf->tx_free_thresh) ? tx_conf->tx_free_thresh :
173 SFC_TX_DEFAULT_FREE_THRESH;
174 txq_info->offloads = offloads;
176 rc = sfc_dma_alloc(sa, "txq", sw_index,
177 efx_txq_size(sa->nic, txq_info->entries),
178 socket_id, &txq->mem);
182 memset(&info, 0, sizeof(info));
183 info.max_fill_level = txq_max_fill_level;
184 info.free_thresh = txq_info->free_thresh;
185 info.offloads = offloads;
186 info.txq_entries = txq_info->entries;
187 info.dma_desc_size_max = encp->enc_tx_dma_desc_size_max;
188 info.txq_hw_ring = txq->mem.esm_base;
189 info.evq_entries = evq_entries;
190 info.evq_hw_ring = evq->mem.esm_base;
191 info.hw_index = txq->hw_index;
192 info.mem_bar = sa->mem_bar.esb_base;
193 info.vi_window_shift = encp->enc_vi_window_shift;
194 info.tso_tcp_header_offset_limit =
195 encp->enc_tx_tso_tcp_header_offset_limit;
197 rc = sa->priv.dp_tx->qcreate(sa->eth_dev->data->port_id, sw_index,
198 &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr,
199 socket_id, &info, &txq_info->dp);
201 goto fail_dp_tx_qinit;
203 evq->dp_txq = txq_info->dp;
205 txq_info->state = SFC_TXQ_INITIALIZED;
207 txq_info->deferred_start = (tx_conf->tx_deferred_start != 0);
212 sfc_dma_free(sa, &txq->mem);
218 txq_info->entries = 0;
222 sfc_log_init(sa, "failed (TxQ = %u, rc = %d)", sw_index, rc);
227 sfc_tx_qfini(struct sfc_adapter *sa, unsigned int sw_index)
229 struct sfc_txq_info *txq_info;
232 sfc_log_init(sa, "TxQ = %u", sw_index);
234 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->txq_count);
235 sa->eth_dev->data->tx_queues[sw_index] = NULL;
237 txq_info = &sfc_sa2shared(sa)->txq_info[sw_index];
239 SFC_ASSERT(txq_info->state == SFC_TXQ_INITIALIZED);
241 sa->priv.dp_tx->qdestroy(txq_info->dp);
244 txq_info->state &= ~SFC_TXQ_INITIALIZED;
245 txq_info->entries = 0;
247 txq = &sa->txq_ctrl[sw_index];
249 sfc_dma_free(sa, &txq->mem);
251 sfc_ev_qfini(txq->evq);
256 sfc_tx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index)
258 sfc_log_init(sa, "TxQ = %u", sw_index);
264 sfc_tx_check_mode(struct sfc_adapter *sa, const struct rte_eth_txmode *txmode)
268 switch (txmode->mq_mode) {
272 sfc_err(sa, "Tx multi-queue mode %u not supported",
278 * These features are claimed to be i40e-specific,
279 * but it does make sense to double-check their absence
281 if (txmode->hw_vlan_reject_tagged) {
282 sfc_err(sa, "Rejecting tagged packets not supported");
286 if (txmode->hw_vlan_reject_untagged) {
287 sfc_err(sa, "Rejecting untagged packets not supported");
291 if (txmode->hw_vlan_insert_pvid) {
292 sfc_err(sa, "Port-based VLAN insertion not supported");
300 * Destroy excess queues that are no longer needed after reconfiguration
304 sfc_tx_fini_queues(struct sfc_adapter *sa, unsigned int nb_tx_queues)
306 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
309 SFC_ASSERT(nb_tx_queues <= sas->txq_count);
311 sw_index = sas->txq_count;
312 while (--sw_index >= (int)nb_tx_queues) {
313 if (sas->txq_info[sw_index].state & SFC_TXQ_INITIALIZED)
314 sfc_tx_qfini(sa, sw_index);
317 sas->txq_count = nb_tx_queues;
321 sfc_tx_configure(struct sfc_adapter *sa)
323 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
324 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
325 const struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
326 const unsigned int nb_tx_queues = sa->eth_dev->data->nb_tx_queues;
329 sfc_log_init(sa, "nb_tx_queues=%u (old %u)",
330 nb_tx_queues, sas->txq_count);
333 * The datapath implementation assumes absence of boundary
334 * limits on Tx DMA descriptors. Addition of these checks on
335 * datapath would simply make the datapath slower.
337 if (encp->enc_tx_dma_desc_boundary != 0) {
339 goto fail_tx_dma_desc_boundary;
342 rc = sfc_tx_check_mode(sa, &dev_conf->txmode);
344 goto fail_check_mode;
346 if (nb_tx_queues == sas->txq_count)
349 if (sas->txq_info == NULL) {
350 sas->txq_info = rte_calloc_socket("sfc-txqs", nb_tx_queues,
351 sizeof(sas->txq_info[0]), 0,
353 if (sas->txq_info == NULL)
354 goto fail_txqs_alloc;
357 * Allocate primary process only TxQ control from heap
358 * since it should not be shared.
361 sa->txq_ctrl = calloc(nb_tx_queues, sizeof(sa->txq_ctrl[0]));
362 if (sa->txq_ctrl == NULL)
363 goto fail_txqs_ctrl_alloc;
365 struct sfc_txq_info *new_txq_info;
366 struct sfc_txq *new_txq_ctrl;
368 if (nb_tx_queues < sas->txq_count)
369 sfc_tx_fini_queues(sa, nb_tx_queues);
372 rte_realloc(sas->txq_info,
373 nb_tx_queues * sizeof(sas->txq_info[0]), 0);
374 if (new_txq_info == NULL && nb_tx_queues > 0)
375 goto fail_txqs_realloc;
377 new_txq_ctrl = realloc(sa->txq_ctrl,
378 nb_tx_queues * sizeof(sa->txq_ctrl[0]));
379 if (new_txq_ctrl == NULL && nb_tx_queues > 0)
380 goto fail_txqs_ctrl_realloc;
382 sas->txq_info = new_txq_info;
383 sa->txq_ctrl = new_txq_ctrl;
384 if (nb_tx_queues > sas->txq_count) {
385 memset(&sas->txq_info[sas->txq_count], 0,
386 (nb_tx_queues - sas->txq_count) *
387 sizeof(sas->txq_info[0]));
388 memset(&sa->txq_ctrl[sas->txq_count], 0,
389 (nb_tx_queues - sas->txq_count) *
390 sizeof(sa->txq_ctrl[0]));
394 while (sas->txq_count < nb_tx_queues) {
395 rc = sfc_tx_qinit_info(sa, sas->txq_count);
397 goto fail_tx_qinit_info;
406 fail_txqs_ctrl_realloc:
408 fail_txqs_ctrl_alloc:
413 fail_tx_dma_desc_boundary:
414 sfc_log_init(sa, "failed (rc = %d)", rc);
419 sfc_tx_close(struct sfc_adapter *sa)
421 sfc_tx_fini_queues(sa, 0);
426 rte_free(sfc_sa2shared(sa)->txq_info);
427 sfc_sa2shared(sa)->txq_info = NULL;
431 sfc_tx_qstart(struct sfc_adapter *sa, unsigned int sw_index)
433 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
434 uint64_t offloads_supported = sfc_tx_get_dev_offload_caps(sa) |
435 sfc_tx_get_queue_offload_caps(sa);
436 struct rte_eth_dev_data *dev_data;
437 struct sfc_txq_info *txq_info;
441 unsigned int desc_index;
444 sfc_log_init(sa, "TxQ = %u", sw_index);
446 SFC_ASSERT(sw_index < sas->txq_count);
447 txq_info = &sas->txq_info[sw_index];
449 SFC_ASSERT(txq_info->state == SFC_TXQ_INITIALIZED);
451 txq = &sa->txq_ctrl[sw_index];
454 rc = sfc_ev_qstart(evq, sfc_evq_index_by_txq_sw_index(sa, sw_index));
458 if (txq_info->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
459 flags |= EFX_TXQ_CKSUM_IPV4;
461 if (txq_info->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)
462 flags |= EFX_TXQ_CKSUM_INNER_IPV4;
464 if ((txq_info->offloads & DEV_TX_OFFLOAD_TCP_CKSUM) ||
465 (txq_info->offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
466 flags |= EFX_TXQ_CKSUM_TCPUDP;
468 if (offloads_supported & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)
469 flags |= EFX_TXQ_CKSUM_INNER_TCPUDP;
472 if (txq_info->offloads & DEV_TX_OFFLOAD_TCP_TSO)
473 flags |= EFX_TXQ_FATSOV2;
475 rc = efx_tx_qcreate(sa->nic, txq->hw_index, 0, &txq->mem,
476 txq_info->entries, 0 /* not used on EF10 */,
478 &txq->common, &desc_index);
480 if (sa->tso && (rc == ENOSPC))
481 sfc_err(sa, "ran out of TSO contexts");
483 goto fail_tx_qcreate;
486 efx_tx_qenable(txq->common);
488 txq_info->state |= SFC_TXQ_STARTED;
490 rc = sa->priv.dp_tx->qstart(txq_info->dp, evq->read_ptr, desc_index);
495 * It seems to be used by DPDK for debug purposes only ('rte_ether')
497 dev_data = sa->eth_dev->data;
498 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STARTED;
503 txq_info->state = SFC_TXQ_INITIALIZED;
504 efx_tx_qdestroy(txq->common);
514 sfc_tx_qstop(struct sfc_adapter *sa, unsigned int sw_index)
516 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
517 struct rte_eth_dev_data *dev_data;
518 struct sfc_txq_info *txq_info;
520 unsigned int retry_count;
521 unsigned int wait_count;
524 sfc_log_init(sa, "TxQ = %u", sw_index);
526 SFC_ASSERT(sw_index < sas->txq_count);
527 txq_info = &sas->txq_info[sw_index];
529 if (txq_info->state == SFC_TXQ_INITIALIZED)
532 SFC_ASSERT(txq_info->state & SFC_TXQ_STARTED);
534 txq = &sa->txq_ctrl[sw_index];
535 sa->priv.dp_tx->qstop(txq_info->dp, &txq->evq->read_ptr);
538 * Retry TX queue flushing in case of flush failed or
539 * timeout; in the worst case it can delay for 6 seconds
541 for (retry_count = 0;
542 ((txq_info->state & SFC_TXQ_FLUSHED) == 0) &&
543 (retry_count < SFC_TX_QFLUSH_ATTEMPTS);
545 rc = efx_tx_qflush(txq->common);
547 txq_info->state |= (rc == EALREADY) ?
548 SFC_TXQ_FLUSHED : SFC_TXQ_FLUSH_FAILED;
553 * Wait for TX queue flush done or flush failed event at least
554 * SFC_TX_QFLUSH_POLL_WAIT_MS milliseconds and not more
555 * than 2 seconds (SFC_TX_QFLUSH_POLL_WAIT_MS multiplied
556 * by SFC_TX_QFLUSH_POLL_ATTEMPTS)
560 rte_delay_ms(SFC_TX_QFLUSH_POLL_WAIT_MS);
561 sfc_ev_qpoll(txq->evq);
562 } while ((txq_info->state & SFC_TXQ_FLUSHING) &&
563 wait_count++ < SFC_TX_QFLUSH_POLL_ATTEMPTS);
565 if (txq_info->state & SFC_TXQ_FLUSHING)
566 sfc_err(sa, "TxQ %u flush timed out", sw_index);
568 if (txq_info->state & SFC_TXQ_FLUSHED)
569 sfc_notice(sa, "TxQ %u flushed", sw_index);
572 sa->priv.dp_tx->qreap(txq_info->dp);
574 txq_info->state = SFC_TXQ_INITIALIZED;
576 efx_tx_qdestroy(txq->common);
578 sfc_ev_qstop(txq->evq);
581 * It seems to be used by DPDK for debug purposes only ('rte_ether')
583 dev_data = sa->eth_dev->data;
584 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STOPPED;
588 sfc_tx_start(struct sfc_adapter *sa)
590 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
591 unsigned int sw_index;
594 sfc_log_init(sa, "txq_count = %u", sas->txq_count);
597 if (!efx_nic_cfg_get(sa->nic)->enc_fw_assisted_tso_v2_enabled) {
598 sfc_warn(sa, "TSO support was unable to be restored");
603 rc = efx_tx_init(sa->nic);
605 goto fail_efx_tx_init;
607 for (sw_index = 0; sw_index < sas->txq_count; ++sw_index) {
608 if (sas->txq_info[sw_index].state == SFC_TXQ_INITIALIZED &&
609 (!(sas->txq_info[sw_index].deferred_start) ||
610 sas->txq_info[sw_index].deferred_started)) {
611 rc = sfc_tx_qstart(sa, sw_index);
620 while (sw_index-- > 0)
621 sfc_tx_qstop(sa, sw_index);
623 efx_tx_fini(sa->nic);
626 sfc_log_init(sa, "failed (rc = %d)", rc);
631 sfc_tx_stop(struct sfc_adapter *sa)
633 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
634 unsigned int sw_index;
636 sfc_log_init(sa, "txq_count = %u", sas->txq_count);
638 sw_index = sas->txq_count;
639 while (sw_index-- > 0) {
640 if (sas->txq_info[sw_index].state & SFC_TXQ_STARTED)
641 sfc_tx_qstop(sa, sw_index);
644 efx_tx_fini(sa->nic);
648 sfc_efx_tx_reap(struct sfc_efx_txq *txq)
650 unsigned int completed;
652 sfc_ev_qpoll(txq->evq);
654 for (completed = txq->completed;
655 completed != txq->pending; completed++) {
656 struct sfc_efx_tx_sw_desc *txd;
658 txd = &txq->sw_ring[completed & txq->ptr_mask];
660 if (txd->mbuf != NULL) {
661 rte_pktmbuf_free(txd->mbuf);
666 txq->completed = completed;
670 * The function is used to insert or update VLAN tag;
671 * the firmware has state of the firmware tag to insert per TxQ
672 * (controlled by option descriptors), hence, if the tag of the
673 * packet to be sent is different from one remembered by the firmware,
674 * the function will update it
677 sfc_efx_tx_maybe_insert_tag(struct sfc_efx_txq *txq, struct rte_mbuf *m,
680 uint16_t this_tag = ((m->ol_flags & PKT_TX_VLAN_PKT) ?
683 if (this_tag == txq->hw_vlan_tci)
687 * The expression inside SFC_ASSERT() is not desired to be checked in
688 * a non-debug build because it might be too expensive on the data path
690 SFC_ASSERT(efx_nic_cfg_get(txq->evq->sa->nic)->enc_hw_tx_insert_vlan_enabled);
692 efx_tx_qdesc_vlantci_create(txq->common, rte_cpu_to_be_16(this_tag),
695 txq->hw_vlan_tci = this_tag;
701 sfc_efx_prepare_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
704 struct sfc_dp_txq *dp_txq = tx_queue;
705 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
706 const efx_nic_cfg_t *encp = efx_nic_cfg_get(txq->evq->sa->nic);
709 for (i = 0; i < nb_pkts; i++) {
713 * EFX Tx datapath may require extra VLAN descriptor if VLAN
714 * insertion offload is requested regardless the offload
715 * requested/supported.
717 ret = sfc_dp_tx_prepare_pkt(tx_pkts[i],
718 encp->enc_tx_tso_tcp_header_offset_limit,
719 txq->max_fill_level, EFX_TX_FATSOV2_OPT_NDESCS,
721 if (unlikely(ret != 0)) {
731 sfc_efx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
733 struct sfc_dp_txq *dp_txq = (struct sfc_dp_txq *)tx_queue;
734 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
735 unsigned int added = txq->added;
736 unsigned int pushed = added;
737 unsigned int pkts_sent = 0;
738 efx_desc_t *pend = &txq->pend_desc[0];
739 const unsigned int hard_max_fill = txq->max_fill_level;
740 const unsigned int soft_max_fill = hard_max_fill - txq->free_thresh;
741 unsigned int fill_level = added - txq->completed;
744 struct rte_mbuf **pktp;
746 if (unlikely((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) == 0))
750 * If insufficient space for a single packet is present,
751 * we should reap; otherwise, we shouldn't do that all the time
752 * to avoid latency increase
754 reap_done = (fill_level > soft_max_fill);
757 sfc_efx_tx_reap(txq);
759 * Recalculate fill level since 'txq->completed'
760 * might have changed on reap
762 fill_level = added - txq->completed;
765 for (pkts_sent = 0, pktp = &tx_pkts[0];
766 (pkts_sent < nb_pkts) && (fill_level <= soft_max_fill);
767 pkts_sent++, pktp++) {
768 uint16_t hw_vlan_tci_prev = txq->hw_vlan_tci;
769 struct rte_mbuf *m_seg = *pktp;
770 size_t pkt_len = m_seg->pkt_len;
771 unsigned int pkt_descs = 0;
775 * Here VLAN TCI is expected to be zero in case if no
776 * DEV_TX_OFFLOAD_VLAN_INSERT capability is advertised;
777 * if the calling app ignores the absence of
778 * DEV_TX_OFFLOAD_VLAN_INSERT and pushes VLAN TCI, then
779 * TX_ERROR will occur
781 pkt_descs += sfc_efx_tx_maybe_insert_tag(txq, m_seg, &pend);
783 if (m_seg->ol_flags & PKT_TX_TCP_SEG) {
785 * We expect correct 'pkt->l[2, 3, 4]_len' values
786 * to be set correctly by the caller
788 if (sfc_efx_tso_do(txq, added, &m_seg, &in_off, &pend,
789 &pkt_descs, &pkt_len) != 0) {
790 /* We may have reached this place if packet
791 * header linearization is needed but the
792 * header length is greater than
795 * We will deceive RTE saying that we have sent
796 * the packet, but we will actually drop it.
797 * Hence, we should revert 'pend' to the
798 * previous state (in case we have added
799 * VLAN descriptor) and start processing
800 * another one packet. But the original
801 * mbuf shouldn't be orphaned
804 txq->hw_vlan_tci = hw_vlan_tci_prev;
806 rte_pktmbuf_free(*pktp);
812 * We've only added 2 FATSOv2 option descriptors
813 * and 1 descriptor for the linearized packet header.
814 * The outstanding work will be done in the same manner
815 * as for the usual non-TSO path
819 for (; m_seg != NULL; m_seg = m_seg->next) {
820 efsys_dma_addr_t next_frag;
823 seg_len = m_seg->data_len;
824 next_frag = rte_mbuf_data_iova(m_seg);
827 * If we've started TSO transaction few steps earlier,
828 * we'll skip packet header using an offset in the
829 * current segment (which has been set to the
830 * first one containing payload)
837 efsys_dma_addr_t frag_addr = next_frag;
841 * It is assumed here that there is no
842 * limitation on address boundary
843 * crossing by DMA descriptor.
845 frag_len = MIN(seg_len, txq->dma_desc_size_max);
846 next_frag += frag_len;
850 efx_tx_qdesc_dma_create(txq->common,
856 } while (seg_len != 0);
861 fill_level += pkt_descs;
862 if (unlikely(fill_level > hard_max_fill)) {
864 * Our estimation for maximum number of descriptors
865 * required to send a packet seems to be wrong.
866 * Try to reap (if we haven't yet).
869 sfc_efx_tx_reap(txq);
871 fill_level = added - txq->completed;
872 if (fill_level > hard_max_fill) {
874 txq->hw_vlan_tci = hw_vlan_tci_prev;
879 txq->hw_vlan_tci = hw_vlan_tci_prev;
884 /* Assign mbuf to the last used desc */
885 txq->sw_ring[(added - 1) & txq->ptr_mask].mbuf = *pktp;
888 if (likely(pkts_sent > 0)) {
889 rc = efx_tx_qdesc_post(txq->common, txq->pend_desc,
890 pend - &txq->pend_desc[0],
891 txq->completed, &txq->added);
894 if (likely(pushed != txq->added))
895 efx_tx_qpush(txq->common, txq->added, pushed);
898 #if SFC_TX_XMIT_PKTS_REAP_AT_LEAST_ONCE
900 sfc_efx_tx_reap(txq);
907 const struct sfc_dp_tx *
908 sfc_dp_tx_by_dp_txq(const struct sfc_dp_txq *dp_txq)
910 const struct sfc_dp_queue *dpq = &dp_txq->dpq;
911 struct rte_eth_dev *eth_dev;
912 struct sfc_adapter_priv *sap;
914 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
915 eth_dev = &rte_eth_devices[dpq->port_id];
917 sap = sfc_adapter_priv_by_eth_dev(eth_dev);
922 struct sfc_txq_info *
923 sfc_txq_info_by_dp_txq(const struct sfc_dp_txq *dp_txq)
925 const struct sfc_dp_queue *dpq = &dp_txq->dpq;
926 struct rte_eth_dev *eth_dev;
927 struct sfc_adapter_shared *sas;
929 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
930 eth_dev = &rte_eth_devices[dpq->port_id];
932 sas = sfc_adapter_shared_by_eth_dev(eth_dev);
934 SFC_ASSERT(dpq->queue_id < sas->txq_count);
935 return &sas->txq_info[dpq->queue_id];
939 sfc_txq_by_dp_txq(const struct sfc_dp_txq *dp_txq)
941 const struct sfc_dp_queue *dpq = &dp_txq->dpq;
942 struct rte_eth_dev *eth_dev;
943 struct sfc_adapter *sa;
945 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
946 eth_dev = &rte_eth_devices[dpq->port_id];
948 sa = sfc_adapter_by_eth_dev(eth_dev);
950 SFC_ASSERT(dpq->queue_id < sfc_sa2shared(sa)->txq_count);
951 return &sa->txq_ctrl[dpq->queue_id];
954 static sfc_dp_tx_qsize_up_rings_t sfc_efx_tx_qsize_up_rings;
956 sfc_efx_tx_qsize_up_rings(uint16_t nb_tx_desc,
957 __rte_unused struct sfc_dp_tx_hw_limits *limits,
958 unsigned int *txq_entries,
959 unsigned int *evq_entries,
960 unsigned int *txq_max_fill_level)
962 *txq_entries = nb_tx_desc;
963 *evq_entries = nb_tx_desc;
964 *txq_max_fill_level = EFX_TXQ_LIMIT(*txq_entries);
968 static sfc_dp_tx_qcreate_t sfc_efx_tx_qcreate;
970 sfc_efx_tx_qcreate(uint16_t port_id, uint16_t queue_id,
971 const struct rte_pci_addr *pci_addr,
973 const struct sfc_dp_tx_qcreate_info *info,
974 struct sfc_dp_txq **dp_txqp)
976 struct sfc_efx_txq *txq;
977 struct sfc_txq *ctrl_txq;
981 txq = rte_zmalloc_socket("sfc-efx-txq", sizeof(*txq),
982 RTE_CACHE_LINE_SIZE, socket_id);
986 sfc_dp_queue_init(&txq->dp.dpq, port_id, queue_id, pci_addr);
989 txq->pend_desc = rte_calloc_socket("sfc-efx-txq-pend-desc",
990 EFX_TXQ_LIMIT(info->txq_entries),
991 sizeof(*txq->pend_desc), 0,
993 if (txq->pend_desc == NULL)
994 goto fail_pend_desc_alloc;
997 txq->sw_ring = rte_calloc_socket("sfc-efx-txq-sw_ring",
999 sizeof(*txq->sw_ring),
1000 RTE_CACHE_LINE_SIZE, socket_id);
1001 if (txq->sw_ring == NULL)
1002 goto fail_sw_ring_alloc;
1004 ctrl_txq = sfc_txq_by_dp_txq(&txq->dp);
1005 if (ctrl_txq->evq->sa->tso) {
1006 rc = sfc_efx_tso_alloc_tsoh_objs(txq->sw_ring,
1007 info->txq_entries, socket_id);
1009 goto fail_alloc_tsoh_objs;
1012 txq->evq = ctrl_txq->evq;
1013 txq->ptr_mask = info->txq_entries - 1;
1014 txq->max_fill_level = info->max_fill_level;
1015 txq->free_thresh = info->free_thresh;
1016 txq->dma_desc_size_max = info->dma_desc_size_max;
1018 *dp_txqp = &txq->dp;
1021 fail_alloc_tsoh_objs:
1022 rte_free(txq->sw_ring);
1025 rte_free(txq->pend_desc);
1027 fail_pend_desc_alloc:
1034 static sfc_dp_tx_qdestroy_t sfc_efx_tx_qdestroy;
1036 sfc_efx_tx_qdestroy(struct sfc_dp_txq *dp_txq)
1038 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1040 sfc_efx_tso_free_tsoh_objs(txq->sw_ring, txq->ptr_mask + 1);
1041 rte_free(txq->sw_ring);
1042 rte_free(txq->pend_desc);
1046 static sfc_dp_tx_qstart_t sfc_efx_tx_qstart;
1048 sfc_efx_tx_qstart(struct sfc_dp_txq *dp_txq,
1049 __rte_unused unsigned int evq_read_ptr,
1050 unsigned int txq_desc_index)
1052 /* libefx-based datapath is specific to libefx-based PMD */
1053 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1054 struct sfc_txq *ctrl_txq = sfc_txq_by_dp_txq(dp_txq);
1056 txq->common = ctrl_txq->common;
1058 txq->pending = txq->completed = txq->added = txq_desc_index;
1059 txq->hw_vlan_tci = 0;
1061 txq->flags |= (SFC_EFX_TXQ_FLAG_STARTED | SFC_EFX_TXQ_FLAG_RUNNING);
1066 static sfc_dp_tx_qstop_t sfc_efx_tx_qstop;
1068 sfc_efx_tx_qstop(struct sfc_dp_txq *dp_txq,
1069 __rte_unused unsigned int *evq_read_ptr)
1071 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1073 txq->flags &= ~SFC_EFX_TXQ_FLAG_RUNNING;
1076 static sfc_dp_tx_qreap_t sfc_efx_tx_qreap;
1078 sfc_efx_tx_qreap(struct sfc_dp_txq *dp_txq)
1080 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1083 sfc_efx_tx_reap(txq);
1085 for (txds = 0; txds <= txq->ptr_mask; txds++) {
1086 if (txq->sw_ring[txds].mbuf != NULL) {
1087 rte_pktmbuf_free(txq->sw_ring[txds].mbuf);
1088 txq->sw_ring[txds].mbuf = NULL;
1092 txq->flags &= ~SFC_EFX_TXQ_FLAG_STARTED;
1095 static sfc_dp_tx_qdesc_status_t sfc_efx_tx_qdesc_status;
1097 sfc_efx_tx_qdesc_status(struct sfc_dp_txq *dp_txq, uint16_t offset)
1099 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1101 if (unlikely(offset > txq->ptr_mask))
1104 if (unlikely(offset >= txq->max_fill_level))
1105 return RTE_ETH_TX_DESC_UNAVAIL;
1108 * Poll EvQ to derive up-to-date 'txq->pending' figure;
1109 * it is required for the queue to be running, but the
1110 * check is omitted because API design assumes that it
1111 * is the duty of the caller to satisfy all conditions
1113 SFC_ASSERT((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) ==
1114 SFC_EFX_TXQ_FLAG_RUNNING);
1115 sfc_ev_qpoll(txq->evq);
1118 * Ring tail is 'txq->pending', and although descriptors
1119 * between 'txq->completed' and 'txq->pending' are still
1120 * in use by the driver, they should be reported as DONE
1122 if (unlikely(offset < (txq->added - txq->pending)))
1123 return RTE_ETH_TX_DESC_FULL;
1126 * There is no separate return value for unused descriptors;
1127 * the latter will be reported as DONE because genuine DONE
1128 * descriptors will be freed anyway in SW on the next burst
1130 return RTE_ETH_TX_DESC_DONE;
1133 struct sfc_dp_tx sfc_efx_tx = {
1135 .name = SFC_KVARG_DATAPATH_EFX,
1139 .features = SFC_DP_TX_FEAT_VLAN_INSERT |
1140 SFC_DP_TX_FEAT_TSO |
1141 SFC_DP_TX_FEAT_MULTI_POOL |
1142 SFC_DP_TX_FEAT_REFCNT |
1143 SFC_DP_TX_FEAT_MULTI_SEG,
1144 .qsize_up_rings = sfc_efx_tx_qsize_up_rings,
1145 .qcreate = sfc_efx_tx_qcreate,
1146 .qdestroy = sfc_efx_tx_qdestroy,
1147 .qstart = sfc_efx_tx_qstart,
1148 .qstop = sfc_efx_tx_qstop,
1149 .qreap = sfc_efx_tx_qreap,
1150 .qdesc_status = sfc_efx_tx_qdesc_status,
1151 .pkt_prepare = sfc_efx_prepare_pkts,
1152 .pkt_burst = sfc_efx_xmit_pkts,