1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2016 Cavium, Inc
5 #ifndef _THUNDERX_NICVF_H
6 #define _THUNDERX_NICVF_H
8 /* Platform/OS/arch specific abstractions */
12 #include "../nicvf_logs.h"
14 #define nicvf_log_error(s, ...) PMD_DRV_LOG(ERR, s, ##__VA_ARGS__)
16 #define nicvf_log_debug(s, ...) PMD_DRV_LOG(DEBUG, s, ##__VA_ARGS__)
18 #define nicvf_mbox_log(s, ...) PMD_MBOX_LOG(DEBUG, s, ##__VA_ARGS__)
20 #define nicvf_log(s, ...) fprintf(stderr, s, ##__VA_ARGS__)
23 #include <rte_cycles.h>
24 #define nicvf_delay_us(x) rte_delay_us(x)
27 #include <rte_atomic.h>
28 #define nicvf_smp_wmb() rte_smp_wmb()
29 #define nicvf_smp_rmb() rte_smp_rmb()
32 #include <rte_common.h>
33 #define nicvf_min(x, y) RTE_MIN(x, y)
34 #define nicvf_log2_u32(x) rte_log2_u32(x)
37 #include <rte_byteorder.h>
38 #define nicvf_cpu_to_be_64(x) rte_cpu_to_be_64(x)
39 #define nicvf_be_to_cpu_64(x) rte_be_to_cpu_64(x)
41 #define NICVF_BYTE_ORDER RTE_BYTE_ORDER
42 #define NICVF_BIG_ENDIAN RTE_BIG_ENDIAN
43 #define NICVF_LITTLE_ENDIAN RTE_LITTLE_ENDIAN
46 #include <rte_ether.h>
47 #define NICVF_MAC_ADDR_SIZE ETHER_ADDR_LEN
50 #define ether_addr_copy(x, y) memcpy(y, x, ETHER_ADDR_LEN)
53 #define nicvf_addr_write(addr, val) rte_write64_relaxed((val), (void *)(addr))
54 #define nicvf_addr_read(addr) rte_read64_relaxed((void *)(addr))
56 /* ARM64 specific functions */
57 #if defined(RTE_ARCH_ARM64)
58 #define nicvf_prefetch_store_keep(_ptr) ({\
59 asm volatile("prfm pstl1keep, [%x0]\n" : : "r" (_ptr)); })
62 #define NICVF_LOAD_PAIR(reg1, reg2, addr) ({ \
64 "ldp %x[x1], %x[x0], [%x[p1]]" \
65 : [x1]"=r"(reg1), [x0]"=r"(reg2)\
69 #else /* non optimized functions for building on non arm64 arch */
71 #define nicvf_prefetch_store_keep(_ptr) do {} while (0)
73 #define NICVF_LOAD_PAIR(reg1, reg2, addr) \
75 reg1 = nicvf_addr_read((uintptr_t)addr); \
76 reg2 = nicvf_addr_read((uintptr_t)addr + 8); \
82 #include "nicvf_mbox.h"
84 #endif /* _THUNDERX_NICVF_H */