4 * Copyright (C) Cavium networks Ltd. 2016.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of Cavium networks nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include <netinet/in.h>
43 #include <sys/queue.h>
44 #include <sys/timerfd.h>
46 #include <rte_alarm.h>
47 #include <rte_atomic.h>
48 #include <rte_branch_prediction.h>
49 #include <rte_byteorder.h>
50 #include <rte_common.h>
51 #include <rte_cycles.h>
52 #include <rte_debug.h>
55 #include <rte_ether.h>
56 #include <rte_ethdev.h>
57 #include <rte_interrupts.h>
59 #include <rte_memory.h>
60 #include <rte_memzone.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
64 #include <rte_tailq.h>
66 #include "base/nicvf_plat.h"
68 #include "nicvf_ethdev.h"
70 #include "nicvf_logs.h"
73 nicvf_atomic_write_link_status(struct rte_eth_dev *dev,
74 struct rte_eth_link *link)
76 struct rte_eth_link *dst = &dev->data->dev_link;
77 struct rte_eth_link *src = link;
79 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
80 *(uint64_t *)src) == 0)
87 nicvf_set_eth_link_status(struct nicvf *nic, struct rte_eth_link *link)
89 link->link_status = nic->link_up;
90 link->link_duplex = ETH_LINK_AUTONEG;
91 if (nic->duplex == NICVF_HALF_DUPLEX)
92 link->link_duplex = ETH_LINK_HALF_DUPLEX;
93 else if (nic->duplex == NICVF_FULL_DUPLEX)
94 link->link_duplex = ETH_LINK_FULL_DUPLEX;
95 link->link_speed = nic->speed;
96 link->link_autoneg = ETH_LINK_SPEED_AUTONEG;
100 nicvf_interrupt(void *arg)
102 struct nicvf *nic = arg;
104 if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) {
105 if (nic->eth_dev->data->dev_conf.intr_conf.lsc)
106 nicvf_set_eth_link_status(nic,
107 &nic->eth_dev->data->dev_link);
108 _rte_eth_dev_callback_process(nic->eth_dev,
109 RTE_ETH_EVENT_INTR_LSC);
112 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
113 nicvf_interrupt, nic);
117 nicvf_periodic_alarm_start(struct nicvf *nic)
119 return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
120 nicvf_interrupt, nic);
124 nicvf_periodic_alarm_stop(struct nicvf *nic)
126 return rte_eal_alarm_cancel(nicvf_interrupt, nic);
130 * Return 0 means link status changed, -1 means not changed
133 nicvf_dev_link_update(struct rte_eth_dev *dev,
134 int wait_to_complete __rte_unused)
136 struct rte_eth_link link;
137 struct nicvf *nic = nicvf_pmd_priv(dev);
139 PMD_INIT_FUNC_TRACE();
141 memset(&link, 0, sizeof(link));
142 nicvf_set_eth_link_status(nic, &link);
143 return nicvf_atomic_write_link_status(dev, &link);
147 nicvf_dev_get_reg_length(struct rte_eth_dev *dev __rte_unused)
149 return nicvf_reg_get_count();
153 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
155 uint64_t *data = regs->data;
156 struct nicvf *nic = nicvf_pmd_priv(dev);
161 /* Support only full register dump */
162 if ((regs->length == 0) ||
163 (regs->length == (uint32_t)nicvf_reg_get_count())) {
164 regs->version = nic->vendor_id << 16 | nic->device_id;
165 nicvf_reg_dump(nic, data);
172 nicvf_qset_cq_alloc(struct nicvf *nic, struct nicvf_rxq *rxq, uint16_t qidx,
175 const struct rte_memzone *rz;
176 uint32_t ring_size = desc_cnt * sizeof(union cq_entry_t);
178 rz = rte_eth_dma_zone_reserve(nic->eth_dev, "cq_ring", qidx, ring_size,
179 NICVF_CQ_BASE_ALIGN_BYTES, nic->node);
181 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring");
185 memset(rz->addr, 0, ring_size);
187 rxq->phys = rz->phys_addr;
188 rxq->desc = rz->addr;
189 rxq->qlen_mask = desc_cnt - 1;
195 nicvf_rx_queue_reset(struct nicvf_rxq *rxq)
198 rxq->available_space = 0;
199 rxq->recv_buffers = 0;
203 nicvf_dev_rx_queue_release(void *rx_queue)
205 struct nicvf_rxq *rxq = rx_queue;
207 PMD_INIT_FUNC_TRACE();
214 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
215 uint16_t nb_desc, unsigned int socket_id,
216 const struct rte_eth_rxconf *rx_conf,
217 struct rte_mempool *mp)
219 uint16_t rx_free_thresh;
220 struct nicvf_rxq *rxq;
221 struct nicvf *nic = nicvf_pmd_priv(dev);
223 PMD_INIT_FUNC_TRACE();
225 /* Socket id check */
226 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
227 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
228 socket_id, nic->node);
230 /* Mempool memory should be contiguous */
231 if (mp->nb_mem_chunks != 1) {
232 PMD_INIT_LOG(ERR, "Non contiguous mempool, check huge page sz");
236 /* Rx deferred start is not supported */
237 if (rx_conf->rx_deferred_start) {
238 PMD_INIT_LOG(ERR, "Rx deferred start not supported");
242 /* Roundup nb_desc to available qsize and validate max number of desc */
243 nb_desc = nicvf_qsize_cq_roundup(nb_desc);
245 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize");
249 /* Check rx_free_thresh upper bound */
250 rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ?
251 rx_conf->rx_free_thresh :
252 NICVF_DEFAULT_RX_FREE_THRESH);
253 if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH ||
254 rx_free_thresh >= nb_desc * .75) {
255 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d",
260 /* Free memory prior to re-allocation if needed */
261 if (dev->data->rx_queues[qidx] != NULL) {
262 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
264 nicvf_dev_rx_queue_release(dev->data->rx_queues[qidx]);
265 dev->data->rx_queues[qidx] = NULL;
268 /* Allocate rxq memory */
269 rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq),
270 RTE_CACHE_LINE_SIZE, nic->node);
272 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d", qidx);
278 rxq->queue_id = qidx;
279 rxq->port_id = dev->data->port_id;
280 rxq->rx_free_thresh = rx_free_thresh;
281 rxq->rx_drop_en = rx_conf->rx_drop_en;
282 rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS;
283 rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR;
284 rxq->precharge_cnt = 0;
285 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD;
287 /* Alloc completion queue */
288 if (nicvf_qset_cq_alloc(nic, rxq, rxq->queue_id, nb_desc)) {
289 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id);
290 nicvf_dev_rx_queue_release(rxq);
294 nicvf_rx_queue_reset(rxq);
296 PMD_RX_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d) phy=%" PRIx64,
297 qidx, rxq, mp->name, nb_desc,
298 rte_mempool_count(mp), rxq->phys);
300 dev->data->rx_queues[qidx] = rxq;
301 dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
306 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
308 struct nicvf *nic = nicvf_pmd_priv(dev);
310 PMD_INIT_FUNC_TRACE();
312 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
313 dev_info->max_rx_pktlen = NIC_HW_MAX_FRS;
314 dev_info->max_rx_queues = (uint16_t)MAX_RCV_QUEUES_PER_QS;
315 dev_info->max_tx_queues = (uint16_t)MAX_SND_QUEUES_PER_QS;
316 dev_info->max_mac_addrs = 1;
317 dev_info->max_vfs = dev->pci_dev->max_vfs;
319 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
320 dev_info->tx_offload_capa =
321 DEV_TX_OFFLOAD_IPV4_CKSUM |
322 DEV_TX_OFFLOAD_UDP_CKSUM |
323 DEV_TX_OFFLOAD_TCP_CKSUM |
324 DEV_TX_OFFLOAD_TCP_TSO |
325 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
327 dev_info->reta_size = nic->rss_info.rss_size;
328 dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE;
329 dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1;
330 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING)
331 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL;
333 dev_info->default_rxconf = (struct rte_eth_rxconf) {
334 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH,
338 dev_info->default_txconf = (struct rte_eth_txconf) {
339 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH,
341 ETH_TXQ_FLAGS_NOMULTSEGS |
342 ETH_TXQ_FLAGS_NOREFCOUNT |
343 ETH_TXQ_FLAGS_NOMULTMEMP |
344 ETH_TXQ_FLAGS_NOVLANOFFL |
345 ETH_TXQ_FLAGS_NOXSUMSCTP,
350 nicvf_dev_configure(struct rte_eth_dev *dev)
352 struct rte_eth_conf *conf = &dev->data->dev_conf;
353 struct rte_eth_rxmode *rxmode = &conf->rxmode;
354 struct rte_eth_txmode *txmode = &conf->txmode;
355 struct nicvf *nic = nicvf_pmd_priv(dev);
357 PMD_INIT_FUNC_TRACE();
359 if (!rte_eal_has_hugepages()) {
360 PMD_INIT_LOG(INFO, "Huge page is not configured");
364 if (txmode->mq_mode) {
365 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported");
369 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
370 rxmode->mq_mode != ETH_MQ_RX_RSS) {
371 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode);
375 if (!rxmode->hw_strip_crc) {
376 PMD_INIT_LOG(NOTICE, "Can't disable hw crc strip");
377 rxmode->hw_strip_crc = 1;
380 if (rxmode->hw_ip_checksum) {
381 PMD_INIT_LOG(NOTICE, "Rxcksum not supported");
382 rxmode->hw_ip_checksum = 0;
385 if (rxmode->split_hdr_size) {
386 PMD_INIT_LOG(INFO, "Rxmode does not support split header");
390 if (rxmode->hw_vlan_filter) {
391 PMD_INIT_LOG(INFO, "VLAN filter not supported");
395 if (rxmode->hw_vlan_extend) {
396 PMD_INIT_LOG(INFO, "VLAN extended not supported");
400 if (rxmode->enable_lro) {
401 PMD_INIT_LOG(INFO, "LRO not supported");
405 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
406 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported");
410 if (conf->dcb_capability_en) {
411 PMD_INIT_LOG(INFO, "DCB enable not supported");
415 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
416 PMD_INIT_LOG(INFO, "Flow director not supported");
420 PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64,
421 dev->data->port_id, nicvf_hw_cap(nic));
426 /* Initialize and register driver with DPDK Application */
427 static const struct eth_dev_ops nicvf_eth_dev_ops = {
428 .dev_configure = nicvf_dev_configure,
429 .link_update = nicvf_dev_link_update,
430 .dev_infos_get = nicvf_dev_info_get,
431 .rx_queue_setup = nicvf_dev_rx_queue_setup,
432 .rx_queue_release = nicvf_dev_rx_queue_release,
433 .get_reg_length = nicvf_dev_get_reg_length,
434 .get_reg = nicvf_dev_get_regs,
438 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev)
441 struct rte_pci_device *pci_dev;
442 struct nicvf *nic = nicvf_pmd_priv(eth_dev);
444 PMD_INIT_FUNC_TRACE();
446 eth_dev->dev_ops = &nicvf_eth_dev_ops;
448 pci_dev = eth_dev->pci_dev;
449 rte_eth_copy_pci_info(eth_dev, pci_dev);
451 nic->device_id = pci_dev->id.device_id;
452 nic->vendor_id = pci_dev->id.vendor_id;
453 nic->subsystem_device_id = pci_dev->id.subsystem_device_id;
454 nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
455 nic->eth_dev = eth_dev;
457 PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u",
458 pci_dev->id.vendor_id, pci_dev->id.device_id,
459 pci_dev->addr.domain, pci_dev->addr.bus,
460 pci_dev->addr.devid, pci_dev->addr.function);
462 nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr;
463 if (!nic->reg_base) {
464 PMD_INIT_LOG(ERR, "Failed to map BAR0");
469 nicvf_disable_all_interrupts(nic);
471 ret = nicvf_periodic_alarm_start(nic);
473 PMD_INIT_LOG(ERR, "Failed to start period alarm");
477 ret = nicvf_mbox_check_pf_ready(nic);
479 PMD_INIT_LOG(ERR, "Failed to get ready message from PF");
483 "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s",
484 nic->node, nic->vf_id,
485 nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass",
486 nic->sqs_mode ? "true" : "false",
487 nic->loopback_supported ? "true" : "false"
492 PMD_INIT_LOG(INFO, "Unsupported SQS VF detected, Detaching...");
493 /* Detach port by returning Positive error number */
498 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
499 if (eth_dev->data->mac_addrs == NULL) {
500 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr");
504 if (is_zero_ether_addr((struct ether_addr *)nic->mac_addr))
505 eth_random_addr(&nic->mac_addr[0]);
507 ether_addr_copy((struct ether_addr *)nic->mac_addr,
508 ð_dev->data->mac_addrs[0]);
510 ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr);
512 PMD_INIT_LOG(ERR, "Failed to set mac addr");
516 ret = nicvf_base_init(nic);
518 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init");
522 ret = nicvf_mbox_get_rss_size(nic);
524 PMD_INIT_LOG(ERR, "Failed to get rss table size");
528 PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x",
529 eth_dev->data->port_id, nic->vendor_id, nic->device_id,
530 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2],
531 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]);
536 rte_free(eth_dev->data->mac_addrs);
538 nicvf_periodic_alarm_stop(nic);
543 static const struct rte_pci_id pci_id_nicvf_map[] = {
545 .class_id = RTE_CLASS_ANY_ID,
546 .vendor_id = PCI_VENDOR_ID_CAVIUM,
547 .device_id = PCI_DEVICE_ID_THUNDERX_PASS1_NICVF,
548 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
549 .subsystem_device_id = PCI_SUB_DEVICE_ID_THUNDERX_PASS1_NICVF,
552 .class_id = RTE_CLASS_ANY_ID,
553 .vendor_id = PCI_VENDOR_ID_CAVIUM,
554 .device_id = PCI_DEVICE_ID_THUNDERX_PASS2_NICVF,
555 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
556 .subsystem_device_id = PCI_SUB_DEVICE_ID_THUNDERX_PASS2_NICVF,
563 static struct eth_driver rte_nicvf_pmd = {
565 .name = "rte_nicvf_pmd",
566 .id_table = pci_id_nicvf_map,
567 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
569 .eth_dev_init = nicvf_eth_dev_init,
570 .dev_private_size = sizeof(struct nicvf),
574 rte_nicvf_pmd_init(const char *name __rte_unused, const char *para __rte_unused)
576 PMD_INIT_FUNC_TRACE();
577 PMD_INIT_LOG(INFO, "librte_pmd_thunderx nicvf version %s",
578 THUNDERX_NICVF_PMD_VERSION);
580 rte_eth_driver_register(&rte_nicvf_pmd);
584 static struct rte_driver rte_nicvf_driver = {
585 .name = "nicvf_driver",
587 .init = rte_nicvf_pmd_init,
590 PMD_REGISTER_DRIVER(rte_nicvf_driver);