1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2016 Cavium, Inc
14 #include <netinet/in.h>
15 #include <sys/queue.h>
17 #include <rte_alarm.h>
18 #include <rte_atomic.h>
19 #include <rte_branch_prediction.h>
20 #include <rte_byteorder.h>
21 #include <rte_common.h>
22 #include <rte_cycles.h>
23 #include <rte_debug.h>
26 #include <rte_ether.h>
27 #include <rte_ethdev.h>
28 #include <rte_ethdev_pci.h>
29 #include <rte_interrupts.h>
31 #include <rte_memory.h>
32 #include <rte_memzone.h>
33 #include <rte_malloc.h>
34 #include <rte_random.h>
36 #include <rte_bus_pci.h>
37 #include <rte_tailq.h>
39 #include "base/nicvf_plat.h"
41 #include "nicvf_ethdev.h"
42 #include "nicvf_rxtx.h"
43 #include "nicvf_svf.h"
44 #include "nicvf_logs.h"
46 int nicvf_logtype_mbox;
47 int nicvf_logtype_init;
48 int nicvf_logtype_driver;
50 static void nicvf_dev_stop(struct rte_eth_dev *dev);
51 static void nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup);
52 static void nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic,
55 RTE_INIT(nicvf_init_log);
59 nicvf_logtype_mbox = rte_log_register("pmd.nicvf.mbox");
60 if (nicvf_logtype_mbox >= 0)
61 rte_log_set_level(nicvf_logtype_mbox, RTE_LOG_NOTICE);
63 nicvf_logtype_init = rte_log_register("pmd.nicvf.init");
64 if (nicvf_logtype_init >= 0)
65 rte_log_set_level(nicvf_logtype_init, RTE_LOG_NOTICE);
67 nicvf_logtype_driver = rte_log_register("pmd.nicvf.driver");
68 if (nicvf_logtype_driver >= 0)
69 rte_log_set_level(nicvf_logtype_driver, RTE_LOG_NOTICE);
73 nicvf_atomic_write_link_status(struct rte_eth_dev *dev,
74 struct rte_eth_link *link)
76 struct rte_eth_link *dst = &dev->data->dev_link;
77 struct rte_eth_link *src = link;
79 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
80 *(uint64_t *)src) == 0)
87 nicvf_set_eth_link_status(struct nicvf *nic, struct rte_eth_link *link)
89 link->link_status = nic->link_up;
90 link->link_duplex = ETH_LINK_AUTONEG;
91 if (nic->duplex == NICVF_HALF_DUPLEX)
92 link->link_duplex = ETH_LINK_HALF_DUPLEX;
93 else if (nic->duplex == NICVF_FULL_DUPLEX)
94 link->link_duplex = ETH_LINK_FULL_DUPLEX;
95 link->link_speed = nic->speed;
96 link->link_autoneg = ETH_LINK_SPEED_AUTONEG;
100 nicvf_interrupt(void *arg)
102 struct rte_eth_dev *dev = arg;
103 struct nicvf *nic = nicvf_pmd_priv(dev);
105 if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) {
106 if (dev->data->dev_conf.intr_conf.lsc)
107 nicvf_set_eth_link_status(nic, &dev->data->dev_link);
108 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
112 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
113 nicvf_interrupt, dev);
117 nicvf_vf_interrupt(void *arg)
119 struct nicvf *nic = arg;
121 nicvf_reg_poll_interrupts(nic);
123 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
124 nicvf_vf_interrupt, nic);
128 nicvf_periodic_alarm_start(void (fn)(void *), void *arg)
130 return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, fn, arg);
134 nicvf_periodic_alarm_stop(void (fn)(void *), void *arg)
136 return rte_eal_alarm_cancel(fn, arg);
140 * Return 0 means link status changed, -1 means not changed
143 nicvf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
145 #define CHECK_INTERVAL 100 /* 100ms */
146 #define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */
147 struct rte_eth_link link;
148 struct nicvf *nic = nicvf_pmd_priv(dev);
151 PMD_INIT_FUNC_TRACE();
153 if (wait_to_complete) {
154 /* rte_eth_link_get() might need to wait up to 9 seconds */
155 for (i = 0; i < MAX_CHECK_TIME; i++) {
156 memset(&link, 0, sizeof(link));
157 nicvf_set_eth_link_status(nic, &link);
158 if (link.link_status)
160 rte_delay_ms(CHECK_INTERVAL);
163 memset(&link, 0, sizeof(link));
164 nicvf_set_eth_link_status(nic, &link);
166 return nicvf_atomic_write_link_status(dev, &link);
170 nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
172 struct nicvf *nic = nicvf_pmd_priv(dev);
173 uint32_t buffsz, frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
176 PMD_INIT_FUNC_TRACE();
178 if (frame_size > NIC_HW_MAX_FRS)
181 if (frame_size < NIC_HW_MIN_FRS)
184 buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
187 * Refuse mtu that requires the support of scattered packets
188 * when this feature has not been enabled before.
190 if (!dev->data->scattered_rx &&
191 (frame_size + 2 * VLAN_TAG_SIZE > buffsz))
194 /* check <seg size> * <max_seg> >= max_frame */
195 if (dev->data->scattered_rx &&
196 (frame_size + 2 * VLAN_TAG_SIZE > buffsz * NIC_HW_MAX_SEGS))
199 if (frame_size > ETHER_MAX_LEN)
200 dev->data->dev_conf.rxmode.jumbo_frame = 1;
202 dev->data->dev_conf.rxmode.jumbo_frame = 0;
204 if (nicvf_mbox_update_hw_max_frs(nic, frame_size))
207 /* Update max frame size */
208 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)frame_size;
211 for (i = 0; i < nic->sqs_count; i++)
212 nic->snicvf[i]->mtu = mtu;
218 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
220 uint64_t *data = regs->data;
221 struct nicvf *nic = nicvf_pmd_priv(dev);
224 regs->length = nicvf_reg_get_count();
225 regs->width = THUNDERX_REG_BYTES;
229 /* Support only full register dump */
230 if ((regs->length == 0) ||
231 (regs->length == (uint32_t)nicvf_reg_get_count())) {
232 regs->version = nic->vendor_id << 16 | nic->device_id;
233 nicvf_reg_dump(nic, data);
240 nicvf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
243 struct nicvf_hw_rx_qstats rx_qstats;
244 struct nicvf_hw_tx_qstats tx_qstats;
245 struct nicvf_hw_stats port_stats;
246 struct nicvf *nic = nicvf_pmd_priv(dev);
247 uint16_t rx_start, rx_end;
248 uint16_t tx_start, tx_end;
251 /* RX queue indices for the first VF */
252 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
254 /* Reading per RX ring stats */
255 for (qidx = rx_start; qidx <= rx_end; qidx++) {
256 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
259 nicvf_hw_get_rx_qstats(nic, &rx_qstats, qidx);
260 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
261 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
264 /* TX queue indices for the first VF */
265 nicvf_tx_range(dev, nic, &tx_start, &tx_end);
267 /* Reading per TX ring stats */
268 for (qidx = tx_start; qidx <= tx_end; qidx++) {
269 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
272 nicvf_hw_get_tx_qstats(nic, &tx_qstats, qidx);
273 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
274 stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
277 for (i = 0; i < nic->sqs_count; i++) {
278 struct nicvf *snic = nic->snicvf[i];
283 /* RX queue indices for a secondary VF */
284 nicvf_rx_range(dev, snic, &rx_start, &rx_end);
286 /* Reading per RX ring stats */
287 for (qidx = rx_start; qidx <= rx_end; qidx++) {
288 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
291 nicvf_hw_get_rx_qstats(snic, &rx_qstats,
292 qidx % MAX_RCV_QUEUES_PER_QS);
293 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
294 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
297 /* TX queue indices for a secondary VF */
298 nicvf_tx_range(dev, snic, &tx_start, &tx_end);
299 /* Reading per TX ring stats */
300 for (qidx = tx_start; qidx <= tx_end; qidx++) {
301 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
304 nicvf_hw_get_tx_qstats(snic, &tx_qstats,
305 qidx % MAX_SND_QUEUES_PER_QS);
306 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
307 stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
311 nicvf_hw_get_stats(nic, &port_stats);
312 stats->ibytes = port_stats.rx_bytes;
313 stats->ipackets = port_stats.rx_ucast_frames;
314 stats->ipackets += port_stats.rx_bcast_frames;
315 stats->ipackets += port_stats.rx_mcast_frames;
316 stats->ierrors = port_stats.rx_l2_errors;
317 stats->imissed = port_stats.rx_drop_red;
318 stats->imissed += port_stats.rx_drop_overrun;
319 stats->imissed += port_stats.rx_drop_bcast;
320 stats->imissed += port_stats.rx_drop_mcast;
321 stats->imissed += port_stats.rx_drop_l3_bcast;
322 stats->imissed += port_stats.rx_drop_l3_mcast;
324 stats->obytes = port_stats.tx_bytes_ok;
325 stats->opackets = port_stats.tx_ucast_frames_ok;
326 stats->opackets += port_stats.tx_bcast_frames_ok;
327 stats->opackets += port_stats.tx_mcast_frames_ok;
328 stats->oerrors = port_stats.tx_drops;
333 static const uint32_t *
334 nicvf_dev_supported_ptypes_get(struct rte_eth_dev *dev)
337 static uint32_t ptypes[32];
338 struct nicvf *nic = nicvf_pmd_priv(dev);
339 static const uint32_t ptypes_common[] = {
341 RTE_PTYPE_L3_IPV4_EXT,
343 RTE_PTYPE_L3_IPV6_EXT,
348 static const uint32_t ptypes_tunnel[] = {
349 RTE_PTYPE_TUNNEL_GRE,
350 RTE_PTYPE_TUNNEL_GENEVE,
351 RTE_PTYPE_TUNNEL_VXLAN,
352 RTE_PTYPE_TUNNEL_NVGRE,
354 static const uint32_t ptypes_end = RTE_PTYPE_UNKNOWN;
356 copied = sizeof(ptypes_common);
357 memcpy(ptypes, ptypes_common, copied);
358 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
359 memcpy((char *)ptypes + copied, ptypes_tunnel,
360 sizeof(ptypes_tunnel));
361 copied += sizeof(ptypes_tunnel);
364 memcpy((char *)ptypes + copied, &ptypes_end, sizeof(ptypes_end));
365 if (dev->rx_pkt_burst == nicvf_recv_pkts ||
366 dev->rx_pkt_burst == nicvf_recv_pkts_multiseg)
373 nicvf_dev_stats_reset(struct rte_eth_dev *dev)
376 uint16_t rxqs = 0, txqs = 0;
377 struct nicvf *nic = nicvf_pmd_priv(dev);
378 uint16_t rx_start, rx_end;
379 uint16_t tx_start, tx_end;
381 /* Reset all primary nic counters */
382 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
383 for (i = rx_start; i <= rx_end; i++)
384 rxqs |= (0x3 << (i * 2));
386 nicvf_tx_range(dev, nic, &tx_start, &tx_end);
387 for (i = tx_start; i <= tx_end; i++)
388 txqs |= (0x3 << (i * 2));
390 nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, rxqs, txqs);
392 /* Reset secondary nic queue counters */
393 for (i = 0; i < nic->sqs_count; i++) {
394 struct nicvf *snic = nic->snicvf[i];
398 nicvf_rx_range(dev, snic, &rx_start, &rx_end);
399 for (i = rx_start; i <= rx_end; i++)
400 rxqs |= (0x3 << ((i % MAX_CMP_QUEUES_PER_QS) * 2));
402 nicvf_tx_range(dev, snic, &tx_start, &tx_end);
403 for (i = tx_start; i <= tx_end; i++)
404 txqs |= (0x3 << ((i % MAX_SND_QUEUES_PER_QS) * 2));
406 nicvf_mbox_reset_stat_counters(snic, 0, 0, rxqs, txqs);
410 /* Promiscuous mode enabled by default in LMAC to VF 1:1 map configuration */
412 nicvf_dev_promisc_enable(struct rte_eth_dev *dev __rte_unused)
416 static inline uint64_t
417 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss)
419 uint64_t nic_rss = 0;
421 if (ethdev_rss & ETH_RSS_IPV4)
422 nic_rss |= RSS_IP_ENA;
424 if (ethdev_rss & ETH_RSS_IPV6)
425 nic_rss |= RSS_IP_ENA;
427 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_UDP)
428 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
430 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_TCP)
431 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
433 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_UDP)
434 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
436 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_TCP)
437 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
439 if (ethdev_rss & ETH_RSS_PORT)
440 nic_rss |= RSS_L2_EXTENDED_HASH_ENA;
442 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
443 if (ethdev_rss & ETH_RSS_VXLAN)
444 nic_rss |= RSS_TUN_VXLAN_ENA;
446 if (ethdev_rss & ETH_RSS_GENEVE)
447 nic_rss |= RSS_TUN_GENEVE_ENA;
449 if (ethdev_rss & ETH_RSS_NVGRE)
450 nic_rss |= RSS_TUN_NVGRE_ENA;
456 static inline uint64_t
457 nicvf_rss_nic_to_ethdev(struct nicvf *nic, uint64_t nic_rss)
459 uint64_t ethdev_rss = 0;
461 if (nic_rss & RSS_IP_ENA)
462 ethdev_rss |= (ETH_RSS_IPV4 | ETH_RSS_IPV6);
464 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA))
465 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_TCP |
466 ETH_RSS_NONFRAG_IPV6_TCP);
468 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA))
469 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_UDP |
470 ETH_RSS_NONFRAG_IPV6_UDP);
472 if (nic_rss & RSS_L2_EXTENDED_HASH_ENA)
473 ethdev_rss |= ETH_RSS_PORT;
475 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
476 if (nic_rss & RSS_TUN_VXLAN_ENA)
477 ethdev_rss |= ETH_RSS_VXLAN;
479 if (nic_rss & RSS_TUN_GENEVE_ENA)
480 ethdev_rss |= ETH_RSS_GENEVE;
482 if (nic_rss & RSS_TUN_NVGRE_ENA)
483 ethdev_rss |= ETH_RSS_NVGRE;
489 nicvf_dev_reta_query(struct rte_eth_dev *dev,
490 struct rte_eth_rss_reta_entry64 *reta_conf,
493 struct nicvf *nic = nicvf_pmd_priv(dev);
494 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
497 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
498 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
499 "(%d) doesn't match the number hardware can supported "
500 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
504 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
508 /* Copy RETA table */
509 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
510 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
511 if ((reta_conf[i].mask >> j) & 0x01)
512 reta_conf[i].reta[j] = tbl[j];
519 nicvf_dev_reta_update(struct rte_eth_dev *dev,
520 struct rte_eth_rss_reta_entry64 *reta_conf,
523 struct nicvf *nic = nicvf_pmd_priv(dev);
524 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
527 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
528 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
529 "(%d) doesn't match the number hardware can supported "
530 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
534 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
538 /* Copy RETA table */
539 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
540 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
541 if ((reta_conf[i].mask >> j) & 0x01)
542 tbl[j] = reta_conf[i].reta[j];
545 return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
549 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
550 struct rte_eth_rss_conf *rss_conf)
552 struct nicvf *nic = nicvf_pmd_priv(dev);
554 if (rss_conf->rss_key)
555 nicvf_rss_get_key(nic, rss_conf->rss_key);
557 rss_conf->rss_key_len = RSS_HASH_KEY_BYTE_SIZE;
558 rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic));
563 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev,
564 struct rte_eth_rss_conf *rss_conf)
566 struct nicvf *nic = nicvf_pmd_priv(dev);
569 if (rss_conf->rss_key &&
570 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) {
571 RTE_LOG(ERR, PMD, "Hash key size mismatch %d",
572 rss_conf->rss_key_len);
576 if (rss_conf->rss_key)
577 nicvf_rss_set_key(nic, rss_conf->rss_key);
579 nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf);
580 nicvf_rss_set_cfg(nic, nic_rss);
585 nicvf_qset_cq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
586 struct nicvf_rxq *rxq, uint16_t qidx, uint32_t desc_cnt)
588 const struct rte_memzone *rz;
589 uint32_t ring_size = CMP_QUEUE_SZ_MAX * sizeof(union cq_entry_t);
591 rz = rte_eth_dma_zone_reserve(dev, "cq_ring",
592 nicvf_netdev_qidx(nic, qidx), ring_size,
593 NICVF_CQ_BASE_ALIGN_BYTES, nic->node);
595 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring");
599 memset(rz->addr, 0, ring_size);
601 rxq->phys = rz->iova;
602 rxq->desc = rz->addr;
603 rxq->qlen_mask = desc_cnt - 1;
609 nicvf_qset_sq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
610 struct nicvf_txq *sq, uint16_t qidx, uint32_t desc_cnt)
612 const struct rte_memzone *rz;
613 uint32_t ring_size = SND_QUEUE_SZ_MAX * sizeof(union sq_entry_t);
615 rz = rte_eth_dma_zone_reserve(dev, "sq",
616 nicvf_netdev_qidx(nic, qidx), ring_size,
617 NICVF_SQ_BASE_ALIGN_BYTES, nic->node);
619 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring");
623 memset(rz->addr, 0, ring_size);
627 sq->qlen_mask = desc_cnt - 1;
633 nicvf_qset_rbdr_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
634 uint32_t desc_cnt, uint32_t buffsz)
636 struct nicvf_rbdr *rbdr;
637 const struct rte_memzone *rz;
640 assert(nic->rbdr == NULL);
641 rbdr = rte_zmalloc_socket("rbdr", sizeof(struct nicvf_rbdr),
642 RTE_CACHE_LINE_SIZE, nic->node);
644 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr");
648 ring_size = sizeof(struct rbdr_entry_t) * RBDR_QUEUE_SZ_MAX;
649 rz = rte_eth_dma_zone_reserve(dev, "rbdr",
650 nicvf_netdev_qidx(nic, 0), ring_size,
651 NICVF_RBDR_BASE_ALIGN_BYTES, nic->node);
653 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr desc ring");
657 memset(rz->addr, 0, ring_size);
659 rbdr->phys = rz->iova;
662 rbdr->desc = rz->addr;
663 rbdr->buffsz = buffsz;
664 rbdr->qlen_mask = desc_cnt - 1;
666 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_STATUS0;
668 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_DOOR;
675 nicvf_rbdr_release_mbuf(struct rte_eth_dev *dev, struct nicvf *nic,
676 nicvf_iova_addr_t phy)
680 struct nicvf_rxq *rxq;
681 uint16_t rx_start, rx_end;
683 /* Get queue ranges for this VF */
684 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
686 for (qidx = rx_start; qidx <= rx_end; qidx++) {
687 rxq = dev->data->rx_queues[qidx];
688 if (rxq->precharge_cnt) {
689 obj = (void *)nicvf_mbuff_phy2virt(phy,
691 rte_mempool_put(rxq->pool, obj);
692 rxq->precharge_cnt--;
699 nicvf_rbdr_release_mbufs(struct rte_eth_dev *dev, struct nicvf *nic)
701 uint32_t qlen_mask, head;
702 struct rbdr_entry_t *entry;
703 struct nicvf_rbdr *rbdr = nic->rbdr;
705 qlen_mask = rbdr->qlen_mask;
707 while (head != rbdr->tail) {
708 entry = rbdr->desc + head;
709 nicvf_rbdr_release_mbuf(dev, nic, entry->full_addr);
711 head = head & qlen_mask;
716 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq)
721 while (head != txq->tail) {
722 if (txq->txbuffs[head]) {
723 rte_pktmbuf_free_seg(txq->txbuffs[head]);
724 txq->txbuffs[head] = NULL;
727 head = head & txq->qlen_mask;
732 nicvf_tx_queue_reset(struct nicvf_txq *txq)
734 uint32_t txq_desc_cnt = txq->qlen_mask + 1;
736 memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt);
737 memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt);
744 nicvf_vf_start_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
747 struct nicvf_txq *txq;
750 assert(qidx < MAX_SND_QUEUES_PER_QS);
752 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
753 RTE_ETH_QUEUE_STATE_STARTED)
756 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)];
758 ret = nicvf_qset_sq_config(nic, qidx, txq);
760 PMD_INIT_LOG(ERR, "Failed to configure sq VF%d %d %d",
761 nic->vf_id, qidx, ret);
762 goto config_sq_error;
765 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
766 RTE_ETH_QUEUE_STATE_STARTED;
770 nicvf_qset_sq_reclaim(nic, qidx);
775 nicvf_vf_stop_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
778 struct nicvf_txq *txq;
781 assert(qidx < MAX_SND_QUEUES_PER_QS);
783 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
784 RTE_ETH_QUEUE_STATE_STOPPED)
787 ret = nicvf_qset_sq_reclaim(nic, qidx);
789 PMD_INIT_LOG(ERR, "Failed to reclaim sq VF%d %d %d",
790 nic->vf_id, qidx, ret);
792 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)];
793 nicvf_tx_queue_release_mbufs(txq);
794 nicvf_tx_queue_reset(txq);
796 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
797 RTE_ETH_QUEUE_STATE_STOPPED;
802 nicvf_configure_cpi(struct rte_eth_dev *dev)
804 struct nicvf *nic = nicvf_pmd_priv(dev);
808 /* Count started rx queues */
809 for (qidx = qcnt = 0; qidx < dev->data->nb_rx_queues; qidx++)
810 if (dev->data->rx_queue_state[qidx] ==
811 RTE_ETH_QUEUE_STATE_STARTED)
814 nic->cpi_alg = CPI_ALG_NONE;
815 ret = nicvf_mbox_config_cpi(nic, qcnt);
817 PMD_INIT_LOG(ERR, "Failed to configure CPI %d", ret);
823 nicvf_configure_rss(struct rte_eth_dev *dev)
825 struct nicvf *nic = nicvf_pmd_priv(dev);
829 rsshf = nicvf_rss_ethdev_to_nic(nic,
830 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf);
831 PMD_DRV_LOG(INFO, "mode=%d rx_queues=%d loopback=%d rsshf=0x%" PRIx64,
832 dev->data->dev_conf.rxmode.mq_mode,
833 dev->data->nb_rx_queues,
834 dev->data->dev_conf.lpbk_mode, rsshf);
836 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE)
837 ret = nicvf_rss_term(nic);
838 else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
839 ret = nicvf_rss_config(nic, dev->data->nb_rx_queues, rsshf);
841 PMD_INIT_LOG(ERR, "Failed to configure RSS %d", ret);
847 nicvf_configure_rss_reta(struct rte_eth_dev *dev)
849 struct nicvf *nic = nicvf_pmd_priv(dev);
850 unsigned int idx, qmap_size;
851 uint8_t qmap[RTE_MAX_QUEUES_PER_PORT];
852 uint8_t default_reta[NIC_MAX_RSS_IDR_TBL_SIZE];
854 if (nic->cpi_alg != CPI_ALG_NONE)
857 /* Prepare queue map */
858 for (idx = 0, qmap_size = 0; idx < dev->data->nb_rx_queues; idx++) {
859 if (dev->data->rx_queue_state[idx] ==
860 RTE_ETH_QUEUE_STATE_STARTED)
861 qmap[qmap_size++] = idx;
864 /* Update default RSS RETA */
865 for (idx = 0; idx < NIC_MAX_RSS_IDR_TBL_SIZE; idx++)
866 default_reta[idx] = qmap[idx % qmap_size];
868 return nicvf_rss_reta_update(nic, default_reta,
869 NIC_MAX_RSS_IDR_TBL_SIZE);
873 nicvf_dev_tx_queue_release(void *sq)
875 struct nicvf_txq *txq;
877 PMD_INIT_FUNC_TRACE();
879 txq = (struct nicvf_txq *)sq;
881 if (txq->txbuffs != NULL) {
882 nicvf_tx_queue_release_mbufs(txq);
883 rte_free(txq->txbuffs);
891 nicvf_set_tx_function(struct rte_eth_dev *dev)
893 struct nicvf_txq *txq;
895 bool multiseg = false;
897 for (i = 0; i < dev->data->nb_tx_queues; i++) {
898 txq = dev->data->tx_queues[i];
899 if ((txq->txq_flags & ETH_TXQ_FLAGS_NOMULTSEGS) == 0) {
905 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
907 PMD_DRV_LOG(DEBUG, "Using multi-segment tx callback");
908 dev->tx_pkt_burst = nicvf_xmit_pkts_multiseg;
910 PMD_DRV_LOG(DEBUG, "Using single-segment tx callback");
911 dev->tx_pkt_burst = nicvf_xmit_pkts;
914 if (txq->pool_free == nicvf_single_pool_free_xmited_buffers)
915 PMD_DRV_LOG(DEBUG, "Using single-mempool tx free method");
917 PMD_DRV_LOG(DEBUG, "Using multi-mempool tx free method");
921 nicvf_set_rx_function(struct rte_eth_dev *dev)
923 if (dev->data->scattered_rx) {
924 PMD_DRV_LOG(DEBUG, "Using multi-segment rx callback");
925 dev->rx_pkt_burst = nicvf_recv_pkts_multiseg;
927 PMD_DRV_LOG(DEBUG, "Using single-segment rx callback");
928 dev->rx_pkt_burst = nicvf_recv_pkts;
933 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
934 uint16_t nb_desc, unsigned int socket_id,
935 const struct rte_eth_txconf *tx_conf)
937 uint16_t tx_free_thresh;
938 uint8_t is_single_pool;
939 struct nicvf_txq *txq;
940 struct nicvf *nic = nicvf_pmd_priv(dev);
942 PMD_INIT_FUNC_TRACE();
944 if (qidx >= MAX_SND_QUEUES_PER_QS)
945 nic = nic->snicvf[qidx / MAX_SND_QUEUES_PER_QS - 1];
947 qidx = qidx % MAX_SND_QUEUES_PER_QS;
949 /* Socket id check */
950 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
951 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
952 socket_id, nic->node);
954 /* Tx deferred start is not supported */
955 if (tx_conf->tx_deferred_start) {
956 PMD_INIT_LOG(ERR, "Tx deferred start not supported");
960 /* Roundup nb_desc to available qsize and validate max number of desc */
961 nb_desc = nicvf_qsize_sq_roundup(nb_desc);
963 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize");
967 /* Validate tx_free_thresh */
968 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
969 tx_conf->tx_free_thresh :
970 NICVF_DEFAULT_TX_FREE_THRESH);
972 if (tx_free_thresh > (nb_desc) ||
973 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) {
975 "tx_free_thresh must be less than the number of TX "
976 "descriptors. (tx_free_thresh=%u port=%d "
977 "queue=%d)", (unsigned int)tx_free_thresh,
978 (int)dev->data->port_id, (int)qidx);
982 /* Free memory prior to re-allocation if needed. */
983 if (dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) {
984 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
985 nicvf_netdev_qidx(nic, qidx));
986 nicvf_dev_tx_queue_release(
987 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]);
988 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL;
991 /* Allocating tx queue data structure */
992 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq),
993 RTE_CACHE_LINE_SIZE, nic->node);
995 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d",
996 nicvf_netdev_qidx(nic, qidx));
1001 txq->queue_id = qidx;
1002 txq->tx_free_thresh = tx_free_thresh;
1003 txq->txq_flags = tx_conf->txq_flags;
1004 txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD;
1005 txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR;
1006 is_single_pool = (txq->txq_flags & ETH_TXQ_FLAGS_NOREFCOUNT &&
1007 txq->txq_flags & ETH_TXQ_FLAGS_NOMULTMEMP);
1009 /* Choose optimum free threshold value for multipool case */
1010 if (!is_single_pool) {
1011 txq->tx_free_thresh = (uint16_t)
1012 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ?
1013 NICVF_TX_FREE_MPOOL_THRESH :
1014 tx_conf->tx_free_thresh);
1015 txq->pool_free = nicvf_multi_pool_free_xmited_buffers;
1017 txq->pool_free = nicvf_single_pool_free_xmited_buffers;
1020 /* Allocate software ring */
1021 txq->txbuffs = rte_zmalloc_socket("txq->txbuffs",
1022 nb_desc * sizeof(struct rte_mbuf *),
1023 RTE_CACHE_LINE_SIZE, nic->node);
1025 if (txq->txbuffs == NULL) {
1026 nicvf_dev_tx_queue_release(txq);
1030 if (nicvf_qset_sq_alloc(dev, nic, txq, qidx, nb_desc)) {
1031 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx);
1032 nicvf_dev_tx_queue_release(txq);
1036 nicvf_tx_queue_reset(txq);
1038 PMD_TX_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p phys=0x%" PRIx64,
1039 nicvf_netdev_qidx(nic, qidx), txq, nb_desc, txq->desc,
1042 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = txq;
1043 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1044 RTE_ETH_QUEUE_STATE_STOPPED;
1049 nicvf_rx_queue_release_mbufs(struct rte_eth_dev *dev, struct nicvf_rxq *rxq)
1052 uint32_t nb_pkts, released_pkts = 0;
1053 uint32_t refill_cnt = 0;
1054 struct rte_mbuf *rx_pkts[NICVF_MAX_RX_FREE_THRESH];
1056 if (dev->rx_pkt_burst == NULL)
1059 while ((rxq_cnt = nicvf_dev_rx_queue_count(dev,
1060 nicvf_netdev_qidx(rxq->nic, rxq->queue_id)))) {
1061 nb_pkts = dev->rx_pkt_burst(rxq, rx_pkts,
1062 NICVF_MAX_RX_FREE_THRESH);
1063 PMD_DRV_LOG(INFO, "nb_pkts=%d rxq_cnt=%d", nb_pkts, rxq_cnt);
1065 rte_pktmbuf_free_seg(rx_pkts[--nb_pkts]);
1071 refill_cnt += nicvf_dev_rbdr_refill(dev,
1072 nicvf_netdev_qidx(rxq->nic, rxq->queue_id));
1074 PMD_DRV_LOG(INFO, "free_cnt=%d refill_cnt=%d",
1075 released_pkts, refill_cnt);
1079 nicvf_rx_queue_reset(struct nicvf_rxq *rxq)
1082 rxq->available_space = 0;
1083 rxq->recv_buffers = 0;
1087 nicvf_vf_start_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
1090 struct nicvf_rxq *rxq;
1093 assert(qidx < MAX_RCV_QUEUES_PER_QS);
1095 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
1096 RTE_ETH_QUEUE_STATE_STARTED)
1099 /* Update rbdr pointer to all rxq */
1100 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)];
1101 rxq->shared_rbdr = nic->rbdr;
1103 ret = nicvf_qset_rq_config(nic, qidx, rxq);
1105 PMD_INIT_LOG(ERR, "Failed to configure rq VF%d %d %d",
1106 nic->vf_id, qidx, ret);
1107 goto config_rq_error;
1109 ret = nicvf_qset_cq_config(nic, qidx, rxq);
1111 PMD_INIT_LOG(ERR, "Failed to configure cq VF%d %d %d",
1112 nic->vf_id, qidx, ret);
1113 goto config_cq_error;
1116 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1117 RTE_ETH_QUEUE_STATE_STARTED;
1121 nicvf_qset_cq_reclaim(nic, qidx);
1123 nicvf_qset_rq_reclaim(nic, qidx);
1128 nicvf_vf_stop_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
1131 struct nicvf_rxq *rxq;
1132 int ret, other_error;
1134 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
1135 RTE_ETH_QUEUE_STATE_STOPPED)
1138 ret = nicvf_qset_rq_reclaim(nic, qidx);
1140 PMD_INIT_LOG(ERR, "Failed to reclaim rq VF%d %d %d",
1141 nic->vf_id, qidx, ret);
1144 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)];
1145 nicvf_rx_queue_release_mbufs(dev, rxq);
1146 nicvf_rx_queue_reset(rxq);
1148 ret = nicvf_qset_cq_reclaim(nic, qidx);
1150 PMD_INIT_LOG(ERR, "Failed to reclaim cq VF%d %d %d",
1151 nic->vf_id, qidx, ret);
1154 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1155 RTE_ETH_QUEUE_STATE_STOPPED;
1160 nicvf_dev_rx_queue_release(void *rx_queue)
1162 PMD_INIT_FUNC_TRACE();
1168 nicvf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1170 struct nicvf *nic = nicvf_pmd_priv(dev);
1173 if (qidx >= MAX_RCV_QUEUES_PER_QS)
1174 nic = nic->snicvf[(qidx / MAX_RCV_QUEUES_PER_QS - 1)];
1176 qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1178 ret = nicvf_vf_start_rx_queue(dev, nic, qidx);
1182 ret = nicvf_configure_cpi(dev);
1186 return nicvf_configure_rss_reta(dev);
1190 nicvf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1193 struct nicvf *nic = nicvf_pmd_priv(dev);
1195 if (qidx >= MAX_SND_QUEUES_PER_QS)
1196 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1198 qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1200 ret = nicvf_vf_stop_rx_queue(dev, nic, qidx);
1201 ret |= nicvf_configure_cpi(dev);
1202 ret |= nicvf_configure_rss_reta(dev);
1207 nicvf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1209 struct nicvf *nic = nicvf_pmd_priv(dev);
1211 if (qidx >= MAX_SND_QUEUES_PER_QS)
1212 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1214 qidx = qidx % MAX_SND_QUEUES_PER_QS;
1216 return nicvf_vf_start_tx_queue(dev, nic, qidx);
1220 nicvf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1222 struct nicvf *nic = nicvf_pmd_priv(dev);
1224 if (qidx >= MAX_SND_QUEUES_PER_QS)
1225 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1227 qidx = qidx % MAX_SND_QUEUES_PER_QS;
1229 return nicvf_vf_stop_tx_queue(dev, nic, qidx);
1233 nicvf_rxq_mbuf_setup(struct nicvf_rxq *rxq)
1236 struct rte_mbuf mb_def;
1238 RTE_BUILD_BUG_ON(sizeof(union mbuf_initializer) != 8);
1239 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
1240 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
1241 offsetof(struct rte_mbuf, data_off) != 2);
1242 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
1243 offsetof(struct rte_mbuf, data_off) != 4);
1244 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
1245 offsetof(struct rte_mbuf, data_off) != 6);
1247 mb_def.data_off = RTE_PKTMBUF_HEADROOM;
1248 mb_def.port = rxq->port_id;
1249 rte_mbuf_refcnt_set(&mb_def, 1);
1251 /* Prevent compiler reordering: rearm_data covers previous fields */
1252 rte_compiler_barrier();
1253 p = (uintptr_t)&mb_def.rearm_data;
1254 rxq->mbuf_initializer.value = *(uint64_t *)p;
1258 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
1259 uint16_t nb_desc, unsigned int socket_id,
1260 const struct rte_eth_rxconf *rx_conf,
1261 struct rte_mempool *mp)
1263 uint16_t rx_free_thresh;
1264 struct nicvf_rxq *rxq;
1265 struct nicvf *nic = nicvf_pmd_priv(dev);
1267 PMD_INIT_FUNC_TRACE();
1269 if (qidx >= MAX_RCV_QUEUES_PER_QS)
1270 nic = nic->snicvf[qidx / MAX_RCV_QUEUES_PER_QS - 1];
1272 qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1274 /* Socket id check */
1275 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
1276 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
1277 socket_id, nic->node);
1279 /* Mempool memory must be contiguous, so must be one memory segment*/
1280 if (mp->nb_mem_chunks != 1) {
1281 PMD_INIT_LOG(ERR, "Non-contiguous mempool, add more huge pages");
1285 /* Mempool memory must be physically contiguous */
1286 if (mp->flags & MEMPOOL_F_NO_PHYS_CONTIG) {
1287 PMD_INIT_LOG(ERR, "Mempool memory must be physically contiguous");
1291 /* Rx deferred start is not supported */
1292 if (rx_conf->rx_deferred_start) {
1293 PMD_INIT_LOG(ERR, "Rx deferred start not supported");
1297 /* Roundup nb_desc to available qsize and validate max number of desc */
1298 nb_desc = nicvf_qsize_cq_roundup(nb_desc);
1300 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize");
1304 /* Check rx_free_thresh upper bound */
1305 rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ?
1306 rx_conf->rx_free_thresh :
1307 NICVF_DEFAULT_RX_FREE_THRESH);
1308 if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH ||
1309 rx_free_thresh >= nb_desc * .75) {
1310 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d",
1315 /* Free memory prior to re-allocation if needed */
1316 if (dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) {
1317 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1318 nicvf_netdev_qidx(nic, qidx));
1319 nicvf_dev_rx_queue_release(
1320 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]);
1321 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL;
1324 /* Allocate rxq memory */
1325 rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq),
1326 RTE_CACHE_LINE_SIZE, nic->node);
1328 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d",
1329 nicvf_netdev_qidx(nic, qidx));
1335 rxq->queue_id = qidx;
1336 rxq->port_id = dev->data->port_id;
1337 rxq->rx_free_thresh = rx_free_thresh;
1338 rxq->rx_drop_en = rx_conf->rx_drop_en;
1339 rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS;
1340 rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR;
1341 rxq->precharge_cnt = 0;
1343 if (nicvf_hw_cap(nic) & NICVF_CAP_CQE_RX2)
1344 rxq->rbptr_offset = NICVF_CQE_RX2_RBPTR_WORD;
1346 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD;
1348 nicvf_rxq_mbuf_setup(rxq);
1350 /* Alloc completion queue */
1351 if (nicvf_qset_cq_alloc(dev, nic, rxq, rxq->queue_id, nb_desc)) {
1352 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id);
1353 nicvf_dev_rx_queue_release(rxq);
1357 nicvf_rx_queue_reset(rxq);
1359 PMD_RX_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d) phy=%" PRIx64,
1360 nicvf_netdev_qidx(nic, qidx), rxq, mp->name, nb_desc,
1361 rte_mempool_avail_count(mp), rxq->phys);
1363 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = rxq;
1364 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1365 RTE_ETH_QUEUE_STATE_STOPPED;
1370 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1372 struct nicvf *nic = nicvf_pmd_priv(dev);
1373 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1375 PMD_INIT_FUNC_TRACE();
1377 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1379 /* Autonegotiation may be disabled */
1380 dev_info->speed_capa = ETH_LINK_SPEED_FIXED;
1381 dev_info->speed_capa |= ETH_LINK_SPEED_10M | ETH_LINK_SPEED_100M |
1382 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
1383 if (nicvf_hw_version(nic) != PCI_SUB_DEVICE_ID_CN81XX_NICVF)
1384 dev_info->speed_capa |= ETH_LINK_SPEED_40G;
1386 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1387 dev_info->max_rx_pktlen = NIC_HW_MAX_FRS;
1388 dev_info->max_rx_queues =
1389 (uint16_t)MAX_RCV_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1);
1390 dev_info->max_tx_queues =
1391 (uint16_t)MAX_SND_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1);
1392 dev_info->max_mac_addrs = 1;
1393 dev_info->max_vfs = pci_dev->max_vfs;
1395 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1396 dev_info->tx_offload_capa =
1397 DEV_TX_OFFLOAD_IPV4_CKSUM |
1398 DEV_TX_OFFLOAD_UDP_CKSUM |
1399 DEV_TX_OFFLOAD_TCP_CKSUM |
1400 DEV_TX_OFFLOAD_TCP_TSO |
1401 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
1403 dev_info->reta_size = nic->rss_info.rss_size;
1404 dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE;
1405 dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1;
1406 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING)
1407 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL;
1409 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1410 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH,
1414 dev_info->default_txconf = (struct rte_eth_txconf) {
1415 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH,
1417 ETH_TXQ_FLAGS_NOMULTSEGS |
1418 ETH_TXQ_FLAGS_NOREFCOUNT |
1419 ETH_TXQ_FLAGS_NOMULTMEMP |
1420 ETH_TXQ_FLAGS_NOVLANOFFL |
1421 ETH_TXQ_FLAGS_NOXSUMSCTP,
1425 static nicvf_iova_addr_t
1426 rbdr_rte_mempool_get(void *dev, void *opaque)
1430 struct nicvf_rxq *rxq;
1431 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)dev;
1432 struct nicvf *nic = (struct nicvf *)opaque;
1433 uint16_t rx_start, rx_end;
1435 /* Get queue ranges for this VF */
1436 nicvf_rx_range(eth_dev, nic, &rx_start, &rx_end);
1438 for (qidx = rx_start; qidx <= rx_end; qidx++) {
1439 rxq = eth_dev->data->rx_queues[qidx];
1440 /* Maintain equal buffer count across all pools */
1441 if (rxq->precharge_cnt >= rxq->qlen_mask)
1443 rxq->precharge_cnt++;
1444 mbuf = (uintptr_t)rte_pktmbuf_alloc(rxq->pool);
1446 return nicvf_mbuff_virt2phy(mbuf, rxq->mbuf_phys_off);
1452 nicvf_vf_start(struct rte_eth_dev *dev, struct nicvf *nic, uint32_t rbdrsz)
1455 uint16_t qidx, data_off;
1456 uint32_t total_rxq_desc, nb_rbdr_desc, exp_buffs;
1457 uint64_t mbuf_phys_off = 0;
1458 struct nicvf_rxq *rxq;
1459 struct rte_mbuf *mbuf;
1460 uint16_t rx_start, rx_end;
1461 uint16_t tx_start, tx_end;
1463 PMD_INIT_FUNC_TRACE();
1465 /* Userspace process exited without proper shutdown in last run */
1466 if (nicvf_qset_rbdr_active(nic, 0))
1467 nicvf_vf_stop(dev, nic, false);
1469 /* Get queue ranges for this VF */
1470 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
1473 * Thunderx nicvf PMD can support more than one pool per port only when
1474 * 1) Data payload size is same across all the pools in given port
1476 * 2) All mbuffs in the pools are from the same hugepage
1478 * 3) Mbuff metadata size is same across all the pools in given port
1480 * This is to support existing application that uses multiple pool/port.
1481 * But, the purpose of using multipool for QoS will not be addressed.
1485 /* Validate mempool attributes */
1486 for (qidx = rx_start; qidx <= rx_end; qidx++) {
1487 rxq = dev->data->rx_queues[qidx];
1488 rxq->mbuf_phys_off = nicvf_mempool_phy_offset(rxq->pool);
1489 mbuf = rte_pktmbuf_alloc(rxq->pool);
1491 PMD_INIT_LOG(ERR, "Failed allocate mbuf VF%d qid=%d "
1493 nic->vf_id, qidx, rxq->pool->name);
1496 data_off = nicvf_mbuff_meta_length(mbuf);
1497 data_off += RTE_PKTMBUF_HEADROOM;
1498 rte_pktmbuf_free(mbuf);
1500 if (data_off % RTE_CACHE_LINE_SIZE) {
1501 PMD_INIT_LOG(ERR, "%s: unaligned data_off=%d delta=%d",
1502 rxq->pool->name, data_off,
1503 data_off % RTE_CACHE_LINE_SIZE);
1506 rxq->mbuf_phys_off -= data_off;
1508 if (mbuf_phys_off == 0)
1509 mbuf_phys_off = rxq->mbuf_phys_off;
1510 if (mbuf_phys_off != rxq->mbuf_phys_off) {
1511 PMD_INIT_LOG(ERR, "pool params not same,%s VF%d %"
1512 PRIx64, rxq->pool->name, nic->vf_id,
1518 /* Check the level of buffers in the pool */
1520 for (qidx = rx_start; qidx <= rx_end; qidx++) {
1521 rxq = dev->data->rx_queues[qidx];
1522 /* Count total numbers of rxq descs */
1523 total_rxq_desc += rxq->qlen_mask + 1;
1524 exp_buffs = RTE_MEMPOOL_CACHE_MAX_SIZE + rxq->rx_free_thresh;
1525 exp_buffs *= dev->data->nb_rx_queues;
1526 if (rte_mempool_avail_count(rxq->pool) < exp_buffs) {
1527 PMD_INIT_LOG(ERR, "Buff shortage in pool=%s (%d/%d)",
1529 rte_mempool_avail_count(rxq->pool),
1535 /* Check RBDR desc overflow */
1536 ret = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1538 PMD_INIT_LOG(ERR, "Reached RBDR desc limit, reduce nr desc "
1539 "VF%d", nic->vf_id);
1544 ret = nicvf_qset_config(nic);
1546 PMD_INIT_LOG(ERR, "Failed to enable qset %d VF%d", ret,
1551 /* Allocate RBDR and RBDR ring desc */
1552 nb_rbdr_desc = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1553 ret = nicvf_qset_rbdr_alloc(dev, nic, nb_rbdr_desc, rbdrsz);
1555 PMD_INIT_LOG(ERR, "Failed to allocate memory for rbdr alloc "
1556 "VF%d", nic->vf_id);
1560 /* Enable and configure RBDR registers */
1561 ret = nicvf_qset_rbdr_config(nic, 0);
1563 PMD_INIT_LOG(ERR, "Failed to configure rbdr %d VF%d", ret,
1565 goto qset_rbdr_free;
1568 /* Fill rte_mempool buffers in RBDR pool and precharge it */
1569 ret = nicvf_qset_rbdr_precharge(dev, nic, 0, rbdr_rte_mempool_get,
1572 PMD_INIT_LOG(ERR, "Failed to fill rbdr %d VF%d", ret,
1574 goto qset_rbdr_reclaim;
1577 PMD_DRV_LOG(INFO, "Filled %d out of %d entries in RBDR VF%d",
1578 nic->rbdr->tail, nb_rbdr_desc, nic->vf_id);
1580 /* Configure VLAN Strip */
1581 nicvf_vlan_hw_strip(nic, dev->data->dev_conf.rxmode.hw_vlan_strip);
1583 /* Based on the packet type(IPv4 or IPv6), the nicvf HW aligns L3 data
1584 * to the 64bit memory address.
1585 * The alignment creates a hole in mbuf(between the end of headroom and
1586 * packet data start). The new revision of the HW provides an option to
1587 * disable the L3 alignment feature and make mbuf layout looks
1588 * more like other NICs. For better application compatibility, disabling
1589 * l3 alignment feature on the hardware revisions it supports
1591 nicvf_apad_config(nic, false);
1593 /* Get queue ranges for this VF */
1594 nicvf_tx_range(dev, nic, &tx_start, &tx_end);
1596 /* Configure TX queues */
1597 for (qidx = tx_start; qidx <= tx_end; qidx++) {
1598 ret = nicvf_vf_start_tx_queue(dev, nic,
1599 qidx % MAX_SND_QUEUES_PER_QS);
1601 goto start_txq_error;
1604 /* Configure RX queues */
1605 for (qidx = rx_start; qidx <= rx_end; qidx++) {
1606 ret = nicvf_vf_start_rx_queue(dev, nic,
1607 qidx % MAX_RCV_QUEUES_PER_QS);
1609 goto start_rxq_error;
1612 if (!nic->sqs_mode) {
1613 /* Configure CPI algorithm */
1614 ret = nicvf_configure_cpi(dev);
1616 goto start_txq_error;
1618 ret = nicvf_mbox_get_rss_size(nic);
1620 PMD_INIT_LOG(ERR, "Failed to get rss table size");
1621 goto qset_rss_error;
1625 ret = nicvf_configure_rss(dev);
1627 goto qset_rss_error;
1630 /* Done; Let PF make the BGX's RX and TX switches to ON position */
1631 nicvf_mbox_cfg_done(nic);
1635 nicvf_rss_term(nic);
1637 for (qidx = rx_start; qidx <= rx_end; qidx++)
1638 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS);
1640 for (qidx = tx_start; qidx <= tx_end; qidx++)
1641 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS);
1643 nicvf_qset_rbdr_reclaim(nic, 0);
1644 nicvf_rbdr_release_mbufs(dev, nic);
1647 rte_free(nic->rbdr);
1651 nicvf_qset_reclaim(nic);
1656 nicvf_dev_start(struct rte_eth_dev *dev)
1661 struct nicvf *nic = nicvf_pmd_priv(dev);
1662 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
1664 uint32_t buffsz = 0, rbdrsz = 0;
1665 struct rte_pktmbuf_pool_private *mbp_priv;
1666 struct nicvf_rxq *rxq;
1668 PMD_INIT_FUNC_TRACE();
1670 /* This function must be called for a primary device */
1671 assert_primary(nic);
1673 /* Validate RBDR buff size */
1674 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) {
1675 rxq = dev->data->rx_queues[qidx];
1676 mbp_priv = rte_mempool_get_priv(rxq->pool);
1677 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
1679 PMD_INIT_LOG(ERR, "rxbuf size must be multiply of 128");
1684 if (rbdrsz != buffsz) {
1685 PMD_INIT_LOG(ERR, "buffsz not same, qidx=%d (%d/%d)",
1686 qidx, rbdrsz, buffsz);
1691 /* Configure loopback */
1692 ret = nicvf_loopback_config(nic, dev->data->dev_conf.lpbk_mode);
1694 PMD_INIT_LOG(ERR, "Failed to configure loopback %d", ret);
1698 /* Reset all statistics counters attached to this port */
1699 ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, 0xFFFF, 0xFFFF);
1701 PMD_INIT_LOG(ERR, "Failed to reset stat counters %d", ret);
1705 /* Setup scatter mode if needed by jumbo */
1706 if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
1707 2 * VLAN_TAG_SIZE > buffsz)
1708 dev->data->scattered_rx = 1;
1709 if (rx_conf->enable_scatter)
1710 dev->data->scattered_rx = 1;
1712 /* Setup MTU based on max_rx_pkt_len or default */
1713 mtu = dev->data->dev_conf.rxmode.jumbo_frame ?
1714 dev->data->dev_conf.rxmode.max_rx_pkt_len
1715 - ETHER_HDR_LEN - ETHER_CRC_LEN
1718 if (nicvf_dev_set_mtu(dev, mtu)) {
1719 PMD_INIT_LOG(ERR, "Failed to set default mtu size");
1723 ret = nicvf_vf_start(dev, nic, rbdrsz);
1727 for (i = 0; i < nic->sqs_count; i++) {
1728 assert(nic->snicvf[i]);
1730 ret = nicvf_vf_start(dev, nic->snicvf[i], rbdrsz);
1735 /* Configure callbacks based on scatter mode */
1736 nicvf_set_tx_function(dev);
1737 nicvf_set_rx_function(dev);
1743 nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup)
1747 struct nicvf *nic = nicvf_pmd_priv(dev);
1749 PMD_INIT_FUNC_TRACE();
1751 /* Teardown secondary vf first */
1752 for (i = 0; i < nic->sqs_count; i++) {
1753 if (!nic->snicvf[i])
1756 nicvf_vf_stop(dev, nic->snicvf[i], cleanup);
1759 /* Stop the primary VF now */
1760 nicvf_vf_stop(dev, nic, cleanup);
1762 /* Disable loopback */
1763 ret = nicvf_loopback_config(nic, 0);
1765 PMD_INIT_LOG(ERR, "Failed to disable loopback %d", ret);
1767 /* Reclaim CPI configuration */
1768 ret = nicvf_mbox_config_cpi(nic, 0);
1770 PMD_INIT_LOG(ERR, "Failed to reclaim CPI config %d", ret);
1774 nicvf_dev_stop(struct rte_eth_dev *dev)
1776 PMD_INIT_FUNC_TRACE();
1778 nicvf_dev_stop_cleanup(dev, false);
1782 nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, bool cleanup)
1786 uint16_t tx_start, tx_end;
1787 uint16_t rx_start, rx_end;
1789 PMD_INIT_FUNC_TRACE();
1792 /* Let PF make the BGX's RX and TX switches to OFF position */
1793 nicvf_mbox_shutdown(nic);
1796 /* Disable VLAN Strip */
1797 nicvf_vlan_hw_strip(nic, 0);
1799 /* Get queue ranges for this VF */
1800 nicvf_tx_range(dev, nic, &tx_start, &tx_end);
1802 for (qidx = tx_start; qidx <= tx_end; qidx++)
1803 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS);
1805 /* Get queue ranges for this VF */
1806 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
1809 for (qidx = rx_start; qidx <= rx_end; qidx++)
1810 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS);
1813 ret = nicvf_qset_rbdr_reclaim(nic, 0);
1815 PMD_INIT_LOG(ERR, "Failed to reclaim RBDR %d", ret);
1817 /* Move all charged buffers in RBDR back to pool */
1818 if (nic->rbdr != NULL)
1819 nicvf_rbdr_release_mbufs(dev, nic);
1822 ret = nicvf_qset_reclaim(nic);
1824 PMD_INIT_LOG(ERR, "Failed to disable qset %d", ret);
1826 /* Disable all interrupts */
1827 nicvf_disable_all_interrupts(nic);
1829 /* Free RBDR SW structure */
1831 rte_free(nic->rbdr);
1837 nicvf_dev_close(struct rte_eth_dev *dev)
1840 struct nicvf *nic = nicvf_pmd_priv(dev);
1842 PMD_INIT_FUNC_TRACE();
1844 nicvf_dev_stop_cleanup(dev, true);
1845 nicvf_periodic_alarm_stop(nicvf_interrupt, dev);
1847 for (i = 0; i < nic->sqs_count; i++) {
1848 if (!nic->snicvf[i])
1851 nicvf_periodic_alarm_stop(nicvf_vf_interrupt, nic->snicvf[i]);
1856 nicvf_request_sqs(struct nicvf *nic)
1860 assert_primary(nic);
1861 assert(nic->sqs_count > 0);
1862 assert(nic->sqs_count <= MAX_SQS_PER_VF);
1864 /* Set no of Rx/Tx queues in each of the SQsets */
1865 for (i = 0; i < nic->sqs_count; i++) {
1866 if (nicvf_svf_empty())
1867 rte_panic("Cannot assign sufficient number of "
1868 "secondary queues to primary VF%" PRIu8 "\n",
1871 nic->snicvf[i] = nicvf_svf_pop();
1872 nic->snicvf[i]->sqs_id = i;
1875 return nicvf_mbox_request_sqs(nic);
1879 nicvf_dev_configure(struct rte_eth_dev *dev)
1881 struct rte_eth_dev_data *data = dev->data;
1882 struct rte_eth_conf *conf = &data->dev_conf;
1883 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1884 struct rte_eth_txmode *txmode = &conf->txmode;
1885 struct nicvf *nic = nicvf_pmd_priv(dev);
1888 PMD_INIT_FUNC_TRACE();
1890 if (!rte_eal_has_hugepages()) {
1891 PMD_INIT_LOG(INFO, "Huge page is not configured");
1895 if (txmode->mq_mode) {
1896 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported");
1900 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1901 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1902 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode);
1906 if (!rxmode->hw_strip_crc) {
1907 PMD_INIT_LOG(NOTICE, "Can't disable hw crc strip");
1908 rxmode->hw_strip_crc = 1;
1911 if (rxmode->hw_ip_checksum) {
1912 PMD_INIT_LOG(NOTICE, "Rxcksum not supported");
1913 rxmode->hw_ip_checksum = 0;
1916 if (rxmode->split_hdr_size) {
1917 PMD_INIT_LOG(INFO, "Rxmode does not support split header");
1921 if (rxmode->hw_vlan_filter) {
1922 PMD_INIT_LOG(INFO, "VLAN filter not supported");
1926 if (rxmode->hw_vlan_extend) {
1927 PMD_INIT_LOG(INFO, "VLAN extended not supported");
1931 if (rxmode->enable_lro) {
1932 PMD_INIT_LOG(INFO, "LRO not supported");
1936 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1937 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported");
1941 if (conf->dcb_capability_en) {
1942 PMD_INIT_LOG(INFO, "DCB enable not supported");
1946 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1947 PMD_INIT_LOG(INFO, "Flow director not supported");
1951 assert_primary(nic);
1952 NICVF_STATIC_ASSERT(MAX_RCV_QUEUES_PER_QS == MAX_SND_QUEUES_PER_QS);
1953 cqcount = RTE_MAX(data->nb_tx_queues, data->nb_rx_queues);
1954 if (cqcount > MAX_RCV_QUEUES_PER_QS) {
1955 nic->sqs_count = RTE_ALIGN_CEIL(cqcount, MAX_RCV_QUEUES_PER_QS);
1956 nic->sqs_count = (nic->sqs_count / MAX_RCV_QUEUES_PER_QS) - 1;
1961 assert(nic->sqs_count <= MAX_SQS_PER_VF);
1963 if (nic->sqs_count > 0) {
1964 if (nicvf_request_sqs(nic)) {
1965 rte_panic("Cannot assign sufficient number of "
1966 "secondary queues to PORT%d VF%" PRIu8 "\n",
1967 dev->data->port_id, nic->vf_id);
1971 PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64,
1972 dev->data->port_id, nicvf_hw_cap(nic));
1977 /* Initialize and register driver with DPDK Application */
1978 static const struct eth_dev_ops nicvf_eth_dev_ops = {
1979 .dev_configure = nicvf_dev_configure,
1980 .dev_start = nicvf_dev_start,
1981 .dev_stop = nicvf_dev_stop,
1982 .link_update = nicvf_dev_link_update,
1983 .dev_close = nicvf_dev_close,
1984 .stats_get = nicvf_dev_stats_get,
1985 .stats_reset = nicvf_dev_stats_reset,
1986 .promiscuous_enable = nicvf_dev_promisc_enable,
1987 .dev_infos_get = nicvf_dev_info_get,
1988 .dev_supported_ptypes_get = nicvf_dev_supported_ptypes_get,
1989 .mtu_set = nicvf_dev_set_mtu,
1990 .reta_update = nicvf_dev_reta_update,
1991 .reta_query = nicvf_dev_reta_query,
1992 .rss_hash_update = nicvf_dev_rss_hash_update,
1993 .rss_hash_conf_get = nicvf_dev_rss_hash_conf_get,
1994 .rx_queue_start = nicvf_dev_rx_queue_start,
1995 .rx_queue_stop = nicvf_dev_rx_queue_stop,
1996 .tx_queue_start = nicvf_dev_tx_queue_start,
1997 .tx_queue_stop = nicvf_dev_tx_queue_stop,
1998 .rx_queue_setup = nicvf_dev_rx_queue_setup,
1999 .rx_queue_release = nicvf_dev_rx_queue_release,
2000 .rx_queue_count = nicvf_dev_rx_queue_count,
2001 .tx_queue_setup = nicvf_dev_tx_queue_setup,
2002 .tx_queue_release = nicvf_dev_tx_queue_release,
2003 .get_reg = nicvf_dev_get_regs,
2007 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev)
2010 struct rte_pci_device *pci_dev;
2011 struct nicvf *nic = nicvf_pmd_priv(eth_dev);
2013 PMD_INIT_FUNC_TRACE();
2015 eth_dev->dev_ops = &nicvf_eth_dev_ops;
2017 /* For secondary processes, the primary has done all the work */
2018 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2020 /* Setup callbacks for secondary process */
2021 nicvf_set_tx_function(eth_dev);
2022 nicvf_set_rx_function(eth_dev);
2025 /* If nic == NULL than it is secondary function
2026 * so ethdev need to be released by caller */
2031 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2032 rte_eth_copy_pci_info(eth_dev, pci_dev);
2034 nic->device_id = pci_dev->id.device_id;
2035 nic->vendor_id = pci_dev->id.vendor_id;
2036 nic->subsystem_device_id = pci_dev->id.subsystem_device_id;
2037 nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2039 PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u",
2040 pci_dev->id.vendor_id, pci_dev->id.device_id,
2041 pci_dev->addr.domain, pci_dev->addr.bus,
2042 pci_dev->addr.devid, pci_dev->addr.function);
2044 nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr;
2045 if (!nic->reg_base) {
2046 PMD_INIT_LOG(ERR, "Failed to map BAR0");
2051 nicvf_disable_all_interrupts(nic);
2053 ret = nicvf_periodic_alarm_start(nicvf_interrupt, eth_dev);
2055 PMD_INIT_LOG(ERR, "Failed to start period alarm");
2059 ret = nicvf_mbox_check_pf_ready(nic);
2061 PMD_INIT_LOG(ERR, "Failed to get ready message from PF");
2065 "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s",
2066 nic->node, nic->vf_id,
2067 nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass",
2068 nic->sqs_mode ? "true" : "false",
2069 nic->loopback_supported ? "true" : "false"
2073 ret = nicvf_base_init(nic);
2075 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init");
2079 if (nic->sqs_mode) {
2080 /* Push nic to stack of secondary vfs */
2081 nicvf_svf_push(nic);
2083 /* Steal nic pointer from the device for further reuse */
2084 eth_dev->data->dev_private = NULL;
2086 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev);
2087 ret = nicvf_periodic_alarm_start(nicvf_vf_interrupt, nic);
2089 PMD_INIT_LOG(ERR, "Failed to start period alarm");
2093 /* Detach port by returning positive error number */
2097 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2098 if (eth_dev->data->mac_addrs == NULL) {
2099 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr");
2103 if (is_zero_ether_addr((struct ether_addr *)nic->mac_addr))
2104 eth_random_addr(&nic->mac_addr[0]);
2106 ether_addr_copy((struct ether_addr *)nic->mac_addr,
2107 ð_dev->data->mac_addrs[0]);
2109 ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr);
2111 PMD_INIT_LOG(ERR, "Failed to set mac addr");
2115 PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x",
2116 eth_dev->data->port_id, nic->vendor_id, nic->device_id,
2117 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2],
2118 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]);
2123 rte_free(eth_dev->data->mac_addrs);
2125 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev);
2130 static const struct rte_pci_id pci_id_nicvf_map[] = {
2132 .class_id = RTE_CLASS_ANY_ID,
2133 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2134 .device_id = PCI_DEVICE_ID_THUNDERX_CN88XX_PASS1_NICVF,
2135 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2136 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF,
2139 .class_id = RTE_CLASS_ANY_ID,
2140 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2141 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2142 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2143 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF,
2146 .class_id = RTE_CLASS_ANY_ID,
2147 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2148 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2149 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2150 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN81XX_NICVF,
2153 .class_id = RTE_CLASS_ANY_ID,
2154 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2155 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2156 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2157 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN83XX_NICVF,
2164 static int nicvf_eth_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2165 struct rte_pci_device *pci_dev)
2167 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct nicvf),
2168 nicvf_eth_dev_init);
2171 static int nicvf_eth_pci_remove(struct rte_pci_device *pci_dev)
2173 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
2176 static struct rte_pci_driver rte_nicvf_pmd = {
2177 .id_table = pci_id_nicvf_map,
2178 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_KEEP_MAPPED_RES |
2179 RTE_PCI_DRV_INTR_LSC,
2180 .probe = nicvf_eth_pci_probe,
2181 .remove = nicvf_eth_pci_remove,
2184 RTE_PMD_REGISTER_PCI(net_thunderx, rte_nicvf_pmd);
2185 RTE_PMD_REGISTER_PCI_TABLE(net_thunderx, pci_id_nicvf_map);
2186 RTE_PMD_REGISTER_KMOD_DEP(net_thunderx, "* igb_uio | uio_pci_generic | vfio-pci");