4 * Copyright (C) Cavium networks Ltd. 2016.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of Cavium networks nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include <netinet/in.h>
43 #include <sys/queue.h>
45 #include <rte_alarm.h>
46 #include <rte_atomic.h>
47 #include <rte_branch_prediction.h>
48 #include <rte_byteorder.h>
49 #include <rte_common.h>
50 #include <rte_cycles.h>
51 #include <rte_debug.h>
54 #include <rte_ether.h>
55 #include <rte_ethdev.h>
56 #include <rte_ethdev_pci.h>
57 #include <rte_interrupts.h>
59 #include <rte_memory.h>
60 #include <rte_memzone.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
64 #include <rte_tailq.h>
66 #include "base/nicvf_plat.h"
68 #include "nicvf_ethdev.h"
69 #include "nicvf_rxtx.h"
70 #include "nicvf_svf.h"
71 #include "nicvf_logs.h"
73 static void nicvf_dev_stop(struct rte_eth_dev *dev);
74 static void nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup);
75 static void nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic,
79 nicvf_atomic_write_link_status(struct rte_eth_dev *dev,
80 struct rte_eth_link *link)
82 struct rte_eth_link *dst = &dev->data->dev_link;
83 struct rte_eth_link *src = link;
85 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
86 *(uint64_t *)src) == 0)
93 nicvf_set_eth_link_status(struct nicvf *nic, struct rte_eth_link *link)
95 link->link_status = nic->link_up;
96 link->link_duplex = ETH_LINK_AUTONEG;
97 if (nic->duplex == NICVF_HALF_DUPLEX)
98 link->link_duplex = ETH_LINK_HALF_DUPLEX;
99 else if (nic->duplex == NICVF_FULL_DUPLEX)
100 link->link_duplex = ETH_LINK_FULL_DUPLEX;
101 link->link_speed = nic->speed;
102 link->link_autoneg = ETH_LINK_SPEED_AUTONEG;
106 nicvf_interrupt(void *arg)
108 struct rte_eth_dev *dev = arg;
109 struct nicvf *nic = nicvf_pmd_priv(dev);
111 if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) {
112 if (dev->data->dev_conf.intr_conf.lsc)
113 nicvf_set_eth_link_status(nic, &dev->data->dev_link);
114 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
118 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
119 nicvf_interrupt, dev);
123 nicvf_vf_interrupt(void *arg)
125 struct nicvf *nic = arg;
127 nicvf_reg_poll_interrupts(nic);
129 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
130 nicvf_vf_interrupt, nic);
134 nicvf_periodic_alarm_start(void (fn)(void *), void *arg)
136 return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, fn, arg);
140 nicvf_periodic_alarm_stop(void (fn)(void *), void *arg)
142 return rte_eal_alarm_cancel(fn, arg);
146 * Return 0 means link status changed, -1 means not changed
149 nicvf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
151 #define CHECK_INTERVAL 100 /* 100ms */
152 #define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */
153 struct rte_eth_link link;
154 struct nicvf *nic = nicvf_pmd_priv(dev);
157 PMD_INIT_FUNC_TRACE();
159 if (wait_to_complete) {
160 /* rte_eth_link_get() might need to wait up to 9 seconds */
161 for (i = 0; i < MAX_CHECK_TIME; i++) {
162 memset(&link, 0, sizeof(link));
163 nicvf_set_eth_link_status(nic, &link);
164 if (link.link_status)
166 rte_delay_ms(CHECK_INTERVAL);
169 memset(&link, 0, sizeof(link));
170 nicvf_set_eth_link_status(nic, &link);
172 return nicvf_atomic_write_link_status(dev, &link);
176 nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
178 struct nicvf *nic = nicvf_pmd_priv(dev);
179 uint32_t buffsz, frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
182 PMD_INIT_FUNC_TRACE();
184 if (frame_size > NIC_HW_MAX_FRS)
187 if (frame_size < NIC_HW_MIN_FRS)
190 buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
193 * Refuse mtu that requires the support of scattered packets
194 * when this feature has not been enabled before.
196 if (!dev->data->scattered_rx &&
197 (frame_size + 2 * VLAN_TAG_SIZE > buffsz))
200 /* check <seg size> * <max_seg> >= max_frame */
201 if (dev->data->scattered_rx &&
202 (frame_size + 2 * VLAN_TAG_SIZE > buffsz * NIC_HW_MAX_SEGS))
205 if (frame_size > ETHER_MAX_LEN)
206 dev->data->dev_conf.rxmode.jumbo_frame = 1;
208 dev->data->dev_conf.rxmode.jumbo_frame = 0;
210 if (nicvf_mbox_update_hw_max_frs(nic, frame_size))
213 /* Update max frame size */
214 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)frame_size;
217 for (i = 0; i < nic->sqs_count; i++)
218 nic->snicvf[i]->mtu = mtu;
224 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
226 uint64_t *data = regs->data;
227 struct nicvf *nic = nicvf_pmd_priv(dev);
230 regs->length = nicvf_reg_get_count();
231 regs->width = THUNDERX_REG_BYTES;
235 /* Support only full register dump */
236 if ((regs->length == 0) ||
237 (regs->length == (uint32_t)nicvf_reg_get_count())) {
238 regs->version = nic->vendor_id << 16 | nic->device_id;
239 nicvf_reg_dump(nic, data);
246 nicvf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
249 struct nicvf_hw_rx_qstats rx_qstats;
250 struct nicvf_hw_tx_qstats tx_qstats;
251 struct nicvf_hw_stats port_stats;
252 struct nicvf *nic = nicvf_pmd_priv(dev);
253 uint16_t rx_start, rx_end;
254 uint16_t tx_start, tx_end;
257 /* RX queue indices for the first VF */
258 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
260 /* Reading per RX ring stats */
261 for (qidx = rx_start; qidx <= rx_end; qidx++) {
262 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
265 nicvf_hw_get_rx_qstats(nic, &rx_qstats, qidx);
266 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
267 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
270 /* TX queue indices for the first VF */
271 nicvf_tx_range(dev, nic, &tx_start, &tx_end);
273 /* Reading per TX ring stats */
274 for (qidx = tx_start; qidx <= tx_end; qidx++) {
275 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
278 nicvf_hw_get_tx_qstats(nic, &tx_qstats, qidx);
279 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
280 stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
283 for (i = 0; i < nic->sqs_count; i++) {
284 struct nicvf *snic = nic->snicvf[i];
289 /* RX queue indices for a secondary VF */
290 nicvf_rx_range(dev, snic, &rx_start, &rx_end);
292 /* Reading per RX ring stats */
293 for (qidx = rx_start; qidx <= rx_end; qidx++) {
294 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
297 nicvf_hw_get_rx_qstats(snic, &rx_qstats,
298 qidx % MAX_RCV_QUEUES_PER_QS);
299 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
300 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
303 /* TX queue indices for a secondary VF */
304 nicvf_tx_range(dev, snic, &tx_start, &tx_end);
305 /* Reading per TX ring stats */
306 for (qidx = tx_start; qidx <= tx_end; qidx++) {
307 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
310 nicvf_hw_get_tx_qstats(snic, &tx_qstats,
311 qidx % MAX_SND_QUEUES_PER_QS);
312 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
313 stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
317 nicvf_hw_get_stats(nic, &port_stats);
318 stats->ibytes = port_stats.rx_bytes;
319 stats->ipackets = port_stats.rx_ucast_frames;
320 stats->ipackets += port_stats.rx_bcast_frames;
321 stats->ipackets += port_stats.rx_mcast_frames;
322 stats->ierrors = port_stats.rx_l2_errors;
323 stats->imissed = port_stats.rx_drop_red;
324 stats->imissed += port_stats.rx_drop_overrun;
325 stats->imissed += port_stats.rx_drop_bcast;
326 stats->imissed += port_stats.rx_drop_mcast;
327 stats->imissed += port_stats.rx_drop_l3_bcast;
328 stats->imissed += port_stats.rx_drop_l3_mcast;
330 stats->obytes = port_stats.tx_bytes_ok;
331 stats->opackets = port_stats.tx_ucast_frames_ok;
332 stats->opackets += port_stats.tx_bcast_frames_ok;
333 stats->opackets += port_stats.tx_mcast_frames_ok;
334 stats->oerrors = port_stats.tx_drops;
337 static const uint32_t *
338 nicvf_dev_supported_ptypes_get(struct rte_eth_dev *dev)
341 static uint32_t ptypes[32];
342 struct nicvf *nic = nicvf_pmd_priv(dev);
343 static const uint32_t ptypes_common[] = {
345 RTE_PTYPE_L3_IPV4_EXT,
347 RTE_PTYPE_L3_IPV6_EXT,
352 static const uint32_t ptypes_tunnel[] = {
353 RTE_PTYPE_TUNNEL_GRE,
354 RTE_PTYPE_TUNNEL_GENEVE,
355 RTE_PTYPE_TUNNEL_VXLAN,
356 RTE_PTYPE_TUNNEL_NVGRE,
358 static const uint32_t ptypes_end = RTE_PTYPE_UNKNOWN;
360 copied = sizeof(ptypes_common);
361 memcpy(ptypes, ptypes_common, copied);
362 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
363 memcpy((char *)ptypes + copied, ptypes_tunnel,
364 sizeof(ptypes_tunnel));
365 copied += sizeof(ptypes_tunnel);
368 memcpy((char *)ptypes + copied, &ptypes_end, sizeof(ptypes_end));
369 if (dev->rx_pkt_burst == nicvf_recv_pkts ||
370 dev->rx_pkt_burst == nicvf_recv_pkts_multiseg)
377 nicvf_dev_stats_reset(struct rte_eth_dev *dev)
380 uint16_t rxqs = 0, txqs = 0;
381 struct nicvf *nic = nicvf_pmd_priv(dev);
382 uint16_t rx_start, rx_end;
383 uint16_t tx_start, tx_end;
385 /* Reset all primary nic counters */
386 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
387 for (i = rx_start; i <= rx_end; i++)
388 rxqs |= (0x3 << (i * 2));
390 nicvf_tx_range(dev, nic, &tx_start, &tx_end);
391 for (i = tx_start; i <= tx_end; i++)
392 txqs |= (0x3 << (i * 2));
394 nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, rxqs, txqs);
396 /* Reset secondary nic queue counters */
397 for (i = 0; i < nic->sqs_count; i++) {
398 struct nicvf *snic = nic->snicvf[i];
402 nicvf_rx_range(dev, snic, &rx_start, &rx_end);
403 for (i = rx_start; i <= rx_end; i++)
404 rxqs |= (0x3 << ((i % MAX_CMP_QUEUES_PER_QS) * 2));
406 nicvf_tx_range(dev, snic, &tx_start, &tx_end);
407 for (i = tx_start; i <= tx_end; i++)
408 txqs |= (0x3 << ((i % MAX_SND_QUEUES_PER_QS) * 2));
410 nicvf_mbox_reset_stat_counters(snic, 0, 0, rxqs, txqs);
414 /* Promiscuous mode enabled by default in LMAC to VF 1:1 map configuration */
416 nicvf_dev_promisc_enable(struct rte_eth_dev *dev __rte_unused)
420 static inline uint64_t
421 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss)
423 uint64_t nic_rss = 0;
425 if (ethdev_rss & ETH_RSS_IPV4)
426 nic_rss |= RSS_IP_ENA;
428 if (ethdev_rss & ETH_RSS_IPV6)
429 nic_rss |= RSS_IP_ENA;
431 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_UDP)
432 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
434 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_TCP)
435 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
437 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_UDP)
438 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
440 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_TCP)
441 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
443 if (ethdev_rss & ETH_RSS_PORT)
444 nic_rss |= RSS_L2_EXTENDED_HASH_ENA;
446 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
447 if (ethdev_rss & ETH_RSS_VXLAN)
448 nic_rss |= RSS_TUN_VXLAN_ENA;
450 if (ethdev_rss & ETH_RSS_GENEVE)
451 nic_rss |= RSS_TUN_GENEVE_ENA;
453 if (ethdev_rss & ETH_RSS_NVGRE)
454 nic_rss |= RSS_TUN_NVGRE_ENA;
460 static inline uint64_t
461 nicvf_rss_nic_to_ethdev(struct nicvf *nic, uint64_t nic_rss)
463 uint64_t ethdev_rss = 0;
465 if (nic_rss & RSS_IP_ENA)
466 ethdev_rss |= (ETH_RSS_IPV4 | ETH_RSS_IPV6);
468 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA))
469 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_TCP |
470 ETH_RSS_NONFRAG_IPV6_TCP);
472 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA))
473 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_UDP |
474 ETH_RSS_NONFRAG_IPV6_UDP);
476 if (nic_rss & RSS_L2_EXTENDED_HASH_ENA)
477 ethdev_rss |= ETH_RSS_PORT;
479 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
480 if (nic_rss & RSS_TUN_VXLAN_ENA)
481 ethdev_rss |= ETH_RSS_VXLAN;
483 if (nic_rss & RSS_TUN_GENEVE_ENA)
484 ethdev_rss |= ETH_RSS_GENEVE;
486 if (nic_rss & RSS_TUN_NVGRE_ENA)
487 ethdev_rss |= ETH_RSS_NVGRE;
493 nicvf_dev_reta_query(struct rte_eth_dev *dev,
494 struct rte_eth_rss_reta_entry64 *reta_conf,
497 struct nicvf *nic = nicvf_pmd_priv(dev);
498 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
501 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
502 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
503 "(%d) doesn't match the number hardware can supported "
504 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
508 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
512 /* Copy RETA table */
513 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
514 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
515 if ((reta_conf[i].mask >> j) & 0x01)
516 reta_conf[i].reta[j] = tbl[j];
523 nicvf_dev_reta_update(struct rte_eth_dev *dev,
524 struct rte_eth_rss_reta_entry64 *reta_conf,
527 struct nicvf *nic = nicvf_pmd_priv(dev);
528 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
531 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
532 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
533 "(%d) doesn't match the number hardware can supported "
534 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
538 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
542 /* Copy RETA table */
543 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
544 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
545 if ((reta_conf[i].mask >> j) & 0x01)
546 tbl[j] = reta_conf[i].reta[j];
549 return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
553 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
554 struct rte_eth_rss_conf *rss_conf)
556 struct nicvf *nic = nicvf_pmd_priv(dev);
558 if (rss_conf->rss_key)
559 nicvf_rss_get_key(nic, rss_conf->rss_key);
561 rss_conf->rss_key_len = RSS_HASH_KEY_BYTE_SIZE;
562 rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic));
567 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev,
568 struct rte_eth_rss_conf *rss_conf)
570 struct nicvf *nic = nicvf_pmd_priv(dev);
573 if (rss_conf->rss_key &&
574 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) {
575 RTE_LOG(ERR, PMD, "Hash key size mismatch %d",
576 rss_conf->rss_key_len);
580 if (rss_conf->rss_key)
581 nicvf_rss_set_key(nic, rss_conf->rss_key);
583 nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf);
584 nicvf_rss_set_cfg(nic, nic_rss);
589 nicvf_qset_cq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
590 struct nicvf_rxq *rxq, uint16_t qidx, uint32_t desc_cnt)
592 const struct rte_memzone *rz;
593 uint32_t ring_size = CMP_QUEUE_SZ_MAX * sizeof(union cq_entry_t);
595 rz = rte_eth_dma_zone_reserve(dev, "cq_ring",
596 nicvf_netdev_qidx(nic, qidx), ring_size,
597 NICVF_CQ_BASE_ALIGN_BYTES, nic->node);
599 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring");
603 memset(rz->addr, 0, ring_size);
605 rxq->phys = rz->phys_addr;
606 rxq->desc = rz->addr;
607 rxq->qlen_mask = desc_cnt - 1;
613 nicvf_qset_sq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
614 struct nicvf_txq *sq, uint16_t qidx, uint32_t desc_cnt)
616 const struct rte_memzone *rz;
617 uint32_t ring_size = SND_QUEUE_SZ_MAX * sizeof(union sq_entry_t);
619 rz = rte_eth_dma_zone_reserve(dev, "sq",
620 nicvf_netdev_qidx(nic, qidx), ring_size,
621 NICVF_SQ_BASE_ALIGN_BYTES, nic->node);
623 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring");
627 memset(rz->addr, 0, ring_size);
629 sq->phys = rz->phys_addr;
631 sq->qlen_mask = desc_cnt - 1;
637 nicvf_qset_rbdr_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
638 uint32_t desc_cnt, uint32_t buffsz)
640 struct nicvf_rbdr *rbdr;
641 const struct rte_memzone *rz;
644 assert(nic->rbdr == NULL);
645 rbdr = rte_zmalloc_socket("rbdr", sizeof(struct nicvf_rbdr),
646 RTE_CACHE_LINE_SIZE, nic->node);
648 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr");
652 ring_size = sizeof(struct rbdr_entry_t) * RBDR_QUEUE_SZ_MAX;
653 rz = rte_eth_dma_zone_reserve(dev, "rbdr",
654 nicvf_netdev_qidx(nic, 0), ring_size,
655 NICVF_RBDR_BASE_ALIGN_BYTES, nic->node);
657 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr desc ring");
661 memset(rz->addr, 0, ring_size);
663 rbdr->phys = rz->phys_addr;
666 rbdr->desc = rz->addr;
667 rbdr->buffsz = buffsz;
668 rbdr->qlen_mask = desc_cnt - 1;
670 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_STATUS0;
672 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_DOOR;
679 nicvf_rbdr_release_mbuf(struct rte_eth_dev *dev, struct nicvf *nic,
680 nicvf_phys_addr_t phy)
684 struct nicvf_rxq *rxq;
685 uint16_t rx_start, rx_end;
687 /* Get queue ranges for this VF */
688 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
690 for (qidx = rx_start; qidx <= rx_end; qidx++) {
691 rxq = dev->data->rx_queues[qidx];
692 if (rxq->precharge_cnt) {
693 obj = (void *)nicvf_mbuff_phy2virt(phy,
695 rte_mempool_put(rxq->pool, obj);
696 rxq->precharge_cnt--;
703 nicvf_rbdr_release_mbufs(struct rte_eth_dev *dev, struct nicvf *nic)
705 uint32_t qlen_mask, head;
706 struct rbdr_entry_t *entry;
707 struct nicvf_rbdr *rbdr = nic->rbdr;
709 qlen_mask = rbdr->qlen_mask;
711 while (head != rbdr->tail) {
712 entry = rbdr->desc + head;
713 nicvf_rbdr_release_mbuf(dev, nic, entry->full_addr);
715 head = head & qlen_mask;
720 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq)
725 while (head != txq->tail) {
726 if (txq->txbuffs[head]) {
727 rte_pktmbuf_free_seg(txq->txbuffs[head]);
728 txq->txbuffs[head] = NULL;
731 head = head & txq->qlen_mask;
736 nicvf_tx_queue_reset(struct nicvf_txq *txq)
738 uint32_t txq_desc_cnt = txq->qlen_mask + 1;
740 memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt);
741 memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt);
748 nicvf_vf_start_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
751 struct nicvf_txq *txq;
754 assert(qidx < MAX_SND_QUEUES_PER_QS);
756 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
757 RTE_ETH_QUEUE_STATE_STARTED)
760 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)];
762 ret = nicvf_qset_sq_config(nic, qidx, txq);
764 PMD_INIT_LOG(ERR, "Failed to configure sq VF%d %d %d",
765 nic->vf_id, qidx, ret);
766 goto config_sq_error;
769 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
770 RTE_ETH_QUEUE_STATE_STARTED;
774 nicvf_qset_sq_reclaim(nic, qidx);
779 nicvf_vf_stop_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
782 struct nicvf_txq *txq;
785 assert(qidx < MAX_SND_QUEUES_PER_QS);
787 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
788 RTE_ETH_QUEUE_STATE_STOPPED)
791 ret = nicvf_qset_sq_reclaim(nic, qidx);
793 PMD_INIT_LOG(ERR, "Failed to reclaim sq VF%d %d %d",
794 nic->vf_id, qidx, ret);
796 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)];
797 nicvf_tx_queue_release_mbufs(txq);
798 nicvf_tx_queue_reset(txq);
800 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
801 RTE_ETH_QUEUE_STATE_STOPPED;
806 nicvf_configure_cpi(struct rte_eth_dev *dev)
808 struct nicvf *nic = nicvf_pmd_priv(dev);
812 /* Count started rx queues */
813 for (qidx = qcnt = 0; qidx < dev->data->nb_rx_queues; qidx++)
814 if (dev->data->rx_queue_state[qidx] ==
815 RTE_ETH_QUEUE_STATE_STARTED)
818 nic->cpi_alg = CPI_ALG_NONE;
819 ret = nicvf_mbox_config_cpi(nic, qcnt);
821 PMD_INIT_LOG(ERR, "Failed to configure CPI %d", ret);
827 nicvf_configure_rss(struct rte_eth_dev *dev)
829 struct nicvf *nic = nicvf_pmd_priv(dev);
833 rsshf = nicvf_rss_ethdev_to_nic(nic,
834 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf);
835 PMD_DRV_LOG(INFO, "mode=%d rx_queues=%d loopback=%d rsshf=0x%" PRIx64,
836 dev->data->dev_conf.rxmode.mq_mode,
837 dev->data->nb_rx_queues,
838 dev->data->dev_conf.lpbk_mode, rsshf);
840 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE)
841 ret = nicvf_rss_term(nic);
842 else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
843 ret = nicvf_rss_config(nic, dev->data->nb_rx_queues, rsshf);
845 PMD_INIT_LOG(ERR, "Failed to configure RSS %d", ret);
851 nicvf_configure_rss_reta(struct rte_eth_dev *dev)
853 struct nicvf *nic = nicvf_pmd_priv(dev);
854 unsigned int idx, qmap_size;
855 uint8_t qmap[RTE_MAX_QUEUES_PER_PORT];
856 uint8_t default_reta[NIC_MAX_RSS_IDR_TBL_SIZE];
858 if (nic->cpi_alg != CPI_ALG_NONE)
861 /* Prepare queue map */
862 for (idx = 0, qmap_size = 0; idx < dev->data->nb_rx_queues; idx++) {
863 if (dev->data->rx_queue_state[idx] ==
864 RTE_ETH_QUEUE_STATE_STARTED)
865 qmap[qmap_size++] = idx;
868 /* Update default RSS RETA */
869 for (idx = 0; idx < NIC_MAX_RSS_IDR_TBL_SIZE; idx++)
870 default_reta[idx] = qmap[idx % qmap_size];
872 return nicvf_rss_reta_update(nic, default_reta,
873 NIC_MAX_RSS_IDR_TBL_SIZE);
877 nicvf_dev_tx_queue_release(void *sq)
879 struct nicvf_txq *txq;
881 PMD_INIT_FUNC_TRACE();
883 txq = (struct nicvf_txq *)sq;
885 if (txq->txbuffs != NULL) {
886 nicvf_tx_queue_release_mbufs(txq);
887 rte_free(txq->txbuffs);
895 nicvf_set_tx_function(struct rte_eth_dev *dev)
897 struct nicvf_txq *txq;
899 bool multiseg = false;
901 for (i = 0; i < dev->data->nb_tx_queues; i++) {
902 txq = dev->data->tx_queues[i];
903 if ((txq->txq_flags & ETH_TXQ_FLAGS_NOMULTSEGS) == 0) {
909 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
911 PMD_DRV_LOG(DEBUG, "Using multi-segment tx callback");
912 dev->tx_pkt_burst = nicvf_xmit_pkts_multiseg;
914 PMD_DRV_LOG(DEBUG, "Using single-segment tx callback");
915 dev->tx_pkt_burst = nicvf_xmit_pkts;
918 if (txq->pool_free == nicvf_single_pool_free_xmited_buffers)
919 PMD_DRV_LOG(DEBUG, "Using single-mempool tx free method");
921 PMD_DRV_LOG(DEBUG, "Using multi-mempool tx free method");
925 nicvf_set_rx_function(struct rte_eth_dev *dev)
927 if (dev->data->scattered_rx) {
928 PMD_DRV_LOG(DEBUG, "Using multi-segment rx callback");
929 dev->rx_pkt_burst = nicvf_recv_pkts_multiseg;
931 PMD_DRV_LOG(DEBUG, "Using single-segment rx callback");
932 dev->rx_pkt_burst = nicvf_recv_pkts;
937 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
938 uint16_t nb_desc, unsigned int socket_id,
939 const struct rte_eth_txconf *tx_conf)
941 uint16_t tx_free_thresh;
942 uint8_t is_single_pool;
943 struct nicvf_txq *txq;
944 struct nicvf *nic = nicvf_pmd_priv(dev);
946 PMD_INIT_FUNC_TRACE();
948 if (qidx >= MAX_SND_QUEUES_PER_QS)
949 nic = nic->snicvf[qidx / MAX_SND_QUEUES_PER_QS - 1];
951 qidx = qidx % MAX_SND_QUEUES_PER_QS;
953 /* Socket id check */
954 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
955 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
956 socket_id, nic->node);
958 /* Tx deferred start is not supported */
959 if (tx_conf->tx_deferred_start) {
960 PMD_INIT_LOG(ERR, "Tx deferred start not supported");
964 /* Roundup nb_desc to available qsize and validate max number of desc */
965 nb_desc = nicvf_qsize_sq_roundup(nb_desc);
967 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize");
971 /* Validate tx_free_thresh */
972 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
973 tx_conf->tx_free_thresh :
974 NICVF_DEFAULT_TX_FREE_THRESH);
976 if (tx_free_thresh > (nb_desc) ||
977 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) {
979 "tx_free_thresh must be less than the number of TX "
980 "descriptors. (tx_free_thresh=%u port=%d "
981 "queue=%d)", (unsigned int)tx_free_thresh,
982 (int)dev->data->port_id, (int)qidx);
986 /* Free memory prior to re-allocation if needed. */
987 if (dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) {
988 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
989 nicvf_netdev_qidx(nic, qidx));
990 nicvf_dev_tx_queue_release(
991 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]);
992 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL;
995 /* Allocating tx queue data structure */
996 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq),
997 RTE_CACHE_LINE_SIZE, nic->node);
999 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d",
1000 nicvf_netdev_qidx(nic, qidx));
1005 txq->queue_id = qidx;
1006 txq->tx_free_thresh = tx_free_thresh;
1007 txq->txq_flags = tx_conf->txq_flags;
1008 txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD;
1009 txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR;
1010 is_single_pool = (txq->txq_flags & ETH_TXQ_FLAGS_NOREFCOUNT &&
1011 txq->txq_flags & ETH_TXQ_FLAGS_NOMULTMEMP);
1013 /* Choose optimum free threshold value for multipool case */
1014 if (!is_single_pool) {
1015 txq->tx_free_thresh = (uint16_t)
1016 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ?
1017 NICVF_TX_FREE_MPOOL_THRESH :
1018 tx_conf->tx_free_thresh);
1019 txq->pool_free = nicvf_multi_pool_free_xmited_buffers;
1021 txq->pool_free = nicvf_single_pool_free_xmited_buffers;
1024 /* Allocate software ring */
1025 txq->txbuffs = rte_zmalloc_socket("txq->txbuffs",
1026 nb_desc * sizeof(struct rte_mbuf *),
1027 RTE_CACHE_LINE_SIZE, nic->node);
1029 if (txq->txbuffs == NULL) {
1030 nicvf_dev_tx_queue_release(txq);
1034 if (nicvf_qset_sq_alloc(dev, nic, txq, qidx, nb_desc)) {
1035 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx);
1036 nicvf_dev_tx_queue_release(txq);
1040 nicvf_tx_queue_reset(txq);
1042 PMD_TX_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p phys=0x%" PRIx64,
1043 nicvf_netdev_qidx(nic, qidx), txq, nb_desc, txq->desc,
1046 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = txq;
1047 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1048 RTE_ETH_QUEUE_STATE_STOPPED;
1053 nicvf_rx_queue_release_mbufs(struct rte_eth_dev *dev, struct nicvf_rxq *rxq)
1056 uint32_t nb_pkts, released_pkts = 0;
1057 uint32_t refill_cnt = 0;
1058 struct rte_mbuf *rx_pkts[NICVF_MAX_RX_FREE_THRESH];
1060 if (dev->rx_pkt_burst == NULL)
1063 while ((rxq_cnt = nicvf_dev_rx_queue_count(dev,
1064 nicvf_netdev_qidx(rxq->nic, rxq->queue_id)))) {
1065 nb_pkts = dev->rx_pkt_burst(rxq, rx_pkts,
1066 NICVF_MAX_RX_FREE_THRESH);
1067 PMD_DRV_LOG(INFO, "nb_pkts=%d rxq_cnt=%d", nb_pkts, rxq_cnt);
1069 rte_pktmbuf_free_seg(rx_pkts[--nb_pkts]);
1075 refill_cnt += nicvf_dev_rbdr_refill(dev,
1076 nicvf_netdev_qidx(rxq->nic, rxq->queue_id));
1078 PMD_DRV_LOG(INFO, "free_cnt=%d refill_cnt=%d",
1079 released_pkts, refill_cnt);
1083 nicvf_rx_queue_reset(struct nicvf_rxq *rxq)
1086 rxq->available_space = 0;
1087 rxq->recv_buffers = 0;
1091 nicvf_vf_start_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
1094 struct nicvf_rxq *rxq;
1097 assert(qidx < MAX_RCV_QUEUES_PER_QS);
1099 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
1100 RTE_ETH_QUEUE_STATE_STARTED)
1103 /* Update rbdr pointer to all rxq */
1104 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)];
1105 rxq->shared_rbdr = nic->rbdr;
1107 ret = nicvf_qset_rq_config(nic, qidx, rxq);
1109 PMD_INIT_LOG(ERR, "Failed to configure rq VF%d %d %d",
1110 nic->vf_id, qidx, ret);
1111 goto config_rq_error;
1113 ret = nicvf_qset_cq_config(nic, qidx, rxq);
1115 PMD_INIT_LOG(ERR, "Failed to configure cq VF%d %d %d",
1116 nic->vf_id, qidx, ret);
1117 goto config_cq_error;
1120 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1121 RTE_ETH_QUEUE_STATE_STARTED;
1125 nicvf_qset_cq_reclaim(nic, qidx);
1127 nicvf_qset_rq_reclaim(nic, qidx);
1132 nicvf_vf_stop_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
1135 struct nicvf_rxq *rxq;
1136 int ret, other_error;
1138 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
1139 RTE_ETH_QUEUE_STATE_STOPPED)
1142 ret = nicvf_qset_rq_reclaim(nic, qidx);
1144 PMD_INIT_LOG(ERR, "Failed to reclaim rq VF%d %d %d",
1145 nic->vf_id, qidx, ret);
1148 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)];
1149 nicvf_rx_queue_release_mbufs(dev, rxq);
1150 nicvf_rx_queue_reset(rxq);
1152 ret = nicvf_qset_cq_reclaim(nic, qidx);
1154 PMD_INIT_LOG(ERR, "Failed to reclaim cq VF%d %d %d",
1155 nic->vf_id, qidx, ret);
1158 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1159 RTE_ETH_QUEUE_STATE_STOPPED;
1164 nicvf_dev_rx_queue_release(void *rx_queue)
1166 PMD_INIT_FUNC_TRACE();
1172 nicvf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1174 struct nicvf *nic = nicvf_pmd_priv(dev);
1177 if (qidx >= MAX_RCV_QUEUES_PER_QS)
1178 nic = nic->snicvf[(qidx / MAX_RCV_QUEUES_PER_QS - 1)];
1180 qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1182 ret = nicvf_vf_start_rx_queue(dev, nic, qidx);
1186 ret = nicvf_configure_cpi(dev);
1190 return nicvf_configure_rss_reta(dev);
1194 nicvf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1197 struct nicvf *nic = nicvf_pmd_priv(dev);
1199 if (qidx >= MAX_SND_QUEUES_PER_QS)
1200 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1202 qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1204 ret = nicvf_vf_stop_rx_queue(dev, nic, qidx);
1205 ret |= nicvf_configure_cpi(dev);
1206 ret |= nicvf_configure_rss_reta(dev);
1211 nicvf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1213 struct nicvf *nic = nicvf_pmd_priv(dev);
1215 if (qidx >= MAX_SND_QUEUES_PER_QS)
1216 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1218 qidx = qidx % MAX_SND_QUEUES_PER_QS;
1220 return nicvf_vf_start_tx_queue(dev, nic, qidx);
1224 nicvf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1226 struct nicvf *nic = nicvf_pmd_priv(dev);
1228 if (qidx >= MAX_SND_QUEUES_PER_QS)
1229 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1231 qidx = qidx % MAX_SND_QUEUES_PER_QS;
1233 return nicvf_vf_stop_tx_queue(dev, nic, qidx);
1237 nicvf_rxq_mbuf_setup(struct nicvf_rxq *rxq)
1240 struct rte_mbuf mb_def;
1242 RTE_BUILD_BUG_ON(sizeof(union mbuf_initializer) != 8);
1243 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
1244 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
1245 offsetof(struct rte_mbuf, data_off) != 2);
1246 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
1247 offsetof(struct rte_mbuf, data_off) != 4);
1248 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
1249 offsetof(struct rte_mbuf, data_off) != 6);
1251 mb_def.data_off = RTE_PKTMBUF_HEADROOM;
1252 mb_def.port = rxq->port_id;
1253 rte_mbuf_refcnt_set(&mb_def, 1);
1255 /* Prevent compiler reordering: rearm_data covers previous fields */
1256 rte_compiler_barrier();
1257 p = (uintptr_t)&mb_def.rearm_data;
1258 rxq->mbuf_initializer.value = *(uint64_t *)p;
1262 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
1263 uint16_t nb_desc, unsigned int socket_id,
1264 const struct rte_eth_rxconf *rx_conf,
1265 struct rte_mempool *mp)
1267 uint16_t rx_free_thresh;
1268 struct nicvf_rxq *rxq;
1269 struct nicvf *nic = nicvf_pmd_priv(dev);
1271 PMD_INIT_FUNC_TRACE();
1273 if (qidx >= MAX_RCV_QUEUES_PER_QS)
1274 nic = nic->snicvf[qidx / MAX_RCV_QUEUES_PER_QS - 1];
1276 qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1278 /* Socket id check */
1279 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
1280 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
1281 socket_id, nic->node);
1283 /* Mempool memory must be contiguous, so must be one memory segment*/
1284 if (mp->nb_mem_chunks != 1) {
1285 PMD_INIT_LOG(ERR, "Non-contiguous mempool, add more huge pages");
1289 /* Mempool memory must be physically contiguous */
1290 if (mp->flags & MEMPOOL_F_NO_PHYS_CONTIG) {
1291 PMD_INIT_LOG(ERR, "Mempool memory must be physically contiguous");
1295 /* Rx deferred start is not supported */
1296 if (rx_conf->rx_deferred_start) {
1297 PMD_INIT_LOG(ERR, "Rx deferred start not supported");
1301 /* Roundup nb_desc to available qsize and validate max number of desc */
1302 nb_desc = nicvf_qsize_cq_roundup(nb_desc);
1304 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize");
1308 /* Check rx_free_thresh upper bound */
1309 rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ?
1310 rx_conf->rx_free_thresh :
1311 NICVF_DEFAULT_RX_FREE_THRESH);
1312 if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH ||
1313 rx_free_thresh >= nb_desc * .75) {
1314 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d",
1319 /* Free memory prior to re-allocation if needed */
1320 if (dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) {
1321 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1322 nicvf_netdev_qidx(nic, qidx));
1323 nicvf_dev_rx_queue_release(
1324 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]);
1325 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL;
1328 /* Allocate rxq memory */
1329 rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq),
1330 RTE_CACHE_LINE_SIZE, nic->node);
1332 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d",
1333 nicvf_netdev_qidx(nic, qidx));
1339 rxq->queue_id = qidx;
1340 rxq->port_id = dev->data->port_id;
1341 rxq->rx_free_thresh = rx_free_thresh;
1342 rxq->rx_drop_en = rx_conf->rx_drop_en;
1343 rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS;
1344 rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR;
1345 rxq->precharge_cnt = 0;
1347 if (nicvf_hw_cap(nic) & NICVF_CAP_CQE_RX2)
1348 rxq->rbptr_offset = NICVF_CQE_RX2_RBPTR_WORD;
1350 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD;
1352 nicvf_rxq_mbuf_setup(rxq);
1354 /* Alloc completion queue */
1355 if (nicvf_qset_cq_alloc(dev, nic, rxq, rxq->queue_id, nb_desc)) {
1356 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id);
1357 nicvf_dev_rx_queue_release(rxq);
1361 nicvf_rx_queue_reset(rxq);
1363 PMD_RX_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d) phy=%" PRIx64,
1364 nicvf_netdev_qidx(nic, qidx), rxq, mp->name, nb_desc,
1365 rte_mempool_avail_count(mp), rxq->phys);
1367 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = rxq;
1368 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1369 RTE_ETH_QUEUE_STATE_STOPPED;
1374 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1376 struct nicvf *nic = nicvf_pmd_priv(dev);
1377 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1379 PMD_INIT_FUNC_TRACE();
1381 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1383 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1384 dev_info->max_rx_pktlen = NIC_HW_MAX_FRS;
1385 dev_info->max_rx_queues =
1386 (uint16_t)MAX_RCV_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1);
1387 dev_info->max_tx_queues =
1388 (uint16_t)MAX_SND_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1);
1389 dev_info->max_mac_addrs = 1;
1390 dev_info->max_vfs = pci_dev->max_vfs;
1392 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1393 dev_info->tx_offload_capa =
1394 DEV_TX_OFFLOAD_IPV4_CKSUM |
1395 DEV_TX_OFFLOAD_UDP_CKSUM |
1396 DEV_TX_OFFLOAD_TCP_CKSUM |
1397 DEV_TX_OFFLOAD_TCP_TSO |
1398 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
1400 dev_info->reta_size = nic->rss_info.rss_size;
1401 dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE;
1402 dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1;
1403 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING)
1404 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL;
1406 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1407 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH,
1411 dev_info->default_txconf = (struct rte_eth_txconf) {
1412 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH,
1414 ETH_TXQ_FLAGS_NOMULTSEGS |
1415 ETH_TXQ_FLAGS_NOREFCOUNT |
1416 ETH_TXQ_FLAGS_NOMULTMEMP |
1417 ETH_TXQ_FLAGS_NOVLANOFFL |
1418 ETH_TXQ_FLAGS_NOXSUMSCTP,
1422 static nicvf_phys_addr_t
1423 rbdr_rte_mempool_get(void *dev, void *opaque)
1427 struct nicvf_rxq *rxq;
1428 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)dev;
1429 struct nicvf *nic = (struct nicvf *)opaque;
1430 uint16_t rx_start, rx_end;
1432 /* Get queue ranges for this VF */
1433 nicvf_rx_range(eth_dev, nic, &rx_start, &rx_end);
1435 for (qidx = rx_start; qidx <= rx_end; qidx++) {
1436 rxq = eth_dev->data->rx_queues[qidx];
1437 /* Maintain equal buffer count across all pools */
1438 if (rxq->precharge_cnt >= rxq->qlen_mask)
1440 rxq->precharge_cnt++;
1441 mbuf = (uintptr_t)rte_pktmbuf_alloc(rxq->pool);
1443 return nicvf_mbuff_virt2phy(mbuf, rxq->mbuf_phys_off);
1449 nicvf_vf_start(struct rte_eth_dev *dev, struct nicvf *nic, uint32_t rbdrsz)
1452 uint16_t qidx, data_off;
1453 uint32_t total_rxq_desc, nb_rbdr_desc, exp_buffs;
1454 uint64_t mbuf_phys_off = 0;
1455 struct nicvf_rxq *rxq;
1456 struct rte_mbuf *mbuf;
1457 uint16_t rx_start, rx_end;
1458 uint16_t tx_start, tx_end;
1460 PMD_INIT_FUNC_TRACE();
1462 /* Userspace process exited without proper shutdown in last run */
1463 if (nicvf_qset_rbdr_active(nic, 0))
1464 nicvf_vf_stop(dev, nic, false);
1466 /* Get queue ranges for this VF */
1467 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
1470 * Thunderx nicvf PMD can support more than one pool per port only when
1471 * 1) Data payload size is same across all the pools in given port
1473 * 2) All mbuffs in the pools are from the same hugepage
1475 * 3) Mbuff metadata size is same across all the pools in given port
1477 * This is to support existing application that uses multiple pool/port.
1478 * But, the purpose of using multipool for QoS will not be addressed.
1482 /* Validate mempool attributes */
1483 for (qidx = rx_start; qidx <= rx_end; qidx++) {
1484 rxq = dev->data->rx_queues[qidx];
1485 rxq->mbuf_phys_off = nicvf_mempool_phy_offset(rxq->pool);
1486 mbuf = rte_pktmbuf_alloc(rxq->pool);
1488 PMD_INIT_LOG(ERR, "Failed allocate mbuf VF%d qid=%d "
1490 nic->vf_id, qidx, rxq->pool->name);
1493 data_off = nicvf_mbuff_meta_length(mbuf);
1494 data_off += RTE_PKTMBUF_HEADROOM;
1495 rte_pktmbuf_free(mbuf);
1497 if (data_off % RTE_CACHE_LINE_SIZE) {
1498 PMD_INIT_LOG(ERR, "%s: unaligned data_off=%d delta=%d",
1499 rxq->pool->name, data_off,
1500 data_off % RTE_CACHE_LINE_SIZE);
1503 rxq->mbuf_phys_off -= data_off;
1505 if (mbuf_phys_off == 0)
1506 mbuf_phys_off = rxq->mbuf_phys_off;
1507 if (mbuf_phys_off != rxq->mbuf_phys_off) {
1508 PMD_INIT_LOG(ERR, "pool params not same,%s VF%d %"
1509 PRIx64, rxq->pool->name, nic->vf_id,
1515 /* Check the level of buffers in the pool */
1517 for (qidx = rx_start; qidx <= rx_end; qidx++) {
1518 rxq = dev->data->rx_queues[qidx];
1519 /* Count total numbers of rxq descs */
1520 total_rxq_desc += rxq->qlen_mask + 1;
1521 exp_buffs = RTE_MEMPOOL_CACHE_MAX_SIZE + rxq->rx_free_thresh;
1522 exp_buffs *= dev->data->nb_rx_queues;
1523 if (rte_mempool_avail_count(rxq->pool) < exp_buffs) {
1524 PMD_INIT_LOG(ERR, "Buff shortage in pool=%s (%d/%d)",
1526 rte_mempool_avail_count(rxq->pool),
1532 /* Check RBDR desc overflow */
1533 ret = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1535 PMD_INIT_LOG(ERR, "Reached RBDR desc limit, reduce nr desc "
1536 "VF%d", nic->vf_id);
1541 ret = nicvf_qset_config(nic);
1543 PMD_INIT_LOG(ERR, "Failed to enable qset %d VF%d", ret,
1548 /* Allocate RBDR and RBDR ring desc */
1549 nb_rbdr_desc = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1550 ret = nicvf_qset_rbdr_alloc(dev, nic, nb_rbdr_desc, rbdrsz);
1552 PMD_INIT_LOG(ERR, "Failed to allocate memory for rbdr alloc "
1553 "VF%d", nic->vf_id);
1557 /* Enable and configure RBDR registers */
1558 ret = nicvf_qset_rbdr_config(nic, 0);
1560 PMD_INIT_LOG(ERR, "Failed to configure rbdr %d VF%d", ret,
1562 goto qset_rbdr_free;
1565 /* Fill rte_mempool buffers in RBDR pool and precharge it */
1566 ret = nicvf_qset_rbdr_precharge(dev, nic, 0, rbdr_rte_mempool_get,
1569 PMD_INIT_LOG(ERR, "Failed to fill rbdr %d VF%d", ret,
1571 goto qset_rbdr_reclaim;
1574 PMD_DRV_LOG(INFO, "Filled %d out of %d entries in RBDR VF%d",
1575 nic->rbdr->tail, nb_rbdr_desc, nic->vf_id);
1577 /* Configure VLAN Strip */
1578 nicvf_vlan_hw_strip(nic, dev->data->dev_conf.rxmode.hw_vlan_strip);
1580 /* Based on the packet type(IPv4 or IPv6), the nicvf HW aligns L3 data
1581 * to the 64bit memory address.
1582 * The alignment creates a hole in mbuf(between the end of headroom and
1583 * packet data start). The new revision of the HW provides an option to
1584 * disable the L3 alignment feature and make mbuf layout looks
1585 * more like other NICs. For better application compatibility, disabling
1586 * l3 alignment feature on the hardware revisions it supports
1588 nicvf_apad_config(nic, false);
1590 /* Get queue ranges for this VF */
1591 nicvf_tx_range(dev, nic, &tx_start, &tx_end);
1593 /* Configure TX queues */
1594 for (qidx = tx_start; qidx <= tx_end; qidx++) {
1595 ret = nicvf_vf_start_tx_queue(dev, nic,
1596 qidx % MAX_SND_QUEUES_PER_QS);
1598 goto start_txq_error;
1601 /* Configure RX queues */
1602 for (qidx = rx_start; qidx <= rx_end; qidx++) {
1603 ret = nicvf_vf_start_rx_queue(dev, nic,
1604 qidx % MAX_RCV_QUEUES_PER_QS);
1606 goto start_rxq_error;
1609 if (!nic->sqs_mode) {
1610 /* Configure CPI algorithm */
1611 ret = nicvf_configure_cpi(dev);
1613 goto start_txq_error;
1615 ret = nicvf_mbox_get_rss_size(nic);
1617 PMD_INIT_LOG(ERR, "Failed to get rss table size");
1618 goto qset_rss_error;
1622 ret = nicvf_configure_rss(dev);
1624 goto qset_rss_error;
1627 /* Done; Let PF make the BGX's RX and TX switches to ON position */
1628 nicvf_mbox_cfg_done(nic);
1632 nicvf_rss_term(nic);
1634 for (qidx = rx_start; qidx <= rx_end; qidx++)
1635 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS);
1637 for (qidx = tx_start; qidx <= tx_end; qidx++)
1638 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS);
1640 nicvf_qset_rbdr_reclaim(nic, 0);
1641 nicvf_rbdr_release_mbufs(dev, nic);
1644 rte_free(nic->rbdr);
1648 nicvf_qset_reclaim(nic);
1653 nicvf_dev_start(struct rte_eth_dev *dev)
1658 struct nicvf *nic = nicvf_pmd_priv(dev);
1659 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
1661 uint32_t buffsz = 0, rbdrsz = 0;
1662 struct rte_pktmbuf_pool_private *mbp_priv;
1663 struct nicvf_rxq *rxq;
1665 PMD_INIT_FUNC_TRACE();
1667 /* This function must be called for a primary device */
1668 assert_primary(nic);
1670 /* Validate RBDR buff size */
1671 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) {
1672 rxq = dev->data->rx_queues[qidx];
1673 mbp_priv = rte_mempool_get_priv(rxq->pool);
1674 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
1676 PMD_INIT_LOG(ERR, "rxbuf size must be multiply of 128");
1681 if (rbdrsz != buffsz) {
1682 PMD_INIT_LOG(ERR, "buffsz not same, qidx=%d (%d/%d)",
1683 qidx, rbdrsz, buffsz);
1688 /* Configure loopback */
1689 ret = nicvf_loopback_config(nic, dev->data->dev_conf.lpbk_mode);
1691 PMD_INIT_LOG(ERR, "Failed to configure loopback %d", ret);
1695 /* Reset all statistics counters attached to this port */
1696 ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, 0xFFFF, 0xFFFF);
1698 PMD_INIT_LOG(ERR, "Failed to reset stat counters %d", ret);
1702 /* Setup scatter mode if needed by jumbo */
1703 if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
1704 2 * VLAN_TAG_SIZE > buffsz)
1705 dev->data->scattered_rx = 1;
1706 if (rx_conf->enable_scatter)
1707 dev->data->scattered_rx = 1;
1709 /* Setup MTU based on max_rx_pkt_len or default */
1710 mtu = dev->data->dev_conf.rxmode.jumbo_frame ?
1711 dev->data->dev_conf.rxmode.max_rx_pkt_len
1712 - ETHER_HDR_LEN - ETHER_CRC_LEN
1715 if (nicvf_dev_set_mtu(dev, mtu)) {
1716 PMD_INIT_LOG(ERR, "Failed to set default mtu size");
1720 ret = nicvf_vf_start(dev, nic, rbdrsz);
1724 for (i = 0; i < nic->sqs_count; i++) {
1725 assert(nic->snicvf[i]);
1727 ret = nicvf_vf_start(dev, nic->snicvf[i], rbdrsz);
1732 /* Configure callbacks based on scatter mode */
1733 nicvf_set_tx_function(dev);
1734 nicvf_set_rx_function(dev);
1740 nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup)
1744 struct nicvf *nic = nicvf_pmd_priv(dev);
1746 PMD_INIT_FUNC_TRACE();
1748 /* Teardown secondary vf first */
1749 for (i = 0; i < nic->sqs_count; i++) {
1750 if (!nic->snicvf[i])
1753 nicvf_vf_stop(dev, nic->snicvf[i], cleanup);
1756 /* Stop the primary VF now */
1757 nicvf_vf_stop(dev, nic, cleanup);
1759 /* Disable loopback */
1760 ret = nicvf_loopback_config(nic, 0);
1762 PMD_INIT_LOG(ERR, "Failed to disable loopback %d", ret);
1764 /* Reclaim CPI configuration */
1765 ret = nicvf_mbox_config_cpi(nic, 0);
1767 PMD_INIT_LOG(ERR, "Failed to reclaim CPI config %d", ret);
1771 nicvf_dev_stop(struct rte_eth_dev *dev)
1773 PMD_INIT_FUNC_TRACE();
1775 nicvf_dev_stop_cleanup(dev, false);
1779 nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, bool cleanup)
1783 uint16_t tx_start, tx_end;
1784 uint16_t rx_start, rx_end;
1786 PMD_INIT_FUNC_TRACE();
1789 /* Let PF make the BGX's RX and TX switches to OFF position */
1790 nicvf_mbox_shutdown(nic);
1793 /* Disable VLAN Strip */
1794 nicvf_vlan_hw_strip(nic, 0);
1796 /* Get queue ranges for this VF */
1797 nicvf_tx_range(dev, nic, &tx_start, &tx_end);
1799 for (qidx = tx_start; qidx <= tx_end; qidx++)
1800 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS);
1802 /* Get queue ranges for this VF */
1803 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
1806 for (qidx = rx_start; qidx <= rx_end; qidx++)
1807 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS);
1810 ret = nicvf_qset_rbdr_reclaim(nic, 0);
1812 PMD_INIT_LOG(ERR, "Failed to reclaim RBDR %d", ret);
1814 /* Move all charged buffers in RBDR back to pool */
1815 if (nic->rbdr != NULL)
1816 nicvf_rbdr_release_mbufs(dev, nic);
1819 ret = nicvf_qset_reclaim(nic);
1821 PMD_INIT_LOG(ERR, "Failed to disable qset %d", ret);
1823 /* Disable all interrupts */
1824 nicvf_disable_all_interrupts(nic);
1826 /* Free RBDR SW structure */
1828 rte_free(nic->rbdr);
1834 nicvf_dev_close(struct rte_eth_dev *dev)
1837 struct nicvf *nic = nicvf_pmd_priv(dev);
1839 PMD_INIT_FUNC_TRACE();
1841 nicvf_dev_stop_cleanup(dev, true);
1842 nicvf_periodic_alarm_stop(nicvf_interrupt, dev);
1844 for (i = 0; i < nic->sqs_count; i++) {
1845 if (!nic->snicvf[i])
1848 nicvf_periodic_alarm_stop(nicvf_vf_interrupt, nic->snicvf[i]);
1853 nicvf_request_sqs(struct nicvf *nic)
1857 assert_primary(nic);
1858 assert(nic->sqs_count > 0);
1859 assert(nic->sqs_count <= MAX_SQS_PER_VF);
1861 /* Set no of Rx/Tx queues in each of the SQsets */
1862 for (i = 0; i < nic->sqs_count; i++) {
1863 if (nicvf_svf_empty())
1864 rte_panic("Cannot assign sufficient number of "
1865 "secondary queues to primary VF%" PRIu8 "\n",
1868 nic->snicvf[i] = nicvf_svf_pop();
1869 nic->snicvf[i]->sqs_id = i;
1872 return nicvf_mbox_request_sqs(nic);
1876 nicvf_dev_configure(struct rte_eth_dev *dev)
1878 struct rte_eth_dev_data *data = dev->data;
1879 struct rte_eth_conf *conf = &data->dev_conf;
1880 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1881 struct rte_eth_txmode *txmode = &conf->txmode;
1882 struct nicvf *nic = nicvf_pmd_priv(dev);
1885 PMD_INIT_FUNC_TRACE();
1887 if (!rte_eal_has_hugepages()) {
1888 PMD_INIT_LOG(INFO, "Huge page is not configured");
1892 if (txmode->mq_mode) {
1893 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported");
1897 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1898 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1899 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode);
1903 if (!rxmode->hw_strip_crc) {
1904 PMD_INIT_LOG(NOTICE, "Can't disable hw crc strip");
1905 rxmode->hw_strip_crc = 1;
1908 if (rxmode->hw_ip_checksum) {
1909 PMD_INIT_LOG(NOTICE, "Rxcksum not supported");
1910 rxmode->hw_ip_checksum = 0;
1913 if (rxmode->split_hdr_size) {
1914 PMD_INIT_LOG(INFO, "Rxmode does not support split header");
1918 if (rxmode->hw_vlan_filter) {
1919 PMD_INIT_LOG(INFO, "VLAN filter not supported");
1923 if (rxmode->hw_vlan_extend) {
1924 PMD_INIT_LOG(INFO, "VLAN extended not supported");
1928 if (rxmode->enable_lro) {
1929 PMD_INIT_LOG(INFO, "LRO not supported");
1933 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1934 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported");
1938 if (conf->dcb_capability_en) {
1939 PMD_INIT_LOG(INFO, "DCB enable not supported");
1943 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1944 PMD_INIT_LOG(INFO, "Flow director not supported");
1948 assert_primary(nic);
1949 NICVF_STATIC_ASSERT(MAX_RCV_QUEUES_PER_QS == MAX_SND_QUEUES_PER_QS);
1950 cqcount = RTE_MAX(data->nb_tx_queues, data->nb_rx_queues);
1951 if (cqcount > MAX_RCV_QUEUES_PER_QS) {
1952 nic->sqs_count = RTE_ALIGN_CEIL(cqcount, MAX_RCV_QUEUES_PER_QS);
1953 nic->sqs_count = (nic->sqs_count / MAX_RCV_QUEUES_PER_QS) - 1;
1958 assert(nic->sqs_count <= MAX_SQS_PER_VF);
1960 if (nic->sqs_count > 0) {
1961 if (nicvf_request_sqs(nic)) {
1962 rte_panic("Cannot assign sufficient number of "
1963 "secondary queues to PORT%d VF%" PRIu8 "\n",
1964 dev->data->port_id, nic->vf_id);
1968 PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64,
1969 dev->data->port_id, nicvf_hw_cap(nic));
1974 /* Initialize and register driver with DPDK Application */
1975 static const struct eth_dev_ops nicvf_eth_dev_ops = {
1976 .dev_configure = nicvf_dev_configure,
1977 .dev_start = nicvf_dev_start,
1978 .dev_stop = nicvf_dev_stop,
1979 .link_update = nicvf_dev_link_update,
1980 .dev_close = nicvf_dev_close,
1981 .stats_get = nicvf_dev_stats_get,
1982 .stats_reset = nicvf_dev_stats_reset,
1983 .promiscuous_enable = nicvf_dev_promisc_enable,
1984 .dev_infos_get = nicvf_dev_info_get,
1985 .dev_supported_ptypes_get = nicvf_dev_supported_ptypes_get,
1986 .mtu_set = nicvf_dev_set_mtu,
1987 .reta_update = nicvf_dev_reta_update,
1988 .reta_query = nicvf_dev_reta_query,
1989 .rss_hash_update = nicvf_dev_rss_hash_update,
1990 .rss_hash_conf_get = nicvf_dev_rss_hash_conf_get,
1991 .rx_queue_start = nicvf_dev_rx_queue_start,
1992 .rx_queue_stop = nicvf_dev_rx_queue_stop,
1993 .tx_queue_start = nicvf_dev_tx_queue_start,
1994 .tx_queue_stop = nicvf_dev_tx_queue_stop,
1995 .rx_queue_setup = nicvf_dev_rx_queue_setup,
1996 .rx_queue_release = nicvf_dev_rx_queue_release,
1997 .rx_queue_count = nicvf_dev_rx_queue_count,
1998 .tx_queue_setup = nicvf_dev_tx_queue_setup,
1999 .tx_queue_release = nicvf_dev_tx_queue_release,
2000 .get_reg = nicvf_dev_get_regs,
2004 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev)
2007 struct rte_pci_device *pci_dev;
2008 struct nicvf *nic = nicvf_pmd_priv(eth_dev);
2010 PMD_INIT_FUNC_TRACE();
2012 eth_dev->dev_ops = &nicvf_eth_dev_ops;
2014 /* For secondary processes, the primary has done all the work */
2015 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2017 /* Setup callbacks for secondary process */
2018 nicvf_set_tx_function(eth_dev);
2019 nicvf_set_rx_function(eth_dev);
2022 /* If nic == NULL than it is secondary function
2023 * so ethdev need to be released by caller */
2028 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2029 rte_eth_copy_pci_info(eth_dev, pci_dev);
2031 nic->device_id = pci_dev->id.device_id;
2032 nic->vendor_id = pci_dev->id.vendor_id;
2033 nic->subsystem_device_id = pci_dev->id.subsystem_device_id;
2034 nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2036 PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u",
2037 pci_dev->id.vendor_id, pci_dev->id.device_id,
2038 pci_dev->addr.domain, pci_dev->addr.bus,
2039 pci_dev->addr.devid, pci_dev->addr.function);
2041 nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr;
2042 if (!nic->reg_base) {
2043 PMD_INIT_LOG(ERR, "Failed to map BAR0");
2048 nicvf_disable_all_interrupts(nic);
2050 ret = nicvf_periodic_alarm_start(nicvf_interrupt, eth_dev);
2052 PMD_INIT_LOG(ERR, "Failed to start period alarm");
2056 ret = nicvf_mbox_check_pf_ready(nic);
2058 PMD_INIT_LOG(ERR, "Failed to get ready message from PF");
2062 "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s",
2063 nic->node, nic->vf_id,
2064 nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass",
2065 nic->sqs_mode ? "true" : "false",
2066 nic->loopback_supported ? "true" : "false"
2070 ret = nicvf_base_init(nic);
2072 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init");
2076 if (nic->sqs_mode) {
2077 /* Push nic to stack of secondary vfs */
2078 nicvf_svf_push(nic);
2080 /* Steal nic pointer from the device for further reuse */
2081 eth_dev->data->dev_private = NULL;
2083 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev);
2084 ret = nicvf_periodic_alarm_start(nicvf_vf_interrupt, nic);
2086 PMD_INIT_LOG(ERR, "Failed to start period alarm");
2090 /* Detach port by returning positive error number */
2094 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2095 if (eth_dev->data->mac_addrs == NULL) {
2096 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr");
2100 if (is_zero_ether_addr((struct ether_addr *)nic->mac_addr))
2101 eth_random_addr(&nic->mac_addr[0]);
2103 ether_addr_copy((struct ether_addr *)nic->mac_addr,
2104 ð_dev->data->mac_addrs[0]);
2106 ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr);
2108 PMD_INIT_LOG(ERR, "Failed to set mac addr");
2112 PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x",
2113 eth_dev->data->port_id, nic->vendor_id, nic->device_id,
2114 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2],
2115 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]);
2120 rte_free(eth_dev->data->mac_addrs);
2122 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev);
2127 static const struct rte_pci_id pci_id_nicvf_map[] = {
2129 .class_id = RTE_CLASS_ANY_ID,
2130 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2131 .device_id = PCI_DEVICE_ID_THUNDERX_CN88XX_PASS1_NICVF,
2132 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2133 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF,
2136 .class_id = RTE_CLASS_ANY_ID,
2137 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2138 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2139 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2140 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF,
2143 .class_id = RTE_CLASS_ANY_ID,
2144 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2145 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2146 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2147 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN81XX_NICVF,
2150 .class_id = RTE_CLASS_ANY_ID,
2151 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2152 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2153 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2154 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN83XX_NICVF,
2161 static int nicvf_eth_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2162 struct rte_pci_device *pci_dev)
2164 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct nicvf),
2165 nicvf_eth_dev_init);
2168 static int nicvf_eth_pci_remove(struct rte_pci_device *pci_dev)
2170 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
2173 static struct rte_pci_driver rte_nicvf_pmd = {
2174 .id_table = pci_id_nicvf_map,
2175 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_KEEP_MAPPED_RES |
2176 RTE_PCI_DRV_INTR_LSC,
2177 .probe = nicvf_eth_pci_probe,
2178 .remove = nicvf_eth_pci_remove,
2181 RTE_PMD_REGISTER_PCI(net_thunderx, rte_nicvf_pmd);
2182 RTE_PMD_REGISTER_PCI_TABLE(net_thunderx, pci_id_nicvf_map);
2183 RTE_PMD_REGISTER_KMOD_DEP(net_thunderx, "* igb_uio | uio_pci_generic | vfio-pci");