drivers/net/thunderx/nicvf_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2016 Cavium, Inc
   3  */
   4
   5 #include <unistd.h>
   6 #include <stdint.h>
   7 #include <stdio.h>
   8 #include <stdlib.h>
   9
  10 #include <rte_atomic.h>
  11 #include <rte_branch_prediction.h>
  12 #include <rte_byteorder.h>
  13 #include <rte_common.h>
  14 #include <rte_cycles.h>
  15 #include <rte_errno.h>
  16 #include <rte_ethdev_driver.h>
  17 #include <rte_ether.h>
  18 #include <rte_log.h>
  19 #include <rte_mbuf.h>
  20 #include <rte_prefetch.h>
  21
  22 #include "base/nicvf_plat.h"
  23
  24 #include "nicvf_ethdev.h"
  25 #include "nicvf_rxtx.h"
  26 #include "nicvf_logs.h"
  27
  28 static inline void __hot
  29 fill_sq_desc_header(union sq_entry_t *entry, struct rte_mbuf *pkt)
  30 {
  31         /* Local variable sqe to avoid read from sq desc memory*/
  32         union sq_entry_t sqe;
  33         uint64_t ol_flags;
  34
  35         /* Fill SQ header descriptor */
  36         sqe.buff[0] = 0;
  37         sqe.hdr.subdesc_type = SQ_DESC_TYPE_HEADER;
  38         /* Number of sub-descriptors following this one */
  39         sqe.hdr.subdesc_cnt = pkt->nb_segs;
  40         sqe.hdr.tot_len = pkt->pkt_len;
  41
  42         ol_flags = pkt->ol_flags & NICVF_TX_OFFLOAD_MASK;
  43         if (unlikely(ol_flags)) {
  44                 /* L4 cksum */
  45                 uint64_t l4_flags = ol_flags & PKT_TX_L4_MASK;
  46                 if (l4_flags == PKT_TX_TCP_CKSUM)
  47                         sqe.hdr.csum_l4 = SEND_L4_CSUM_TCP;
  48                 else if (l4_flags == PKT_TX_UDP_CKSUM)
  49                         sqe.hdr.csum_l4 = SEND_L4_CSUM_UDP;
  50                 else
  51                         sqe.hdr.csum_l4 = SEND_L4_CSUM_DISABLE;
  52
  53                 sqe.hdr.l3_offset = pkt->l2_len;
  54                 sqe.hdr.l4_offset = pkt->l3_len + pkt->l2_len;
  55
  56                 /* L3 cksum */
  57                 if (ol_flags & PKT_TX_IP_CKSUM)
  58                         sqe.hdr.csum_l3 = 1;
  59         }
  60
  61         entry->buff[0] = sqe.buff[0];
  62 }
  63
  64 void __hot
  65 nicvf_single_pool_free_xmited_buffers(struct nicvf_txq *sq)
  66 {
  67         int j = 0;
  68         uint32_t curr_head;
  69         uint32_t head = sq->head;
  70         struct rte_mbuf **txbuffs = sq->txbuffs;
  71         void *obj_p[NICVF_MAX_TX_FREE_THRESH] __rte_cache_aligned;
  72
  73         curr_head = nicvf_addr_read(sq->sq_head) >> 4;
  74         while (head != curr_head) {
  75                 if (txbuffs[head])
  76                         obj_p[j++] = txbuffs[head];
  77
  78                 head = (head + 1) & sq->qlen_mask;
  79         }
  80
  81         rte_mempool_put_bulk(sq->pool, obj_p, j);
  82         sq->head = curr_head;
  83         sq->xmit_bufs -= j;
  84         NICVF_TX_ASSERT(sq->xmit_bufs >= 0);
  85 }
  86
  87 void __hot
  88 nicvf_multi_pool_free_xmited_buffers(struct nicvf_txq *sq)
  89 {
  90         uint32_t n = 0;
  91         uint32_t curr_head;
  92         uint32_t head = sq->head;
  93         struct rte_mbuf **txbuffs = sq->txbuffs;
  94
  95         curr_head = nicvf_addr_read(sq->sq_head) >> 4;
  96         while (head != curr_head) {
  97                 if (txbuffs[head]) {
  98                         rte_pktmbuf_free_seg(txbuffs[head]);
  99                         n++;
 100                 }
 101
 102                 head = (head + 1) & sq->qlen_mask;
 103         }
 104
 105         sq->head = curr_head;
 106         sq->xmit_bufs -= n;
 107         NICVF_TX_ASSERT(sq->xmit_bufs >= 0);
 108 }
 109
 110 static inline uint32_t __hot
 111 nicvf_free_tx_desc(struct nicvf_txq *sq)
 112 {
 113         return ((sq->head - sq->tail - 1) & sq->qlen_mask);
 114 }
 115
 116 /* Send Header + Packet */
 117 #define TX_DESC_PER_PKT 2
 118
 119 static inline uint32_t __hot
 120 nicvf_free_xmitted_buffers(struct nicvf_txq *sq, struct rte_mbuf **tx_pkts,
 121                             uint16_t nb_pkts)
 122 {
 123         uint32_t free_desc = nicvf_free_tx_desc(sq);
 124
 125         if (free_desc < nb_pkts * TX_DESC_PER_PKT ||
 126                         sq->xmit_bufs > sq->tx_free_thresh) {
 127                 if (unlikely(sq->pool == NULL))
 128                         sq->pool = tx_pkts[0]->pool;
 129
 130                 sq->pool_free(sq);
 131                 /* Freed now, let see the number of free descs again */
 132                 free_desc = nicvf_free_tx_desc(sq);
 133         }
 134         return free_desc;
 135 }
 136
 137 uint16_t __hot
 138 nicvf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
 139 {
 140         int i;
 141         uint32_t free_desc;
 142         uint32_t tail;
 143         struct nicvf_txq *sq = tx_queue;
 144         union sq_entry_t *desc_ptr = sq->desc;
 145         struct rte_mbuf **txbuffs = sq->txbuffs;
 146         struct rte_mbuf *pkt;
 147         uint32_t qlen_mask = sq->qlen_mask;
 148
 149         tail = sq->tail;
 150         free_desc = nicvf_free_xmitted_buffers(sq, tx_pkts, nb_pkts);
 151
 152         for (i = 0; i < nb_pkts && (int)free_desc >= TX_DESC_PER_PKT; i++) {
 153                 pkt = tx_pkts[i];
 154
 155                 txbuffs[tail] = NULL;
 156                 fill_sq_desc_header(desc_ptr + tail, pkt);
 157                 tail = (tail + 1) & qlen_mask;
 158
 159                 txbuffs[tail] = pkt;
 160                 fill_sq_desc_gather(desc_ptr + tail, pkt);
 161                 tail = (tail + 1) & qlen_mask;
 162                 free_desc -= TX_DESC_PER_PKT;
 163         }
 164
 165         if (likely(i)) {
 166                 sq->tail = tail;
 167                 sq->xmit_bufs += i;
 168                 rte_wmb();
 169
 170                 /* Inform HW to xmit the packets */
 171                 nicvf_addr_write(sq->sq_door, i * TX_DESC_PER_PKT);
 172         }
 173         return i;
 174 }
 175
 176 uint16_t __hot
 177 nicvf_xmit_pkts_multiseg(void *tx_queue, struct rte_mbuf **tx_pkts,
 178                          uint16_t nb_pkts)
 179 {
 180         int i, k;
 181         uint32_t used_desc, next_used_desc, used_bufs, free_desc, tail;
 182         struct nicvf_txq *sq = tx_queue;
 183         union sq_entry_t *desc_ptr = sq->desc;
 184         struct rte_mbuf **txbuffs = sq->txbuffs;
 185         struct rte_mbuf *pkt, *seg;
 186         uint32_t qlen_mask = sq->qlen_mask;
 187         uint16_t nb_segs;
 188
 189         tail = sq->tail;
 190         used_desc = 0;
 191         used_bufs = 0;
 192
 193         free_desc = nicvf_free_xmitted_buffers(sq, tx_pkts, nb_pkts);
 194
 195         for (i = 0; i < nb_pkts; i++) {
 196                 pkt = tx_pkts[i];
 197
 198                 nb_segs = pkt->nb_segs;
 199
 200                 next_used_desc = used_desc + nb_segs + 1;
 201                 if (next_used_desc > free_desc)
 202                         break;
 203                 used_desc = next_used_desc;
 204                 used_bufs += nb_segs;
 205
 206                 txbuffs[tail] = NULL;
 207                 fill_sq_desc_header(desc_ptr + tail, pkt);
 208                 tail = (tail + 1) & qlen_mask;
 209
 210                 txbuffs[tail] = pkt;
 211                 fill_sq_desc_gather(desc_ptr + tail, pkt);
 212                 tail = (tail + 1) & qlen_mask;
 213
 214                 seg = pkt->next;
 215                 for (k = 1; k < nb_segs; k++) {
 216                         txbuffs[tail] = seg;
 217                         fill_sq_desc_gather(desc_ptr + tail, seg);
 218                         tail = (tail + 1) & qlen_mask;
 219                         seg = seg->next;
 220                 }
 221         }
 222
 223         if (likely(used_desc)) {
 224                 sq->tail = tail;
 225                 sq->xmit_bufs += used_bufs;
 226                 rte_wmb();
 227
 228                 /* Inform HW to xmit the packets */
 229                 nicvf_addr_write(sq->sq_door, used_desc);
 230         }
 231         return i;
 232 }
 233
 234 static const uint32_t ptype_table[16][16] __rte_cache_aligned = {
 235         [L3_NONE][L4_NONE] = RTE_PTYPE_UNKNOWN,
 236         [L3_NONE][L4_IPSEC_ESP] = RTE_PTYPE_UNKNOWN,
 237         [L3_NONE][L4_IPFRAG] = RTE_PTYPE_L4_FRAG,
 238         [L3_NONE][L4_IPCOMP] = RTE_PTYPE_UNKNOWN,
 239         [L3_NONE][L4_TCP] = RTE_PTYPE_L4_TCP,
 240         [L3_NONE][L4_UDP_PASS1] = RTE_PTYPE_L4_UDP,
 241         [L3_NONE][L4_GRE] = RTE_PTYPE_TUNNEL_GRE,
 242         [L3_NONE][L4_UDP_PASS2] = RTE_PTYPE_L4_UDP,
 243         [L3_NONE][L4_UDP_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
 244         [L3_NONE][L4_UDP_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
 245         [L3_NONE][L4_NVGRE] = RTE_PTYPE_TUNNEL_NVGRE,
 246
 247         [L3_IPV4][L4_NONE] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_UNKNOWN,
 248         [L3_IPV4][L4_IPSEC_ESP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L3_IPV4,
 249         [L3_IPV4][L4_IPFRAG] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_FRAG,
 250         [L3_IPV4][L4_IPCOMP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_UNKNOWN,
 251         [L3_IPV4][L4_TCP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
 252         [L3_IPV4][L4_UDP_PASS1] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
 253         [L3_IPV4][L4_GRE] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_GRE,
 254         [L3_IPV4][L4_UDP_PASS2] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
 255         [L3_IPV4][L4_UDP_GENEVE] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_GENEVE,
 256         [L3_IPV4][L4_UDP_VXLAN] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_VXLAN,
 257         [L3_IPV4][L4_NVGRE] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_NVGRE,
 258
 259         [L3_IPV4_OPT][L4_NONE] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_UNKNOWN,
 260         [L3_IPV4_OPT][L4_IPSEC_ESP] =  RTE_PTYPE_L3_IPV4_EXT |
 261                                 RTE_PTYPE_L3_IPV4,
 262         [L3_IPV4_OPT][L4_IPFRAG] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_FRAG,
 263         [L3_IPV4_OPT][L4_IPCOMP] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_UNKNOWN,
 264         [L3_IPV4_OPT][L4_TCP] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_TCP,
 265         [L3_IPV4_OPT][L4_UDP_PASS1] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_UDP,
 266         [L3_IPV4_OPT][L4_GRE] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_GRE,
 267         [L3_IPV4_OPT][L4_UDP_PASS2] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_UDP,
 268         [L3_IPV4_OPT][L4_UDP_GENEVE] = RTE_PTYPE_L3_IPV4_EXT |
 269                                 RTE_PTYPE_TUNNEL_GENEVE,
 270         [L3_IPV4_OPT][L4_UDP_VXLAN] = RTE_PTYPE_L3_IPV4_EXT |
 271                                 RTE_PTYPE_TUNNEL_VXLAN,
 272         [L3_IPV4_OPT][L4_NVGRE] = RTE_PTYPE_L3_IPV4_EXT |
 273                                 RTE_PTYPE_TUNNEL_NVGRE,
 274
 275         [L3_IPV6][L4_NONE] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_UNKNOWN,
 276         [L3_IPV6][L4_IPSEC_ESP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L3_IPV4,
 277         [L3_IPV6][L4_IPFRAG] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_FRAG,
 278         [L3_IPV6][L4_IPCOMP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_UNKNOWN,
 279         [L3_IPV6][L4_TCP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
 280         [L3_IPV6][L4_UDP_PASS1] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
 281         [L3_IPV6][L4_GRE] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_TUNNEL_GRE,
 282         [L3_IPV6][L4_UDP_PASS2] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
 283         [L3_IPV6][L4_UDP_GENEVE] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_TUNNEL_GENEVE,
 284         [L3_IPV6][L4_UDP_VXLAN] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_TUNNEL_VXLAN,
 285         [L3_IPV6][L4_NVGRE] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_TUNNEL_NVGRE,
 286
 287         [L3_IPV6_OPT][L4_NONE] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_UNKNOWN,
 288         [L3_IPV6_OPT][L4_IPSEC_ESP] =  RTE_PTYPE_L3_IPV6_EXT |
 289                                         RTE_PTYPE_L3_IPV4,
 290         [L3_IPV6_OPT][L4_IPFRAG] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_FRAG,
 291         [L3_IPV6_OPT][L4_IPCOMP] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_UNKNOWN,
 292         [L3_IPV6_OPT][L4_TCP] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_TCP,
 293         [L3_IPV6_OPT][L4_UDP_PASS1] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,
 294         [L3_IPV6_OPT][L4_GRE] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_TUNNEL_GRE,
 295         [L3_IPV6_OPT][L4_UDP_PASS2] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,
 296         [L3_IPV6_OPT][L4_UDP_GENEVE] = RTE_PTYPE_L3_IPV6_EXT |
 297                                         RTE_PTYPE_TUNNEL_GENEVE,
 298         [L3_IPV6_OPT][L4_UDP_VXLAN] = RTE_PTYPE_L3_IPV6_EXT |
 299                                         RTE_PTYPE_TUNNEL_VXLAN,
 300         [L3_IPV6_OPT][L4_NVGRE] = RTE_PTYPE_L3_IPV6_EXT |
 301                                         RTE_PTYPE_TUNNEL_NVGRE,
 302
 303         [L3_ET_STOP][L4_NONE] = RTE_PTYPE_UNKNOWN,
 304         [L3_ET_STOP][L4_IPSEC_ESP] = RTE_PTYPE_UNKNOWN,
 305         [L3_ET_STOP][L4_IPFRAG] = RTE_PTYPE_L4_FRAG,
 306         [L3_ET_STOP][L4_IPCOMP] = RTE_PTYPE_UNKNOWN,
 307         [L3_ET_STOP][L4_TCP] = RTE_PTYPE_L4_TCP,
 308         [L3_ET_STOP][L4_UDP_PASS1] = RTE_PTYPE_L4_UDP,
 309         [L3_ET_STOP][L4_GRE] = RTE_PTYPE_TUNNEL_GRE,
 310         [L3_ET_STOP][L4_UDP_PASS2] = RTE_PTYPE_L4_UDP,
 311         [L3_ET_STOP][L4_UDP_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
 312         [L3_ET_STOP][L4_UDP_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
 313         [L3_ET_STOP][L4_NVGRE] = RTE_PTYPE_TUNNEL_NVGRE,
 314
 315         [L3_OTHER][L4_NONE] = RTE_PTYPE_UNKNOWN,
 316         [L3_OTHER][L4_IPSEC_ESP] = RTE_PTYPE_UNKNOWN,
 317         [L3_OTHER][L4_IPFRAG] = RTE_PTYPE_L4_FRAG,
 318         [L3_OTHER][L4_IPCOMP] = RTE_PTYPE_UNKNOWN,
 319         [L3_OTHER][L4_TCP] = RTE_PTYPE_L4_TCP,
 320         [L3_OTHER][L4_UDP_PASS1] = RTE_PTYPE_L4_UDP,
 321         [L3_OTHER][L4_GRE] = RTE_PTYPE_TUNNEL_GRE,
 322         [L3_OTHER][L4_UDP_PASS2] = RTE_PTYPE_L4_UDP,
 323         [L3_OTHER][L4_UDP_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
 324         [L3_OTHER][L4_UDP_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
 325         [L3_OTHER][L4_NVGRE] = RTE_PTYPE_TUNNEL_NVGRE,
 326 };
 327
 328 static inline uint32_t __hot
 329 nicvf_rx_classify_pkt(cqe_rx_word0_t cqe_rx_w0)
 330 {
 331         return ptype_table[cqe_rx_w0.l3_type][cqe_rx_w0.l4_type];
 332 }
 333
 334 static inline uint64_t __hot
 335 nicvf_set_olflags(const cqe_rx_word0_t cqe_rx_w0)
 336 {
 337         static const uint64_t flag_table[3] __rte_cache_aligned = {
 338                 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD,
 339                 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_UNKNOWN,
 340                 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD,
 341         };
 342
 343         const uint8_t idx = (cqe_rx_w0.err_opcode == CQE_RX_ERR_L4_CHK) << 1 |
 344                 (cqe_rx_w0.err_opcode == CQE_RX_ERR_IP_CHK);
 345         return flag_table[idx];
 346 }
 347
 348 static inline int __hot
 349 nicvf_fill_rbdr(struct nicvf_rxq *rxq, int to_fill)
 350 {
 351         int i;
 352         uint32_t ltail, next_tail;
 353         struct nicvf_rbdr *rbdr = rxq->shared_rbdr;
 354         uint64_t mbuf_phys_off = rxq->mbuf_phys_off;
 355         struct rbdr_entry_t *desc = rbdr->desc;
 356         uint32_t qlen_mask = rbdr->qlen_mask;
 357         uintptr_t door = rbdr->rbdr_door;
 358         void *obj_p[NICVF_MAX_RX_FREE_THRESH] __rte_cache_aligned;
 359
 360         if (unlikely(rte_mempool_get_bulk(rxq->pool, obj_p, to_fill) < 0)) {
 361                 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
 362                         to_fill;
 363                 return 0;
 364         }
 365
 366         NICVF_RX_ASSERT((unsigned int)to_fill <= (qlen_mask -
 367                 (nicvf_addr_read(rbdr->rbdr_status) & NICVF_RBDR_COUNT_MASK)));
 368
 369         next_tail = __atomic_fetch_add(&rbdr->next_tail, to_fill,
 370                                         __ATOMIC_ACQUIRE);
 371         ltail = next_tail;
 372         for (i = 0; i < to_fill; i++) {
 373                 struct rbdr_entry_t *entry = desc + (ltail & qlen_mask);
 374
 375                 entry->full_addr = nicvf_mbuff_virt2phy((uintptr_t)obj_p[i],
 376                                                         mbuf_phys_off);
 377                 ltail++;
 378         }
 379
 380         while (__atomic_load_n(&rbdr->tail, __ATOMIC_RELAXED) != next_tail)
 381                 rte_pause();
 382
 383         __atomic_store_n(&rbdr->tail, ltail, __ATOMIC_RELEASE);
 384         nicvf_addr_write(door, to_fill);
 385         return to_fill;
 386 }
 387
 388 static inline int32_t __hot
 389 nicvf_rx_pkts_to_process(struct nicvf_rxq *rxq, uint16_t nb_pkts,
 390                          int32_t available_space)
 391 {
 392         if (unlikely(available_space < nb_pkts))
 393                 rxq->available_space = nicvf_addr_read(rxq->cq_status)
 394                                                 & NICVF_CQ_CQE_COUNT_MASK;
 395
 396         return RTE_MIN(nb_pkts, available_space);
 397 }
 398
 399 static inline void __hot
 400 nicvf_rx_offload(cqe_rx_word0_t cqe_rx_w0, cqe_rx_word2_t cqe_rx_w2,
 401                  struct rte_mbuf *pkt)
 402 {
 403         if (likely(cqe_rx_w0.rss_alg)) {
 404                 pkt->hash.rss = cqe_rx_w2.rss_tag;
 405                 pkt->ol_flags |= PKT_RX_RSS_HASH;
 406
 407         }
 408 }
 409
 410 static __rte_always_inline uint16_t
 411 nicvf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts,
 412                 const uint32_t flag)
 413 {
 414         uint32_t i, to_process;
 415         struct cqe_rx_t *cqe_rx;
 416         struct rte_mbuf *pkt;
 417         cqe_rx_word0_t cqe_rx_w0;
 418         cqe_rx_word1_t cqe_rx_w1;
 419         cqe_rx_word2_t cqe_rx_w2;
 420         cqe_rx_word3_t cqe_rx_w3;
 421         struct nicvf_rxq *rxq = rx_queue;
 422         union cq_entry_t *desc = rxq->desc;
 423         const uint64_t cqe_mask = rxq->qlen_mask;
 424         uint64_t rb0_ptr, mbuf_phys_off = rxq->mbuf_phys_off;
 425         const uint64_t mbuf_init = rxq->mbuf_initializer.value;
 426         uint32_t cqe_head = rxq->head & cqe_mask;
 427         int32_t available_space = rxq->available_space;
 428         const uint8_t rbptr_offset = rxq->rbptr_offset;
 429
 430         to_process = nicvf_rx_pkts_to_process(rxq, nb_pkts, available_space);
 431
 432         for (i = 0; i < to_process; i++) {
 433                 rte_prefetch_non_temporal(&desc[cqe_head + 2]);
 434                 cqe_rx = (struct cqe_rx_t *)&desc[cqe_head];
 435                 NICVF_RX_ASSERT(((struct cq_entry_type_t *)cqe_rx)->cqe_type
 436                                                  == CQE_TYPE_RX);
 437
 438                 NICVF_LOAD_PAIR(cqe_rx_w0.u64, cqe_rx_w1.u64, cqe_rx);
 439                 NICVF_LOAD_PAIR(cqe_rx_w2.u64, cqe_rx_w3.u64, &cqe_rx->word2);
 440                 rb0_ptr = *((uint64_t *)cqe_rx + rbptr_offset);
 441                 pkt = (struct rte_mbuf *)nicvf_mbuff_phy2virt
 442                                 (rb0_ptr - cqe_rx_w1.align_pad, mbuf_phys_off);
 443
 444                 if (flag & NICVF_RX_OFFLOAD_NONE)
 445                         pkt->ol_flags = 0;
 446                 if (flag & NICVF_RX_OFFLOAD_CKSUM)
 447                         pkt->ol_flags = nicvf_set_olflags(cqe_rx_w0);
 448                 pkt->data_len = cqe_rx_w3.rb0_sz;
 449                 pkt->pkt_len = cqe_rx_w3.rb0_sz;
 450                 pkt->packet_type = nicvf_rx_classify_pkt(cqe_rx_w0);
 451                 nicvf_mbuff_init_update(pkt, mbuf_init, cqe_rx_w1.align_pad);
 452                 nicvf_rx_offload(cqe_rx_w0, cqe_rx_w2, pkt);
 453                 rx_pkts[i] = pkt;
 454                 cqe_head = (cqe_head + 1) & cqe_mask;
 455                 nicvf_prefetch_store_keep(pkt);
 456         }
 457
 458         if (likely(to_process)) {
 459                 rxq->available_space -= to_process;
 460                 rxq->head = cqe_head;
 461                 nicvf_addr_write(rxq->cq_door, to_process);
 462                 rxq->recv_buffers += to_process;
 463         }
 464         if (rxq->recv_buffers > rxq->rx_free_thresh) {
 465                 rxq->recv_buffers -= nicvf_fill_rbdr(rxq, rxq->rx_free_thresh);
 466                 NICVF_RX_ASSERT(rxq->recv_buffers >= 0);
 467         }
 468
 469         return to_process;
 470 }
 471
 472 uint16_t __hot
 473 nicvf_recv_pkts_no_offload(void *rx_queue, struct rte_mbuf **rx_pkts,
 474                 uint16_t nb_pkts)
 475 {
 476         return nicvf_recv_pkts(rx_queue, rx_pkts, nb_pkts,
 477                         NICVF_RX_OFFLOAD_NONE);
 478 }
 479
 480 uint16_t __hot
 481 nicvf_recv_pkts_cksum(void *rx_queue, struct rte_mbuf **rx_pkts,
 482                 uint16_t nb_pkts)
 483 {
 484         return nicvf_recv_pkts(rx_queue, rx_pkts, nb_pkts,
 485                         NICVF_RX_OFFLOAD_CKSUM);
 486 }
 487
 488 static __rte_always_inline uint16_t __hot
 489 nicvf_process_cq_mseg_entry(struct cqe_rx_t *cqe_rx,
 490                         uint64_t mbuf_phys_off,
 491                         struct rte_mbuf **rx_pkt, uint8_t rbptr_offset,
 492                         uint64_t mbuf_init, const uint32_t flag)
 493 {
 494         struct rte_mbuf *pkt, *seg, *prev;
 495         cqe_rx_word0_t cqe_rx_w0;
 496         cqe_rx_word1_t cqe_rx_w1;
 497         cqe_rx_word2_t cqe_rx_w2;
 498         uint16_t *rb_sz, nb_segs, seg_idx;
 499         uint64_t *rb_ptr;
 500
 501         NICVF_LOAD_PAIR(cqe_rx_w0.u64, cqe_rx_w1.u64, cqe_rx);
 502         NICVF_RX_ASSERT(cqe_rx_w0.cqe_type == CQE_TYPE_RX);
 503         cqe_rx_w2 = cqe_rx->word2;
 504         rb_sz = &cqe_rx->word3.rb0_sz;
 505         rb_ptr = (uint64_t *)cqe_rx + rbptr_offset;
 506         nb_segs = cqe_rx_w0.rb_cnt;
 507         pkt = (struct rte_mbuf *)nicvf_mbuff_phy2virt
 508                         (rb_ptr[0] - cqe_rx_w1.align_pad, mbuf_phys_off);
 509
 510         pkt->pkt_len = cqe_rx_w1.pkt_len;
 511         pkt->data_len = rb_sz[nicvf_frag_num(0)];
 512         nicvf_mbuff_init_mseg_update(
 513                                 pkt, mbuf_init, cqe_rx_w1.align_pad, nb_segs);
 514         pkt->packet_type = nicvf_rx_classify_pkt(cqe_rx_w0);
 515         if (flag & NICVF_RX_OFFLOAD_NONE)
 516                 pkt->ol_flags = 0;
 517         if (flag & NICVF_RX_OFFLOAD_CKSUM)
 518                 pkt->ol_flags = nicvf_set_olflags(cqe_rx_w0);
 519         nicvf_rx_offload(cqe_rx_w0, cqe_rx_w2, pkt);
 520
 521         *rx_pkt = pkt;
 522         prev = pkt;
 523         for (seg_idx = 1; seg_idx < nb_segs; seg_idx++) {
 524                 seg = (struct rte_mbuf *)nicvf_mbuff_phy2virt
 525                         (rb_ptr[seg_idx], mbuf_phys_off);
 526
 527                 prev->next = seg;
 528                 seg->data_len = rb_sz[nicvf_frag_num(seg_idx)];
 529                 nicvf_mbuff_init_update(seg, mbuf_init, 0);
 530
 531                 prev = seg;
 532         }
 533         prev->next = NULL;
 534         return nb_segs;
 535 }
 536
 537 static __rte_always_inline uint16_t __hot
 538 nicvf_recv_pkts_multiseg(void *rx_queue, struct rte_mbuf **rx_pkts,
 539                          uint16_t nb_pkts, const uint32_t flag)
 540 {
 541         union cq_entry_t *cq_entry;
 542         struct cqe_rx_t *cqe_rx;
 543         struct nicvf_rxq *rxq = rx_queue;
 544         union cq_entry_t *desc = rxq->desc;
 545         const uint64_t cqe_mask = rxq->qlen_mask;
 546         uint64_t mbuf_phys_off = rxq->mbuf_phys_off;
 547         uint32_t i, to_process, cqe_head, buffers_consumed = 0;
 548         int32_t available_space = rxq->available_space;
 549         uint16_t nb_segs;
 550         const uint64_t mbuf_init = rxq->mbuf_initializer.value;
 551         const uint8_t rbptr_offset = rxq->rbptr_offset;
 552
 553         cqe_head = rxq->head & cqe_mask;
 554         to_process = nicvf_rx_pkts_to_process(rxq, nb_pkts, available_space);
 555
 556         for (i = 0; i < to_process; i++) {
 557                 rte_prefetch_non_temporal(&desc[cqe_head + 2]);
 558                 cq_entry = &desc[cqe_head];
 559                 cqe_rx = (struct cqe_rx_t *)cq_entry;
 560                 nb_segs = nicvf_process_cq_mseg_entry(cqe_rx, mbuf_phys_off,
 561                         rx_pkts + i, rbptr_offset, mbuf_init, flag);
 562                 buffers_consumed += nb_segs;
 563                 cqe_head = (cqe_head + 1) & cqe_mask;
 564                 nicvf_prefetch_store_keep(rx_pkts[i]);
 565         }
 566
 567         if (likely(to_process)) {
 568                 rxq->available_space -= to_process;
 569                 rxq->head = cqe_head;
 570                 nicvf_addr_write(rxq->cq_door, to_process);
 571                 rxq->recv_buffers += buffers_consumed;
 572         }
 573         if (rxq->recv_buffers > rxq->rx_free_thresh) {
 574                 rxq->recv_buffers -= nicvf_fill_rbdr(rxq, rxq->rx_free_thresh);
 575                 NICVF_RX_ASSERT(rxq->recv_buffers >= 0);
 576         }
 577
 578         return to_process;
 579 }
 580
 581 uint16_t __hot
 582 nicvf_recv_pkts_multiseg_no_offload(void *rx_queue, struct rte_mbuf **rx_pkts,
 583                 uint16_t nb_pkts)
 584 {
 585         return nicvf_recv_pkts_multiseg(rx_queue, rx_pkts, nb_pkts,
 586                         NICVF_RX_OFFLOAD_NONE);
 587 }
 588
 589 uint16_t __hot
 590 nicvf_recv_pkts_multiseg_cksum(void *rx_queue, struct rte_mbuf **rx_pkts,
 591                 uint16_t nb_pkts)
 592 {
 593         return nicvf_recv_pkts_multiseg(rx_queue, rx_pkts, nb_pkts,
 594                         NICVF_RX_OFFLOAD_CKSUM);
 595 }
 596
 597 uint32_t
 598 nicvf_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
 599 {
 600         struct nicvf_rxq *rxq;
 601
 602         rxq = dev->data->rx_queues[queue_idx];
 603         return nicvf_addr_read(rxq->cq_status) & NICVF_CQ_CQE_COUNT_MASK;
 604 }
 605
 606 uint32_t
 607 nicvf_dev_rbdr_refill(struct rte_eth_dev *dev, uint16_t queue_idx)
 608 {
 609         struct nicvf_rxq *rxq;
 610         uint32_t to_process;
 611         uint32_t rx_free;
 612
 613         rxq = dev->data->rx_queues[queue_idx];
 614         to_process = rxq->recv_buffers;
 615         while (rxq->recv_buffers > 0) {
 616                 rx_free = RTE_MIN(rxq->recv_buffers, NICVF_MAX_RX_FREE_THRESH);
 617                 rxq->recv_buffers -= nicvf_fill_rbdr(rxq, rx_free);
 618         }
 619
 620         assert(rxq->recv_buffers == 0);
 621         return to_process;
 622 }