drivers/net/txgbe/txgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd.
   3  * Copyright(c) 2010-2017 Intel Corporation
   4  */
   5
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <rte_common.h>
  11 #include <ethdev_pci.h>
  12
  13 #include <rte_interrupts.h>
  14 #include <rte_log.h>
  15 #include <rte_debug.h>
  16 #include <rte_pci.h>
  17 #include <rte_memory.h>
  18 #include <rte_eal.h>
  19 #include <rte_alarm.h>
  20 #include <rte_kvargs.h>
  21
  22 #include "txgbe_logs.h"
  23 #include "base/txgbe.h"
  24 #include "txgbe_ethdev.h"
  25 #include "txgbe_rxtx.h"
  26 #include "txgbe_regs_group.h"
  27
  28 static const struct reg_info txgbe_regs_general[] = {
  29         {TXGBE_RST, 1, 1, "TXGBE_RST"},
  30         {TXGBE_STAT, 1, 1, "TXGBE_STAT"},
  31         {TXGBE_PORTCTL, 1, 1, "TXGBE_PORTCTL"},
  32         {TXGBE_SDP, 1, 1, "TXGBE_SDP"},
  33         {TXGBE_SDPCTL, 1, 1, "TXGBE_SDPCTL"},
  34         {TXGBE_LEDCTL, 1, 1, "TXGBE_LEDCTL"},
  35         {0, 0, 0, ""}
  36 };
  37
  38 static const struct reg_info txgbe_regs_nvm[] = {
  39         {0, 0, 0, ""}
  40 };
  41
  42 static const struct reg_info txgbe_regs_interrupt[] = {
  43         {0, 0, 0, ""}
  44 };
  45
  46 static const struct reg_info txgbe_regs_fctl_others[] = {
  47         {0, 0, 0, ""}
  48 };
  49
  50 static const struct reg_info txgbe_regs_rxdma[] = {
  51         {0, 0, 0, ""}
  52 };
  53
  54 static const struct reg_info txgbe_regs_rx[] = {
  55         {0, 0, 0, ""}
  56 };
  57
  58 static struct reg_info txgbe_regs_tx[] = {
  59         {0, 0, 0, ""}
  60 };
  61
  62 static const struct reg_info txgbe_regs_wakeup[] = {
  63         {0, 0, 0, ""}
  64 };
  65
  66 static const struct reg_info txgbe_regs_dcb[] = {
  67         {0, 0, 0, ""}
  68 };
  69
  70 static const struct reg_info txgbe_regs_mac[] = {
  71         {0, 0, 0, ""}
  72 };
  73
  74 static const struct reg_info txgbe_regs_diagnostic[] = {
  75         {0, 0, 0, ""},
  76 };
  77
  78 /* PF registers */
  79 static const struct reg_info *txgbe_regs_others[] = {
  80                                 txgbe_regs_general,
  81                                 txgbe_regs_nvm,
  82                                 txgbe_regs_interrupt,
  83                                 txgbe_regs_fctl_others,
  84                                 txgbe_regs_rxdma,
  85                                 txgbe_regs_rx,
  86                                 txgbe_regs_tx,
  87                                 txgbe_regs_wakeup,
  88                                 txgbe_regs_dcb,
  89                                 txgbe_regs_mac,
  90                                 txgbe_regs_diagnostic,
  91                                 NULL};
  92
  93 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
  94 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
  95 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
  96 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
  97 static int  txgbe_dev_set_link_up(struct rte_eth_dev *dev);
  98 static int  txgbe_dev_set_link_down(struct rte_eth_dev *dev);
  99 static int txgbe_dev_close(struct rte_eth_dev *dev);
 100 static int txgbe_dev_link_update(struct rte_eth_dev *dev,
 101                                 int wait_to_complete);
 102 static int txgbe_dev_stats_reset(struct rte_eth_dev *dev);
 103 static void txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 104 static void txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev,
 105                                         uint16_t queue);
 106
 107 static void txgbe_dev_link_status_print(struct rte_eth_dev *dev);
 108 static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 109 static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 110 static int txgbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev);
 111 static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 112 static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 113 static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 114                                       struct rte_intr_handle *handle);
 115 static void txgbe_dev_interrupt_handler(void *param);
 116 static void txgbe_dev_interrupt_delayed_handler(void *param);
 117 static void txgbe_configure_msix(struct rte_eth_dev *dev);
 118
 119 static int txgbe_filter_restore(struct rte_eth_dev *dev);
 120 static void txgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 121
 122 #define TXGBE_SET_HWSTRIP(h, q) do {\
 123                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 124                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 125                 (h)->bitmap[idx] |= 1 << bit;\
 126         } while (0)
 127
 128 #define TXGBE_CLEAR_HWSTRIP(h, q) do {\
 129                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 130                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 131                 (h)->bitmap[idx] &= ~(1 << bit);\
 132         } while (0)
 133
 134 #define TXGBE_GET_HWSTRIP(h, q, r) do {\
 135                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 136                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 137                 (r) = (h)->bitmap[idx] >> bit & 1;\
 138         } while (0)
 139
 140 /*
 141  * The set of PCI devices this driver supports
 142  */
 143 static const struct rte_pci_id pci_id_txgbe_map[] = {
 144         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_SP1000) },
 145         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820) },
 146         { .vendor_id = 0, /* sentinel */ },
 147 };
 148
 149 static const struct rte_eth_desc_lim rx_desc_lim = {
 150         .nb_max = TXGBE_RING_DESC_MAX,
 151         .nb_min = TXGBE_RING_DESC_MIN,
 152         .nb_align = TXGBE_RXD_ALIGN,
 153 };
 154
 155 static const struct rte_eth_desc_lim tx_desc_lim = {
 156         .nb_max = TXGBE_RING_DESC_MAX,
 157         .nb_min = TXGBE_RING_DESC_MIN,
 158         .nb_align = TXGBE_TXD_ALIGN,
 159         .nb_seg_max = TXGBE_TX_MAX_SEG,
 160         .nb_mtu_seg_max = TXGBE_TX_MAX_SEG,
 161 };
 162
 163 static const struct eth_dev_ops txgbe_eth_dev_ops;
 164
 165 #define HW_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, m)}
 166 #define HW_XSTAT_NAME(m, n) {n, offsetof(struct txgbe_hw_stats, m)}
 167 static const struct rte_txgbe_xstats_name_off rte_txgbe_stats_strings[] = {
 168         /* MNG RxTx */
 169         HW_XSTAT(mng_bmc2host_packets),
 170         HW_XSTAT(mng_host2bmc_packets),
 171         /* Basic RxTx */
 172         HW_XSTAT(rx_packets),
 173         HW_XSTAT(tx_packets),
 174         HW_XSTAT(rx_bytes),
 175         HW_XSTAT(tx_bytes),
 176         HW_XSTAT(rx_total_bytes),
 177         HW_XSTAT(rx_total_packets),
 178         HW_XSTAT(tx_total_packets),
 179         HW_XSTAT(rx_total_missed_packets),
 180         HW_XSTAT(rx_broadcast_packets),
 181         HW_XSTAT(rx_multicast_packets),
 182         HW_XSTAT(rx_management_packets),
 183         HW_XSTAT(tx_management_packets),
 184         HW_XSTAT(rx_management_dropped),
 185
 186         /* Basic Error */
 187         HW_XSTAT(rx_crc_errors),
 188         HW_XSTAT(rx_illegal_byte_errors),
 189         HW_XSTAT(rx_error_bytes),
 190         HW_XSTAT(rx_mac_short_packet_dropped),
 191         HW_XSTAT(rx_length_errors),
 192         HW_XSTAT(rx_undersize_errors),
 193         HW_XSTAT(rx_fragment_errors),
 194         HW_XSTAT(rx_oversize_errors),
 195         HW_XSTAT(rx_jabber_errors),
 196         HW_XSTAT(rx_l3_l4_xsum_error),
 197         HW_XSTAT(mac_local_errors),
 198         HW_XSTAT(mac_remote_errors),
 199
 200         /* Flow Director */
 201         HW_XSTAT(flow_director_added_filters),
 202         HW_XSTAT(flow_director_removed_filters),
 203         HW_XSTAT(flow_director_filter_add_errors),
 204         HW_XSTAT(flow_director_filter_remove_errors),
 205         HW_XSTAT(flow_director_matched_filters),
 206         HW_XSTAT(flow_director_missed_filters),
 207
 208         /* FCoE */
 209         HW_XSTAT(rx_fcoe_crc_errors),
 210         HW_XSTAT(rx_fcoe_mbuf_allocation_errors),
 211         HW_XSTAT(rx_fcoe_dropped),
 212         HW_XSTAT(rx_fcoe_packets),
 213         HW_XSTAT(tx_fcoe_packets),
 214         HW_XSTAT(rx_fcoe_bytes),
 215         HW_XSTAT(tx_fcoe_bytes),
 216         HW_XSTAT(rx_fcoe_no_ddp),
 217         HW_XSTAT(rx_fcoe_no_ddp_ext_buff),
 218
 219         /* MACSEC */
 220         HW_XSTAT(tx_macsec_pkts_untagged),
 221         HW_XSTAT(tx_macsec_pkts_encrypted),
 222         HW_XSTAT(tx_macsec_pkts_protected),
 223         HW_XSTAT(tx_macsec_octets_encrypted),
 224         HW_XSTAT(tx_macsec_octets_protected),
 225         HW_XSTAT(rx_macsec_pkts_untagged),
 226         HW_XSTAT(rx_macsec_pkts_badtag),
 227         HW_XSTAT(rx_macsec_pkts_nosci),
 228         HW_XSTAT(rx_macsec_pkts_unknownsci),
 229         HW_XSTAT(rx_macsec_octets_decrypted),
 230         HW_XSTAT(rx_macsec_octets_validated),
 231         HW_XSTAT(rx_macsec_sc_pkts_unchecked),
 232         HW_XSTAT(rx_macsec_sc_pkts_delayed),
 233         HW_XSTAT(rx_macsec_sc_pkts_late),
 234         HW_XSTAT(rx_macsec_sa_pkts_ok),
 235         HW_XSTAT(rx_macsec_sa_pkts_invalid),
 236         HW_XSTAT(rx_macsec_sa_pkts_notvalid),
 237         HW_XSTAT(rx_macsec_sa_pkts_unusedsa),
 238         HW_XSTAT(rx_macsec_sa_pkts_notusingsa),
 239
 240         /* MAC RxTx */
 241         HW_XSTAT(rx_size_64_packets),
 242         HW_XSTAT(rx_size_65_to_127_packets),
 243         HW_XSTAT(rx_size_128_to_255_packets),
 244         HW_XSTAT(rx_size_256_to_511_packets),
 245         HW_XSTAT(rx_size_512_to_1023_packets),
 246         HW_XSTAT(rx_size_1024_to_max_packets),
 247         HW_XSTAT(tx_size_64_packets),
 248         HW_XSTAT(tx_size_65_to_127_packets),
 249         HW_XSTAT(tx_size_128_to_255_packets),
 250         HW_XSTAT(tx_size_256_to_511_packets),
 251         HW_XSTAT(tx_size_512_to_1023_packets),
 252         HW_XSTAT(tx_size_1024_to_max_packets),
 253
 254         /* Flow Control */
 255         HW_XSTAT(tx_xon_packets),
 256         HW_XSTAT(rx_xon_packets),
 257         HW_XSTAT(tx_xoff_packets),
 258         HW_XSTAT(rx_xoff_packets),
 259
 260         HW_XSTAT_NAME(tx_xon_packets, "tx_flow_control_xon_packets"),
 261         HW_XSTAT_NAME(rx_xon_packets, "rx_flow_control_xon_packets"),
 262         HW_XSTAT_NAME(tx_xoff_packets, "tx_flow_control_xoff_packets"),
 263         HW_XSTAT_NAME(rx_xoff_packets, "rx_flow_control_xoff_packets"),
 264 };
 265
 266 #define TXGBE_NB_HW_STATS (sizeof(rte_txgbe_stats_strings) / \
 267                            sizeof(rte_txgbe_stats_strings[0]))
 268
 269 /* Per-priority statistics */
 270 #define UP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, up[0].m)}
 271 static const struct rte_txgbe_xstats_name_off rte_txgbe_up_strings[] = {
 272         UP_XSTAT(rx_up_packets),
 273         UP_XSTAT(tx_up_packets),
 274         UP_XSTAT(rx_up_bytes),
 275         UP_XSTAT(tx_up_bytes),
 276         UP_XSTAT(rx_up_drop_packets),
 277
 278         UP_XSTAT(tx_up_xon_packets),
 279         UP_XSTAT(rx_up_xon_packets),
 280         UP_XSTAT(tx_up_xoff_packets),
 281         UP_XSTAT(rx_up_xoff_packets),
 282         UP_XSTAT(rx_up_dropped),
 283         UP_XSTAT(rx_up_mbuf_alloc_errors),
 284         UP_XSTAT(tx_up_xon2off_packets),
 285 };
 286
 287 #define TXGBE_NB_UP_STATS (sizeof(rte_txgbe_up_strings) / \
 288                            sizeof(rte_txgbe_up_strings[0]))
 289
 290 /* Per-queue statistics */
 291 #define QP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, qp[0].m)}
 292 static const struct rte_txgbe_xstats_name_off rte_txgbe_qp_strings[] = {
 293         QP_XSTAT(rx_qp_packets),
 294         QP_XSTAT(tx_qp_packets),
 295         QP_XSTAT(rx_qp_bytes),
 296         QP_XSTAT(tx_qp_bytes),
 297         QP_XSTAT(rx_qp_mc_packets),
 298 };
 299
 300 #define TXGBE_NB_QP_STATS (sizeof(rte_txgbe_qp_strings) / \
 301                            sizeof(rte_txgbe_qp_strings[0]))
 302
 303 static inline int
 304 txgbe_is_sfp(struct txgbe_hw *hw)
 305 {
 306         switch (hw->phy.type) {
 307         case txgbe_phy_sfp_avago:
 308         case txgbe_phy_sfp_ftl:
 309         case txgbe_phy_sfp_intel:
 310         case txgbe_phy_sfp_unknown:
 311         case txgbe_phy_sfp_tyco_passive:
 312         case txgbe_phy_sfp_unknown_passive:
 313                 return 1;
 314         default:
 315                 return 0;
 316         }
 317 }
 318
 319 static inline int32_t
 320 txgbe_pf_reset_hw(struct txgbe_hw *hw)
 321 {
 322         uint32_t ctrl_ext;
 323         int32_t status;
 324
 325         status = hw->mac.reset_hw(hw);
 326
 327         ctrl_ext = rd32(hw, TXGBE_PORTCTL);
 328         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 329         ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
 330         wr32(hw, TXGBE_PORTCTL, ctrl_ext);
 331         txgbe_flush(hw);
 332
 333         if (status == TXGBE_ERR_SFP_NOT_PRESENT)
 334                 status = 0;
 335         return status;
 336 }
 337
 338 static inline void
 339 txgbe_enable_intr(struct rte_eth_dev *dev)
 340 {
 341         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
 342         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 343
 344         wr32(hw, TXGBE_IENMISC, intr->mask_misc);
 345         wr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK);
 346         wr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK);
 347         txgbe_flush(hw);
 348 }
 349
 350 static void
 351 txgbe_disable_intr(struct txgbe_hw *hw)
 352 {
 353         PMD_INIT_FUNC_TRACE();
 354
 355         wr32(hw, TXGBE_IENMISC, ~BIT_MASK32);
 356         wr32(hw, TXGBE_IMS(0), TXGBE_IMC_MASK);
 357         wr32(hw, TXGBE_IMS(1), TXGBE_IMC_MASK);
 358         txgbe_flush(hw);
 359 }
 360
 361 static int
 362 txgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 363                                   uint16_t queue_id,
 364                                   uint8_t stat_idx,
 365                                   uint8_t is_rx)
 366 {
 367         struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
 368         struct txgbe_stat_mappings *stat_mappings =
 369                 TXGBE_DEV_STAT_MAPPINGS(eth_dev);
 370         uint32_t qsmr_mask = 0;
 371         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 372         uint32_t q_map;
 373         uint8_t n, offset;
 374
 375         if (hw->mac.type != txgbe_mac_raptor)
 376                 return -ENOSYS;
 377
 378         if (stat_idx & !QMAP_FIELD_RESERVED_BITS_MASK)
 379                 return -EIO;
 380
 381         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 382                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 383                      queue_id, stat_idx);
 384
 385         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 386         if (n >= TXGBE_NB_STAT_MAPPING) {
 387                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 388                 return -EIO;
 389         }
 390         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 391
 392         /* Now clear any previous stat_idx set */
 393         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 394         if (!is_rx)
 395                 stat_mappings->tqsm[n] &= ~clearing_mask;
 396         else
 397                 stat_mappings->rqsm[n] &= ~clearing_mask;
 398
 399         q_map = (uint32_t)stat_idx;
 400         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 401         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 402         if (!is_rx)
 403                 stat_mappings->tqsm[n] |= qsmr_mask;
 404         else
 405                 stat_mappings->rqsm[n] |= qsmr_mask;
 406
 407         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 408                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 409                      queue_id, stat_idx);
 410         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 411                      is_rx ? stat_mappings->rqsm[n] : stat_mappings->tqsm[n]);
 412         return 0;
 413 }
 414
 415 static void
 416 txgbe_dcb_init(struct txgbe_hw *hw, struct txgbe_dcb_config *dcb_config)
 417 {
 418         int i;
 419         u8 bwgp;
 420         struct txgbe_dcb_tc_config *tc;
 421
 422         UNREFERENCED_PARAMETER(hw);
 423
 424         dcb_config->num_tcs.pg_tcs = TXGBE_DCB_TC_MAX;
 425         dcb_config->num_tcs.pfc_tcs = TXGBE_DCB_TC_MAX;
 426         bwgp = (u8)(100 / TXGBE_DCB_TC_MAX);
 427         for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
 428                 tc = &dcb_config->tc_config[i];
 429                 tc->path[TXGBE_DCB_TX_CONFIG].bwg_id = i;
 430                 tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent = bwgp + (i & 1);
 431                 tc->path[TXGBE_DCB_RX_CONFIG].bwg_id = i;
 432                 tc->path[TXGBE_DCB_RX_CONFIG].bwg_percent = bwgp + (i & 1);
 433                 tc->pfc = txgbe_dcb_pfc_disabled;
 434         }
 435
 436         /* Initialize default user to priority mapping, UPx->TC0 */
 437         tc = &dcb_config->tc_config[0];
 438         tc->path[TXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 439         tc->path[TXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 440         for (i = 0; i < TXGBE_DCB_BWG_MAX; i++) {
 441                 dcb_config->bw_percentage[i][TXGBE_DCB_TX_CONFIG] = 100;
 442                 dcb_config->bw_percentage[i][TXGBE_DCB_RX_CONFIG] = 100;
 443         }
 444         dcb_config->rx_pba_cfg = txgbe_dcb_pba_equal;
 445         dcb_config->pfc_mode_enable = false;
 446         dcb_config->vt_mode = true;
 447         dcb_config->round_robin_enable = false;
 448         /* support all DCB capabilities */
 449         dcb_config->support.capabilities = 0xFF;
 450 }
 451
 452 /*
 453  * Ensure that all locks are released before first NVM or PHY access
 454  */
 455 static void
 456 txgbe_swfw_lock_reset(struct txgbe_hw *hw)
 457 {
 458         uint16_t mask;
 459
 460         /*
 461          * These ones are more tricky since they are common to all ports; but
 462          * swfw_sync retries last long enough (1s) to be almost sure that if
 463          * lock can not be taken it is due to an improper lock of the
 464          * semaphore.
 465          */
 466         mask = TXGBE_MNGSEM_SWPHY |
 467                TXGBE_MNGSEM_SWMBX |
 468                TXGBE_MNGSEM_SWFLASH;
 469         if (hw->mac.acquire_swfw_sync(hw, mask) < 0)
 470                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 471
 472         hw->mac.release_swfw_sync(hw, mask);
 473 }
 474
 475 static int
 476 txgbe_handle_devarg(__rte_unused const char *key, const char *value,
 477                   void *extra_args)
 478 {
 479         uint16_t *n = extra_args;
 480
 481         if (value == NULL || extra_args == NULL)
 482                 return -EINVAL;
 483
 484         *n = (uint16_t)strtoul(value, NULL, 10);
 485         if (*n == USHRT_MAX && errno == ERANGE)
 486                 return -1;
 487
 488         return 0;
 489 }
 490
 491 static void
 492 txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs)
 493 {
 494         struct rte_kvargs *kvlist;
 495         u16 auto_neg = 1;
 496         u16 poll = 0;
 497         u16 present = 1;
 498         u16 sgmii = 0;
 499         u16 ffe_set = 0;
 500         u16 ffe_main = 27;
 501         u16 ffe_pre = 8;
 502         u16 ffe_post = 44;
 503
 504         if (devargs == NULL)
 505                 goto null;
 506
 507         kvlist = rte_kvargs_parse(devargs->args, txgbe_valid_arguments);
 508         if (kvlist == NULL)
 509                 goto null;
 510
 511         rte_kvargs_process(kvlist, TXGBE_DEVARG_BP_AUTO,
 512                            &txgbe_handle_devarg, &auto_neg);
 513         rte_kvargs_process(kvlist, TXGBE_DEVARG_KR_POLL,
 514                            &txgbe_handle_devarg, &poll);
 515         rte_kvargs_process(kvlist, TXGBE_DEVARG_KR_PRESENT,
 516                            &txgbe_handle_devarg, &present);
 517         rte_kvargs_process(kvlist, TXGBE_DEVARG_KX_SGMII,
 518                            &txgbe_handle_devarg, &sgmii);
 519         rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_SET,
 520                            &txgbe_handle_devarg, &ffe_set);
 521         rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_MAIN,
 522                            &txgbe_handle_devarg, &ffe_main);
 523         rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_PRE,
 524                            &txgbe_handle_devarg, &ffe_pre);
 525         rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_POST,
 526                            &txgbe_handle_devarg, &ffe_post);
 527         rte_kvargs_free(kvlist);
 528
 529 null:
 530         hw->devarg.auto_neg = auto_neg;
 531         hw->devarg.poll = poll;
 532         hw->devarg.present = present;
 533         hw->devarg.sgmii = sgmii;
 534         hw->phy.ffe_set = ffe_set;
 535         hw->phy.ffe_main = ffe_main;
 536         hw->phy.ffe_pre = ffe_pre;
 537         hw->phy.ffe_post = ffe_post;
 538 }
 539
 540 static int
 541 eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
 542 {
 543         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 544         struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
 545         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(eth_dev);
 546         struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(eth_dev);
 547         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(eth_dev);
 548         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
 549         struct txgbe_bw_conf *bw_conf = TXGBE_DEV_BW_CONF(eth_dev);
 550         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 551         const struct rte_memzone *mz;
 552         uint32_t ctrl_ext;
 553         uint16_t csum;
 554         int err, i, ret;
 555
 556         PMD_INIT_FUNC_TRACE();
 557
 558         eth_dev->dev_ops = &txgbe_eth_dev_ops;
 559         eth_dev->rx_queue_count       = txgbe_dev_rx_queue_count;
 560         eth_dev->rx_descriptor_status = txgbe_dev_rx_descriptor_status;
 561         eth_dev->tx_descriptor_status = txgbe_dev_tx_descriptor_status;
 562         eth_dev->rx_pkt_burst = &txgbe_recv_pkts;
 563         eth_dev->tx_pkt_burst = &txgbe_xmit_pkts;
 564         eth_dev->tx_pkt_prepare = &txgbe_prep_pkts;
 565
 566         /*
 567          * For secondary processes, we don't initialise any further as primary
 568          * has already done this work. Only check we don't need a different
 569          * RX and TX function.
 570          */
 571         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 572                 struct txgbe_tx_queue *txq;
 573                 /* TX queue function in primary, set by last queue initialized
 574                  * Tx queue may not initialized by primary process
 575                  */
 576                 if (eth_dev->data->tx_queues) {
 577                         uint16_t nb_tx_queues = eth_dev->data->nb_tx_queues;
 578                         txq = eth_dev->data->tx_queues[nb_tx_queues - 1];
 579                         txgbe_set_tx_function(eth_dev, txq);
 580                 } else {
 581                         /* Use default TX function if we get here */
 582                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
 583                                      "Using default TX function.");
 584                 }
 585
 586                 txgbe_set_rx_function(eth_dev);
 587
 588                 return 0;
 589         }
 590
 591         rte_eth_copy_pci_info(eth_dev, pci_dev);
 592
 593         /* Vendor and Device ID need to be set before init of shared code */
 594         hw->device_id = pci_dev->id.device_id;
 595         hw->vendor_id = pci_dev->id.vendor_id;
 596         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 597         hw->allow_unsupported_sfp = 1;
 598
 599         /* Reserve memory for interrupt status block */
 600         mz = rte_eth_dma_zone_reserve(eth_dev, "txgbe_driver", -1,
 601                 16, TXGBE_ALIGN, SOCKET_ID_ANY);
 602         if (mz == NULL)
 603                 return -ENOMEM;
 604
 605         hw->isb_dma = TMZ_PADDR(mz);
 606         hw->isb_mem = TMZ_VADDR(mz);
 607
 608         txgbe_parse_devargs(hw, pci_dev->device.devargs);
 609         /* Initialize the shared code (base driver) */
 610         err = txgbe_init_shared_code(hw);
 611         if (err != 0) {
 612                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", err);
 613                 return -EIO;
 614         }
 615
 616         /* Unlock any pending hardware semaphore */
 617         txgbe_swfw_lock_reset(hw);
 618
 619 #ifdef RTE_LIB_SECURITY
 620         /* Initialize security_ctx only for primary process*/
 621         if (txgbe_ipsec_ctx_create(eth_dev))
 622                 return -ENOMEM;
 623 #endif
 624
 625         /* Initialize DCB configuration*/
 626         memset(dcb_config, 0, sizeof(struct txgbe_dcb_config));
 627         txgbe_dcb_init(hw, dcb_config);
 628
 629         /* Get Hardware Flow Control setting */
 630         hw->fc.requested_mode = txgbe_fc_full;
 631         hw->fc.current_mode = txgbe_fc_full;
 632         hw->fc.pause_time = TXGBE_FC_PAUSE_TIME;
 633         for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
 634                 hw->fc.low_water[i] = TXGBE_FC_XON_LOTH;
 635                 hw->fc.high_water[i] = TXGBE_FC_XOFF_HITH;
 636         }
 637         hw->fc.send_xon = 1;
 638
 639         err = hw->rom.init_params(hw);
 640         if (err != 0) {
 641                 PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err);
 642                 return -EIO;
 643         }
 644
 645         /* Make sure we have a good EEPROM before we read from it */
 646         err = hw->rom.validate_checksum(hw, &csum);
 647         if (err != 0) {
 648                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", err);
 649                 return -EIO;
 650         }
 651
 652         err = hw->mac.init_hw(hw);
 653
 654         /*
 655          * Devices with copper phys will fail to initialise if txgbe_init_hw()
 656          * is called too soon after the kernel driver unbinding/binding occurs.
 657          * The failure occurs in txgbe_identify_phy() for all devices,
 658          * but for non-copper devies, txgbe_identify_sfp_module() is
 659          * also called. See txgbe_identify_phy(). The reason for the
 660          * failure is not known, and only occuts when virtualisation features
 661          * are disabled in the bios. A delay of 200ms  was found to be enough by
 662          * trial-and-error, and is doubled to be safe.
 663          */
 664         if (err && hw->phy.media_type == txgbe_media_type_copper) {
 665                 rte_delay_ms(200);
 666                 err = hw->mac.init_hw(hw);
 667         }
 668
 669         if (err == TXGBE_ERR_SFP_NOT_PRESENT)
 670                 err = 0;
 671
 672         if (err == TXGBE_ERR_EEPROM_VERSION) {
 673                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 674                              "LOM.  Please be aware there may be issues associated "
 675                              "with your hardware.");
 676                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 677                              "please contact your hardware representative "
 678                              "who provided you with this hardware.");
 679         } else if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) {
 680                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 681         }
 682         if (err) {
 683                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err);
 684                 return -EIO;
 685         }
 686
 687         /* Reset the hw statistics */
 688         txgbe_dev_stats_reset(eth_dev);
 689
 690         /* disable interrupt */
 691         txgbe_disable_intr(hw);
 692
 693         /* Allocate memory for storing MAC addresses */
 694         eth_dev->data->mac_addrs = rte_zmalloc("txgbe", RTE_ETHER_ADDR_LEN *
 695                                                hw->mac.num_rar_entries, 0);
 696         if (eth_dev->data->mac_addrs == NULL) {
 697                 PMD_INIT_LOG(ERR,
 698                              "Failed to allocate %u bytes needed to store "
 699                              "MAC addresses",
 700                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 701                 return -ENOMEM;
 702         }
 703
 704         /* Copy the permanent MAC address */
 705         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
 706                         &eth_dev->data->mac_addrs[0]);
 707
 708         /* Allocate memory for storing hash filter MAC addresses */
 709         eth_dev->data->hash_mac_addrs = rte_zmalloc("txgbe",
 710                         RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC, 0);
 711         if (eth_dev->data->hash_mac_addrs == NULL) {
 712                 PMD_INIT_LOG(ERR,
 713                              "Failed to allocate %d bytes needed to store MAC addresses",
 714                              RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC);
 715                 return -ENOMEM;
 716         }
 717
 718         /* initialize the vfta */
 719         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 720
 721         /* initialize the hw strip bitmap*/
 722         memset(hwstrip, 0, sizeof(*hwstrip));
 723
 724         /* initialize PF if max_vfs not zero */
 725         ret = txgbe_pf_host_init(eth_dev);
 726         if (ret) {
 727                 rte_free(eth_dev->data->mac_addrs);
 728                 eth_dev->data->mac_addrs = NULL;
 729                 rte_free(eth_dev->data->hash_mac_addrs);
 730                 eth_dev->data->hash_mac_addrs = NULL;
 731                 return ret;
 732         }
 733
 734         ctrl_ext = rd32(hw, TXGBE_PORTCTL);
 735         /* let hardware know driver is loaded */
 736         ctrl_ext |= TXGBE_PORTCTL_DRVLOAD;
 737         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 738         ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
 739         wr32(hw, TXGBE_PORTCTL, ctrl_ext);
 740         txgbe_flush(hw);
 741
 742         if (txgbe_is_sfp(hw) && hw->phy.sfp_type != txgbe_sfp_type_not_present)
 743                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 744                              (int)hw->mac.type, (int)hw->phy.type,
 745                              (int)hw->phy.sfp_type);
 746         else
 747                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 748                              (int)hw->mac.type, (int)hw->phy.type);
 749
 750         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 751                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 752                      pci_dev->id.device_id);
 753
 754         rte_intr_callback_register(intr_handle,
 755                                    txgbe_dev_interrupt_handler, eth_dev);
 756
 757         /* enable uio/vfio intr/eventfd mapping */
 758         rte_intr_enable(intr_handle);
 759
 760         /* enable support intr */
 761         txgbe_enable_intr(eth_dev);
 762
 763         /* initialize filter info */
 764         memset(filter_info, 0,
 765                sizeof(struct txgbe_filter_info));
 766
 767         /* initialize 5tuple filter list */
 768         TAILQ_INIT(&filter_info->fivetuple_list);
 769
 770         /* initialize flow director filter list & hash */
 771         txgbe_fdir_filter_init(eth_dev);
 772
 773         /* initialize l2 tunnel filter list & hash */
 774         txgbe_l2_tn_filter_init(eth_dev);
 775
 776         /* initialize flow filter lists */
 777         txgbe_filterlist_init();
 778
 779         /* initialize bandwidth configuration info */
 780         memset(bw_conf, 0, sizeof(struct txgbe_bw_conf));
 781
 782         /* initialize Traffic Manager configuration */
 783         txgbe_tm_conf_init(eth_dev);
 784
 785         return 0;
 786 }
 787
 788 static int
 789 eth_txgbe_dev_uninit(struct rte_eth_dev *eth_dev)
 790 {
 791         PMD_INIT_FUNC_TRACE();
 792
 793         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 794                 return 0;
 795
 796         txgbe_dev_close(eth_dev);
 797
 798         return 0;
 799 }
 800
 801 static int txgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 802 {
 803         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
 804         struct txgbe_5tuple_filter *p_5tuple;
 805
 806         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 807                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 808                              p_5tuple,
 809                              entries);
 810                 rte_free(p_5tuple);
 811         }
 812         memset(filter_info->fivetuple_mask, 0,
 813                sizeof(uint32_t) * TXGBE_5TUPLE_ARRAY_SIZE);
 814
 815         return 0;
 816 }
 817
 818 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
 819 {
 820         struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev);
 821         struct txgbe_fdir_filter *fdir_filter;
 822
 823         if (fdir_info->hash_map)
 824                 rte_free(fdir_info->hash_map);
 825         if (fdir_info->hash_handle)
 826                 rte_hash_free(fdir_info->hash_handle);
 827
 828         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
 829                 TAILQ_REMOVE(&fdir_info->fdir_list,
 830                              fdir_filter,
 831                              entries);
 832                 rte_free(fdir_filter);
 833         }
 834
 835         return 0;
 836 }
 837
 838 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
 839 {
 840         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev);
 841         struct txgbe_l2_tn_filter *l2_tn_filter;
 842
 843         if (l2_tn_info->hash_map)
 844                 rte_free(l2_tn_info->hash_map);
 845         if (l2_tn_info->hash_handle)
 846                 rte_hash_free(l2_tn_info->hash_handle);
 847
 848         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
 849                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
 850                              l2_tn_filter,
 851                              entries);
 852                 rte_free(l2_tn_filter);
 853         }
 854
 855         return 0;
 856 }
 857
 858 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
 859 {
 860         struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev);
 861         char fdir_hash_name[RTE_HASH_NAMESIZE];
 862         struct rte_hash_parameters fdir_hash_params = {
 863                 .name = fdir_hash_name,
 864                 .entries = TXGBE_MAX_FDIR_FILTER_NUM,
 865                 .key_len = sizeof(struct txgbe_atr_input),
 866                 .hash_func = rte_hash_crc,
 867                 .hash_func_init_val = 0,
 868                 .socket_id = rte_socket_id(),
 869         };
 870
 871         TAILQ_INIT(&fdir_info->fdir_list);
 872         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 873                  "fdir_%s", TDEV_NAME(eth_dev));
 874         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
 875         if (!fdir_info->hash_handle) {
 876                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 877                 return -EINVAL;
 878         }
 879         fdir_info->hash_map = rte_zmalloc("txgbe",
 880                                           sizeof(struct txgbe_fdir_filter *) *
 881                                           TXGBE_MAX_FDIR_FILTER_NUM,
 882                                           0);
 883         if (!fdir_info->hash_map) {
 884                 PMD_INIT_LOG(ERR,
 885                              "Failed to allocate memory for fdir hash map!");
 886                 return -ENOMEM;
 887         }
 888         fdir_info->mask_added = FALSE;
 889
 890         return 0;
 891 }
 892
 893 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
 894 {
 895         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev);
 896         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
 897         struct rte_hash_parameters l2_tn_hash_params = {
 898                 .name = l2_tn_hash_name,
 899                 .entries = TXGBE_MAX_L2_TN_FILTER_NUM,
 900                 .key_len = sizeof(struct txgbe_l2_tn_key),
 901                 .hash_func = rte_hash_crc,
 902                 .hash_func_init_val = 0,
 903                 .socket_id = rte_socket_id(),
 904         };
 905
 906         TAILQ_INIT(&l2_tn_info->l2_tn_list);
 907         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
 908                  "l2_tn_%s", TDEV_NAME(eth_dev));
 909         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
 910         if (!l2_tn_info->hash_handle) {
 911                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
 912                 return -EINVAL;
 913         }
 914         l2_tn_info->hash_map = rte_zmalloc("txgbe",
 915                                    sizeof(struct txgbe_l2_tn_filter *) *
 916                                    TXGBE_MAX_L2_TN_FILTER_NUM,
 917                                    0);
 918         if (!l2_tn_info->hash_map) {
 919                 PMD_INIT_LOG(ERR,
 920                         "Failed to allocate memory for L2 TN hash map!");
 921                 return -ENOMEM;
 922         }
 923         l2_tn_info->e_tag_en = FALSE;
 924         l2_tn_info->e_tag_fwd_en = FALSE;
 925         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
 926
 927         return 0;
 928 }
 929
 930 static int
 931 eth_txgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 932                 struct rte_pci_device *pci_dev)
 933 {
 934         return rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 935                         sizeof(struct txgbe_adapter),
 936                         eth_dev_pci_specific_init, pci_dev,
 937                         eth_txgbe_dev_init, NULL);
 938 }
 939
 940 static int eth_txgbe_pci_remove(struct rte_pci_device *pci_dev)
 941 {
 942         struct rte_eth_dev *ethdev;
 943
 944         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 945         if (!ethdev)
 946                 return 0;
 947
 948         return rte_eth_dev_destroy(ethdev, eth_txgbe_dev_uninit);
 949 }
 950
 951 static struct rte_pci_driver rte_txgbe_pmd = {
 952         .id_table = pci_id_txgbe_map,
 953         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
 954                      RTE_PCI_DRV_INTR_LSC,
 955         .probe = eth_txgbe_pci_probe,
 956         .remove = eth_txgbe_pci_remove,
 957 };
 958
 959 static int
 960 txgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 961 {
 962         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 963         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
 964         uint32_t vfta;
 965         uint32_t vid_idx;
 966         uint32_t vid_bit;
 967
 968         vid_idx = (uint32_t)((vlan_id >> 5) & 0x7F);
 969         vid_bit = (uint32_t)(1 << (vlan_id & 0x1F));
 970         vfta = rd32(hw, TXGBE_VLANTBL(vid_idx));
 971         if (on)
 972                 vfta |= vid_bit;
 973         else
 974                 vfta &= ~vid_bit;
 975         wr32(hw, TXGBE_VLANTBL(vid_idx), vfta);
 976
 977         /* update local VFTA copy */
 978         shadow_vfta->vfta[vid_idx] = vfta;
 979
 980         return 0;
 981 }
 982
 983 static void
 984 txgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
 985 {
 986         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 987         struct txgbe_rx_queue *rxq;
 988         bool restart;
 989         uint32_t rxcfg, rxbal, rxbah;
 990
 991         if (on)
 992                 txgbe_vlan_hw_strip_enable(dev, queue);
 993         else
 994                 txgbe_vlan_hw_strip_disable(dev, queue);
 995
 996         rxq = dev->data->rx_queues[queue];
 997         rxbal = rd32(hw, TXGBE_RXBAL(rxq->reg_idx));
 998         rxbah = rd32(hw, TXGBE_RXBAH(rxq->reg_idx));
 999         rxcfg = rd32(hw, TXGBE_RXCFG(rxq->reg_idx));
1000         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
1001                 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
1002                         !(rxcfg & TXGBE_RXCFG_VLAN);
1003                 rxcfg |= TXGBE_RXCFG_VLAN;
1004         } else {
1005                 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
1006                         (rxcfg & TXGBE_RXCFG_VLAN);
1007                 rxcfg &= ~TXGBE_RXCFG_VLAN;
1008         }
1009         rxcfg &= ~TXGBE_RXCFG_ENA;
1010
1011         if (restart) {
1012                 /* set vlan strip for ring */
1013                 txgbe_dev_rx_queue_stop(dev, queue);
1014                 wr32(hw, TXGBE_RXBAL(rxq->reg_idx), rxbal);
1015                 wr32(hw, TXGBE_RXBAH(rxq->reg_idx), rxbah);
1016                 wr32(hw, TXGBE_RXCFG(rxq->reg_idx), rxcfg);
1017                 txgbe_dev_rx_queue_start(dev, queue);
1018         }
1019 }
1020
1021 static int
1022 txgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1023                     enum rte_vlan_type vlan_type,
1024                     uint16_t tpid)
1025 {
1026         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1027         int ret = 0;
1028         uint32_t portctrl, vlan_ext, qinq;
1029
1030         portctrl = rd32(hw, TXGBE_PORTCTL);
1031
1032         vlan_ext = (portctrl & TXGBE_PORTCTL_VLANEXT);
1033         qinq = vlan_ext && (portctrl & TXGBE_PORTCTL_QINQ);
1034         switch (vlan_type) {
1035         case ETH_VLAN_TYPE_INNER:
1036                 if (vlan_ext) {
1037                         wr32m(hw, TXGBE_VLANCTL,
1038                                 TXGBE_VLANCTL_TPID_MASK,
1039                                 TXGBE_VLANCTL_TPID(tpid));
1040                         wr32m(hw, TXGBE_DMATXCTRL,
1041                                 TXGBE_DMATXCTRL_TPID_MASK,
1042                                 TXGBE_DMATXCTRL_TPID(tpid));
1043                 } else {
1044                         ret = -ENOTSUP;
1045                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1046                                     " by single VLAN");
1047                 }
1048
1049                 if (qinq) {
1050                         wr32m(hw, TXGBE_TAGTPID(0),
1051                                 TXGBE_TAGTPID_LSB_MASK,
1052                                 TXGBE_TAGTPID_LSB(tpid));
1053                 }
1054                 break;
1055         case ETH_VLAN_TYPE_OUTER:
1056                 if (vlan_ext) {
1057                         /* Only the high 16-bits is valid */
1058                         wr32m(hw, TXGBE_EXTAG,
1059                                 TXGBE_EXTAG_VLAN_MASK,
1060                                 TXGBE_EXTAG_VLAN(tpid));
1061                 } else {
1062                         wr32m(hw, TXGBE_VLANCTL,
1063                                 TXGBE_VLANCTL_TPID_MASK,
1064                                 TXGBE_VLANCTL_TPID(tpid));
1065                         wr32m(hw, TXGBE_DMATXCTRL,
1066                                 TXGBE_DMATXCTRL_TPID_MASK,
1067                                 TXGBE_DMATXCTRL_TPID(tpid));
1068                 }
1069
1070                 if (qinq) {
1071                         wr32m(hw, TXGBE_TAGTPID(0),
1072                                 TXGBE_TAGTPID_MSB_MASK,
1073                                 TXGBE_TAGTPID_MSB(tpid));
1074                 }
1075                 break;
1076         default:
1077                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1078                 return -EINVAL;
1079         }
1080
1081         return ret;
1082 }
1083
1084 void
1085 txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1086 {
1087         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1088         uint32_t vlnctrl;
1089
1090         PMD_INIT_FUNC_TRACE();
1091
1092         /* Filter Table Disable */
1093         vlnctrl = rd32(hw, TXGBE_VLANCTL);
1094         vlnctrl &= ~TXGBE_VLANCTL_VFE;
1095         wr32(hw, TXGBE_VLANCTL, vlnctrl);
1096 }
1097
1098 void
1099 txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1100 {
1101         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1102         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
1103         uint32_t vlnctrl;
1104         uint16_t i;
1105
1106         PMD_INIT_FUNC_TRACE();
1107
1108         /* Filter Table Enable */
1109         vlnctrl = rd32(hw, TXGBE_VLANCTL);
1110         vlnctrl &= ~TXGBE_VLANCTL_CFIENA;
1111         vlnctrl |= TXGBE_VLANCTL_VFE;
1112         wr32(hw, TXGBE_VLANCTL, vlnctrl);
1113
1114         /* write whatever is in local vfta copy */
1115         for (i = 0; i < TXGBE_VFTA_SIZE; i++)
1116                 wr32(hw, TXGBE_VLANTBL(i), shadow_vfta->vfta[i]);
1117 }
1118
1119 void
1120 txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1121 {
1122         struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(dev);
1123         struct txgbe_rx_queue *rxq;
1124
1125         if (queue >= TXGBE_MAX_RX_QUEUE_NUM)
1126                 return;
1127
1128         if (on)
1129                 TXGBE_SET_HWSTRIP(hwstrip, queue);
1130         else
1131                 TXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1132
1133         if (queue >= dev->data->nb_rx_queues)
1134                 return;
1135
1136         rxq = dev->data->rx_queues[queue];
1137
1138         if (on) {
1139                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1140                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1141         } else {
1142                 rxq->vlan_flags = PKT_RX_VLAN;
1143                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1144         }
1145 }
1146
1147 static void
1148 txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1149 {
1150         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1151         uint32_t ctrl;
1152
1153         PMD_INIT_FUNC_TRACE();
1154
1155         ctrl = rd32(hw, TXGBE_RXCFG(queue));
1156         ctrl &= ~TXGBE_RXCFG_VLAN;
1157         wr32(hw, TXGBE_RXCFG(queue), ctrl);
1158
1159         /* record those setting for HW strip per queue */
1160         txgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1161 }
1162
1163 static void
1164 txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1165 {
1166         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1167         uint32_t ctrl;
1168
1169         PMD_INIT_FUNC_TRACE();
1170
1171         ctrl = rd32(hw, TXGBE_RXCFG(queue));
1172         ctrl |= TXGBE_RXCFG_VLAN;
1173         wr32(hw, TXGBE_RXCFG(queue), ctrl);
1174
1175         /* record those setting for HW strip per queue */
1176         txgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1177 }
1178
1179 static void
1180 txgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1181 {
1182         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1183         uint32_t ctrl;
1184
1185         PMD_INIT_FUNC_TRACE();
1186
1187         ctrl = rd32(hw, TXGBE_PORTCTL);
1188         ctrl &= ~TXGBE_PORTCTL_VLANEXT;
1189         ctrl &= ~TXGBE_PORTCTL_QINQ;
1190         wr32(hw, TXGBE_PORTCTL, ctrl);
1191 }
1192
1193 static void
1194 txgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1195 {
1196         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1197         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
1198         struct rte_eth_txmode *txmode = &dev->data->dev_conf.txmode;
1199         uint32_t ctrl;
1200
1201         PMD_INIT_FUNC_TRACE();
1202
1203         ctrl  = rd32(hw, TXGBE_PORTCTL);
1204         ctrl |= TXGBE_PORTCTL_VLANEXT;
1205         if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP ||
1206             txmode->offloads & DEV_TX_OFFLOAD_QINQ_INSERT)
1207                 ctrl |= TXGBE_PORTCTL_QINQ;
1208         wr32(hw, TXGBE_PORTCTL, ctrl);
1209 }
1210
1211 void
1212 txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
1213 {
1214         struct txgbe_rx_queue *rxq;
1215         uint16_t i;
1216
1217         PMD_INIT_FUNC_TRACE();
1218
1219         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1220                 rxq = dev->data->rx_queues[i];
1221
1222                 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1223                         txgbe_vlan_strip_queue_set(dev, i, 1);
1224                 else
1225                         txgbe_vlan_strip_queue_set(dev, i, 0);
1226         }
1227 }
1228
1229 void
1230 txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
1231 {
1232         uint16_t i;
1233         struct rte_eth_rxmode *rxmode;
1234         struct txgbe_rx_queue *rxq;
1235
1236         if (mask & ETH_VLAN_STRIP_MASK) {
1237                 rxmode = &dev->data->dev_conf.rxmode;
1238                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1239                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1240                                 rxq = dev->data->rx_queues[i];
1241                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1242                         }
1243                 else
1244                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1245                                 rxq = dev->data->rx_queues[i];
1246                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1247                         }
1248         }
1249 }
1250
1251 static int
1252 txgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
1253 {
1254         struct rte_eth_rxmode *rxmode;
1255         rxmode = &dev->data->dev_conf.rxmode;
1256
1257         if (mask & ETH_VLAN_STRIP_MASK)
1258                 txgbe_vlan_hw_strip_config(dev);
1259
1260         if (mask & ETH_VLAN_FILTER_MASK) {
1261                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1262                         txgbe_vlan_hw_filter_enable(dev);
1263                 else
1264                         txgbe_vlan_hw_filter_disable(dev);
1265         }
1266
1267         if (mask & ETH_VLAN_EXTEND_MASK) {
1268                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1269                         txgbe_vlan_hw_extend_enable(dev);
1270                 else
1271                         txgbe_vlan_hw_extend_disable(dev);
1272         }
1273
1274         return 0;
1275 }
1276
1277 static int
1278 txgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1279 {
1280         txgbe_config_vlan_strip_on_all_queues(dev, mask);
1281
1282         txgbe_vlan_offload_config(dev, mask);
1283
1284         return 0;
1285 }
1286
1287 static void
1288 txgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1289 {
1290         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1291         /* VLNCTL: enable vlan filtering and allow all vlan tags through */
1292         uint32_t vlanctrl = rd32(hw, TXGBE_VLANCTL);
1293
1294         vlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */
1295         wr32(hw, TXGBE_VLANCTL, vlanctrl);
1296 }
1297
1298 static int
1299 txgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1300 {
1301         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1302
1303         switch (nb_rx_q) {
1304         case 1:
1305         case 2:
1306                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1307                 break;
1308         case 4:
1309                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1310                 break;
1311         default:
1312                 return -EINVAL;
1313         }
1314
1315         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
1316                 TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1317         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
1318                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1319         return 0;
1320 }
1321
1322 static int
1323 txgbe_check_mq_mode(struct rte_eth_dev *dev)
1324 {
1325         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1326         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1327         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1328
1329         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1330                 /* check multi-queue mode */
1331                 switch (dev_conf->rxmode.mq_mode) {
1332                 case ETH_MQ_RX_VMDQ_DCB:
1333                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
1334                         break;
1335                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1336                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1337                         PMD_INIT_LOG(ERR, "SRIOV active,"
1338                                         " unsupported mq_mode rx %d.",
1339                                         dev_conf->rxmode.mq_mode);
1340                         return -EINVAL;
1341                 case ETH_MQ_RX_RSS:
1342                 case ETH_MQ_RX_VMDQ_RSS:
1343                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1344                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1345                                 if (txgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1346                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1347                                                 " invalid queue number"
1348                                                 " for VMDQ RSS, allowed"
1349                                                 " value are 1, 2 or 4.");
1350                                         return -EINVAL;
1351                                 }
1352                         break;
1353                 case ETH_MQ_RX_VMDQ_ONLY:
1354                 case ETH_MQ_RX_NONE:
1355                         /* if nothing mq mode configure, use default scheme */
1356                         dev->data->dev_conf.rxmode.mq_mode =
1357                                 ETH_MQ_RX_VMDQ_ONLY;
1358                         break;
1359                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1360                         /* SRIOV only works in VMDq enable mode */
1361                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1362                                         " wrong mq_mode rx %d.",
1363                                         dev_conf->rxmode.mq_mode);
1364                         return -EINVAL;
1365                 }
1366
1367                 switch (dev_conf->txmode.mq_mode) {
1368                 case ETH_MQ_TX_VMDQ_DCB:
1369                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
1370                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
1371                         break;
1372                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1373                         dev->data->dev_conf.txmode.mq_mode =
1374                                 ETH_MQ_TX_VMDQ_ONLY;
1375                         break;
1376                 }
1377
1378                 /* check valid queue number */
1379                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1380                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1381                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1382                                         " nb_rx_q=%d nb_tx_q=%d queue number"
1383                                         " must be less than or equal to %d.",
1384                                         nb_rx_q, nb_tx_q,
1385                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1386                         return -EINVAL;
1387                 }
1388         } else {
1389                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1390                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1391                                           " not supported.");
1392                         return -EINVAL;
1393                 }
1394                 /* check configuration for vmdb+dcb mode */
1395                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1396                         const struct rte_eth_vmdq_dcb_conf *conf;
1397
1398                         if (nb_rx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1399                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1400                                                 TXGBE_VMDQ_DCB_NB_QUEUES);
1401                                 return -EINVAL;
1402                         }
1403                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1404                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1405                                conf->nb_queue_pools == ETH_32_POOLS)) {
1406                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1407                                                 " nb_queue_pools must be %d or %d.",
1408                                                 ETH_16_POOLS, ETH_32_POOLS);
1409                                 return -EINVAL;
1410                         }
1411                 }
1412                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1413                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1414
1415                         if (nb_tx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1416                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1417                                                  TXGBE_VMDQ_DCB_NB_QUEUES);
1418                                 return -EINVAL;
1419                         }
1420                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1421                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1422                                conf->nb_queue_pools == ETH_32_POOLS)) {
1423                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1424                                                 " nb_queue_pools != %d and"
1425                                                 " nb_queue_pools != %d.",
1426                                                 ETH_16_POOLS, ETH_32_POOLS);
1427                                 return -EINVAL;
1428                         }
1429                 }
1430
1431                 /* For DCB mode check our configuration before we go further */
1432                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1433                         const struct rte_eth_dcb_rx_conf *conf;
1434
1435                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1436                         if (!(conf->nb_tcs == ETH_4_TCS ||
1437                                conf->nb_tcs == ETH_8_TCS)) {
1438                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1439                                                 " and nb_tcs != %d.",
1440                                                 ETH_4_TCS, ETH_8_TCS);
1441                                 return -EINVAL;
1442                         }
1443                 }
1444
1445                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1446                         const struct rte_eth_dcb_tx_conf *conf;
1447
1448                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1449                         if (!(conf->nb_tcs == ETH_4_TCS ||
1450                                conf->nb_tcs == ETH_8_TCS)) {
1451                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1452                                                 " and nb_tcs != %d.",
1453                                                 ETH_4_TCS, ETH_8_TCS);
1454                                 return -EINVAL;
1455                         }
1456                 }
1457         }
1458         return 0;
1459 }
1460
1461 static int
1462 txgbe_dev_configure(struct rte_eth_dev *dev)
1463 {
1464         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1465         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1466         int ret;
1467
1468         PMD_INIT_FUNC_TRACE();
1469
1470         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1471                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1472
1473         /* multiple queue mode checking */
1474         ret  = txgbe_check_mq_mode(dev);
1475         if (ret != 0) {
1476                 PMD_DRV_LOG(ERR, "txgbe_check_mq_mode fails with %d.",
1477                             ret);
1478                 return ret;
1479         }
1480
1481         /* set flag to update link status after init */
1482         intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
1483
1484         /*
1485          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1486          * allocation Rx preconditions we will reset it.
1487          */
1488         adapter->rx_bulk_alloc_allowed = true;
1489
1490         return 0;
1491 }
1492
1493 static void
1494 txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
1495 {
1496         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1497         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1498         uint32_t gpie;
1499
1500         gpie = rd32(hw, TXGBE_GPIOINTEN);
1501         gpie |= TXGBE_GPIOBIT_6;
1502         wr32(hw, TXGBE_GPIOINTEN, gpie);
1503         intr->mask_misc |= TXGBE_ICRMISC_GPIO;
1504         intr->mask_misc |= TXGBE_ICRMISC_ANDONE;
1505 }
1506
1507 int
1508 txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
1509                         uint16_t tx_rate, uint64_t q_msk)
1510 {
1511         struct txgbe_hw *hw;
1512         struct txgbe_vf_info *vfinfo;
1513         struct rte_eth_link link;
1514         uint8_t  nb_q_per_pool;
1515         uint32_t queue_stride;
1516         uint32_t queue_idx, idx = 0, vf_idx;
1517         uint32_t queue_end;
1518         uint16_t total_rate = 0;
1519         struct rte_pci_device *pci_dev;
1520         int ret;
1521
1522         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1523         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
1524         if (ret < 0)
1525                 return ret;
1526
1527         if (vf >= pci_dev->max_vfs)
1528                 return -EINVAL;
1529
1530         if (tx_rate > link.link_speed)
1531                 return -EINVAL;
1532
1533         if (q_msk == 0)
1534                 return 0;
1535
1536         hw = TXGBE_DEV_HW(dev);
1537         vfinfo = *(TXGBE_DEV_VFDATA(dev));
1538         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1539         queue_stride = TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1540         queue_idx = vf * queue_stride;
1541         queue_end = queue_idx + nb_q_per_pool - 1;
1542         if (queue_end >= hw->mac.max_tx_queues)
1543                 return -EINVAL;
1544
1545         if (vfinfo) {
1546                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
1547                         if (vf_idx == vf)
1548                                 continue;
1549                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
1550                                 idx++)
1551                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
1552                 }
1553         } else {
1554                 return -EINVAL;
1555         }
1556
1557         /* Store tx_rate for this vf. */
1558         for (idx = 0; idx < nb_q_per_pool; idx++) {
1559                 if (((uint64_t)0x1 << idx) & q_msk) {
1560                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
1561                                 vfinfo[vf].tx_rate[idx] = tx_rate;
1562                         total_rate += tx_rate;
1563                 }
1564         }
1565
1566         if (total_rate > dev->data->dev_link.link_speed) {
1567                 /* Reset stored TX rate of the VF if it causes exceed
1568                  * link speed.
1569                  */
1570                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
1571                 return -EINVAL;
1572         }
1573
1574         /* Set ARBTXRATE of each queue/pool for vf X  */
1575         for (; queue_idx <= queue_end; queue_idx++) {
1576                 if (0x1 & q_msk)
1577                         txgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
1578                 q_msk = q_msk >> 1;
1579         }
1580
1581         return 0;
1582 }
1583
1584 /*
1585  * Configure device link speed and setup link.
1586  * It returns 0 on success.
1587  */
1588 static int
1589 txgbe_dev_start(struct rte_eth_dev *dev)
1590 {
1591         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1592         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
1593         struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1594         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1595         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1596         uint32_t intr_vector = 0;
1597         int err;
1598         bool link_up = false, negotiate = 0;
1599         uint32_t speed = 0;
1600         uint32_t allowed_speeds = 0;
1601         int mask = 0;
1602         int status;
1603         uint16_t vf, idx;
1604         uint32_t *link_speeds;
1605         struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev);
1606
1607         PMD_INIT_FUNC_TRACE();
1608
1609         /* TXGBE devices don't support:
1610          *    - half duplex (checked afterwards for valid speeds)
1611          *    - fixed speed: TODO implement
1612          */
1613         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1614                 PMD_INIT_LOG(ERR,
1615                 "Invalid link_speeds for port %u, fix speed not supported",
1616                                 dev->data->port_id);
1617                 return -EINVAL;
1618         }
1619
1620         /* Stop the link setup handler before resetting the HW. */
1621         rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1622
1623         /* disable uio/vfio intr/eventfd mapping */
1624         rte_intr_disable(intr_handle);
1625
1626         /* stop adapter */
1627         hw->adapter_stopped = 0;
1628         txgbe_stop_hw(hw);
1629
1630         /* reinitialize adapter
1631          * this calls reset and start
1632          */
1633         hw->nb_rx_queues = dev->data->nb_rx_queues;
1634         hw->nb_tx_queues = dev->data->nb_tx_queues;
1635         status = txgbe_pf_reset_hw(hw);
1636         if (status != 0)
1637                 return -1;
1638         hw->mac.start_hw(hw);
1639         hw->mac.get_link_status = true;
1640
1641         /* configure PF module if SRIOV enabled */
1642         txgbe_pf_host_configure(dev);
1643
1644         txgbe_dev_phy_intr_setup(dev);
1645
1646         /* check and configure queue intr-vector mapping */
1647         if ((rte_intr_cap_multiple(intr_handle) ||
1648              !RTE_ETH_DEV_SRIOV(dev).active) &&
1649             dev->data->dev_conf.intr_conf.rxq != 0) {
1650                 intr_vector = dev->data->nb_rx_queues;
1651                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1652                         return -1;
1653         }
1654
1655         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1656                 intr_handle->intr_vec =
1657                         rte_zmalloc("intr_vec",
1658                                     dev->data->nb_rx_queues * sizeof(int), 0);
1659                 if (intr_handle->intr_vec == NULL) {
1660                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1661                                      " intr_vec", dev->data->nb_rx_queues);
1662                         return -ENOMEM;
1663                 }
1664         }
1665
1666         /* confiugre msix for sleep until rx interrupt */
1667         txgbe_configure_msix(dev);
1668
1669         /* initialize transmission unit */
1670         txgbe_dev_tx_init(dev);
1671
1672         /* This can fail when allocating mbufs for descriptor rings */
1673         err = txgbe_dev_rx_init(dev);
1674         if (err) {
1675                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1676                 goto error;
1677         }
1678
1679         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
1680                 ETH_VLAN_EXTEND_MASK;
1681         err = txgbe_vlan_offload_config(dev, mask);
1682         if (err) {
1683                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
1684                 goto error;
1685         }
1686
1687         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1688                 /* Enable vlan filtering for VMDq */
1689                 txgbe_vmdq_vlan_hw_filter_enable(dev);
1690         }
1691
1692         /* Configure DCB hw */
1693         txgbe_configure_pb(dev);
1694         txgbe_configure_port(dev);
1695         txgbe_configure_dcb(dev);
1696
1697         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1698                 err = txgbe_fdir_configure(dev);
1699                 if (err)
1700                         goto error;
1701         }
1702
1703         /* Restore vf rate limit */
1704         if (vfinfo != NULL) {
1705                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
1706                         for (idx = 0; idx < TXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1707                                 if (vfinfo[vf].tx_rate[idx] != 0)
1708                                         txgbe_set_vf_rate_limit(dev, vf,
1709                                                 vfinfo[vf].tx_rate[idx],
1710                                                 1 << idx);
1711         }
1712
1713         err = txgbe_dev_rxtx_start(dev);
1714         if (err < 0) {
1715                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1716                 goto error;
1717         }
1718
1719         /* Skip link setup if loopback mode is enabled. */
1720         if (hw->mac.type == txgbe_mac_raptor &&
1721             dev->data->dev_conf.lpbk_mode)
1722                 goto skip_link_setup;
1723
1724         if (txgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1725                 err = hw->mac.setup_sfp(hw);
1726                 if (err)
1727                         goto error;
1728         }
1729
1730         if (hw->phy.media_type == txgbe_media_type_copper) {
1731                 /* Turn on the copper */
1732                 hw->phy.set_phy_power(hw, true);
1733         } else {
1734                 /* Turn on the laser */
1735                 hw->mac.enable_tx_laser(hw);
1736         }
1737
1738         if ((hw->subsystem_device_id & 0xFF) != TXGBE_DEV_ID_KR_KX_KX4)
1739                 err = hw->mac.check_link(hw, &speed, &link_up, 0);
1740         if (err)
1741                 goto error;
1742         dev->data->dev_link.link_status = link_up;
1743
1744         err = hw->mac.get_link_capabilities(hw, &speed, &negotiate);
1745         if (err)
1746                 goto error;
1747
1748         allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
1749                         ETH_LINK_SPEED_10G;
1750
1751         link_speeds = &dev->data->dev_conf.link_speeds;
1752         if (*link_speeds & ~allowed_speeds) {
1753                 PMD_INIT_LOG(ERR, "Invalid link setting");
1754                 goto error;
1755         }
1756
1757         speed = 0x0;
1758         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
1759                 speed = (TXGBE_LINK_SPEED_100M_FULL |
1760                          TXGBE_LINK_SPEED_1GB_FULL |
1761                          TXGBE_LINK_SPEED_10GB_FULL);
1762         } else {
1763                 if (*link_speeds & ETH_LINK_SPEED_10G)
1764                         speed |= TXGBE_LINK_SPEED_10GB_FULL;
1765                 if (*link_speeds & ETH_LINK_SPEED_5G)
1766                         speed |= TXGBE_LINK_SPEED_5GB_FULL;
1767                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
1768                         speed |= TXGBE_LINK_SPEED_2_5GB_FULL;
1769                 if (*link_speeds & ETH_LINK_SPEED_1G)
1770                         speed |= TXGBE_LINK_SPEED_1GB_FULL;
1771                 if (*link_speeds & ETH_LINK_SPEED_100M)
1772                         speed |= TXGBE_LINK_SPEED_100M_FULL;
1773         }
1774
1775         err = hw->mac.setup_link(hw, speed, link_up);
1776         if (err)
1777                 goto error;
1778
1779 skip_link_setup:
1780
1781         if (rte_intr_allow_others(intr_handle)) {
1782                 txgbe_dev_misc_interrupt_setup(dev);
1783                 /* check if lsc interrupt is enabled */
1784                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1785                         txgbe_dev_lsc_interrupt_setup(dev, TRUE);
1786                 else
1787                         txgbe_dev_lsc_interrupt_setup(dev, FALSE);
1788                 txgbe_dev_macsec_interrupt_setup(dev);
1789                 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
1790         } else {
1791                 rte_intr_callback_unregister(intr_handle,
1792                                              txgbe_dev_interrupt_handler, dev);
1793                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1794                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1795                                      " no intr multiplex");
1796         }
1797
1798         /* check if rxq interrupt is enabled */
1799         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1800             rte_intr_dp_is_en(intr_handle))
1801                 txgbe_dev_rxq_interrupt_setup(dev);
1802
1803         /* enable uio/vfio intr/eventfd mapping */
1804         rte_intr_enable(intr_handle);
1805
1806         /* resume enabled intr since hw reset */
1807         txgbe_enable_intr(dev);
1808         txgbe_l2_tunnel_conf(dev);
1809         txgbe_filter_restore(dev);
1810
1811         if (tm_conf->root && !tm_conf->committed)
1812                 PMD_DRV_LOG(WARNING,
1813                             "please call hierarchy_commit() "
1814                             "before starting the port");
1815
1816         /*
1817          * Update link status right before return, because it may
1818          * start link configuration process in a separate thread.
1819          */
1820         txgbe_dev_link_update(dev, 0);
1821
1822         wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_ORD_MASK);
1823
1824         txgbe_read_stats_registers(hw, hw_stats);
1825         hw->offset_loaded = 1;
1826
1827         return 0;
1828
1829 error:
1830         PMD_INIT_LOG(ERR, "failure in dev start: %d", err);
1831         txgbe_dev_clear_queues(dev);
1832         return -EIO;
1833 }
1834
1835 /*
1836  * Stop device: disable rx and tx functions to allow for reconfiguring.
1837  */
1838 static int
1839 txgbe_dev_stop(struct rte_eth_dev *dev)
1840 {
1841         struct rte_eth_link link;
1842         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1843         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1844         struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1845         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1846         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1847         int vf;
1848         struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev);
1849
1850         if (hw->adapter_stopped)
1851                 return 0;
1852
1853         PMD_INIT_FUNC_TRACE();
1854
1855         rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1856
1857         /* disable interrupts */
1858         txgbe_disable_intr(hw);
1859
1860         /* reset the NIC */
1861         txgbe_pf_reset_hw(hw);
1862         hw->adapter_stopped = 0;
1863
1864         /* stop adapter */
1865         txgbe_stop_hw(hw);
1866
1867         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
1868                 vfinfo[vf].clear_to_send = false;
1869
1870         if (hw->phy.media_type == txgbe_media_type_copper) {
1871                 /* Turn off the copper */
1872                 hw->phy.set_phy_power(hw, false);
1873         } else {
1874                 /* Turn off the laser */
1875                 hw->mac.disable_tx_laser(hw);
1876         }
1877
1878         txgbe_dev_clear_queues(dev);
1879
1880         /* Clear stored conf */
1881         dev->data->scattered_rx = 0;
1882         dev->data->lro = 0;
1883
1884         /* Clear recorded link status */
1885         memset(&link, 0, sizeof(link));
1886         rte_eth_linkstatus_set(dev, &link);
1887
1888         if (!rte_intr_allow_others(intr_handle))
1889                 /* resume to the default handler */
1890                 rte_intr_callback_register(intr_handle,
1891                                            txgbe_dev_interrupt_handler,
1892                                            (void *)dev);
1893
1894         /* Clean datapath event and queue/vec mapping */
1895         rte_intr_efd_disable(intr_handle);
1896         if (intr_handle->intr_vec != NULL) {
1897                 rte_free(intr_handle->intr_vec);
1898                 intr_handle->intr_vec = NULL;
1899         }
1900
1901         /* reset hierarchy commit */
1902         tm_conf->committed = false;
1903
1904         adapter->rss_reta_updated = 0;
1905         wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_SEL_MASK);
1906
1907         hw->adapter_stopped = true;
1908         dev->data->dev_started = 0;
1909
1910         return 0;
1911 }
1912
1913 /*
1914  * Set device link up: enable tx.
1915  */
1916 static int
1917 txgbe_dev_set_link_up(struct rte_eth_dev *dev)
1918 {
1919         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1920
1921         if (hw->phy.media_type == txgbe_media_type_copper) {
1922                 /* Turn on the copper */
1923                 hw->phy.set_phy_power(hw, true);
1924         } else {
1925                 /* Turn on the laser */
1926                 hw->mac.enable_tx_laser(hw);
1927                 txgbe_dev_link_update(dev, 0);
1928         }
1929
1930         return 0;
1931 }
1932
1933 /*
1934  * Set device link down: disable tx.
1935  */
1936 static int
1937 txgbe_dev_set_link_down(struct rte_eth_dev *dev)
1938 {
1939         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1940
1941         if (hw->phy.media_type == txgbe_media_type_copper) {
1942                 /* Turn off the copper */
1943                 hw->phy.set_phy_power(hw, false);
1944         } else {
1945                 /* Turn off the laser */
1946                 hw->mac.disable_tx_laser(hw);
1947                 txgbe_dev_link_update(dev, 0);
1948         }
1949
1950         return 0;
1951 }
1952
1953 /*
1954  * Reset and stop device.
1955  */
1956 static int
1957 txgbe_dev_close(struct rte_eth_dev *dev)
1958 {
1959         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1960         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1961         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1962         int retries = 0;
1963         int ret;
1964
1965         PMD_INIT_FUNC_TRACE();
1966
1967         txgbe_pf_reset_hw(hw);
1968
1969         ret = txgbe_dev_stop(dev);
1970
1971         txgbe_dev_free_queues(dev);
1972
1973         /* reprogram the RAR[0] in case user changed it. */
1974         txgbe_set_rar(hw, 0, hw->mac.addr, 0, true);
1975
1976         /* Unlock any pending hardware semaphore */
1977         txgbe_swfw_lock_reset(hw);
1978
1979         /* disable uio intr before callback unregister */
1980         rte_intr_disable(intr_handle);
1981
1982         do {
1983                 ret = rte_intr_callback_unregister(intr_handle,
1984                                 txgbe_dev_interrupt_handler, dev);
1985                 if (ret >= 0 || ret == -ENOENT) {
1986                         break;
1987                 } else if (ret != -EAGAIN) {
1988                         PMD_INIT_LOG(ERR,
1989                                 "intr callback unregister failed: %d",
1990                                 ret);
1991                 }
1992                 rte_delay_ms(100);
1993         } while (retries++ < (10 + TXGBE_LINK_UP_TIME));
1994
1995         /* cancel the delay handler before remove dev */
1996         rte_eal_alarm_cancel(txgbe_dev_interrupt_delayed_handler, dev);
1997
1998         /* uninitialize PF if max_vfs not zero */
1999         txgbe_pf_host_uninit(dev);
2000
2001         rte_free(dev->data->mac_addrs);
2002         dev->data->mac_addrs = NULL;
2003
2004         rte_free(dev->data->hash_mac_addrs);
2005         dev->data->hash_mac_addrs = NULL;
2006
2007         /* remove all the fdir filters & hash */
2008         txgbe_fdir_filter_uninit(dev);
2009
2010         /* remove all the L2 tunnel filters & hash */
2011         txgbe_l2_tn_filter_uninit(dev);
2012
2013         /* Remove all ntuple filters of the device */
2014         txgbe_ntuple_filter_uninit(dev);
2015
2016         /* clear all the filters list */
2017         txgbe_filterlist_flush();
2018
2019         /* Remove all Traffic Manager configuration */
2020         txgbe_tm_conf_uninit(dev);
2021
2022 #ifdef RTE_LIB_SECURITY
2023         rte_free(dev->security_ctx);
2024 #endif
2025
2026         return ret;
2027 }
2028
2029 /*
2030  * Reset PF device.
2031  */
2032 static int
2033 txgbe_dev_reset(struct rte_eth_dev *dev)
2034 {
2035         int ret;
2036
2037         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2038          * its VF to make them align with it. The detailed notification
2039          * mechanism is PMD specific. As to txgbe PF, it is rather complex.
2040          * To avoid unexpected behavior in VF, currently reset of PF with
2041          * SR-IOV activation is not supported. It might be supported later.
2042          */
2043         if (dev->data->sriov.active)
2044                 return -ENOTSUP;
2045
2046         ret = eth_txgbe_dev_uninit(dev);
2047         if (ret)
2048                 return ret;
2049
2050         ret = eth_txgbe_dev_init(dev, NULL);
2051
2052         return ret;
2053 }
2054
2055 #define UPDATE_QP_COUNTER_32bit(reg, last_counter, counter)     \
2056         {                                                       \
2057                 uint32_t current_counter = rd32(hw, reg);       \
2058                 if (current_counter < last_counter)             \
2059                         current_counter += 0x100000000LL;       \
2060                 if (!hw->offset_loaded)                         \
2061                         last_counter = current_counter;         \
2062                 counter = current_counter - last_counter;       \
2063                 counter &= 0xFFFFFFFFLL;                        \
2064         }
2065
2066 #define UPDATE_QP_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
2067         {                                                                \
2068                 uint64_t current_counter_lsb = rd32(hw, reg_lsb);        \
2069                 uint64_t current_counter_msb = rd32(hw, reg_msb);        \
2070                 uint64_t current_counter = (current_counter_msb << 32) | \
2071                         current_counter_lsb;                             \
2072                 if (current_counter < last_counter)                      \
2073                         current_counter += 0x1000000000LL;               \
2074                 if (!hw->offset_loaded)                                  \
2075                         last_counter = current_counter;                  \
2076                 counter = current_counter - last_counter;                \
2077                 counter &= 0xFFFFFFFFFLL;                                \
2078         }
2079
2080 void
2081 txgbe_read_stats_registers(struct txgbe_hw *hw,
2082                            struct txgbe_hw_stats *hw_stats)
2083 {
2084         unsigned int i;
2085
2086         /* QP Stats */
2087         for (i = 0; i < hw->nb_rx_queues; i++) {
2088                 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXPKT(i),
2089                         hw->qp_last[i].rx_qp_packets,
2090                         hw_stats->qp[i].rx_qp_packets);
2091                 UPDATE_QP_COUNTER_36bit(TXGBE_QPRXOCTL(i), TXGBE_QPRXOCTH(i),
2092                         hw->qp_last[i].rx_qp_bytes,
2093                         hw_stats->qp[i].rx_qp_bytes);
2094                 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXMPKT(i),
2095                         hw->qp_last[i].rx_qp_mc_packets,
2096                         hw_stats->qp[i].rx_qp_mc_packets);
2097         }
2098
2099         for (i = 0; i < hw->nb_tx_queues; i++) {
2100                 UPDATE_QP_COUNTER_32bit(TXGBE_QPTXPKT(i),
2101                         hw->qp_last[i].tx_qp_packets,
2102                         hw_stats->qp[i].tx_qp_packets);
2103                 UPDATE_QP_COUNTER_36bit(TXGBE_QPTXOCTL(i), TXGBE_QPTXOCTH(i),
2104                         hw->qp_last[i].tx_qp_bytes,
2105                         hw_stats->qp[i].tx_qp_bytes);
2106         }
2107         /* PB Stats */
2108         for (i = 0; i < TXGBE_MAX_UP; i++) {
2109                 hw_stats->up[i].rx_up_xon_packets +=
2110                                 rd32(hw, TXGBE_PBRXUPXON(i));
2111                 hw_stats->up[i].rx_up_xoff_packets +=
2112                                 rd32(hw, TXGBE_PBRXUPXOFF(i));
2113                 hw_stats->up[i].tx_up_xon_packets +=
2114                                 rd32(hw, TXGBE_PBTXUPXON(i));
2115                 hw_stats->up[i].tx_up_xoff_packets +=
2116                                 rd32(hw, TXGBE_PBTXUPXOFF(i));
2117                 hw_stats->up[i].tx_up_xon2off_packets +=
2118                                 rd32(hw, TXGBE_PBTXUPOFF(i));
2119                 hw_stats->up[i].rx_up_dropped +=
2120                                 rd32(hw, TXGBE_PBRXMISS(i));
2121         }
2122         hw_stats->rx_xon_packets += rd32(hw, TXGBE_PBRXLNKXON);
2123         hw_stats->rx_xoff_packets += rd32(hw, TXGBE_PBRXLNKXOFF);
2124         hw_stats->tx_xon_packets += rd32(hw, TXGBE_PBTXLNKXON);
2125         hw_stats->tx_xoff_packets += rd32(hw, TXGBE_PBTXLNKXOFF);
2126
2127         /* DMA Stats */
2128         hw_stats->rx_packets += rd32(hw, TXGBE_DMARXPKT);
2129         hw_stats->tx_packets += rd32(hw, TXGBE_DMATXPKT);
2130
2131         hw_stats->rx_bytes += rd64(hw, TXGBE_DMARXOCTL);
2132         hw_stats->tx_bytes += rd64(hw, TXGBE_DMATXOCTL);
2133         hw_stats->rx_dma_drop += rd32(hw, TXGBE_DMARXDROP);
2134         hw_stats->rx_drop_packets += rd32(hw, TXGBE_PBRXDROP);
2135
2136         /* MAC Stats */
2137         hw_stats->rx_crc_errors += rd64(hw, TXGBE_MACRXERRCRCL);
2138         hw_stats->rx_multicast_packets += rd64(hw, TXGBE_MACRXMPKTL);
2139         hw_stats->tx_multicast_packets += rd64(hw, TXGBE_MACTXMPKTL);
2140
2141         hw_stats->rx_total_packets += rd64(hw, TXGBE_MACRXPKTL);
2142         hw_stats->tx_total_packets += rd64(hw, TXGBE_MACTXPKTL);
2143         hw_stats->rx_total_bytes += rd64(hw, TXGBE_MACRXGBOCTL);
2144
2145         hw_stats->rx_broadcast_packets += rd64(hw, TXGBE_MACRXOCTL);
2146         hw_stats->tx_broadcast_packets += rd32(hw, TXGBE_MACTXOCTL);
2147
2148         hw_stats->rx_size_64_packets += rd64(hw, TXGBE_MACRX1TO64L);
2149         hw_stats->rx_size_65_to_127_packets += rd64(hw, TXGBE_MACRX65TO127L);
2150         hw_stats->rx_size_128_to_255_packets += rd64(hw, TXGBE_MACRX128TO255L);
2151         hw_stats->rx_size_256_to_511_packets += rd64(hw, TXGBE_MACRX256TO511L);
2152         hw_stats->rx_size_512_to_1023_packets +=
2153                         rd64(hw, TXGBE_MACRX512TO1023L);
2154         hw_stats->rx_size_1024_to_max_packets +=
2155                         rd64(hw, TXGBE_MACRX1024TOMAXL);
2156         hw_stats->tx_size_64_packets += rd64(hw, TXGBE_MACTX1TO64L);
2157         hw_stats->tx_size_65_to_127_packets += rd64(hw, TXGBE_MACTX65TO127L);
2158         hw_stats->tx_size_128_to_255_packets += rd64(hw, TXGBE_MACTX128TO255L);
2159         hw_stats->tx_size_256_to_511_packets += rd64(hw, TXGBE_MACTX256TO511L);
2160         hw_stats->tx_size_512_to_1023_packets +=
2161                         rd64(hw, TXGBE_MACTX512TO1023L);
2162         hw_stats->tx_size_1024_to_max_packets +=
2163                         rd64(hw, TXGBE_MACTX1024TOMAXL);
2164
2165         hw_stats->rx_undersize_errors += rd64(hw, TXGBE_MACRXERRLENL);
2166         hw_stats->rx_oversize_errors += rd32(hw, TXGBE_MACRXOVERSIZE);
2167         hw_stats->rx_jabber_errors += rd32(hw, TXGBE_MACRXJABBER);
2168
2169         /* MNG Stats */
2170         hw_stats->mng_bmc2host_packets = rd32(hw, TXGBE_MNGBMC2OS);
2171         hw_stats->mng_host2bmc_packets = rd32(hw, TXGBE_MNGOS2BMC);
2172         hw_stats->rx_management_packets = rd32(hw, TXGBE_DMARXMNG);
2173         hw_stats->tx_management_packets = rd32(hw, TXGBE_DMATXMNG);
2174
2175         /* FCoE Stats */
2176         hw_stats->rx_fcoe_crc_errors += rd32(hw, TXGBE_FCOECRC);
2177         hw_stats->rx_fcoe_mbuf_allocation_errors += rd32(hw, TXGBE_FCOELAST);
2178         hw_stats->rx_fcoe_dropped += rd32(hw, TXGBE_FCOERPDC);
2179         hw_stats->rx_fcoe_packets += rd32(hw, TXGBE_FCOEPRC);
2180         hw_stats->tx_fcoe_packets += rd32(hw, TXGBE_FCOEPTC);
2181         hw_stats->rx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWRC);
2182         hw_stats->tx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWTC);
2183
2184         /* Flow Director Stats */
2185         hw_stats->flow_director_matched_filters += rd32(hw, TXGBE_FDIRMATCH);
2186         hw_stats->flow_director_missed_filters += rd32(hw, TXGBE_FDIRMISS);
2187         hw_stats->flow_director_added_filters +=
2188                 TXGBE_FDIRUSED_ADD(rd32(hw, TXGBE_FDIRUSED));
2189         hw_stats->flow_director_removed_filters +=
2190                 TXGBE_FDIRUSED_REM(rd32(hw, TXGBE_FDIRUSED));
2191         hw_stats->flow_director_filter_add_errors +=
2192                 TXGBE_FDIRFAIL_ADD(rd32(hw, TXGBE_FDIRFAIL));
2193         hw_stats->flow_director_filter_remove_errors +=
2194                 TXGBE_FDIRFAIL_REM(rd32(hw, TXGBE_FDIRFAIL));
2195
2196         /* MACsec Stats */
2197         hw_stats->tx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECTX_UTPKT);
2198         hw_stats->tx_macsec_pkts_encrypted +=
2199                         rd32(hw, TXGBE_LSECTX_ENCPKT);
2200         hw_stats->tx_macsec_pkts_protected +=
2201                         rd32(hw, TXGBE_LSECTX_PROTPKT);
2202         hw_stats->tx_macsec_octets_encrypted +=
2203                         rd32(hw, TXGBE_LSECTX_ENCOCT);
2204         hw_stats->tx_macsec_octets_protected +=
2205                         rd32(hw, TXGBE_LSECTX_PROTOCT);
2206         hw_stats->rx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECRX_UTPKT);
2207         hw_stats->rx_macsec_pkts_badtag += rd32(hw, TXGBE_LSECRX_BTPKT);
2208         hw_stats->rx_macsec_pkts_nosci += rd32(hw, TXGBE_LSECRX_NOSCIPKT);
2209         hw_stats->rx_macsec_pkts_unknownsci += rd32(hw, TXGBE_LSECRX_UNSCIPKT);
2210         hw_stats->rx_macsec_octets_decrypted += rd32(hw, TXGBE_LSECRX_DECOCT);
2211         hw_stats->rx_macsec_octets_validated += rd32(hw, TXGBE_LSECRX_VLDOCT);
2212         hw_stats->rx_macsec_sc_pkts_unchecked +=
2213                         rd32(hw, TXGBE_LSECRX_UNCHKPKT);
2214         hw_stats->rx_macsec_sc_pkts_delayed += rd32(hw, TXGBE_LSECRX_DLYPKT);
2215         hw_stats->rx_macsec_sc_pkts_late += rd32(hw, TXGBE_LSECRX_LATEPKT);
2216         for (i = 0; i < 2; i++) {
2217                 hw_stats->rx_macsec_sa_pkts_ok +=
2218                         rd32(hw, TXGBE_LSECRX_OKPKT(i));
2219                 hw_stats->rx_macsec_sa_pkts_invalid +=
2220                         rd32(hw, TXGBE_LSECRX_INVPKT(i));
2221                 hw_stats->rx_macsec_sa_pkts_notvalid +=
2222                         rd32(hw, TXGBE_LSECRX_BADPKT(i));
2223         }
2224         hw_stats->rx_macsec_sa_pkts_unusedsa +=
2225                         rd32(hw, TXGBE_LSECRX_INVSAPKT);
2226         hw_stats->rx_macsec_sa_pkts_notusingsa +=
2227                         rd32(hw, TXGBE_LSECRX_BADSAPKT);
2228
2229         hw_stats->rx_total_missed_packets = 0;
2230         for (i = 0; i < TXGBE_MAX_UP; i++) {
2231                 hw_stats->rx_total_missed_packets +=
2232                         hw_stats->up[i].rx_up_dropped;
2233         }
2234 }
2235
2236 static int
2237 txgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2238 {
2239         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2240         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2241         struct txgbe_stat_mappings *stat_mappings =
2242                         TXGBE_DEV_STAT_MAPPINGS(dev);
2243         uint32_t i, j;
2244
2245         txgbe_read_stats_registers(hw, hw_stats);
2246
2247         if (stats == NULL)
2248                 return -EINVAL;
2249
2250         /* Fill out the rte_eth_stats statistics structure */
2251         stats->ipackets = hw_stats->rx_packets;
2252         stats->ibytes = hw_stats->rx_bytes;
2253         stats->opackets = hw_stats->tx_packets;
2254         stats->obytes = hw_stats->tx_bytes;
2255
2256         memset(&stats->q_ipackets, 0, sizeof(stats->q_ipackets));
2257         memset(&stats->q_opackets, 0, sizeof(stats->q_opackets));
2258         memset(&stats->q_ibytes, 0, sizeof(stats->q_ibytes));
2259         memset(&stats->q_obytes, 0, sizeof(stats->q_obytes));
2260         memset(&stats->q_errors, 0, sizeof(stats->q_errors));
2261         for (i = 0; i < TXGBE_MAX_QP; i++) {
2262                 uint32_t n = i / NB_QMAP_FIELDS_PER_QSM_REG;
2263                 uint32_t offset = (i % NB_QMAP_FIELDS_PER_QSM_REG) * 8;
2264                 uint32_t q_map;
2265
2266                 q_map = (stat_mappings->rqsm[n] >> offset)
2267                                 & QMAP_FIELD_RESERVED_BITS_MASK;
2268                 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2269                      ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2270                 stats->q_ipackets[j] += hw_stats->qp[i].rx_qp_packets;
2271                 stats->q_ibytes[j] += hw_stats->qp[i].rx_qp_bytes;
2272
2273                 q_map = (stat_mappings->tqsm[n] >> offset)
2274                                 & QMAP_FIELD_RESERVED_BITS_MASK;
2275                 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2276                      ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2277                 stats->q_opackets[j] += hw_stats->qp[i].tx_qp_packets;
2278                 stats->q_obytes[j] += hw_stats->qp[i].tx_qp_bytes;
2279         }
2280
2281         /* Rx Errors */
2282         stats->imissed  = hw_stats->rx_total_missed_packets +
2283                           hw_stats->rx_dma_drop;
2284         stats->ierrors  = hw_stats->rx_crc_errors +
2285                           hw_stats->rx_mac_short_packet_dropped +
2286                           hw_stats->rx_length_errors +
2287                           hw_stats->rx_undersize_errors +
2288                           hw_stats->rx_oversize_errors +
2289                           hw_stats->rx_drop_packets +
2290                           hw_stats->rx_illegal_byte_errors +
2291                           hw_stats->rx_error_bytes +
2292                           hw_stats->rx_fragment_errors +
2293                           hw_stats->rx_fcoe_crc_errors +
2294                           hw_stats->rx_fcoe_mbuf_allocation_errors;
2295
2296         /* Tx Errors */
2297         stats->oerrors  = 0;
2298         return 0;
2299 }
2300
2301 static int
2302 txgbe_dev_stats_reset(struct rte_eth_dev *dev)
2303 {
2304         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2305         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2306
2307         /* HW registers are cleared on read */
2308         hw->offset_loaded = 0;
2309         txgbe_dev_stats_get(dev, NULL);
2310         hw->offset_loaded = 1;
2311
2312         /* Reset software totals */
2313         memset(hw_stats, 0, sizeof(*hw_stats));
2314
2315         return 0;
2316 }
2317
2318 /* This function calculates the number of xstats based on the current config */
2319 static unsigned
2320 txgbe_xstats_calc_num(struct rte_eth_dev *dev)
2321 {
2322         int nb_queues = max(dev->data->nb_rx_queues, dev->data->nb_tx_queues);
2323         return TXGBE_NB_HW_STATS +
2324                TXGBE_NB_UP_STATS * TXGBE_MAX_UP +
2325                TXGBE_NB_QP_STATS * nb_queues;
2326 }
2327
2328 static inline int
2329 txgbe_get_name_by_id(uint32_t id, char *name, uint32_t size)
2330 {
2331         int nb, st;
2332
2333         /* Extended stats from txgbe_hw_stats */
2334         if (id < TXGBE_NB_HW_STATS) {
2335                 snprintf(name, size, "[hw]%s",
2336                         rte_txgbe_stats_strings[id].name);
2337                 return 0;
2338         }
2339         id -= TXGBE_NB_HW_STATS;
2340
2341         /* Priority Stats */
2342         if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2343                 nb = id / TXGBE_NB_UP_STATS;
2344                 st = id % TXGBE_NB_UP_STATS;
2345                 snprintf(name, size, "[p%u]%s", nb,
2346                         rte_txgbe_up_strings[st].name);
2347                 return 0;
2348         }
2349         id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2350
2351         /* Queue Stats */
2352         if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2353                 nb = id / TXGBE_NB_QP_STATS;
2354                 st = id % TXGBE_NB_QP_STATS;
2355                 snprintf(name, size, "[q%u]%s", nb,
2356                         rte_txgbe_qp_strings[st].name);
2357                 return 0;
2358         }
2359         id -= TXGBE_NB_QP_STATS * TXGBE_MAX_QP;
2360
2361         return -(int)(id + 1);
2362 }
2363
2364 static inline int
2365 txgbe_get_offset_by_id(uint32_t id, uint32_t *offset)
2366 {
2367         int nb, st;
2368
2369         /* Extended stats from txgbe_hw_stats */
2370         if (id < TXGBE_NB_HW_STATS) {
2371                 *offset = rte_txgbe_stats_strings[id].offset;
2372                 return 0;
2373         }
2374         id -= TXGBE_NB_HW_STATS;
2375
2376         /* Priority Stats */
2377         if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2378                 nb = id / TXGBE_NB_UP_STATS;
2379                 st = id % TXGBE_NB_UP_STATS;
2380                 *offset = rte_txgbe_up_strings[st].offset +
2381                         nb * (TXGBE_NB_UP_STATS * sizeof(uint64_t));
2382                 return 0;
2383         }
2384         id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2385
2386         /* Queue Stats */
2387         if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2388                 nb = id / TXGBE_NB_QP_STATS;
2389                 st = id % TXGBE_NB_QP_STATS;
2390                 *offset = rte_txgbe_qp_strings[st].offset +
2391                         nb * (TXGBE_NB_QP_STATS * sizeof(uint64_t));
2392                 return 0;
2393         }
2394
2395         return -1;
2396 }
2397
2398 static int txgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
2399         struct rte_eth_xstat_name *xstats_names, unsigned int limit)
2400 {
2401         unsigned int i, count;
2402
2403         count = txgbe_xstats_calc_num(dev);
2404         if (xstats_names == NULL)
2405                 return count;
2406
2407         /* Note: limit >= cnt_stats checked upstream
2408          * in rte_eth_xstats_names()
2409          */
2410         limit = min(limit, count);
2411
2412         /* Extended stats from txgbe_hw_stats */
2413         for (i = 0; i < limit; i++) {
2414                 if (txgbe_get_name_by_id(i, xstats_names[i].name,
2415                         sizeof(xstats_names[i].name))) {
2416                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2417                         break;
2418                 }
2419         }
2420
2421         return i;
2422 }
2423
2424 static int txgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
2425         struct rte_eth_xstat_name *xstats_names,
2426         const uint64_t *ids,
2427         unsigned int limit)
2428 {
2429         unsigned int i;
2430
2431         if (ids == NULL)
2432                 return txgbe_dev_xstats_get_names(dev, xstats_names, limit);
2433
2434         for (i = 0; i < limit; i++) {
2435                 if (txgbe_get_name_by_id(ids[i], xstats_names[i].name,
2436                                 sizeof(xstats_names[i].name))) {
2437                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2438                         return -1;
2439                 }
2440         }
2441
2442         return i;
2443 }
2444
2445 static int
2446 txgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2447                                          unsigned int limit)
2448 {
2449         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2450         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2451         unsigned int i, count;
2452
2453         txgbe_read_stats_registers(hw, hw_stats);
2454
2455         /* If this is a reset xstats is NULL, and we have cleared the
2456          * registers by reading them.
2457          */
2458         count = txgbe_xstats_calc_num(dev);
2459         if (xstats == NULL)
2460                 return count;
2461
2462         limit = min(limit, txgbe_xstats_calc_num(dev));
2463
2464         /* Extended stats from txgbe_hw_stats */
2465         for (i = 0; i < limit; i++) {
2466                 uint32_t offset = 0;
2467
2468                 if (txgbe_get_offset_by_id(i, &offset)) {
2469                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2470                         break;
2471                 }
2472                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + offset);
2473                 xstats[i].id = i;
2474         }
2475
2476         return i;
2477 }
2478
2479 static int
2480 txgbe_dev_xstats_get_(struct rte_eth_dev *dev, uint64_t *values,
2481                                          unsigned int limit)
2482 {
2483         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2484         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2485         unsigned int i, count;
2486
2487         txgbe_read_stats_registers(hw, hw_stats);
2488
2489         /* If this is a reset xstats is NULL, and we have cleared the
2490          * registers by reading them.
2491          */
2492         count = txgbe_xstats_calc_num(dev);
2493         if (values == NULL)
2494                 return count;
2495
2496         limit = min(limit, txgbe_xstats_calc_num(dev));
2497
2498         /* Extended stats from txgbe_hw_stats */
2499         for (i = 0; i < limit; i++) {
2500                 uint32_t offset;
2501
2502                 if (txgbe_get_offset_by_id(i, &offset)) {
2503                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2504                         break;
2505                 }
2506                 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2507         }
2508
2509         return i;
2510 }
2511
2512 static int
2513 txgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
2514                 uint64_t *values, unsigned int limit)
2515 {
2516         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2517         unsigned int i;
2518
2519         if (ids == NULL)
2520                 return txgbe_dev_xstats_get_(dev, values, limit);
2521
2522         for (i = 0; i < limit; i++) {
2523                 uint32_t offset;
2524
2525                 if (txgbe_get_offset_by_id(ids[i], &offset)) {
2526                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2527                         break;
2528                 }
2529                 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2530         }
2531
2532         return i;
2533 }
2534
2535 static int
2536 txgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2537 {
2538         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2539         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2540
2541         /* HW registers are cleared on read */
2542         hw->offset_loaded = 0;
2543         txgbe_read_stats_registers(hw, hw_stats);
2544         hw->offset_loaded = 1;
2545
2546         /* Reset software totals */
2547         memset(hw_stats, 0, sizeof(*hw_stats));
2548
2549         return 0;
2550 }
2551
2552 static int
2553 txgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2554 {
2555         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2556         u32 etrack_id;
2557         int ret;
2558
2559         hw->phy.get_fw_version(hw, &etrack_id);
2560
2561         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
2562         if (ret < 0)
2563                 return -EINVAL;
2564
2565         ret += 1; /* add the size of '\0' */
2566         if (fw_size < (size_t)ret)
2567                 return ret;
2568         else
2569                 return 0;
2570 }
2571
2572 static int
2573 txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2574 {
2575         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2576         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2577
2578         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2579         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2580         dev_info->min_rx_bufsize = 1024;
2581         dev_info->max_rx_pktlen = 15872;
2582         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2583         dev_info->max_hash_mac_addrs = TXGBE_VMDQ_NUM_UC_MAC;
2584         dev_info->max_vfs = pci_dev->max_vfs;
2585         dev_info->max_vmdq_pools = ETH_64_POOLS;
2586         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2587         dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev);
2588         dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) |
2589                                      dev_info->rx_queue_offload_capa);
2590         dev_info->tx_queue_offload_capa = txgbe_get_tx_queue_offloads(dev);
2591         dev_info->tx_offload_capa = txgbe_get_tx_port_offloads(dev);
2592
2593         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2594                 .rx_thresh = {
2595                         .pthresh = TXGBE_DEFAULT_RX_PTHRESH,
2596                         .hthresh = TXGBE_DEFAULT_RX_HTHRESH,
2597                         .wthresh = TXGBE_DEFAULT_RX_WTHRESH,
2598                 },
2599                 .rx_free_thresh = TXGBE_DEFAULT_RX_FREE_THRESH,
2600                 .rx_drop_en = 0,
2601                 .offloads = 0,
2602         };
2603
2604         dev_info->default_txconf = (struct rte_eth_txconf) {
2605                 .tx_thresh = {
2606                         .pthresh = TXGBE_DEFAULT_TX_PTHRESH,
2607                         .hthresh = TXGBE_DEFAULT_TX_HTHRESH,
2608                         .wthresh = TXGBE_DEFAULT_TX_WTHRESH,
2609                 },
2610                 .tx_free_thresh = TXGBE_DEFAULT_TX_FREE_THRESH,
2611                 .offloads = 0,
2612         };
2613
2614         dev_info->rx_desc_lim = rx_desc_lim;
2615         dev_info->tx_desc_lim = tx_desc_lim;
2616
2617         dev_info->hash_key_size = TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2618         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2619         dev_info->flow_type_rss_offloads = TXGBE_RSS_OFFLOAD_ALL;
2620
2621         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2622         dev_info->speed_capa |= ETH_LINK_SPEED_100M;
2623
2624         /* Driver-preferred Rx/Tx parameters */
2625         dev_info->default_rxportconf.burst_size = 32;
2626         dev_info->default_txportconf.burst_size = 32;
2627         dev_info->default_rxportconf.nb_queues = 1;
2628         dev_info->default_txportconf.nb_queues = 1;
2629         dev_info->default_rxportconf.ring_size = 256;
2630         dev_info->default_txportconf.ring_size = 256;
2631
2632         return 0;
2633 }
2634
2635 const uint32_t *
2636 txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2637 {
2638         if (dev->rx_pkt_burst == txgbe_recv_pkts ||
2639             dev->rx_pkt_burst == txgbe_recv_pkts_lro_single_alloc ||
2640             dev->rx_pkt_burst == txgbe_recv_pkts_lro_bulk_alloc ||
2641             dev->rx_pkt_burst == txgbe_recv_pkts_bulk_alloc)
2642                 return txgbe_get_supported_ptypes();
2643
2644         return NULL;
2645 }
2646
2647 void
2648 txgbe_dev_setup_link_alarm_handler(void *param)
2649 {
2650         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2651         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2652         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2653         u32 speed;
2654         bool autoneg = false;
2655
2656         speed = hw->phy.autoneg_advertised;
2657         if (!speed)
2658                 hw->mac.get_link_capabilities(hw, &speed, &autoneg);
2659
2660         hw->mac.setup_link(hw, speed, true);
2661
2662         intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2663 }
2664
2665 /* return 0 means link status changed, -1 means not changed */
2666 int
2667 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
2668                             int wait_to_complete)
2669 {
2670         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2671         struct rte_eth_link link;
2672         u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2673         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2674         bool link_up;
2675         int err;
2676         int wait = 1;
2677
2678         memset(&link, 0, sizeof(link));
2679         link.link_status = ETH_LINK_DOWN;
2680         link.link_speed = ETH_SPEED_NUM_NONE;
2681         link.link_duplex = ETH_LINK_HALF_DUPLEX;
2682         link.link_autoneg = ETH_LINK_AUTONEG;
2683
2684         hw->mac.get_link_status = true;
2685
2686         if (intr->flags & TXGBE_FLAG_NEED_LINK_CONFIG)
2687                 return rte_eth_linkstatus_set(dev, &link);
2688
2689         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2690         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2691                 wait = 0;
2692
2693         err = hw->mac.check_link(hw, &link_speed, &link_up, wait);
2694
2695         if (err != 0) {
2696                 link.link_speed = ETH_SPEED_NUM_100M;
2697                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2698                 return rte_eth_linkstatus_set(dev, &link);
2699         }
2700
2701         if (link_up == 0) {
2702                 if ((hw->subsystem_device_id & 0xFF) ==
2703                                 TXGBE_DEV_ID_KR_KX_KX4) {
2704                         hw->mac.bp_down_event(hw);
2705                 } else if (hw->phy.media_type == txgbe_media_type_fiber) {
2706                         intr->flags |= TXGBE_FLAG_NEED_LINK_CONFIG;
2707                         rte_eal_alarm_set(10,
2708                                 txgbe_dev_setup_link_alarm_handler, dev);
2709                 }
2710                 return rte_eth_linkstatus_set(dev, &link);
2711         }
2712
2713         intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2714         link.link_status = ETH_LINK_UP;
2715         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2716
2717         switch (link_speed) {
2718         default:
2719         case TXGBE_LINK_SPEED_UNKNOWN:
2720                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2721                 link.link_speed = ETH_SPEED_NUM_100M;
2722                 break;
2723
2724         case TXGBE_LINK_SPEED_100M_FULL:
2725                 link.link_speed = ETH_SPEED_NUM_100M;
2726                 break;
2727
2728         case TXGBE_LINK_SPEED_1GB_FULL:
2729                 link.link_speed = ETH_SPEED_NUM_1G;
2730                 break;
2731
2732         case TXGBE_LINK_SPEED_2_5GB_FULL:
2733                 link.link_speed = ETH_SPEED_NUM_2_5G;
2734                 break;
2735
2736         case TXGBE_LINK_SPEED_5GB_FULL:
2737                 link.link_speed = ETH_SPEED_NUM_5G;
2738                 break;
2739
2740         case TXGBE_LINK_SPEED_10GB_FULL:
2741                 link.link_speed = ETH_SPEED_NUM_10G;
2742                 break;
2743         }
2744
2745         return rte_eth_linkstatus_set(dev, &link);
2746 }
2747
2748 static int
2749 txgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2750 {
2751         return txgbe_dev_link_update_share(dev, wait_to_complete);
2752 }
2753
2754 static int
2755 txgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2756 {
2757         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2758         uint32_t fctrl;
2759
2760         fctrl = rd32(hw, TXGBE_PSRCTL);
2761         fctrl |= (TXGBE_PSRCTL_UCP | TXGBE_PSRCTL_MCP);
2762         wr32(hw, TXGBE_PSRCTL, fctrl);
2763
2764         return 0;
2765 }
2766
2767 static int
2768 txgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2769 {
2770         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2771         uint32_t fctrl;
2772
2773         fctrl = rd32(hw, TXGBE_PSRCTL);
2774         fctrl &= (~TXGBE_PSRCTL_UCP);
2775         if (dev->data->all_multicast == 1)
2776                 fctrl |= TXGBE_PSRCTL_MCP;
2777         else
2778                 fctrl &= (~TXGBE_PSRCTL_MCP);
2779         wr32(hw, TXGBE_PSRCTL, fctrl);
2780
2781         return 0;
2782 }
2783
2784 static int
2785 txgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2786 {
2787         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2788         uint32_t fctrl;
2789
2790         fctrl = rd32(hw, TXGBE_PSRCTL);
2791         fctrl |= TXGBE_PSRCTL_MCP;
2792         wr32(hw, TXGBE_PSRCTL, fctrl);
2793
2794         return 0;
2795 }
2796
2797 static int
2798 txgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2799 {
2800         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2801         uint32_t fctrl;
2802
2803         if (dev->data->promiscuous == 1)
2804                 return 0; /* must remain in all_multicast mode */
2805
2806         fctrl = rd32(hw, TXGBE_PSRCTL);
2807         fctrl &= (~TXGBE_PSRCTL_MCP);
2808         wr32(hw, TXGBE_PSRCTL, fctrl);
2809
2810         return 0;
2811 }
2812
2813 /**
2814  * It clears the interrupt causes and enables the interrupt.
2815  * It will be called once only during nic initialized.
2816  *
2817  * @param dev
2818  *  Pointer to struct rte_eth_dev.
2819  * @param on
2820  *  Enable or Disable.
2821  *
2822  * @return
2823  *  - On success, zero.
2824  *  - On failure, a negative value.
2825  */
2826 static int
2827 txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2828 {
2829         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2830
2831         txgbe_dev_link_status_print(dev);
2832         if (on)
2833                 intr->mask_misc |= TXGBE_ICRMISC_LSC;
2834         else
2835                 intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2836
2837         return 0;
2838 }
2839
2840 static int
2841 txgbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev)
2842 {
2843         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2844         u64 mask;
2845
2846         mask = TXGBE_ICR_MASK;
2847         mask &= (1ULL << TXGBE_MISC_VEC_ID);
2848         intr->mask |= mask;
2849         intr->mask_misc |= TXGBE_ICRMISC_GPIO;
2850         intr->mask_misc |= TXGBE_ICRMISC_ANDONE;
2851         return 0;
2852 }
2853
2854 /**
2855  * It clears the interrupt causes and enables the interrupt.
2856  * It will be called once only during nic initialized.
2857  *
2858  * @param dev
2859  *  Pointer to struct rte_eth_dev.
2860  *
2861  * @return
2862  *  - On success, zero.
2863  *  - On failure, a negative value.
2864  */
2865 static int
2866 txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2867 {
2868         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2869         u64 mask;
2870
2871         mask = TXGBE_ICR_MASK;
2872         mask &= ~((1ULL << TXGBE_RX_VEC_START) - 1);
2873         intr->mask |= mask;
2874
2875         return 0;
2876 }
2877
2878 /**
2879  * It clears the interrupt causes and enables the interrupt.
2880  * It will be called once only during nic initialized.
2881  *
2882  * @param dev
2883  *  Pointer to struct rte_eth_dev.
2884  *
2885  * @return
2886  *  - On success, zero.
2887  *  - On failure, a negative value.
2888  */
2889 static int
2890 txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
2891 {
2892         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2893
2894         intr->mask_misc |= TXGBE_ICRMISC_LNKSEC;
2895
2896         return 0;
2897 }
2898
2899 /*
2900  * It reads ICR and sets flag (TXGBE_ICRMISC_LSC) for the link_update.
2901  *
2902  * @param dev
2903  *  Pointer to struct rte_eth_dev.
2904  *
2905  * @return
2906  *  - On success, zero.
2907  *  - On failure, a negative value.
2908  */
2909 static int
2910 txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2911 {
2912         uint32_t eicr;
2913         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2914         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2915
2916         /* clear all cause mask */
2917         txgbe_disable_intr(hw);
2918
2919         /* read-on-clear nic registers here */
2920         eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
2921         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
2922
2923         intr->flags = 0;
2924
2925         /* set flag for async link update */
2926         if (eicr & TXGBE_ICRMISC_LSC)
2927                 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
2928
2929         if (eicr & TXGBE_ICRMISC_ANDONE)
2930                 intr->flags |= TXGBE_FLAG_NEED_AN_CONFIG;
2931
2932         if (eicr & TXGBE_ICRMISC_VFMBX)
2933                 intr->flags |= TXGBE_FLAG_MAILBOX;
2934
2935         if (eicr & TXGBE_ICRMISC_LNKSEC)
2936                 intr->flags |= TXGBE_FLAG_MACSEC;
2937
2938         if (eicr & TXGBE_ICRMISC_GPIO)
2939                 intr->flags |= TXGBE_FLAG_PHY_INTERRUPT;
2940
2941         return 0;
2942 }
2943
2944 /**
2945  * It gets and then prints the link status.
2946  *
2947  * @param dev
2948  *  Pointer to struct rte_eth_dev.
2949  *
2950  * @return
2951  *  - On success, zero.
2952  *  - On failure, a negative value.
2953  */
2954 static void
2955 txgbe_dev_link_status_print(struct rte_eth_dev *dev)
2956 {
2957         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2958         struct rte_eth_link link;
2959
2960         rte_eth_linkstatus_get(dev, &link);
2961
2962         if (link.link_status) {
2963                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2964                                         (int)(dev->data->port_id),
2965                                         (unsigned int)link.link_speed,
2966                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2967                                         "full-duplex" : "half-duplex");
2968         } else {
2969                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2970                                 (int)(dev->data->port_id));
2971         }
2972         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2973                                 pci_dev->addr.domain,
2974                                 pci_dev->addr.bus,
2975                                 pci_dev->addr.devid,
2976                                 pci_dev->addr.function);
2977 }
2978
2979 /*
2980  * It executes link_update after knowing an interrupt occurred.
2981  *
2982  * @param dev
2983  *  Pointer to struct rte_eth_dev.
2984  *
2985  * @return
2986  *  - On success, zero.
2987  *  - On failure, a negative value.
2988  */
2989 static int
2990 txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
2991                            struct rte_intr_handle *intr_handle)
2992 {
2993         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2994         int64_t timeout;
2995         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2996
2997         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2998
2999         if (intr->flags & TXGBE_FLAG_MAILBOX) {
3000                 txgbe_pf_mbx_process(dev);
3001                 intr->flags &= ~TXGBE_FLAG_MAILBOX;
3002         }
3003
3004         if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
3005                 hw->phy.handle_lasi(hw);
3006                 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
3007         }
3008
3009         if (intr->flags & TXGBE_FLAG_NEED_AN_CONFIG) {
3010                 if (hw->devarg.auto_neg == 1 && hw->devarg.poll == 0) {
3011                         hw->mac.kr_handle(hw);
3012                         intr->flags &= ~TXGBE_FLAG_NEED_AN_CONFIG;
3013                 }
3014         }
3015
3016         if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
3017                 struct rte_eth_link link;
3018
3019                 /*get the link status before link update, for predicting later*/
3020                 rte_eth_linkstatus_get(dev, &link);
3021
3022                 txgbe_dev_link_update(dev, 0);
3023
3024                 /* likely to up */
3025                 if (!link.link_status)
3026                         /* handle it 1 sec later, wait it being stable */
3027                         timeout = TXGBE_LINK_UP_CHECK_TIMEOUT;
3028                 /* likely to down */
3029                 else if ((hw->subsystem_device_id & 0xFF) ==
3030                                 TXGBE_DEV_ID_KR_KX_KX4 &&
3031                                 hw->devarg.auto_neg == 1)
3032                         /* handle it 2 sec later for backplane AN73 */
3033                         timeout = 2000;
3034                 else
3035                         /* handle it 4 sec later, wait it being stable */
3036                         timeout = TXGBE_LINK_DOWN_CHECK_TIMEOUT;
3037
3038                 txgbe_dev_link_status_print(dev);
3039                 if (rte_eal_alarm_set(timeout * 1000,
3040                                       txgbe_dev_interrupt_delayed_handler,
3041                                       (void *)dev) < 0) {
3042                         PMD_DRV_LOG(ERR, "Error setting alarm");
3043                 } else {
3044                         /* only disable lsc interrupt */
3045                         intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
3046
3047                         intr->mask_orig = intr->mask;
3048                         /* only disable all misc interrupts */
3049                         intr->mask &= ~(1ULL << TXGBE_MISC_VEC_ID);
3050                 }
3051         }
3052
3053         PMD_DRV_LOG(DEBUG, "enable intr immediately");
3054         txgbe_enable_intr(dev);
3055         rte_intr_enable(intr_handle);
3056
3057         return 0;
3058 }
3059
3060 /**
3061  * Interrupt handler which shall be registered for alarm callback for delayed
3062  * handling specific interrupt to wait for the stable nic state. As the
3063  * NIC interrupt state is not stable for txgbe after link is just down,
3064  * it needs to wait 4 seconds to get the stable status.
3065  *
3066  * @param handle
3067  *  Pointer to interrupt handle.
3068  * @param param
3069  *  The address of parameter (struct rte_eth_dev *) registered before.
3070  *
3071  * @return
3072  *  void
3073  */
3074 static void
3075 txgbe_dev_interrupt_delayed_handler(void *param)
3076 {
3077         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3078         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3079         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3080         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
3081         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3082         uint32_t eicr;
3083
3084         txgbe_disable_intr(hw);
3085
3086         eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
3087         if (eicr & TXGBE_ICRMISC_VFMBX)
3088                 txgbe_pf_mbx_process(dev);
3089
3090         if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
3091                 hw->phy.handle_lasi(hw);
3092                 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
3093         }
3094
3095         if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
3096                 txgbe_dev_link_update(dev, 0);
3097                 intr->flags &= ~TXGBE_FLAG_NEED_LINK_UPDATE;
3098                 txgbe_dev_link_status_print(dev);
3099                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
3100                                               NULL);
3101         }
3102
3103         if (intr->flags & TXGBE_FLAG_MACSEC) {
3104                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3105                                               NULL);
3106                 intr->flags &= ~TXGBE_FLAG_MACSEC;
3107         }
3108
3109         /* restore original mask */
3110         intr->mask_misc |= TXGBE_ICRMISC_LSC;
3111
3112         intr->mask = intr->mask_orig;
3113         intr->mask_orig = 0;
3114
3115         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3116         txgbe_enable_intr(dev);
3117         rte_intr_enable(intr_handle);
3118 }
3119
3120 /**
3121  * Interrupt handler triggered by NIC  for handling
3122  * specific interrupt.
3123  *
3124  * @param handle
3125  *  Pointer to interrupt handle.
3126  * @param param
3127  *  The address of parameter (struct rte_eth_dev *) registered before.
3128  *
3129  * @return
3130  *  void
3131  */
3132 static void
3133 txgbe_dev_interrupt_handler(void *param)
3134 {
3135         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3136
3137         txgbe_dev_interrupt_get_status(dev);
3138         txgbe_dev_interrupt_action(dev, dev->intr_handle);
3139 }
3140
3141 static int
3142 txgbe_dev_led_on(struct rte_eth_dev *dev)
3143 {
3144         struct txgbe_hw *hw;
3145
3146         hw = TXGBE_DEV_HW(dev);
3147         return txgbe_led_on(hw, 4) == 0 ? 0 : -ENOTSUP;
3148 }
3149
3150 static int
3151 txgbe_dev_led_off(struct rte_eth_dev *dev)
3152 {
3153         struct txgbe_hw *hw;
3154
3155         hw = TXGBE_DEV_HW(dev);
3156         return txgbe_led_off(hw, 4) == 0 ? 0 : -ENOTSUP;
3157 }
3158
3159 static int
3160 txgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3161 {
3162         struct txgbe_hw *hw;
3163         uint32_t mflcn_reg;
3164         uint32_t fccfg_reg;
3165         int rx_pause;
3166         int tx_pause;
3167
3168         hw = TXGBE_DEV_HW(dev);
3169
3170         fc_conf->pause_time = hw->fc.pause_time;
3171         fc_conf->high_water = hw->fc.high_water[0];
3172         fc_conf->low_water = hw->fc.low_water[0];
3173         fc_conf->send_xon = hw->fc.send_xon;
3174         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3175
3176         /*
3177          * Return rx_pause status according to actual setting of
3178          * RXFCCFG register.
3179          */
3180         mflcn_reg = rd32(hw, TXGBE_RXFCCFG);
3181         if (mflcn_reg & (TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC))
3182                 rx_pause = 1;
3183         else
3184                 rx_pause = 0;
3185
3186         /*
3187          * Return tx_pause status according to actual setting of
3188          * TXFCCFG register.
3189          */
3190         fccfg_reg = rd32(hw, TXGBE_TXFCCFG);
3191         if (fccfg_reg & (TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC))
3192                 tx_pause = 1;
3193         else
3194                 tx_pause = 0;
3195
3196         if (rx_pause && tx_pause)
3197                 fc_conf->mode = RTE_FC_FULL;
3198         else if (rx_pause)
3199                 fc_conf->mode = RTE_FC_RX_PAUSE;
3200         else if (tx_pause)
3201                 fc_conf->mode = RTE_FC_TX_PAUSE;
3202         else
3203                 fc_conf->mode = RTE_FC_NONE;
3204
3205         return 0;
3206 }
3207
3208 static int
3209 txgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3210 {
3211         struct txgbe_hw *hw;
3212         int err;
3213         uint32_t rx_buf_size;
3214         uint32_t max_high_water;
3215         enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
3216                 txgbe_fc_none,
3217                 txgbe_fc_rx_pause,
3218                 txgbe_fc_tx_pause,
3219                 txgbe_fc_full
3220         };
3221
3222         PMD_INIT_FUNC_TRACE();
3223
3224         hw = TXGBE_DEV_HW(dev);
3225         rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(0));
3226         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3227
3228         /*
3229          * At least reserve one Ethernet frame for watermark
3230          * high_water/low_water in kilo bytes for txgbe
3231          */
3232         max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
3233         if (fc_conf->high_water > max_high_water ||
3234             fc_conf->high_water < fc_conf->low_water) {
3235                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3236                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3237                 return -EINVAL;
3238         }
3239
3240         hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[fc_conf->mode];
3241         hw->fc.pause_time     = fc_conf->pause_time;
3242         hw->fc.high_water[0]  = fc_conf->high_water;
3243         hw->fc.low_water[0]   = fc_conf->low_water;
3244         hw->fc.send_xon       = fc_conf->send_xon;
3245         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3246
3247         err = txgbe_fc_enable(hw);
3248
3249         /* Not negotiated is not an error case */
3250         if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED) {
3251                 wr32m(hw, TXGBE_MACRXFLT, TXGBE_MACRXFLT_CTL_MASK,
3252                       (fc_conf->mac_ctrl_frame_fwd
3253                        ? TXGBE_MACRXFLT_CTL_NOPS : TXGBE_MACRXFLT_CTL_DROP));
3254                 txgbe_flush(hw);
3255
3256                 return 0;
3257         }
3258
3259         PMD_INIT_LOG(ERR, "txgbe_fc_enable = 0x%x", err);
3260         return -EIO;
3261 }
3262
3263 static int
3264 txgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
3265                 struct rte_eth_pfc_conf *pfc_conf)
3266 {
3267         int err;
3268         uint32_t rx_buf_size;
3269         uint32_t max_high_water;
3270         uint8_t tc_num;
3271         uint8_t  map[TXGBE_DCB_UP_MAX] = { 0 };
3272         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3273         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
3274
3275         enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
3276                 txgbe_fc_none,
3277                 txgbe_fc_rx_pause,
3278                 txgbe_fc_tx_pause,
3279                 txgbe_fc_full
3280         };
3281
3282         PMD_INIT_FUNC_TRACE();
3283
3284         txgbe_dcb_unpack_map_cee(dcb_config, TXGBE_DCB_RX_CONFIG, map);
3285         tc_num = map[pfc_conf->priority];
3286         rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(tc_num));
3287         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3288         /*
3289          * At least reserve one Ethernet frame for watermark
3290          * high_water/low_water in kilo bytes for txgbe
3291          */
3292         max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
3293         if (pfc_conf->fc.high_water > max_high_water ||
3294             pfc_conf->fc.high_water <= pfc_conf->fc.low_water) {
3295                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3296                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3297                 return -EINVAL;
3298         }
3299
3300         hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[pfc_conf->fc.mode];
3301         hw->fc.pause_time = pfc_conf->fc.pause_time;
3302         hw->fc.send_xon = pfc_conf->fc.send_xon;
3303         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3304         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3305
3306         err = txgbe_dcb_pfc_enable(hw, tc_num);
3307
3308         /* Not negotiated is not an error case */
3309         if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED)
3310                 return 0;
3311
3312         PMD_INIT_LOG(ERR, "txgbe_dcb_pfc_enable = 0x%x", err);
3313         return -EIO;
3314 }
3315
3316 int
3317 txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3318                           struct rte_eth_rss_reta_entry64 *reta_conf,
3319                           uint16_t reta_size)
3320 {
3321         uint8_t i, j, mask;
3322         uint32_t reta;
3323         uint16_t idx, shift;
3324         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3325         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3326
3327         PMD_INIT_FUNC_TRACE();
3328
3329         if (!txgbe_rss_update_sp(hw->mac.type)) {
3330                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3331                         "NIC.");
3332                 return -ENOTSUP;
3333         }
3334
3335         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3336                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3337                         "(%d) doesn't match the number hardware can supported "
3338                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3339                 return -EINVAL;
3340         }
3341
3342         for (i = 0; i < reta_size; i += 4) {
3343                 idx = i / RTE_RETA_GROUP_SIZE;
3344                 shift = i % RTE_RETA_GROUP_SIZE;
3345                 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3346                 if (!mask)
3347                         continue;
3348
3349                 reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2);
3350                 for (j = 0; j < 4; j++) {
3351                         if (RS8(mask, j, 0x1)) {
3352                                 reta  &= ~(MS32(8 * j, 0xFF));
3353                                 reta |= LS32(reta_conf[idx].reta[shift + j],
3354                                                 8 * j, 0xFF);
3355                         }
3356                 }
3357                 wr32at(hw, TXGBE_REG_RSSTBL, i >> 2, reta);
3358         }
3359         adapter->rss_reta_updated = 1;
3360
3361         return 0;
3362 }
3363
3364 int
3365 txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3366                          struct rte_eth_rss_reta_entry64 *reta_conf,
3367                          uint16_t reta_size)
3368 {
3369         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3370         uint8_t i, j, mask;
3371         uint32_t reta;
3372         uint16_t idx, shift;
3373
3374         PMD_INIT_FUNC_TRACE();
3375
3376         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3377                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3378                         "(%d) doesn't match the number hardware can supported "
3379                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3380                 return -EINVAL;
3381         }
3382
3383         for (i = 0; i < reta_size; i += 4) {
3384                 idx = i / RTE_RETA_GROUP_SIZE;
3385                 shift = i % RTE_RETA_GROUP_SIZE;
3386                 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3387                 if (!mask)
3388                         continue;
3389
3390                 reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2);
3391                 for (j = 0; j < 4; j++) {
3392                         if (RS8(mask, j, 0x1))
3393                                 reta_conf[idx].reta[shift + j] =
3394                                         (uint16_t)RS32(reta, 8 * j, 0xFF);
3395                 }
3396         }
3397
3398         return 0;
3399 }
3400
3401 static int
3402 txgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3403                                 uint32_t index, uint32_t pool)
3404 {
3405         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3406         uint32_t enable_addr = 1;
3407
3408         return txgbe_set_rar(hw, index, mac_addr->addr_bytes,
3409                              pool, enable_addr);
3410 }
3411
3412 static void
3413 txgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3414 {
3415         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3416
3417         txgbe_clear_rar(hw, index);
3418 }
3419
3420 static int
3421 txgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3422 {
3423         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3424
3425         txgbe_remove_rar(dev, 0);
3426         txgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
3427
3428         return 0;
3429 }
3430
3431 static int
3432 txgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3433 {
3434         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3435         struct rte_eth_dev_info dev_info;
3436         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
3437         struct rte_eth_dev_data *dev_data = dev->data;
3438         int ret;
3439
3440         ret = txgbe_dev_info_get(dev, &dev_info);
3441         if (ret != 0)
3442                 return ret;
3443
3444         /* check that mtu is within the allowed range */
3445         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
3446                 return -EINVAL;
3447
3448         /* If device is started, refuse mtu that requires the support of
3449          * scattered packets when this feature has not been enabled before.
3450          */
3451         if (dev_data->dev_started && !dev_data->scattered_rx &&
3452             (frame_size + 2 * TXGBE_VLAN_TAG_SIZE >
3453              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3454                 PMD_INIT_LOG(ERR, "Stop port first.");
3455                 return -EINVAL;
3456         }
3457
3458         /* update max frame size */
3459         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3460
3461         if (hw->mode)
3462                 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3463                         TXGBE_FRAME_SIZE_MAX);
3464         else
3465                 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3466                         TXGBE_FRMSZ_MAX(frame_size));
3467
3468         return 0;
3469 }
3470
3471 static uint32_t
3472 txgbe_uta_vector(struct txgbe_hw *hw, struct rte_ether_addr *uc_addr)
3473 {
3474         uint32_t vector = 0;
3475
3476         switch (hw->mac.mc_filter_type) {
3477         case 0:   /* use bits [47:36] of the address */
3478                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3479                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3480                 break;
3481         case 1:   /* use bits [46:35] of the address */
3482                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3483                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3484                 break;
3485         case 2:   /* use bits [45:34] of the address */
3486                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3487                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3488                 break;
3489         case 3:   /* use bits [43:32] of the address */
3490                 vector = ((uc_addr->addr_bytes[4]) |
3491                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3492                 break;
3493         default:  /* Invalid mc_filter_type */
3494                 break;
3495         }
3496
3497         /* vector can only be 12-bits or boundary will be exceeded */
3498         vector &= 0xFFF;
3499         return vector;
3500 }
3501
3502 static int
3503 txgbe_uc_hash_table_set(struct rte_eth_dev *dev,
3504                         struct rte_ether_addr *mac_addr, uint8_t on)
3505 {
3506         uint32_t vector;
3507         uint32_t uta_idx;
3508         uint32_t reg_val;
3509         uint32_t uta_mask;
3510         uint32_t psrctl;
3511
3512         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3513         struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3514
3515         /* The UTA table only exists on pf hardware */
3516         if (hw->mac.type < txgbe_mac_raptor)
3517                 return -ENOTSUP;
3518
3519         vector = txgbe_uta_vector(hw, mac_addr);
3520         uta_idx = (vector >> 5) & 0x7F;
3521         uta_mask = 0x1UL << (vector & 0x1F);
3522
3523         if (!!on == !!(uta_info->uta_shadow[uta_idx] & uta_mask))
3524                 return 0;
3525
3526         reg_val = rd32(hw, TXGBE_UCADDRTBL(uta_idx));
3527         if (on) {
3528                 uta_info->uta_in_use++;
3529                 reg_val |= uta_mask;
3530                 uta_info->uta_shadow[uta_idx] |= uta_mask;
3531         } else {
3532                 uta_info->uta_in_use--;
3533                 reg_val &= ~uta_mask;
3534                 uta_info->uta_shadow[uta_idx] &= ~uta_mask;
3535         }
3536
3537         wr32(hw, TXGBE_UCADDRTBL(uta_idx), reg_val);
3538
3539         psrctl = rd32(hw, TXGBE_PSRCTL);
3540         if (uta_info->uta_in_use > 0)
3541                 psrctl |= TXGBE_PSRCTL_UCHFENA;
3542         else
3543                 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3544
3545         psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3546         psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3547         wr32(hw, TXGBE_PSRCTL, psrctl);
3548
3549         return 0;
3550 }
3551
3552 static int
3553 txgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3554 {
3555         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3556         struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3557         uint32_t psrctl;
3558         int i;
3559
3560         /* The UTA table only exists on pf hardware */
3561         if (hw->mac.type < txgbe_mac_raptor)
3562                 return -ENOTSUP;
3563
3564         if (on) {
3565                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3566                         uta_info->uta_shadow[i] = ~0;
3567                         wr32(hw, TXGBE_UCADDRTBL(i), ~0);
3568                 }
3569         } else {
3570                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3571                         uta_info->uta_shadow[i] = 0;
3572                         wr32(hw, TXGBE_UCADDRTBL(i), 0);
3573                 }
3574         }
3575
3576         psrctl = rd32(hw, TXGBE_PSRCTL);
3577         if (on)
3578                 psrctl |= TXGBE_PSRCTL_UCHFENA;
3579         else
3580                 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3581
3582         psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3583         psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3584         wr32(hw, TXGBE_PSRCTL, psrctl);
3585
3586         return 0;
3587 }
3588
3589 uint32_t
3590 txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3591 {
3592         uint32_t new_val = orig_val;
3593
3594         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3595                 new_val |= TXGBE_POOLETHCTL_UTA;
3596         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3597                 new_val |= TXGBE_POOLETHCTL_MCHA;
3598         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3599                 new_val |= TXGBE_POOLETHCTL_UCHA;
3600         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3601                 new_val |= TXGBE_POOLETHCTL_BCA;
3602         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3603                 new_val |= TXGBE_POOLETHCTL_MCP;
3604
3605         return new_val;
3606 }
3607
3608 static int
3609 txgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
3610 {
3611         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3612         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3613         uint32_t mask;
3614         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3615
3616         if (queue_id < 32) {
3617                 mask = rd32(hw, TXGBE_IMS(0));
3618                 mask &= (1 << queue_id);
3619                 wr32(hw, TXGBE_IMS(0), mask);
3620         } else if (queue_id < 64) {
3621                 mask = rd32(hw, TXGBE_IMS(1));
3622                 mask &= (1 << (queue_id - 32));
3623                 wr32(hw, TXGBE_IMS(1), mask);
3624         }
3625         rte_intr_enable(intr_handle);
3626
3627         return 0;
3628 }
3629
3630 static int
3631 txgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
3632 {
3633         uint32_t mask;
3634         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3635
3636         if (queue_id < 32) {
3637                 mask = rd32(hw, TXGBE_IMS(0));
3638                 mask &= ~(1 << queue_id);
3639                 wr32(hw, TXGBE_IMS(0), mask);
3640         } else if (queue_id < 64) {
3641                 mask = rd32(hw, TXGBE_IMS(1));
3642                 mask &= ~(1 << (queue_id - 32));
3643                 wr32(hw, TXGBE_IMS(1), mask);
3644         }
3645
3646         return 0;
3647 }
3648
3649 /**
3650  * set the IVAR registers, mapping interrupt causes to vectors
3651  * @param hw
3652  *  pointer to txgbe_hw struct
3653  * @direction
3654  *  0 for Rx, 1 for Tx, -1 for other causes
3655  * @queue
3656  *  queue to map the corresponding interrupt to
3657  * @msix_vector
3658  *  the vector to map to the corresponding queue
3659  */
3660 void
3661 txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
3662                    uint8_t queue, uint8_t msix_vector)
3663 {
3664         uint32_t tmp, idx;
3665
3666         if (direction == -1) {
3667                 /* other causes */
3668                 msix_vector |= TXGBE_IVARMISC_VLD;
3669                 idx = 0;
3670                 tmp = rd32(hw, TXGBE_IVARMISC);
3671                 tmp &= ~(0xFF << idx);
3672                 tmp |= (msix_vector << idx);
3673                 wr32(hw, TXGBE_IVARMISC, tmp);
3674         } else {
3675                 /* rx or tx causes */
3676                 /* Workround for ICR lost */
3677                 idx = ((16 * (queue & 1)) + (8 * direction));
3678                 tmp = rd32(hw, TXGBE_IVAR(queue >> 1));
3679                 tmp &= ~(0xFF << idx);
3680                 tmp |= (msix_vector << idx);
3681                 wr32(hw, TXGBE_IVAR(queue >> 1), tmp);
3682         }
3683 }
3684
3685 /**
3686  * Sets up the hardware to properly generate MSI-X interrupts
3687  * @hw
3688  *  board private structure
3689  */
3690 static void
3691 txgbe_configure_msix(struct rte_eth_dev *dev)
3692 {
3693         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3694         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3695         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3696         uint32_t queue_id, base = TXGBE_MISC_VEC_ID;
3697         uint32_t vec = TXGBE_MISC_VEC_ID;
3698         uint32_t gpie;
3699
3700         /* won't configure msix register if no mapping is done
3701          * between intr vector and event fd
3702          * but if misx has been enabled already, need to configure
3703          * auto clean, auto mask and throttling.
3704          */
3705         gpie = rd32(hw, TXGBE_GPIE);
3706         if (!rte_intr_dp_is_en(intr_handle) &&
3707             !(gpie & TXGBE_GPIE_MSIX))
3708                 return;
3709
3710         if (rte_intr_allow_others(intr_handle)) {
3711                 base = TXGBE_RX_VEC_START;
3712                 vec = base;
3713         }
3714
3715         /* setup GPIE for MSI-x mode */
3716         gpie = rd32(hw, TXGBE_GPIE);
3717         gpie |= TXGBE_GPIE_MSIX;
3718         wr32(hw, TXGBE_GPIE, gpie);
3719
3720         /* Populate the IVAR table and set the ITR values to the
3721          * corresponding register.
3722          */
3723         if (rte_intr_dp_is_en(intr_handle)) {
3724                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
3725                         queue_id++) {
3726                         /* by default, 1:1 mapping */
3727                         txgbe_set_ivar_map(hw, 0, queue_id, vec);
3728                         intr_handle->intr_vec[queue_id] = vec;
3729                         if (vec < base + intr_handle->nb_efd - 1)
3730                                 vec++;
3731                 }
3732
3733                 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
3734         }
3735         wr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID),
3736                         TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
3737                         | TXGBE_ITR_WRDSA);
3738 }
3739
3740 int
3741 txgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3742                            uint16_t queue_idx, uint16_t tx_rate)
3743 {
3744         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3745         uint32_t bcnrc_val;
3746
3747         if (queue_idx >= hw->mac.max_tx_queues)
3748                 return -EINVAL;
3749
3750         if (tx_rate != 0) {
3751                 bcnrc_val = TXGBE_ARBTXRATE_MAX(tx_rate);
3752                 bcnrc_val |= TXGBE_ARBTXRATE_MIN(tx_rate / 2);
3753         } else {
3754                 bcnrc_val = 0;
3755         }
3756
3757         /*
3758          * Set global transmit compensation time to the MMW_SIZE in ARBTXMMW
3759          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
3760          */
3761         wr32(hw, TXGBE_ARBTXMMW, 0x14);
3762
3763         /* Set ARBTXRATE of queue X */
3764         wr32(hw, TXGBE_ARBPOOLIDX, queue_idx);
3765         wr32(hw, TXGBE_ARBTXRATE, bcnrc_val);
3766         txgbe_flush(hw);
3767
3768         return 0;
3769 }
3770
3771 int
3772 txgbe_syn_filter_set(struct rte_eth_dev *dev,
3773                         struct rte_eth_syn_filter *filter,
3774                         bool add)
3775 {
3776         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3777         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3778         uint32_t syn_info;
3779         uint32_t synqf;
3780
3781         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
3782                 return -EINVAL;
3783
3784         syn_info = filter_info->syn_info;
3785
3786         if (add) {
3787                 if (syn_info & TXGBE_SYNCLS_ENA)
3788                         return -EINVAL;
3789                 synqf = (uint32_t)TXGBE_SYNCLS_QPID(filter->queue);
3790                 synqf |= TXGBE_SYNCLS_ENA;
3791
3792                 if (filter->hig_pri)
3793                         synqf |= TXGBE_SYNCLS_HIPRIO;
3794                 else
3795                         synqf &= ~TXGBE_SYNCLS_HIPRIO;
3796         } else {
3797                 synqf = rd32(hw, TXGBE_SYNCLS);
3798                 if (!(syn_info & TXGBE_SYNCLS_ENA))
3799                         return -ENOENT;
3800                 synqf &= ~(TXGBE_SYNCLS_QPID_MASK | TXGBE_SYNCLS_ENA);
3801         }
3802
3803         filter_info->syn_info = synqf;
3804         wr32(hw, TXGBE_SYNCLS, synqf);
3805         txgbe_flush(hw);
3806         return 0;
3807 }
3808
3809 static inline enum txgbe_5tuple_protocol
3810 convert_protocol_type(uint8_t protocol_value)
3811 {
3812         if (protocol_value == IPPROTO_TCP)
3813                 return TXGBE_5TF_PROT_TCP;
3814         else if (protocol_value == IPPROTO_UDP)
3815                 return TXGBE_5TF_PROT_UDP;
3816         else if (protocol_value == IPPROTO_SCTP)
3817                 return TXGBE_5TF_PROT_SCTP;
3818         else
3819                 return TXGBE_5TF_PROT_NONE;
3820 }
3821
3822 /* inject a 5-tuple filter to HW */
3823 static inline void
3824 txgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
3825                            struct txgbe_5tuple_filter *filter)
3826 {
3827         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3828         int i;
3829         uint32_t ftqf, sdpqf;
3830         uint32_t l34timir = 0;
3831         uint32_t mask = TXGBE_5TFCTL0_MASK;
3832
3833         i = filter->index;
3834         sdpqf = TXGBE_5TFPORT_DST(be_to_le16(filter->filter_info.dst_port));
3835         sdpqf |= TXGBE_5TFPORT_SRC(be_to_le16(filter->filter_info.src_port));
3836
3837         ftqf = TXGBE_5TFCTL0_PROTO(filter->filter_info.proto);
3838         ftqf |= TXGBE_5TFCTL0_PRI(filter->filter_info.priority);
3839         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3840                 mask &= ~TXGBE_5TFCTL0_MSADDR;
3841         if (filter->filter_info.dst_ip_mask == 0)
3842                 mask &= ~TXGBE_5TFCTL0_MDADDR;
3843         if (filter->filter_info.src_port_mask == 0)
3844                 mask &= ~TXGBE_5TFCTL0_MSPORT;
3845         if (filter->filter_info.dst_port_mask == 0)
3846                 mask &= ~TXGBE_5TFCTL0_MDPORT;
3847         if (filter->filter_info.proto_mask == 0)
3848                 mask &= ~TXGBE_5TFCTL0_MPROTO;
3849         ftqf |= mask;
3850         ftqf |= TXGBE_5TFCTL0_MPOOL;
3851         ftqf |= TXGBE_5TFCTL0_ENA;
3852
3853         wr32(hw, TXGBE_5TFDADDR(i), be_to_le32(filter->filter_info.dst_ip));
3854         wr32(hw, TXGBE_5TFSADDR(i), be_to_le32(filter->filter_info.src_ip));
3855         wr32(hw, TXGBE_5TFPORT(i), sdpqf);
3856         wr32(hw, TXGBE_5TFCTL0(i), ftqf);
3857
3858         l34timir |= TXGBE_5TFCTL1_QP(filter->queue);
3859         wr32(hw, TXGBE_5TFCTL1(i), l34timir);
3860 }
3861
3862 /*
3863  * add a 5tuple filter
3864  *
3865  * @param
3866  * dev: Pointer to struct rte_eth_dev.
3867  * index: the index the filter allocates.
3868  * filter: pointer to the filter that will be added.
3869  * rx_queue: the queue id the filter assigned to.
3870  *
3871  * @return
3872  *    - On success, zero.
3873  *    - On failure, a negative value.
3874  */
3875 static int
3876 txgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3877                         struct txgbe_5tuple_filter *filter)
3878 {
3879         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3880         int i, idx, shift;
3881
3882         /*
3883          * look for an unused 5tuple filter index,
3884          * and insert the filter to list.
3885          */
3886         for (i = 0; i < TXGBE_MAX_FTQF_FILTERS; i++) {
3887                 idx = i / (sizeof(uint32_t) * NBBY);
3888                 shift = i % (sizeof(uint32_t) * NBBY);
3889                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3890                         filter_info->fivetuple_mask[idx] |= 1 << shift;
3891                         filter->index = i;
3892                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3893                                           filter,
3894                                           entries);
3895                         break;
3896                 }
3897         }
3898         if (i >= TXGBE_MAX_FTQF_FILTERS) {
3899                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3900                 return -ENOSYS;
3901         }
3902
3903         txgbe_inject_5tuple_filter(dev, filter);
3904
3905         return 0;
3906 }
3907
3908 /*
3909  * remove a 5tuple filter
3910  *
3911  * @param
3912  * dev: Pointer to struct rte_eth_dev.
3913  * filter: the pointer of the filter will be removed.
3914  */
3915 static void
3916 txgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3917                         struct txgbe_5tuple_filter *filter)
3918 {
3919         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3920         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3921         uint16_t index = filter->index;
3922
3923         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
3924                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
3925         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3926         rte_free(filter);
3927
3928         wr32(hw, TXGBE_5TFDADDR(index), 0);
3929         wr32(hw, TXGBE_5TFSADDR(index), 0);
3930         wr32(hw, TXGBE_5TFPORT(index), 0);
3931         wr32(hw, TXGBE_5TFCTL0(index), 0);
3932         wr32(hw, TXGBE_5TFCTL1(index), 0);
3933 }
3934
3935 static inline struct txgbe_5tuple_filter *
3936 txgbe_5tuple_filter_lookup(struct txgbe_5tuple_filter_list *filter_list,
3937                         struct txgbe_5tuple_filter_info *key)
3938 {
3939         struct txgbe_5tuple_filter *it;
3940
3941         TAILQ_FOREACH(it, filter_list, entries) {
3942                 if (memcmp(key, &it->filter_info,
3943                         sizeof(struct txgbe_5tuple_filter_info)) == 0) {
3944                         return it;
3945                 }
3946         }
3947         return NULL;
3948 }
3949
3950 /* translate elements in struct rte_eth_ntuple_filter
3951  * to struct txgbe_5tuple_filter_info
3952  */
3953 static inline int
3954 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
3955                         struct txgbe_5tuple_filter_info *filter_info)
3956 {
3957         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM ||
3958                 filter->priority > TXGBE_5TUPLE_MAX_PRI ||
3959                 filter->priority < TXGBE_5TUPLE_MIN_PRI)
3960                 return -EINVAL;
3961
3962         switch (filter->dst_ip_mask) {
3963         case UINT32_MAX:
3964                 filter_info->dst_ip_mask = 0;
3965                 filter_info->dst_ip = filter->dst_ip;
3966                 break;
3967         case 0:
3968                 filter_info->dst_ip_mask = 1;
3969                 break;
3970         default:
3971                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3972                 return -EINVAL;
3973         }
3974
3975         switch (filter->src_ip_mask) {
3976         case UINT32_MAX:
3977                 filter_info->src_ip_mask = 0;
3978                 filter_info->src_ip = filter->src_ip;
3979                 break;
3980         case 0:
3981                 filter_info->src_ip_mask = 1;
3982                 break;
3983         default:
3984                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3985                 return -EINVAL;
3986         }
3987
3988         switch (filter->dst_port_mask) {
3989         case UINT16_MAX:
3990                 filter_info->dst_port_mask = 0;
3991                 filter_info->dst_port = filter->dst_port;
3992                 break;
3993         case 0:
3994                 filter_info->dst_port_mask = 1;
3995                 break;
3996         default:
3997                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3998                 return -EINVAL;
3999         }
4000
4001         switch (filter->src_port_mask) {
4002         case UINT16_MAX:
4003                 filter_info->src_port_mask = 0;
4004                 filter_info->src_port = filter->src_port;
4005                 break;
4006         case 0:
4007                 filter_info->src_port_mask = 1;
4008                 break;
4009         default:
4010                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4011                 return -EINVAL;
4012         }
4013
4014         switch (filter->proto_mask) {
4015         case UINT8_MAX:
4016                 filter_info->proto_mask = 0;
4017                 filter_info->proto =
4018                         convert_protocol_type(filter->proto);
4019                 break;
4020         case 0:
4021                 filter_info->proto_mask = 1;
4022                 break;
4023         default:
4024                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4025                 return -EINVAL;
4026         }
4027
4028         filter_info->priority = (uint8_t)filter->priority;
4029         return 0;
4030 }
4031
4032 /*
4033  * add or delete a ntuple filter
4034  *
4035  * @param
4036  * dev: Pointer to struct rte_eth_dev.
4037  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4038  * add: if true, add filter, if false, remove filter
4039  *
4040  * @return
4041  *    - On success, zero.
4042  *    - On failure, a negative value.
4043  */
4044 int
4045 txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4046                         struct rte_eth_ntuple_filter *ntuple_filter,
4047                         bool add)
4048 {
4049         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4050         struct txgbe_5tuple_filter_info filter_5tuple;
4051         struct txgbe_5tuple_filter *filter;
4052         int ret;
4053
4054         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4055                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4056                 return -EINVAL;
4057         }
4058
4059         memset(&filter_5tuple, 0, sizeof(struct txgbe_5tuple_filter_info));
4060         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4061         if (ret < 0)
4062                 return ret;
4063
4064         filter = txgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4065                                          &filter_5tuple);
4066         if (filter != NULL && add) {
4067                 PMD_DRV_LOG(ERR, "filter exists.");
4068                 return -EEXIST;
4069         }
4070         if (filter == NULL && !add) {
4071                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4072                 return -ENOENT;
4073         }
4074
4075         if (add) {
4076                 filter = rte_zmalloc("txgbe_5tuple_filter",
4077                                 sizeof(struct txgbe_5tuple_filter), 0);
4078                 if (filter == NULL)
4079                         return -ENOMEM;
4080                 rte_memcpy(&filter->filter_info,
4081                                  &filter_5tuple,
4082                                  sizeof(struct txgbe_5tuple_filter_info));
4083                 filter->queue = ntuple_filter->queue;
4084                 ret = txgbe_add_5tuple_filter(dev, filter);
4085                 if (ret < 0) {
4086                         rte_free(filter);
4087                         return ret;
4088                 }
4089         } else {
4090                 txgbe_remove_5tuple_filter(dev, filter);
4091         }
4092
4093         return 0;
4094 }
4095
4096 int
4097 txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4098                         struct rte_eth_ethertype_filter *filter,
4099                         bool add)
4100 {
4101         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4102         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4103         uint32_t etqf = 0;
4104         uint32_t etqs = 0;
4105         int ret;
4106         struct txgbe_ethertype_filter ethertype_filter;
4107
4108         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
4109                 return -EINVAL;
4110
4111         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4112             filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4113                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4114                         " ethertype filter.", filter->ether_type);
4115                 return -EINVAL;
4116         }
4117
4118         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4119                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4120                 return -EINVAL;
4121         }
4122         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4123                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4124                 return -EINVAL;
4125         }
4126
4127         ret = txgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4128         if (ret >= 0 && add) {
4129                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4130                             filter->ether_type);
4131                 return -EEXIST;
4132         }
4133         if (ret < 0 && !add) {
4134                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4135                             filter->ether_type);
4136                 return -ENOENT;
4137         }
4138
4139         if (add) {
4140                 etqf = TXGBE_ETFLT_ENA;
4141                 etqf |= TXGBE_ETFLT_ETID(filter->ether_type);
4142                 etqs |= TXGBE_ETCLS_QPID(filter->queue);
4143                 etqs |= TXGBE_ETCLS_QENA;
4144
4145                 ethertype_filter.ethertype = filter->ether_type;
4146                 ethertype_filter.etqf = etqf;
4147                 ethertype_filter.etqs = etqs;
4148                 ethertype_filter.conf = FALSE;
4149                 ret = txgbe_ethertype_filter_insert(filter_info,
4150                                                     &ethertype_filter);
4151                 if (ret < 0) {
4152                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4153                         return -ENOSPC;
4154                 }
4155         } else {
4156                 ret = txgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4157                 if (ret < 0)
4158                         return -ENOSYS;
4159         }
4160         wr32(hw, TXGBE_ETFLT(ret), etqf);
4161         wr32(hw, TXGBE_ETCLS(ret), etqs);
4162         txgbe_flush(hw);
4163
4164         return 0;
4165 }
4166
4167 static int
4168 txgbe_dev_flow_ops_get(__rte_unused struct rte_eth_dev *dev,
4169                        const struct rte_flow_ops **ops)
4170 {
4171         *ops = &txgbe_flow_ops;
4172         return 0;
4173 }
4174
4175 static u8 *
4176 txgbe_dev_addr_list_itr(__rte_unused struct txgbe_hw *hw,
4177                         u8 **mc_addr_ptr, u32 *vmdq)
4178 {
4179         u8 *mc_addr;
4180
4181         *vmdq = 0;
4182         mc_addr = *mc_addr_ptr;
4183         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
4184         return mc_addr;
4185 }
4186
4187 int
4188 txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
4189                           struct rte_ether_addr *mc_addr_set,
4190                           uint32_t nb_mc_addr)
4191 {
4192         struct txgbe_hw *hw;
4193         u8 *mc_addr_list;
4194
4195         hw = TXGBE_DEV_HW(dev);
4196         mc_addr_list = (u8 *)mc_addr_set;
4197         return hw->mac.update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
4198                                          txgbe_dev_addr_list_itr, TRUE);
4199 }
4200
4201 static uint64_t
4202 txgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
4203 {
4204         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4205         uint64_t systime_cycles;
4206
4207         systime_cycles = (uint64_t)rd32(hw, TXGBE_TSTIMEL);
4208         systime_cycles |= (uint64_t)rd32(hw, TXGBE_TSTIMEH) << 32;
4209
4210         return systime_cycles;
4211 }
4212
4213 static uint64_t
4214 txgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4215 {
4216         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4217         uint64_t rx_tstamp_cycles;
4218
4219         /* TSRXSTMPL stores ns and TSRXSTMPH stores seconds. */
4220         rx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSRXSTMPL);
4221         rx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSRXSTMPH) << 32;
4222
4223         return rx_tstamp_cycles;
4224 }
4225
4226 static uint64_t
4227 txgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4228 {
4229         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4230         uint64_t tx_tstamp_cycles;
4231
4232         /* TSTXSTMPL stores ns and TSTXSTMPH stores seconds. */
4233         tx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSTXSTMPL);
4234         tx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSTXSTMPH) << 32;
4235
4236         return tx_tstamp_cycles;
4237 }
4238
4239 static void
4240 txgbe_start_timecounters(struct rte_eth_dev *dev)
4241 {
4242         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4243         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4244         struct rte_eth_link link;
4245         uint32_t incval = 0;
4246         uint32_t shift = 0;
4247
4248         /* Get current link speed. */
4249         txgbe_dev_link_update(dev, 1);
4250         rte_eth_linkstatus_get(dev, &link);
4251
4252         switch (link.link_speed) {
4253         case ETH_SPEED_NUM_100M:
4254                 incval = TXGBE_INCVAL_100;
4255                 shift = TXGBE_INCVAL_SHIFT_100;
4256                 break;
4257         case ETH_SPEED_NUM_1G:
4258                 incval = TXGBE_INCVAL_1GB;
4259                 shift = TXGBE_INCVAL_SHIFT_1GB;
4260                 break;
4261         case ETH_SPEED_NUM_10G:
4262         default:
4263                 incval = TXGBE_INCVAL_10GB;
4264                 shift = TXGBE_INCVAL_SHIFT_10GB;
4265                 break;
4266         }
4267
4268         wr32(hw, TXGBE_TSTIMEINC, TXGBE_TSTIMEINC_VP(incval, 2));
4269
4270         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4271         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4272         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4273
4274         adapter->systime_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4275         adapter->systime_tc.cc_shift = shift;
4276         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4277
4278         adapter->rx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4279         adapter->rx_tstamp_tc.cc_shift = shift;
4280         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4281
4282         adapter->tx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4283         adapter->tx_tstamp_tc.cc_shift = shift;
4284         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4285 }
4286
4287 static int
4288 txgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4289 {
4290         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4291
4292         adapter->systime_tc.nsec += delta;
4293         adapter->rx_tstamp_tc.nsec += delta;
4294         adapter->tx_tstamp_tc.nsec += delta;
4295
4296         return 0;
4297 }
4298
4299 static int
4300 txgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4301 {
4302         uint64_t ns;
4303         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4304
4305         ns = rte_timespec_to_ns(ts);
4306         /* Set the timecounters to a new value. */
4307         adapter->systime_tc.nsec = ns;
4308         adapter->rx_tstamp_tc.nsec = ns;
4309         adapter->tx_tstamp_tc.nsec = ns;
4310
4311         return 0;
4312 }
4313
4314 static int
4315 txgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4316 {
4317         uint64_t ns, systime_cycles;
4318         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4319
4320         systime_cycles = txgbe_read_systime_cyclecounter(dev);
4321         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4322         *ts = rte_ns_to_timespec(ns);
4323
4324         return 0;
4325 }
4326
4327 static int
4328 txgbe_timesync_enable(struct rte_eth_dev *dev)
4329 {
4330         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4331         uint32_t tsync_ctl;
4332
4333         /* Stop the timesync system time. */
4334         wr32(hw, TXGBE_TSTIMEINC, 0x0);
4335         /* Reset the timesync system time value. */
4336         wr32(hw, TXGBE_TSTIMEL, 0x0);
4337         wr32(hw, TXGBE_TSTIMEH, 0x0);
4338
4339         txgbe_start_timecounters(dev);
4340
4341         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4342         wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588),
4343                 RTE_ETHER_TYPE_1588 | TXGBE_ETFLT_ENA | TXGBE_ETFLT_1588);
4344
4345         /* Enable timestamping of received PTP packets. */
4346         tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4347         tsync_ctl |= TXGBE_TSRXCTL_ENA;
4348         wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4349
4350         /* Enable timestamping of transmitted PTP packets. */
4351         tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4352         tsync_ctl |= TXGBE_TSTXCTL_ENA;
4353         wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4354
4355         txgbe_flush(hw);
4356
4357         return 0;
4358 }
4359
4360 static int
4361 txgbe_timesync_disable(struct rte_eth_dev *dev)
4362 {
4363         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4364         uint32_t tsync_ctl;
4365
4366         /* Disable timestamping of transmitted PTP packets. */
4367         tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4368         tsync_ctl &= ~TXGBE_TSTXCTL_ENA;
4369         wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4370
4371         /* Disable timestamping of received PTP packets. */
4372         tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4373         tsync_ctl &= ~TXGBE_TSRXCTL_ENA;
4374         wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4375
4376         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4377         wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588), 0);
4378
4379         /* Stop incrementating the System Time registers. */
4380         wr32(hw, TXGBE_TSTIMEINC, 0);
4381
4382         return 0;
4383 }
4384
4385 static int
4386 txgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4387                                  struct timespec *timestamp,
4388                                  uint32_t flags __rte_unused)
4389 {
4390         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4391         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4392         uint32_t tsync_rxctl;
4393         uint64_t rx_tstamp_cycles;
4394         uint64_t ns;
4395
4396         tsync_rxctl = rd32(hw, TXGBE_TSRXCTL);
4397         if ((tsync_rxctl & TXGBE_TSRXCTL_VLD) == 0)
4398                 return -EINVAL;
4399
4400         rx_tstamp_cycles = txgbe_read_rx_tstamp_cyclecounter(dev);
4401         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4402         *timestamp = rte_ns_to_timespec(ns);
4403
4404         return  0;
4405 }
4406
4407 static int
4408 txgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4409                                  struct timespec *timestamp)
4410 {
4411         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4412         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4413         uint32_t tsync_txctl;
4414         uint64_t tx_tstamp_cycles;
4415         uint64_t ns;
4416
4417         tsync_txctl = rd32(hw, TXGBE_TSTXCTL);
4418         if ((tsync_txctl & TXGBE_TSTXCTL_VLD) == 0)
4419                 return -EINVAL;
4420
4421         tx_tstamp_cycles = txgbe_read_tx_tstamp_cyclecounter(dev);
4422         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4423         *timestamp = rte_ns_to_timespec(ns);
4424
4425         return 0;
4426 }
4427
4428 static int
4429 txgbe_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4430 {
4431         int count = 0;
4432         int g_ind = 0;
4433         const struct reg_info *reg_group;
4434         const struct reg_info **reg_set = txgbe_regs_others;
4435
4436         while ((reg_group = reg_set[g_ind++]))
4437                 count += txgbe_regs_group_count(reg_group);
4438
4439         return count;
4440 }
4441
4442 static int
4443 txgbe_get_regs(struct rte_eth_dev *dev,
4444               struct rte_dev_reg_info *regs)
4445 {
4446         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4447         uint32_t *data = regs->data;
4448         int g_ind = 0;
4449         int count = 0;
4450         const struct reg_info *reg_group;
4451         const struct reg_info **reg_set = txgbe_regs_others;
4452
4453         if (data == NULL) {
4454                 regs->length = txgbe_get_reg_length(dev);
4455                 regs->width = sizeof(uint32_t);
4456                 return 0;
4457         }
4458
4459         /* Support only full register dump */
4460         if (regs->length == 0 ||
4461             regs->length == (uint32_t)txgbe_get_reg_length(dev)) {
4462                 regs->version = hw->mac.type << 24 |
4463                                 hw->revision_id << 16 |
4464                                 hw->device_id;
4465                 while ((reg_group = reg_set[g_ind++]))
4466                         count += txgbe_read_regs_group(dev, &data[count],
4467                                                       reg_group);
4468                 return 0;
4469         }
4470
4471         return -ENOTSUP;
4472 }
4473
4474 static int
4475 txgbe_get_eeprom_length(struct rte_eth_dev *dev)
4476 {
4477         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4478
4479         /* Return unit is byte count */
4480         return hw->rom.word_size * 2;
4481 }
4482
4483 static int
4484 txgbe_get_eeprom(struct rte_eth_dev *dev,
4485                 struct rte_dev_eeprom_info *in_eeprom)
4486 {
4487         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4488         struct txgbe_rom_info *eeprom = &hw->rom;
4489         uint16_t *data = in_eeprom->data;
4490         int first, length;
4491
4492         first = in_eeprom->offset >> 1;
4493         length = in_eeprom->length >> 1;
4494         if (first > hw->rom.word_size ||
4495             ((first + length) > hw->rom.word_size))
4496                 return -EINVAL;
4497
4498         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4499
4500         return eeprom->readw_buffer(hw, first, length, data);
4501 }
4502
4503 static int
4504 txgbe_set_eeprom(struct rte_eth_dev *dev,
4505                 struct rte_dev_eeprom_info *in_eeprom)
4506 {
4507         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4508         struct txgbe_rom_info *eeprom = &hw->rom;
4509         uint16_t *data = in_eeprom->data;
4510         int first, length;
4511
4512         first = in_eeprom->offset >> 1;
4513         length = in_eeprom->length >> 1;
4514         if (first > hw->rom.word_size ||
4515             ((first + length) > hw->rom.word_size))
4516                 return -EINVAL;
4517
4518         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4519
4520         return eeprom->writew_buffer(hw,  first, length, data);
4521 }
4522
4523 static int
4524 txgbe_get_module_info(struct rte_eth_dev *dev,
4525                       struct rte_eth_dev_module_info *modinfo)
4526 {
4527         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4528         uint32_t status;
4529         uint8_t sff8472_rev, addr_mode;
4530         bool page_swap = false;
4531
4532         /* Check whether we support SFF-8472 or not */
4533         status = hw->phy.read_i2c_eeprom(hw,
4534                                              TXGBE_SFF_SFF_8472_COMP,
4535                                              &sff8472_rev);
4536         if (status != 0)
4537                 return -EIO;
4538
4539         /* addressing mode is not supported */
4540         status = hw->phy.read_i2c_eeprom(hw,
4541                                              TXGBE_SFF_SFF_8472_SWAP,
4542                                              &addr_mode);
4543         if (status != 0)
4544                 return -EIO;
4545
4546         if (addr_mode & TXGBE_SFF_ADDRESSING_MODE) {
4547                 PMD_DRV_LOG(ERR,
4548                             "Address change required to access page 0xA2, "
4549                             "but not supported. Please report the module "
4550                             "type to the driver maintainers.");
4551                 page_swap = true;
4552         }
4553
4554         if (sff8472_rev == TXGBE_SFF_SFF_8472_UNSUP || page_swap) {
4555                 /* We have a SFP, but it does not support SFF-8472 */
4556                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
4557                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
4558         } else {
4559                 /* We have a SFP which supports a revision of SFF-8472. */
4560                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
4561                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
4562         }
4563
4564         return 0;
4565 }
4566
4567 static int
4568 txgbe_get_module_eeprom(struct rte_eth_dev *dev,
4569                         struct rte_dev_eeprom_info *info)
4570 {
4571         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4572         uint32_t status = TXGBE_ERR_PHY_ADDR_INVALID;
4573         uint8_t databyte = 0xFF;
4574         uint8_t *data = info->data;
4575         uint32_t i = 0;
4576
4577         if (info->length == 0)
4578                 return -EINVAL;
4579
4580         for (i = info->offset; i < info->offset + info->length; i++) {
4581                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
4582                         status = hw->phy.read_i2c_eeprom(hw, i, &databyte);
4583                 else
4584                         status = hw->phy.read_i2c_sff8472(hw, i, &databyte);
4585
4586                 if (status != 0)
4587                         return -EIO;
4588
4589                 data[i - info->offset] = databyte;
4590         }
4591
4592         return 0;
4593 }
4594
4595 bool
4596 txgbe_rss_update_sp(enum txgbe_mac_type mac_type)
4597 {
4598         switch (mac_type) {
4599         case txgbe_mac_raptor:
4600         case txgbe_mac_raptor_vf:
4601                 return 1;
4602         default:
4603                 return 0;
4604         }
4605 }
4606
4607 static int
4608 txgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
4609                         struct rte_eth_dcb_info *dcb_info)
4610 {
4611         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
4612         struct txgbe_dcb_tc_config *tc;
4613         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
4614         uint8_t nb_tcs;
4615         uint8_t i, j;
4616
4617         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
4618                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
4619         else
4620                 dcb_info->nb_tcs = 1;
4621
4622         tc_queue = &dcb_info->tc_queue;
4623         nb_tcs = dcb_info->nb_tcs;
4624
4625         if (dcb_config->vt_mode) { /* vt is enabled */
4626                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
4627                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
4628                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
4629                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
4630                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
4631                         for (j = 0; j < nb_tcs; j++) {
4632                                 tc_queue->tc_rxq[0][j].base = j;
4633                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
4634                                 tc_queue->tc_txq[0][j].base = j;
4635                                 tc_queue->tc_txq[0][j].nb_queue = 1;
4636                         }
4637                 } else {
4638                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
4639                                 for (j = 0; j < nb_tcs; j++) {
4640                                         tc_queue->tc_rxq[i][j].base =
4641                                                 i * nb_tcs + j;
4642                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
4643                                         tc_queue->tc_txq[i][j].base =
4644                                                 i * nb_tcs + j;
4645                                         tc_queue->tc_txq[i][j].nb_queue = 1;
4646                                 }
4647                         }
4648                 }
4649         } else { /* vt is disabled */
4650                 struct rte_eth_dcb_rx_conf *rx_conf =
4651                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
4652                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
4653                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
4654                 if (dcb_info->nb_tcs == ETH_4_TCS) {
4655                         for (i = 0; i < dcb_info->nb_tcs; i++) {
4656                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
4657                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4658                         }
4659                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
4660                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
4661                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
4662                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
4663                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
4664                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4665                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4666                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4667                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
4668                         for (i = 0; i < dcb_info->nb_tcs; i++) {
4669                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
4670                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4671                         }
4672                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
4673                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
4674                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
4675                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
4676                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
4677                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
4678                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
4679                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
4680                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
4681                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4682                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4683                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4684                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
4685                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
4686                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
4687                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
4688                 }
4689         }
4690         for (i = 0; i < dcb_info->nb_tcs; i++) {
4691                 tc = &dcb_config->tc_config[i];
4692                 dcb_info->tc_bws[i] = tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent;
4693         }
4694         return 0;
4695 }
4696
4697 /* Update e-tag ether type */
4698 static int
4699 txgbe_update_e_tag_eth_type(struct txgbe_hw *hw,
4700                             uint16_t ether_type)
4701 {
4702         uint32_t etag_etype;
4703
4704         etag_etype = rd32(hw, TXGBE_EXTAG);
4705         etag_etype &= ~TXGBE_EXTAG_ETAG_MASK;
4706         etag_etype |= ether_type;
4707         wr32(hw, TXGBE_EXTAG, etag_etype);
4708         txgbe_flush(hw);
4709
4710         return 0;
4711 }
4712
4713 /* Enable e-tag tunnel */
4714 static int
4715 txgbe_e_tag_enable(struct txgbe_hw *hw)
4716 {
4717         uint32_t etag_etype;
4718
4719         etag_etype = rd32(hw, TXGBE_PORTCTL);
4720         etag_etype |= TXGBE_PORTCTL_ETAG;
4721         wr32(hw, TXGBE_PORTCTL, etag_etype);
4722         txgbe_flush(hw);
4723
4724         return 0;
4725 }
4726
4727 static int
4728 txgbe_e_tag_filter_del(struct rte_eth_dev *dev,
4729                        struct txgbe_l2_tunnel_conf  *l2_tunnel)
4730 {
4731         int ret = 0;
4732         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4733         uint32_t i, rar_entries;
4734         uint32_t rar_low, rar_high;
4735
4736         rar_entries = hw->mac.num_rar_entries;
4737
4738         for (i = 1; i < rar_entries; i++) {
4739                 wr32(hw, TXGBE_ETHADDRIDX, i);
4740                 rar_high = rd32(hw, TXGBE_ETHADDRH);
4741                 rar_low  = rd32(hw, TXGBE_ETHADDRL);
4742                 if ((rar_high & TXGBE_ETHADDRH_VLD) &&
4743                     (rar_high & TXGBE_ETHADDRH_ETAG) &&
4744                     (TXGBE_ETHADDRL_ETAG(rar_low) ==
4745                      l2_tunnel->tunnel_id)) {
4746                         wr32(hw, TXGBE_ETHADDRL, 0);
4747                         wr32(hw, TXGBE_ETHADDRH, 0);
4748
4749                         txgbe_clear_vmdq(hw, i, BIT_MASK32);
4750
4751                         return ret;
4752                 }
4753         }
4754
4755         return ret;
4756 }
4757
4758 static int
4759 txgbe_e_tag_filter_add(struct rte_eth_dev *dev,
4760                        struct txgbe_l2_tunnel_conf *l2_tunnel)
4761 {
4762         int ret = 0;
4763         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4764         uint32_t i, rar_entries;
4765         uint32_t rar_low, rar_high;
4766
4767         /* One entry for one tunnel. Try to remove potential existing entry. */
4768         txgbe_e_tag_filter_del(dev, l2_tunnel);
4769
4770         rar_entries = hw->mac.num_rar_entries;
4771
4772         for (i = 1; i < rar_entries; i++) {
4773                 wr32(hw, TXGBE_ETHADDRIDX, i);
4774                 rar_high = rd32(hw, TXGBE_ETHADDRH);
4775                 if (rar_high & TXGBE_ETHADDRH_VLD) {
4776                         continue;
4777                 } else {
4778                         txgbe_set_vmdq(hw, i, l2_tunnel->pool);
4779                         rar_high = TXGBE_ETHADDRH_VLD | TXGBE_ETHADDRH_ETAG;
4780                         rar_low = l2_tunnel->tunnel_id;
4781
4782                         wr32(hw, TXGBE_ETHADDRL, rar_low);
4783                         wr32(hw, TXGBE_ETHADDRH, rar_high);
4784
4785                         return ret;
4786                 }
4787         }
4788
4789         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
4790                      " Please remove a rule before adding a new one.");
4791         return -EINVAL;
4792 }
4793
4794 static inline struct txgbe_l2_tn_filter *
4795 txgbe_l2_tn_filter_lookup(struct txgbe_l2_tn_info *l2_tn_info,
4796                           struct txgbe_l2_tn_key *key)
4797 {
4798         int ret;
4799
4800         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
4801         if (ret < 0)
4802                 return NULL;
4803
4804         return l2_tn_info->hash_map[ret];
4805 }
4806
4807 static inline int
4808 txgbe_insert_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info,
4809                           struct txgbe_l2_tn_filter *l2_tn_filter)
4810 {
4811         int ret;
4812
4813         ret = rte_hash_add_key(l2_tn_info->hash_handle,
4814                                &l2_tn_filter->key);
4815
4816         if (ret < 0) {
4817                 PMD_DRV_LOG(ERR,
4818                             "Failed to insert L2 tunnel filter"
4819                             " to hash table %d!",
4820                             ret);
4821                 return ret;
4822         }
4823
4824         l2_tn_info->hash_map[ret] = l2_tn_filter;
4825
4826         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
4827
4828         return 0;
4829 }
4830
4831 static inline int
4832 txgbe_remove_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info,
4833                           struct txgbe_l2_tn_key *key)
4834 {
4835         int ret;
4836         struct txgbe_l2_tn_filter *l2_tn_filter;
4837
4838         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
4839
4840         if (ret < 0) {
4841                 PMD_DRV_LOG(ERR,
4842                             "No such L2 tunnel filter to delete %d!",
4843                             ret);
4844                 return ret;
4845         }
4846
4847         l2_tn_filter = l2_tn_info->hash_map[ret];
4848         l2_tn_info->hash_map[ret] = NULL;
4849
4850         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
4851         rte_free(l2_tn_filter);
4852
4853         return 0;
4854 }
4855
4856 /* Add l2 tunnel filter */
4857 int
4858 txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
4859                                struct txgbe_l2_tunnel_conf *l2_tunnel,
4860                                bool restore)
4861 {
4862         int ret;
4863         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
4864         struct txgbe_l2_tn_key key;
4865         struct txgbe_l2_tn_filter *node;
4866
4867         if (!restore) {
4868                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
4869                 key.tn_id = l2_tunnel->tunnel_id;
4870
4871                 node = txgbe_l2_tn_filter_lookup(l2_tn_info, &key);
4872
4873                 if (node) {
4874                         PMD_DRV_LOG(ERR,
4875                                     "The L2 tunnel filter already exists!");
4876                         return -EINVAL;
4877                 }
4878
4879                 node = rte_zmalloc("txgbe_l2_tn",
4880                                    sizeof(struct txgbe_l2_tn_filter),
4881                                    0);
4882                 if (!node)
4883                         return -ENOMEM;
4884
4885                 rte_memcpy(&node->key,
4886                                  &key,
4887                                  sizeof(struct txgbe_l2_tn_key));
4888                 node->pool = l2_tunnel->pool;
4889                 ret = txgbe_insert_l2_tn_filter(l2_tn_info, node);
4890                 if (ret < 0) {
4891                         rte_free(node);
4892                         return ret;
4893                 }
4894         }
4895
4896         switch (l2_tunnel->l2_tunnel_type) {
4897         case RTE_L2_TUNNEL_TYPE_E_TAG:
4898                 ret = txgbe_e_tag_filter_add(dev, l2_tunnel);
4899                 break;
4900         default:
4901                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4902                 ret = -EINVAL;
4903                 break;
4904         }
4905
4906         if (!restore && ret < 0)
4907                 (void)txgbe_remove_l2_tn_filter(l2_tn_info, &key);
4908
4909         return ret;
4910 }
4911
4912 /* Delete l2 tunnel filter */
4913 int
4914 txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
4915                                struct txgbe_l2_tunnel_conf *l2_tunnel)
4916 {
4917         int ret;
4918         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
4919         struct txgbe_l2_tn_key key;
4920
4921         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
4922         key.tn_id = l2_tunnel->tunnel_id;
4923         ret = txgbe_remove_l2_tn_filter(l2_tn_info, &key);
4924         if (ret < 0)
4925                 return ret;
4926
4927         switch (l2_tunnel->l2_tunnel_type) {
4928         case RTE_L2_TUNNEL_TYPE_E_TAG:
4929                 ret = txgbe_e_tag_filter_del(dev, l2_tunnel);
4930                 break;
4931         default:
4932                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4933                 ret = -EINVAL;
4934                 break;
4935         }
4936
4937         return ret;
4938 }
4939
4940 static int
4941 txgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
4942 {
4943         int ret = 0;
4944         uint32_t ctrl;
4945         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4946
4947         ctrl = rd32(hw, TXGBE_POOLCTL);
4948         ctrl &= ~TXGBE_POOLCTL_MODE_MASK;
4949         if (en)
4950                 ctrl |= TXGBE_PSRPOOL_MODE_ETAG;
4951         wr32(hw, TXGBE_POOLCTL, ctrl);
4952
4953         return ret;
4954 }
4955
4956 /* Add UDP tunneling port */
4957 static int
4958 txgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4959                               struct rte_eth_udp_tunnel *udp_tunnel)
4960 {
4961         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4962         int ret = 0;
4963
4964         if (udp_tunnel == NULL)
4965                 return -EINVAL;
4966
4967         switch (udp_tunnel->prot_type) {
4968         case RTE_TUNNEL_TYPE_VXLAN:
4969                 if (udp_tunnel->udp_port == 0) {
4970                         PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
4971                         ret = -EINVAL;
4972                         break;
4973                 }
4974                 wr32(hw, TXGBE_VXLANPORT, udp_tunnel->udp_port);
4975                 break;
4976         case RTE_TUNNEL_TYPE_GENEVE:
4977                 if (udp_tunnel->udp_port == 0) {
4978                         PMD_DRV_LOG(ERR, "Add Geneve port 0 is not allowed.");
4979                         ret = -EINVAL;
4980                         break;
4981                 }
4982                 wr32(hw, TXGBE_GENEVEPORT, udp_tunnel->udp_port);
4983                 break;
4984         case RTE_TUNNEL_TYPE_TEREDO:
4985                 if (udp_tunnel->udp_port == 0) {
4986                         PMD_DRV_LOG(ERR, "Add Teredo port 0 is not allowed.");
4987                         ret = -EINVAL;
4988                         break;
4989                 }
4990                 wr32(hw, TXGBE_TEREDOPORT, udp_tunnel->udp_port);
4991                 break;
4992         case RTE_TUNNEL_TYPE_VXLAN_GPE:
4993                 if (udp_tunnel->udp_port == 0) {
4994                         PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
4995                         ret = -EINVAL;
4996                         break;
4997                 }
4998                 wr32(hw, TXGBE_VXLANPORTGPE, udp_tunnel->udp_port);
4999                 break;
5000         default:
5001                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5002                 ret = -EINVAL;
5003                 break;
5004         }
5005
5006         txgbe_flush(hw);
5007
5008         return ret;
5009 }
5010
5011 /* Remove UDP tunneling port */
5012 static int
5013 txgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5014                               struct rte_eth_udp_tunnel *udp_tunnel)
5015 {
5016         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5017         int ret = 0;
5018         uint16_t cur_port;
5019
5020         if (udp_tunnel == NULL)
5021                 return -EINVAL;
5022
5023         switch (udp_tunnel->prot_type) {
5024         case RTE_TUNNEL_TYPE_VXLAN:
5025                 cur_port = (uint16_t)rd32(hw, TXGBE_VXLANPORT);
5026                 if (cur_port != udp_tunnel->udp_port) {
5027                         PMD_DRV_LOG(ERR, "Port %u does not exist.",
5028                                         udp_tunnel->udp_port);
5029                         ret = -EINVAL;
5030                         break;
5031                 }
5032                 wr32(hw, TXGBE_VXLANPORT, 0);
5033                 break;
5034         case RTE_TUNNEL_TYPE_GENEVE:
5035                 cur_port = (uint16_t)rd32(hw, TXGBE_GENEVEPORT);
5036                 if (cur_port != udp_tunnel->udp_port) {
5037                         PMD_DRV_LOG(ERR, "Port %u does not exist.",
5038                                         udp_tunnel->udp_port);
5039                         ret = -EINVAL;
5040                         break;
5041                 }
5042                 wr32(hw, TXGBE_GENEVEPORT, 0);
5043                 break;
5044         case RTE_TUNNEL_TYPE_TEREDO:
5045                 cur_port = (uint16_t)rd32(hw, TXGBE_TEREDOPORT);
5046                 if (cur_port != udp_tunnel->udp_port) {
5047                         PMD_DRV_LOG(ERR, "Port %u does not exist.",
5048                                         udp_tunnel->udp_port);
5049                         ret = -EINVAL;
5050                         break;
5051                 }
5052                 wr32(hw, TXGBE_TEREDOPORT, 0);
5053                 break;
5054         case RTE_TUNNEL_TYPE_VXLAN_GPE:
5055                 cur_port = (uint16_t)rd32(hw, TXGBE_VXLANPORTGPE);
5056                 if (cur_port != udp_tunnel->udp_port) {
5057                         PMD_DRV_LOG(ERR, "Port %u does not exist.",
5058                                         udp_tunnel->udp_port);
5059                         ret = -EINVAL;
5060                         break;
5061                 }
5062                 wr32(hw, TXGBE_VXLANPORTGPE, 0);
5063                 break;
5064         default:
5065                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5066                 ret = -EINVAL;
5067                 break;
5068         }
5069
5070         txgbe_flush(hw);
5071
5072         return ret;
5073 }
5074
5075 /* restore n-tuple filter */
5076 static inline void
5077 txgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
5078 {
5079         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5080         struct txgbe_5tuple_filter *node;
5081
5082         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
5083                 txgbe_inject_5tuple_filter(dev, node);
5084         }
5085 }
5086
5087 /* restore ethernet type filter */
5088 static inline void
5089 txgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
5090 {
5091         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5092         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5093         int i;
5094
5095         for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
5096                 if (filter_info->ethertype_mask & (1 << i)) {
5097                         wr32(hw, TXGBE_ETFLT(i),
5098                                         filter_info->ethertype_filters[i].etqf);
5099                         wr32(hw, TXGBE_ETCLS(i),
5100                                         filter_info->ethertype_filters[i].etqs);
5101                         txgbe_flush(hw);
5102                 }
5103         }
5104 }
5105
5106 /* restore SYN filter */
5107 static inline void
5108 txgbe_syn_filter_restore(struct rte_eth_dev *dev)
5109 {
5110         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5111         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5112         uint32_t synqf;
5113
5114         synqf = filter_info->syn_info;
5115
5116         if (synqf & TXGBE_SYNCLS_ENA) {
5117                 wr32(hw, TXGBE_SYNCLS, synqf);
5118                 txgbe_flush(hw);
5119         }
5120 }
5121
5122 /* restore L2 tunnel filter */
5123 static inline void
5124 txgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
5125 {
5126         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
5127         struct txgbe_l2_tn_filter *node;
5128         struct txgbe_l2_tunnel_conf l2_tn_conf;
5129
5130         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
5131                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
5132                 l2_tn_conf.tunnel_id      = node->key.tn_id;
5133                 l2_tn_conf.pool           = node->pool;
5134                 (void)txgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
5135         }
5136 }
5137
5138 /* restore rss filter */
5139 static inline void
5140 txgbe_rss_filter_restore(struct rte_eth_dev *dev)
5141 {
5142         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5143
5144         if (filter_info->rss_info.conf.queue_num)
5145                 txgbe_config_rss_filter(dev,
5146                         &filter_info->rss_info, TRUE);
5147 }
5148
5149 static int
5150 txgbe_filter_restore(struct rte_eth_dev *dev)
5151 {
5152         txgbe_ntuple_filter_restore(dev);
5153         txgbe_ethertype_filter_restore(dev);
5154         txgbe_syn_filter_restore(dev);
5155         txgbe_fdir_filter_restore(dev);
5156         txgbe_l2_tn_filter_restore(dev);
5157         txgbe_rss_filter_restore(dev);
5158
5159         return 0;
5160 }
5161
5162 static void
5163 txgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
5164 {
5165         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
5166         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5167
5168         if (l2_tn_info->e_tag_en)
5169                 (void)txgbe_e_tag_enable(hw);
5170
5171         if (l2_tn_info->e_tag_fwd_en)
5172                 (void)txgbe_e_tag_forwarding_en_dis(dev, 1);
5173
5174         (void)txgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
5175 }
5176
5177 /* remove all the n-tuple filters */
5178 void
5179 txgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
5180 {
5181         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5182         struct txgbe_5tuple_filter *p_5tuple;
5183
5184         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
5185                 txgbe_remove_5tuple_filter(dev, p_5tuple);
5186 }
5187
5188 /* remove all the ether type filters */
5189 void
5190 txgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
5191 {
5192         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5193         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5194         int i;
5195
5196         for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
5197                 if (filter_info->ethertype_mask & (1 << i) &&
5198                     !filter_info->ethertype_filters[i].conf) {
5199                         (void)txgbe_ethertype_filter_remove(filter_info,
5200                                                             (uint8_t)i);
5201                         wr32(hw, TXGBE_ETFLT(i), 0);
5202                         wr32(hw, TXGBE_ETCLS(i), 0);
5203                         txgbe_flush(hw);
5204                 }
5205         }
5206 }
5207
5208 /* remove the SYN filter */
5209 void
5210 txgbe_clear_syn_filter(struct rte_eth_dev *dev)
5211 {
5212         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5213         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5214
5215         if (filter_info->syn_info & TXGBE_SYNCLS_ENA) {
5216                 filter_info->syn_info = 0;
5217
5218                 wr32(hw, TXGBE_SYNCLS, 0);
5219                 txgbe_flush(hw);
5220         }
5221 }
5222
5223 /* remove all the L2 tunnel filters */
5224 int
5225 txgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
5226 {
5227         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
5228         struct txgbe_l2_tn_filter *l2_tn_filter;
5229         struct txgbe_l2_tunnel_conf l2_tn_conf;
5230         int ret = 0;
5231
5232         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
5233                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
5234                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
5235                 l2_tn_conf.pool           = l2_tn_filter->pool;
5236                 ret = txgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
5237                 if (ret < 0)
5238                         return ret;
5239         }
5240
5241         return 0;
5242 }
5243
5244 static const struct eth_dev_ops txgbe_eth_dev_ops = {
5245         .dev_configure              = txgbe_dev_configure,
5246         .dev_infos_get              = txgbe_dev_info_get,
5247         .dev_start                  = txgbe_dev_start,
5248         .dev_stop                   = txgbe_dev_stop,
5249         .dev_set_link_up            = txgbe_dev_set_link_up,
5250         .dev_set_link_down          = txgbe_dev_set_link_down,
5251         .dev_close                  = txgbe_dev_close,
5252         .dev_reset                  = txgbe_dev_reset,
5253         .promiscuous_enable         = txgbe_dev_promiscuous_enable,
5254         .promiscuous_disable        = txgbe_dev_promiscuous_disable,
5255         .allmulticast_enable        = txgbe_dev_allmulticast_enable,
5256         .allmulticast_disable       = txgbe_dev_allmulticast_disable,
5257         .link_update                = txgbe_dev_link_update,
5258         .stats_get                  = txgbe_dev_stats_get,
5259         .xstats_get                 = txgbe_dev_xstats_get,
5260         .xstats_get_by_id           = txgbe_dev_xstats_get_by_id,
5261         .stats_reset                = txgbe_dev_stats_reset,
5262         .xstats_reset               = txgbe_dev_xstats_reset,
5263         .xstats_get_names           = txgbe_dev_xstats_get_names,
5264         .xstats_get_names_by_id     = txgbe_dev_xstats_get_names_by_id,
5265         .queue_stats_mapping_set    = txgbe_dev_queue_stats_mapping_set,
5266         .fw_version_get             = txgbe_fw_version_get,
5267         .dev_supported_ptypes_get   = txgbe_dev_supported_ptypes_get,
5268         .mtu_set                    = txgbe_dev_mtu_set,
5269         .vlan_filter_set            = txgbe_vlan_filter_set,
5270         .vlan_tpid_set              = txgbe_vlan_tpid_set,
5271         .vlan_offload_set           = txgbe_vlan_offload_set,
5272         .vlan_strip_queue_set       = txgbe_vlan_strip_queue_set,
5273         .rx_queue_start             = txgbe_dev_rx_queue_start,
5274         .rx_queue_stop              = txgbe_dev_rx_queue_stop,
5275         .tx_queue_start             = txgbe_dev_tx_queue_start,
5276         .tx_queue_stop              = txgbe_dev_tx_queue_stop,
5277         .rx_queue_setup             = txgbe_dev_rx_queue_setup,
5278         .rx_queue_intr_enable       = txgbe_dev_rx_queue_intr_enable,
5279         .rx_queue_intr_disable      = txgbe_dev_rx_queue_intr_disable,
5280         .rx_queue_release           = txgbe_dev_rx_queue_release,
5281         .tx_queue_setup             = txgbe_dev_tx_queue_setup,
5282         .tx_queue_release           = txgbe_dev_tx_queue_release,
5283         .dev_led_on                 = txgbe_dev_led_on,
5284         .dev_led_off                = txgbe_dev_led_off,
5285         .flow_ctrl_get              = txgbe_flow_ctrl_get,
5286         .flow_ctrl_set              = txgbe_flow_ctrl_set,
5287         .priority_flow_ctrl_set     = txgbe_priority_flow_ctrl_set,
5288         .mac_addr_add               = txgbe_add_rar,
5289         .mac_addr_remove            = txgbe_remove_rar,
5290         .mac_addr_set               = txgbe_set_default_mac_addr,
5291         .uc_hash_table_set          = txgbe_uc_hash_table_set,
5292         .uc_all_hash_table_set      = txgbe_uc_all_hash_table_set,
5293         .set_queue_rate_limit       = txgbe_set_queue_rate_limit,
5294         .reta_update                = txgbe_dev_rss_reta_update,
5295         .reta_query                 = txgbe_dev_rss_reta_query,
5296         .rss_hash_update            = txgbe_dev_rss_hash_update,
5297         .rss_hash_conf_get          = txgbe_dev_rss_hash_conf_get,
5298         .flow_ops_get               = txgbe_dev_flow_ops_get,
5299         .set_mc_addr_list           = txgbe_dev_set_mc_addr_list,
5300         .rxq_info_get               = txgbe_rxq_info_get,
5301         .txq_info_get               = txgbe_txq_info_get,
5302         .timesync_enable            = txgbe_timesync_enable,
5303         .timesync_disable           = txgbe_timesync_disable,
5304         .timesync_read_rx_timestamp = txgbe_timesync_read_rx_timestamp,
5305         .timesync_read_tx_timestamp = txgbe_timesync_read_tx_timestamp,
5306         .get_reg                    = txgbe_get_regs,
5307         .get_eeprom_length          = txgbe_get_eeprom_length,
5308         .get_eeprom                 = txgbe_get_eeprom,
5309         .set_eeprom                 = txgbe_set_eeprom,
5310         .get_module_info            = txgbe_get_module_info,
5311         .get_module_eeprom          = txgbe_get_module_eeprom,
5312         .get_dcb_info               = txgbe_dev_get_dcb_info,
5313         .timesync_adjust_time       = txgbe_timesync_adjust_time,
5314         .timesync_read_time         = txgbe_timesync_read_time,
5315         .timesync_write_time        = txgbe_timesync_write_time,
5316         .udp_tunnel_port_add        = txgbe_dev_udp_tunnel_port_add,
5317         .udp_tunnel_port_del        = txgbe_dev_udp_tunnel_port_del,
5318         .tm_ops_get                 = txgbe_tm_ops_get,
5319         .tx_done_cleanup            = txgbe_dev_tx_done_cleanup,
5320 };
5321
5322 RTE_PMD_REGISTER_PCI(net_txgbe, rte_txgbe_pmd);
5323 RTE_PMD_REGISTER_PCI_TABLE(net_txgbe, pci_id_txgbe_map);
5324 RTE_PMD_REGISTER_KMOD_DEP(net_txgbe, "* igb_uio | uio_pci_generic | vfio-pci");
5325 RTE_PMD_REGISTER_PARAM_STRING(net_txgbe,
5326                               TXGBE_DEVARG_BP_AUTO "=<0|1>"
5327                               TXGBE_DEVARG_KR_POLL "=<0|1>"
5328                               TXGBE_DEVARG_KR_PRESENT "=<0|1>"
5329                               TXGBE_DEVARG_KX_SGMII "=<0|1>"
5330                               TXGBE_DEVARG_FFE_SET "=<0-4>"
5331                               TXGBE_DEVARG_FFE_MAIN "=<uint16>"
5332                               TXGBE_DEVARG_FFE_PRE "=<uint16>"
5333                               TXGBE_DEVARG_FFE_POST "=<uint16>");
5334
5335 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_init, init, NOTICE);
5336 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_driver, driver, NOTICE);
5337 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_bp, bp, NOTICE);
5338
5339 #ifdef RTE_LIBRTE_TXGBE_DEBUG_RX
5340         RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_rx, rx, DEBUG);
5341 #endif
5342 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX
5343         RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_tx, tx, DEBUG);
5344 #endif
5345
5346 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX_FREE
5347         RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_tx_free, tx_free, DEBUG);
5348 #endif