1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
9 #include <rte_common.h>
10 #include <ethdev_pci.h>
12 #include <rte_interrupts.h>
14 #include <rte_debug.h>
16 #include <rte_memory.h>
18 #include <rte_alarm.h>
19 #include <rte_kvargs.h>
21 #include "txgbe_logs.h"
22 #include "base/txgbe.h"
23 #include "txgbe_ethdev.h"
24 #include "txgbe_rxtx.h"
25 #include "txgbe_regs_group.h"
27 static const struct reg_info txgbe_regs_general[] = {
28 {TXGBE_RST, 1, 1, "TXGBE_RST"},
29 {TXGBE_STAT, 1, 1, "TXGBE_STAT"},
30 {TXGBE_PORTCTL, 1, 1, "TXGBE_PORTCTL"},
31 {TXGBE_SDP, 1, 1, "TXGBE_SDP"},
32 {TXGBE_SDPCTL, 1, 1, "TXGBE_SDPCTL"},
33 {TXGBE_LEDCTL, 1, 1, "TXGBE_LEDCTL"},
37 static const struct reg_info txgbe_regs_nvm[] = {
41 static const struct reg_info txgbe_regs_interrupt[] = {
45 static const struct reg_info txgbe_regs_fctl_others[] = {
49 static const struct reg_info txgbe_regs_rxdma[] = {
53 static const struct reg_info txgbe_regs_rx[] = {
57 static struct reg_info txgbe_regs_tx[] = {
61 static const struct reg_info txgbe_regs_wakeup[] = {
65 static const struct reg_info txgbe_regs_dcb[] = {
69 static const struct reg_info txgbe_regs_mac[] = {
73 static const struct reg_info txgbe_regs_diagnostic[] = {
78 static const struct reg_info *txgbe_regs_others[] = {
82 txgbe_regs_fctl_others,
89 txgbe_regs_diagnostic,
92 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
93 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
94 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
95 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
96 static int txgbe_dev_set_link_up(struct rte_eth_dev *dev);
97 static int txgbe_dev_set_link_down(struct rte_eth_dev *dev);
98 static int txgbe_dev_close(struct rte_eth_dev *dev);
99 static int txgbe_dev_link_update(struct rte_eth_dev *dev,
100 int wait_to_complete);
101 static int txgbe_dev_stats_reset(struct rte_eth_dev *dev);
102 static void txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
103 static void txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev,
106 static void txgbe_dev_link_status_print(struct rte_eth_dev *dev);
107 static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
108 static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
109 static int txgbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev);
110 static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
111 static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
112 static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
113 struct rte_intr_handle *handle);
114 static void txgbe_dev_interrupt_handler(void *param);
115 static void txgbe_dev_interrupt_delayed_handler(void *param);
116 static void txgbe_configure_msix(struct rte_eth_dev *dev);
118 static int txgbe_filter_restore(struct rte_eth_dev *dev);
119 static void txgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
121 #define TXGBE_SET_HWSTRIP(h, q) do {\
122 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
123 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
124 (h)->bitmap[idx] |= 1 << bit;\
127 #define TXGBE_CLEAR_HWSTRIP(h, q) do {\
128 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
129 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
130 (h)->bitmap[idx] &= ~(1 << bit);\
133 #define TXGBE_GET_HWSTRIP(h, q, r) do {\
134 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
135 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
136 (r) = (h)->bitmap[idx] >> bit & 1;\
140 * The set of PCI devices this driver supports
142 static const struct rte_pci_id pci_id_txgbe_map[] = {
143 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_SP1000) },
144 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820) },
145 { .vendor_id = 0, /* sentinel */ },
148 static const struct rte_eth_desc_lim rx_desc_lim = {
149 .nb_max = TXGBE_RING_DESC_MAX,
150 .nb_min = TXGBE_RING_DESC_MIN,
151 .nb_align = TXGBE_RXD_ALIGN,
154 static const struct rte_eth_desc_lim tx_desc_lim = {
155 .nb_max = TXGBE_RING_DESC_MAX,
156 .nb_min = TXGBE_RING_DESC_MIN,
157 .nb_align = TXGBE_TXD_ALIGN,
158 .nb_seg_max = TXGBE_TX_MAX_SEG,
159 .nb_mtu_seg_max = TXGBE_TX_MAX_SEG,
162 static const struct eth_dev_ops txgbe_eth_dev_ops;
164 #define HW_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, m)}
165 #define HW_XSTAT_NAME(m, n) {n, offsetof(struct txgbe_hw_stats, m)}
166 static const struct rte_txgbe_xstats_name_off rte_txgbe_stats_strings[] = {
168 HW_XSTAT(mng_bmc2host_packets),
169 HW_XSTAT(mng_host2bmc_packets),
171 HW_XSTAT(rx_packets),
172 HW_XSTAT(tx_packets),
175 HW_XSTAT(rx_total_bytes),
176 HW_XSTAT(rx_total_packets),
177 HW_XSTAT(tx_total_packets),
178 HW_XSTAT(rx_total_missed_packets),
179 HW_XSTAT(rx_broadcast_packets),
180 HW_XSTAT(rx_multicast_packets),
181 HW_XSTAT(rx_management_packets),
182 HW_XSTAT(tx_management_packets),
183 HW_XSTAT(rx_management_dropped),
186 HW_XSTAT(rx_crc_errors),
187 HW_XSTAT(rx_illegal_byte_errors),
188 HW_XSTAT(rx_error_bytes),
189 HW_XSTAT(rx_mac_short_packet_dropped),
190 HW_XSTAT(rx_length_errors),
191 HW_XSTAT(rx_undersize_errors),
192 HW_XSTAT(rx_fragment_errors),
193 HW_XSTAT(rx_oversize_errors),
194 HW_XSTAT(rx_jabber_errors),
195 HW_XSTAT(rx_l3_l4_xsum_error),
196 HW_XSTAT(mac_local_errors),
197 HW_XSTAT(mac_remote_errors),
200 HW_XSTAT(flow_director_added_filters),
201 HW_XSTAT(flow_director_removed_filters),
202 HW_XSTAT(flow_director_filter_add_errors),
203 HW_XSTAT(flow_director_filter_remove_errors),
204 HW_XSTAT(flow_director_matched_filters),
205 HW_XSTAT(flow_director_missed_filters),
208 HW_XSTAT(rx_fcoe_crc_errors),
209 HW_XSTAT(rx_fcoe_mbuf_allocation_errors),
210 HW_XSTAT(rx_fcoe_dropped),
211 HW_XSTAT(rx_fcoe_packets),
212 HW_XSTAT(tx_fcoe_packets),
213 HW_XSTAT(rx_fcoe_bytes),
214 HW_XSTAT(tx_fcoe_bytes),
215 HW_XSTAT(rx_fcoe_no_ddp),
216 HW_XSTAT(rx_fcoe_no_ddp_ext_buff),
219 HW_XSTAT(tx_macsec_pkts_untagged),
220 HW_XSTAT(tx_macsec_pkts_encrypted),
221 HW_XSTAT(tx_macsec_pkts_protected),
222 HW_XSTAT(tx_macsec_octets_encrypted),
223 HW_XSTAT(tx_macsec_octets_protected),
224 HW_XSTAT(rx_macsec_pkts_untagged),
225 HW_XSTAT(rx_macsec_pkts_badtag),
226 HW_XSTAT(rx_macsec_pkts_nosci),
227 HW_XSTAT(rx_macsec_pkts_unknownsci),
228 HW_XSTAT(rx_macsec_octets_decrypted),
229 HW_XSTAT(rx_macsec_octets_validated),
230 HW_XSTAT(rx_macsec_sc_pkts_unchecked),
231 HW_XSTAT(rx_macsec_sc_pkts_delayed),
232 HW_XSTAT(rx_macsec_sc_pkts_late),
233 HW_XSTAT(rx_macsec_sa_pkts_ok),
234 HW_XSTAT(rx_macsec_sa_pkts_invalid),
235 HW_XSTAT(rx_macsec_sa_pkts_notvalid),
236 HW_XSTAT(rx_macsec_sa_pkts_unusedsa),
237 HW_XSTAT(rx_macsec_sa_pkts_notusingsa),
240 HW_XSTAT(rx_size_64_packets),
241 HW_XSTAT(rx_size_65_to_127_packets),
242 HW_XSTAT(rx_size_128_to_255_packets),
243 HW_XSTAT(rx_size_256_to_511_packets),
244 HW_XSTAT(rx_size_512_to_1023_packets),
245 HW_XSTAT(rx_size_1024_to_max_packets),
246 HW_XSTAT(tx_size_64_packets),
247 HW_XSTAT(tx_size_65_to_127_packets),
248 HW_XSTAT(tx_size_128_to_255_packets),
249 HW_XSTAT(tx_size_256_to_511_packets),
250 HW_XSTAT(tx_size_512_to_1023_packets),
251 HW_XSTAT(tx_size_1024_to_max_packets),
254 HW_XSTAT(tx_xon_packets),
255 HW_XSTAT(rx_xon_packets),
256 HW_XSTAT(tx_xoff_packets),
257 HW_XSTAT(rx_xoff_packets),
259 HW_XSTAT_NAME(tx_xon_packets, "tx_flow_control_xon_packets"),
260 HW_XSTAT_NAME(rx_xon_packets, "rx_flow_control_xon_packets"),
261 HW_XSTAT_NAME(tx_xoff_packets, "tx_flow_control_xoff_packets"),
262 HW_XSTAT_NAME(rx_xoff_packets, "rx_flow_control_xoff_packets"),
265 #define TXGBE_NB_HW_STATS (sizeof(rte_txgbe_stats_strings) / \
266 sizeof(rte_txgbe_stats_strings[0]))
268 /* Per-priority statistics */
269 #define UP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, up[0].m)}
270 static const struct rte_txgbe_xstats_name_off rte_txgbe_up_strings[] = {
271 UP_XSTAT(rx_up_packets),
272 UP_XSTAT(tx_up_packets),
273 UP_XSTAT(rx_up_bytes),
274 UP_XSTAT(tx_up_bytes),
275 UP_XSTAT(rx_up_drop_packets),
277 UP_XSTAT(tx_up_xon_packets),
278 UP_XSTAT(rx_up_xon_packets),
279 UP_XSTAT(tx_up_xoff_packets),
280 UP_XSTAT(rx_up_xoff_packets),
281 UP_XSTAT(rx_up_dropped),
282 UP_XSTAT(rx_up_mbuf_alloc_errors),
283 UP_XSTAT(tx_up_xon2off_packets),
286 #define TXGBE_NB_UP_STATS (sizeof(rte_txgbe_up_strings) / \
287 sizeof(rte_txgbe_up_strings[0]))
289 /* Per-queue statistics */
290 #define QP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, qp[0].m)}
291 static const struct rte_txgbe_xstats_name_off rte_txgbe_qp_strings[] = {
292 QP_XSTAT(rx_qp_packets),
293 QP_XSTAT(tx_qp_packets),
294 QP_XSTAT(rx_qp_bytes),
295 QP_XSTAT(tx_qp_bytes),
296 QP_XSTAT(rx_qp_mc_packets),
299 #define TXGBE_NB_QP_STATS (sizeof(rte_txgbe_qp_strings) / \
300 sizeof(rte_txgbe_qp_strings[0]))
303 txgbe_is_sfp(struct txgbe_hw *hw)
305 switch (hw->phy.type) {
306 case txgbe_phy_sfp_avago:
307 case txgbe_phy_sfp_ftl:
308 case txgbe_phy_sfp_intel:
309 case txgbe_phy_sfp_unknown:
310 case txgbe_phy_sfp_tyco_passive:
311 case txgbe_phy_sfp_unknown_passive:
318 static inline int32_t
319 txgbe_pf_reset_hw(struct txgbe_hw *hw)
324 status = hw->mac.reset_hw(hw);
326 ctrl_ext = rd32(hw, TXGBE_PORTCTL);
327 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
328 ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
329 wr32(hw, TXGBE_PORTCTL, ctrl_ext);
332 if (status == TXGBE_ERR_SFP_NOT_PRESENT)
338 txgbe_enable_intr(struct rte_eth_dev *dev)
340 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
341 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
343 wr32(hw, TXGBE_IENMISC, intr->mask_misc);
344 wr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK);
345 wr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK);
350 txgbe_disable_intr(struct txgbe_hw *hw)
352 PMD_INIT_FUNC_TRACE();
354 wr32(hw, TXGBE_IENMISC, ~BIT_MASK32);
355 wr32(hw, TXGBE_IMS(0), TXGBE_IMC_MASK);
356 wr32(hw, TXGBE_IMS(1), TXGBE_IMC_MASK);
361 txgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
366 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
367 struct txgbe_stat_mappings *stat_mappings =
368 TXGBE_DEV_STAT_MAPPINGS(eth_dev);
369 uint32_t qsmr_mask = 0;
370 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
374 if (hw->mac.type != txgbe_mac_raptor)
377 if (stat_idx & !QMAP_FIELD_RESERVED_BITS_MASK)
380 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
381 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
384 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
385 if (n >= TXGBE_NB_STAT_MAPPING) {
386 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
389 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
391 /* Now clear any previous stat_idx set */
392 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
394 stat_mappings->tqsm[n] &= ~clearing_mask;
396 stat_mappings->rqsm[n] &= ~clearing_mask;
398 q_map = (uint32_t)stat_idx;
399 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
400 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
402 stat_mappings->tqsm[n] |= qsmr_mask;
404 stat_mappings->rqsm[n] |= qsmr_mask;
406 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
407 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
409 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
410 is_rx ? stat_mappings->rqsm[n] : stat_mappings->tqsm[n]);
415 txgbe_dcb_init(struct txgbe_hw *hw, struct txgbe_dcb_config *dcb_config)
419 struct txgbe_dcb_tc_config *tc;
421 UNREFERENCED_PARAMETER(hw);
423 dcb_config->num_tcs.pg_tcs = TXGBE_DCB_TC_MAX;
424 dcb_config->num_tcs.pfc_tcs = TXGBE_DCB_TC_MAX;
425 bwgp = (u8)(100 / TXGBE_DCB_TC_MAX);
426 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
427 tc = &dcb_config->tc_config[i];
428 tc->path[TXGBE_DCB_TX_CONFIG].bwg_id = i;
429 tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent = bwgp + (i & 1);
430 tc->path[TXGBE_DCB_RX_CONFIG].bwg_id = i;
431 tc->path[TXGBE_DCB_RX_CONFIG].bwg_percent = bwgp + (i & 1);
432 tc->pfc = txgbe_dcb_pfc_disabled;
435 /* Initialize default user to priority mapping, UPx->TC0 */
436 tc = &dcb_config->tc_config[0];
437 tc->path[TXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
438 tc->path[TXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
439 for (i = 0; i < TXGBE_DCB_BWG_MAX; i++) {
440 dcb_config->bw_percentage[i][TXGBE_DCB_TX_CONFIG] = 100;
441 dcb_config->bw_percentage[i][TXGBE_DCB_RX_CONFIG] = 100;
443 dcb_config->rx_pba_cfg = txgbe_dcb_pba_equal;
444 dcb_config->pfc_mode_enable = false;
445 dcb_config->vt_mode = true;
446 dcb_config->round_robin_enable = false;
447 /* support all DCB capabilities */
448 dcb_config->support.capabilities = 0xFF;
452 * Ensure that all locks are released before first NVM or PHY access
455 txgbe_swfw_lock_reset(struct txgbe_hw *hw)
460 * These ones are more tricky since they are common to all ports; but
461 * swfw_sync retries last long enough (1s) to be almost sure that if
462 * lock can not be taken it is due to an improper lock of the
465 mask = TXGBE_MNGSEM_SWPHY |
467 TXGBE_MNGSEM_SWFLASH;
468 if (hw->mac.acquire_swfw_sync(hw, mask) < 0)
469 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
471 hw->mac.release_swfw_sync(hw, mask);
475 txgbe_handle_devarg(__rte_unused const char *key, const char *value,
478 uint16_t *n = extra_args;
480 if (value == NULL || extra_args == NULL)
483 *n = (uint16_t)strtoul(value, NULL, 10);
484 if (*n == USHRT_MAX && errno == ERANGE)
491 txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs)
493 struct rte_kvargs *kvlist;
506 kvlist = rte_kvargs_parse(devargs->args, txgbe_valid_arguments);
510 rte_kvargs_process(kvlist, TXGBE_DEVARG_BP_AUTO,
511 &txgbe_handle_devarg, &auto_neg);
512 rte_kvargs_process(kvlist, TXGBE_DEVARG_KR_POLL,
513 &txgbe_handle_devarg, &poll);
514 rte_kvargs_process(kvlist, TXGBE_DEVARG_KR_PRESENT,
515 &txgbe_handle_devarg, &present);
516 rte_kvargs_process(kvlist, TXGBE_DEVARG_KX_SGMII,
517 &txgbe_handle_devarg, &sgmii);
518 rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_SET,
519 &txgbe_handle_devarg, &ffe_set);
520 rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_MAIN,
521 &txgbe_handle_devarg, &ffe_main);
522 rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_PRE,
523 &txgbe_handle_devarg, &ffe_pre);
524 rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_POST,
525 &txgbe_handle_devarg, &ffe_post);
526 rte_kvargs_free(kvlist);
529 hw->devarg.auto_neg = auto_neg;
530 hw->devarg.poll = poll;
531 hw->devarg.present = present;
532 hw->devarg.sgmii = sgmii;
533 hw->phy.ffe_set = ffe_set;
534 hw->phy.ffe_main = ffe_main;
535 hw->phy.ffe_pre = ffe_pre;
536 hw->phy.ffe_post = ffe_post;
540 eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
542 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
543 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
544 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(eth_dev);
545 struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(eth_dev);
546 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(eth_dev);
547 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
548 struct txgbe_bw_conf *bw_conf = TXGBE_DEV_BW_CONF(eth_dev);
549 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
550 const struct rte_memzone *mz;
555 PMD_INIT_FUNC_TRACE();
557 eth_dev->dev_ops = &txgbe_eth_dev_ops;
558 eth_dev->rx_queue_count = txgbe_dev_rx_queue_count;
559 eth_dev->rx_descriptor_status = txgbe_dev_rx_descriptor_status;
560 eth_dev->tx_descriptor_status = txgbe_dev_tx_descriptor_status;
561 eth_dev->rx_pkt_burst = &txgbe_recv_pkts;
562 eth_dev->tx_pkt_burst = &txgbe_xmit_pkts;
563 eth_dev->tx_pkt_prepare = &txgbe_prep_pkts;
566 * For secondary processes, we don't initialise any further as primary
567 * has already done this work. Only check we don't need a different
568 * RX and TX function.
570 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
571 struct txgbe_tx_queue *txq;
572 /* TX queue function in primary, set by last queue initialized
573 * Tx queue may not initialized by primary process
575 if (eth_dev->data->tx_queues) {
576 uint16_t nb_tx_queues = eth_dev->data->nb_tx_queues;
577 txq = eth_dev->data->tx_queues[nb_tx_queues - 1];
578 txgbe_set_tx_function(eth_dev, txq);
580 /* Use default TX function if we get here */
581 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
582 "Using default TX function.");
585 txgbe_set_rx_function(eth_dev);
590 rte_eth_copy_pci_info(eth_dev, pci_dev);
592 /* Vendor and Device ID need to be set before init of shared code */
593 hw->device_id = pci_dev->id.device_id;
594 hw->vendor_id = pci_dev->id.vendor_id;
595 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
596 hw->allow_unsupported_sfp = 1;
598 /* Reserve memory for interrupt status block */
599 mz = rte_eth_dma_zone_reserve(eth_dev, "txgbe_driver", -1,
600 16, TXGBE_ALIGN, SOCKET_ID_ANY);
604 hw->isb_dma = TMZ_PADDR(mz);
605 hw->isb_mem = TMZ_VADDR(mz);
607 txgbe_parse_devargs(hw, pci_dev->device.devargs);
608 /* Initialize the shared code (base driver) */
609 err = txgbe_init_shared_code(hw);
611 PMD_INIT_LOG(ERR, "Shared code init failed: %d", err);
615 /* Unlock any pending hardware semaphore */
616 txgbe_swfw_lock_reset(hw);
618 #ifdef RTE_LIB_SECURITY
619 /* Initialize security_ctx only for primary process*/
620 if (txgbe_ipsec_ctx_create(eth_dev))
624 /* Initialize DCB configuration*/
625 memset(dcb_config, 0, sizeof(struct txgbe_dcb_config));
626 txgbe_dcb_init(hw, dcb_config);
628 /* Get Hardware Flow Control setting */
629 hw->fc.requested_mode = txgbe_fc_full;
630 hw->fc.current_mode = txgbe_fc_full;
631 hw->fc.pause_time = TXGBE_FC_PAUSE_TIME;
632 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
633 hw->fc.low_water[i] = TXGBE_FC_XON_LOTH;
634 hw->fc.high_water[i] = TXGBE_FC_XOFF_HITH;
638 err = hw->rom.init_params(hw);
640 PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err);
644 /* Make sure we have a good EEPROM before we read from it */
645 err = hw->rom.validate_checksum(hw, &csum);
647 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", err);
651 err = hw->mac.init_hw(hw);
654 * Devices with copper phys will fail to initialise if txgbe_init_hw()
655 * is called too soon after the kernel driver unbinding/binding occurs.
656 * The failure occurs in txgbe_identify_phy() for all devices,
657 * but for non-copper devies, txgbe_identify_sfp_module() is
658 * also called. See txgbe_identify_phy(). The reason for the
659 * failure is not known, and only occuts when virtualisation features
660 * are disabled in the bios. A delay of 200ms was found to be enough by
661 * trial-and-error, and is doubled to be safe.
663 if (err && hw->phy.media_type == txgbe_media_type_copper) {
665 err = hw->mac.init_hw(hw);
668 if (err == TXGBE_ERR_SFP_NOT_PRESENT)
671 if (err == TXGBE_ERR_EEPROM_VERSION) {
672 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
673 "LOM. Please be aware there may be issues associated "
674 "with your hardware.");
675 PMD_INIT_LOG(ERR, "If you are experiencing problems "
676 "please contact your hardware representative "
677 "who provided you with this hardware.");
678 } else if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) {
679 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
682 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err);
686 /* Reset the hw statistics */
687 txgbe_dev_stats_reset(eth_dev);
689 /* disable interrupt */
690 txgbe_disable_intr(hw);
692 /* Allocate memory for storing MAC addresses */
693 eth_dev->data->mac_addrs = rte_zmalloc("txgbe", RTE_ETHER_ADDR_LEN *
694 hw->mac.num_rar_entries, 0);
695 if (eth_dev->data->mac_addrs == NULL) {
697 "Failed to allocate %u bytes needed to store "
699 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
703 /* Copy the permanent MAC address */
704 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
705 ð_dev->data->mac_addrs[0]);
707 /* Allocate memory for storing hash filter MAC addresses */
708 eth_dev->data->hash_mac_addrs = rte_zmalloc("txgbe",
709 RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC, 0);
710 if (eth_dev->data->hash_mac_addrs == NULL) {
712 "Failed to allocate %d bytes needed to store MAC addresses",
713 RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC);
717 /* initialize the vfta */
718 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
720 /* initialize the hw strip bitmap*/
721 memset(hwstrip, 0, sizeof(*hwstrip));
723 /* initialize PF if max_vfs not zero */
724 ret = txgbe_pf_host_init(eth_dev);
726 rte_free(eth_dev->data->mac_addrs);
727 eth_dev->data->mac_addrs = NULL;
728 rte_free(eth_dev->data->hash_mac_addrs);
729 eth_dev->data->hash_mac_addrs = NULL;
733 ctrl_ext = rd32(hw, TXGBE_PORTCTL);
734 /* let hardware know driver is loaded */
735 ctrl_ext |= TXGBE_PORTCTL_DRVLOAD;
736 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
737 ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
738 wr32(hw, TXGBE_PORTCTL, ctrl_ext);
741 if (txgbe_is_sfp(hw) && hw->phy.sfp_type != txgbe_sfp_type_not_present)
742 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
743 (int)hw->mac.type, (int)hw->phy.type,
744 (int)hw->phy.sfp_type);
746 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
747 (int)hw->mac.type, (int)hw->phy.type);
749 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
750 eth_dev->data->port_id, pci_dev->id.vendor_id,
751 pci_dev->id.device_id);
753 rte_intr_callback_register(intr_handle,
754 txgbe_dev_interrupt_handler, eth_dev);
756 /* enable uio/vfio intr/eventfd mapping */
757 rte_intr_enable(intr_handle);
759 /* enable support intr */
760 txgbe_enable_intr(eth_dev);
762 /* initialize filter info */
763 memset(filter_info, 0,
764 sizeof(struct txgbe_filter_info));
766 /* initialize 5tuple filter list */
767 TAILQ_INIT(&filter_info->fivetuple_list);
769 /* initialize flow director filter list & hash */
770 txgbe_fdir_filter_init(eth_dev);
772 /* initialize l2 tunnel filter list & hash */
773 txgbe_l2_tn_filter_init(eth_dev);
775 /* initialize flow filter lists */
776 txgbe_filterlist_init();
778 /* initialize bandwidth configuration info */
779 memset(bw_conf, 0, sizeof(struct txgbe_bw_conf));
781 /* initialize Traffic Manager configuration */
782 txgbe_tm_conf_init(eth_dev);
788 eth_txgbe_dev_uninit(struct rte_eth_dev *eth_dev)
790 PMD_INIT_FUNC_TRACE();
792 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
795 txgbe_dev_close(eth_dev);
800 static int txgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
802 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
803 struct txgbe_5tuple_filter *p_5tuple;
805 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
806 TAILQ_REMOVE(&filter_info->fivetuple_list,
811 memset(filter_info->fivetuple_mask, 0,
812 sizeof(uint32_t) * TXGBE_5TUPLE_ARRAY_SIZE);
817 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
819 struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev);
820 struct txgbe_fdir_filter *fdir_filter;
822 if (fdir_info->hash_map)
823 rte_free(fdir_info->hash_map);
824 if (fdir_info->hash_handle)
825 rte_hash_free(fdir_info->hash_handle);
827 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
828 TAILQ_REMOVE(&fdir_info->fdir_list,
831 rte_free(fdir_filter);
837 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
839 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev);
840 struct txgbe_l2_tn_filter *l2_tn_filter;
842 if (l2_tn_info->hash_map)
843 rte_free(l2_tn_info->hash_map);
844 if (l2_tn_info->hash_handle)
845 rte_hash_free(l2_tn_info->hash_handle);
847 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
848 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
851 rte_free(l2_tn_filter);
857 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
859 struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev);
860 char fdir_hash_name[RTE_HASH_NAMESIZE];
861 struct rte_hash_parameters fdir_hash_params = {
862 .name = fdir_hash_name,
863 .entries = TXGBE_MAX_FDIR_FILTER_NUM,
864 .key_len = sizeof(struct txgbe_atr_input),
865 .hash_func = rte_hash_crc,
866 .hash_func_init_val = 0,
867 .socket_id = rte_socket_id(),
870 TAILQ_INIT(&fdir_info->fdir_list);
871 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
872 "fdir_%s", TDEV_NAME(eth_dev));
873 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
874 if (!fdir_info->hash_handle) {
875 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
878 fdir_info->hash_map = rte_zmalloc("txgbe",
879 sizeof(struct txgbe_fdir_filter *) *
880 TXGBE_MAX_FDIR_FILTER_NUM,
882 if (!fdir_info->hash_map) {
884 "Failed to allocate memory for fdir hash map!");
887 fdir_info->mask_added = FALSE;
892 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
894 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev);
895 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
896 struct rte_hash_parameters l2_tn_hash_params = {
897 .name = l2_tn_hash_name,
898 .entries = TXGBE_MAX_L2_TN_FILTER_NUM,
899 .key_len = sizeof(struct txgbe_l2_tn_key),
900 .hash_func = rte_hash_crc,
901 .hash_func_init_val = 0,
902 .socket_id = rte_socket_id(),
905 TAILQ_INIT(&l2_tn_info->l2_tn_list);
906 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
907 "l2_tn_%s", TDEV_NAME(eth_dev));
908 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
909 if (!l2_tn_info->hash_handle) {
910 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
913 l2_tn_info->hash_map = rte_zmalloc("txgbe",
914 sizeof(struct txgbe_l2_tn_filter *) *
915 TXGBE_MAX_L2_TN_FILTER_NUM,
917 if (!l2_tn_info->hash_map) {
919 "Failed to allocate memory for L2 TN hash map!");
922 l2_tn_info->e_tag_en = FALSE;
923 l2_tn_info->e_tag_fwd_en = FALSE;
924 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
930 eth_txgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
931 struct rte_pci_device *pci_dev)
933 struct rte_eth_dev *pf_ethdev;
934 struct rte_eth_devargs eth_da;
937 if (pci_dev->device.devargs) {
938 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
943 memset(ð_da, 0, sizeof(eth_da));
946 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
947 sizeof(struct txgbe_adapter),
948 eth_dev_pci_specific_init, pci_dev,
949 eth_txgbe_dev_init, NULL);
951 if (retval || eth_da.nb_representor_ports < 1)
953 if (eth_da.type != RTE_ETH_REPRESENTOR_VF)
956 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
957 if (pf_ethdev == NULL)
963 static int eth_txgbe_pci_remove(struct rte_pci_device *pci_dev)
965 struct rte_eth_dev *ethdev;
967 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
971 return rte_eth_dev_destroy(ethdev, eth_txgbe_dev_uninit);
974 static struct rte_pci_driver rte_txgbe_pmd = {
975 .id_table = pci_id_txgbe_map,
976 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
977 RTE_PCI_DRV_INTR_LSC,
978 .probe = eth_txgbe_pci_probe,
979 .remove = eth_txgbe_pci_remove,
983 txgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
985 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
986 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
991 vid_idx = (uint32_t)((vlan_id >> 5) & 0x7F);
992 vid_bit = (uint32_t)(1 << (vlan_id & 0x1F));
993 vfta = rd32(hw, TXGBE_VLANTBL(vid_idx));
998 wr32(hw, TXGBE_VLANTBL(vid_idx), vfta);
1000 /* update local VFTA copy */
1001 shadow_vfta->vfta[vid_idx] = vfta;
1007 txgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1009 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1010 struct txgbe_rx_queue *rxq;
1012 uint32_t rxcfg, rxbal, rxbah;
1015 txgbe_vlan_hw_strip_enable(dev, queue);
1017 txgbe_vlan_hw_strip_disable(dev, queue);
1019 rxq = dev->data->rx_queues[queue];
1020 rxbal = rd32(hw, TXGBE_RXBAL(rxq->reg_idx));
1021 rxbah = rd32(hw, TXGBE_RXBAH(rxq->reg_idx));
1022 rxcfg = rd32(hw, TXGBE_RXCFG(rxq->reg_idx));
1023 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
1024 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
1025 !(rxcfg & TXGBE_RXCFG_VLAN);
1026 rxcfg |= TXGBE_RXCFG_VLAN;
1028 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
1029 (rxcfg & TXGBE_RXCFG_VLAN);
1030 rxcfg &= ~TXGBE_RXCFG_VLAN;
1032 rxcfg &= ~TXGBE_RXCFG_ENA;
1035 /* set vlan strip for ring */
1036 txgbe_dev_rx_queue_stop(dev, queue);
1037 wr32(hw, TXGBE_RXBAL(rxq->reg_idx), rxbal);
1038 wr32(hw, TXGBE_RXBAH(rxq->reg_idx), rxbah);
1039 wr32(hw, TXGBE_RXCFG(rxq->reg_idx), rxcfg);
1040 txgbe_dev_rx_queue_start(dev, queue);
1045 txgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1046 enum rte_vlan_type vlan_type,
1049 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1051 uint32_t portctrl, vlan_ext, qinq;
1053 portctrl = rd32(hw, TXGBE_PORTCTL);
1055 vlan_ext = (portctrl & TXGBE_PORTCTL_VLANEXT);
1056 qinq = vlan_ext && (portctrl & TXGBE_PORTCTL_QINQ);
1057 switch (vlan_type) {
1058 case ETH_VLAN_TYPE_INNER:
1060 wr32m(hw, TXGBE_VLANCTL,
1061 TXGBE_VLANCTL_TPID_MASK,
1062 TXGBE_VLANCTL_TPID(tpid));
1063 wr32m(hw, TXGBE_DMATXCTRL,
1064 TXGBE_DMATXCTRL_TPID_MASK,
1065 TXGBE_DMATXCTRL_TPID(tpid));
1068 PMD_DRV_LOG(ERR, "Inner type is not supported"
1073 wr32m(hw, TXGBE_TAGTPID(0),
1074 TXGBE_TAGTPID_LSB_MASK,
1075 TXGBE_TAGTPID_LSB(tpid));
1078 case ETH_VLAN_TYPE_OUTER:
1080 /* Only the high 16-bits is valid */
1081 wr32m(hw, TXGBE_EXTAG,
1082 TXGBE_EXTAG_VLAN_MASK,
1083 TXGBE_EXTAG_VLAN(tpid));
1085 wr32m(hw, TXGBE_VLANCTL,
1086 TXGBE_VLANCTL_TPID_MASK,
1087 TXGBE_VLANCTL_TPID(tpid));
1088 wr32m(hw, TXGBE_DMATXCTRL,
1089 TXGBE_DMATXCTRL_TPID_MASK,
1090 TXGBE_DMATXCTRL_TPID(tpid));
1094 wr32m(hw, TXGBE_TAGTPID(0),
1095 TXGBE_TAGTPID_MSB_MASK,
1096 TXGBE_TAGTPID_MSB(tpid));
1100 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1108 txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1110 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1113 PMD_INIT_FUNC_TRACE();
1115 /* Filter Table Disable */
1116 vlnctrl = rd32(hw, TXGBE_VLANCTL);
1117 vlnctrl &= ~TXGBE_VLANCTL_VFE;
1118 wr32(hw, TXGBE_VLANCTL, vlnctrl);
1122 txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1124 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1125 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
1129 PMD_INIT_FUNC_TRACE();
1131 /* Filter Table Enable */
1132 vlnctrl = rd32(hw, TXGBE_VLANCTL);
1133 vlnctrl &= ~TXGBE_VLANCTL_CFIENA;
1134 vlnctrl |= TXGBE_VLANCTL_VFE;
1135 wr32(hw, TXGBE_VLANCTL, vlnctrl);
1137 /* write whatever is in local vfta copy */
1138 for (i = 0; i < TXGBE_VFTA_SIZE; i++)
1139 wr32(hw, TXGBE_VLANTBL(i), shadow_vfta->vfta[i]);
1143 txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1145 struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(dev);
1146 struct txgbe_rx_queue *rxq;
1148 if (queue >= TXGBE_MAX_RX_QUEUE_NUM)
1152 TXGBE_SET_HWSTRIP(hwstrip, queue);
1154 TXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1156 if (queue >= dev->data->nb_rx_queues)
1159 rxq = dev->data->rx_queues[queue];
1162 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1163 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1165 rxq->vlan_flags = PKT_RX_VLAN;
1166 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1171 txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1173 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1176 PMD_INIT_FUNC_TRACE();
1178 ctrl = rd32(hw, TXGBE_RXCFG(queue));
1179 ctrl &= ~TXGBE_RXCFG_VLAN;
1180 wr32(hw, TXGBE_RXCFG(queue), ctrl);
1182 /* record those setting for HW strip per queue */
1183 txgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1187 txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1189 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1192 PMD_INIT_FUNC_TRACE();
1194 ctrl = rd32(hw, TXGBE_RXCFG(queue));
1195 ctrl |= TXGBE_RXCFG_VLAN;
1196 wr32(hw, TXGBE_RXCFG(queue), ctrl);
1198 /* record those setting for HW strip per queue */
1199 txgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1203 txgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1205 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1208 PMD_INIT_FUNC_TRACE();
1210 ctrl = rd32(hw, TXGBE_PORTCTL);
1211 ctrl &= ~TXGBE_PORTCTL_VLANEXT;
1212 ctrl &= ~TXGBE_PORTCTL_QINQ;
1213 wr32(hw, TXGBE_PORTCTL, ctrl);
1217 txgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1219 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1220 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
1221 struct rte_eth_txmode *txmode = &dev->data->dev_conf.txmode;
1224 PMD_INIT_FUNC_TRACE();
1226 ctrl = rd32(hw, TXGBE_PORTCTL);
1227 ctrl |= TXGBE_PORTCTL_VLANEXT;
1228 if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP ||
1229 txmode->offloads & DEV_TX_OFFLOAD_QINQ_INSERT)
1230 ctrl |= TXGBE_PORTCTL_QINQ;
1231 wr32(hw, TXGBE_PORTCTL, ctrl);
1235 txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
1237 struct txgbe_rx_queue *rxq;
1240 PMD_INIT_FUNC_TRACE();
1242 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1243 rxq = dev->data->rx_queues[i];
1245 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1246 txgbe_vlan_strip_queue_set(dev, i, 1);
1248 txgbe_vlan_strip_queue_set(dev, i, 0);
1253 txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
1256 struct rte_eth_rxmode *rxmode;
1257 struct txgbe_rx_queue *rxq;
1259 if (mask & ETH_VLAN_STRIP_MASK) {
1260 rxmode = &dev->data->dev_conf.rxmode;
1261 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1262 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1263 rxq = dev->data->rx_queues[i];
1264 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1267 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1268 rxq = dev->data->rx_queues[i];
1269 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1275 txgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
1277 struct rte_eth_rxmode *rxmode;
1278 rxmode = &dev->data->dev_conf.rxmode;
1280 if (mask & ETH_VLAN_STRIP_MASK)
1281 txgbe_vlan_hw_strip_config(dev);
1283 if (mask & ETH_VLAN_FILTER_MASK) {
1284 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1285 txgbe_vlan_hw_filter_enable(dev);
1287 txgbe_vlan_hw_filter_disable(dev);
1290 if (mask & ETH_VLAN_EXTEND_MASK) {
1291 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1292 txgbe_vlan_hw_extend_enable(dev);
1294 txgbe_vlan_hw_extend_disable(dev);
1301 txgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1303 txgbe_config_vlan_strip_on_all_queues(dev, mask);
1305 txgbe_vlan_offload_config(dev, mask);
1311 txgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1313 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1314 /* VLNCTL: enable vlan filtering and allow all vlan tags through */
1315 uint32_t vlanctrl = rd32(hw, TXGBE_VLANCTL);
1317 vlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */
1318 wr32(hw, TXGBE_VLANCTL, vlanctrl);
1322 txgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1324 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1329 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1332 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1338 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
1339 TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1340 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
1341 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1346 txgbe_check_mq_mode(struct rte_eth_dev *dev)
1348 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1349 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1350 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1352 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1353 /* check multi-queue mode */
1354 switch (dev_conf->rxmode.mq_mode) {
1355 case ETH_MQ_RX_VMDQ_DCB:
1356 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
1358 case ETH_MQ_RX_VMDQ_DCB_RSS:
1359 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1360 PMD_INIT_LOG(ERR, "SRIOV active,"
1361 " unsupported mq_mode rx %d.",
1362 dev_conf->rxmode.mq_mode);
1365 case ETH_MQ_RX_VMDQ_RSS:
1366 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1367 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1368 if (txgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1369 PMD_INIT_LOG(ERR, "SRIOV is active,"
1370 " invalid queue number"
1371 " for VMDQ RSS, allowed"
1372 " value are 1, 2 or 4.");
1376 case ETH_MQ_RX_VMDQ_ONLY:
1377 case ETH_MQ_RX_NONE:
1378 /* if nothing mq mode configure, use default scheme */
1379 dev->data->dev_conf.rxmode.mq_mode =
1380 ETH_MQ_RX_VMDQ_ONLY;
1382 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1383 /* SRIOV only works in VMDq enable mode */
1384 PMD_INIT_LOG(ERR, "SRIOV is active,"
1385 " wrong mq_mode rx %d.",
1386 dev_conf->rxmode.mq_mode);
1390 switch (dev_conf->txmode.mq_mode) {
1391 case ETH_MQ_TX_VMDQ_DCB:
1392 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
1393 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
1395 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1396 dev->data->dev_conf.txmode.mq_mode =
1397 ETH_MQ_TX_VMDQ_ONLY;
1401 /* check valid queue number */
1402 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1403 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1404 PMD_INIT_LOG(ERR, "SRIOV is active,"
1405 " nb_rx_q=%d nb_tx_q=%d queue number"
1406 " must be less than or equal to %d.",
1408 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1412 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1413 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1417 /* check configuration for vmdb+dcb mode */
1418 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1419 const struct rte_eth_vmdq_dcb_conf *conf;
1421 if (nb_rx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1422 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1423 TXGBE_VMDQ_DCB_NB_QUEUES);
1426 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1427 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1428 conf->nb_queue_pools == ETH_32_POOLS)) {
1429 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1430 " nb_queue_pools must be %d or %d.",
1431 ETH_16_POOLS, ETH_32_POOLS);
1435 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1436 const struct rte_eth_vmdq_dcb_tx_conf *conf;
1438 if (nb_tx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1439 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1440 TXGBE_VMDQ_DCB_NB_QUEUES);
1443 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1444 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1445 conf->nb_queue_pools == ETH_32_POOLS)) {
1446 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1447 " nb_queue_pools != %d and"
1448 " nb_queue_pools != %d.",
1449 ETH_16_POOLS, ETH_32_POOLS);
1454 /* For DCB mode check our configuration before we go further */
1455 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1456 const struct rte_eth_dcb_rx_conf *conf;
1458 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1459 if (!(conf->nb_tcs == ETH_4_TCS ||
1460 conf->nb_tcs == ETH_8_TCS)) {
1461 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1462 " and nb_tcs != %d.",
1463 ETH_4_TCS, ETH_8_TCS);
1468 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1469 const struct rte_eth_dcb_tx_conf *conf;
1471 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1472 if (!(conf->nb_tcs == ETH_4_TCS ||
1473 conf->nb_tcs == ETH_8_TCS)) {
1474 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1475 " and nb_tcs != %d.",
1476 ETH_4_TCS, ETH_8_TCS);
1485 txgbe_dev_configure(struct rte_eth_dev *dev)
1487 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1488 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1491 PMD_INIT_FUNC_TRACE();
1493 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1494 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1496 /* multiple queue mode checking */
1497 ret = txgbe_check_mq_mode(dev);
1499 PMD_DRV_LOG(ERR, "txgbe_check_mq_mode fails with %d.",
1504 /* set flag to update link status after init */
1505 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
1508 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1509 * allocation Rx preconditions we will reset it.
1511 adapter->rx_bulk_alloc_allowed = true;
1517 txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
1519 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1520 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1523 gpie = rd32(hw, TXGBE_GPIOINTEN);
1524 gpie |= TXGBE_GPIOBIT_6;
1525 wr32(hw, TXGBE_GPIOINTEN, gpie);
1526 intr->mask_misc |= TXGBE_ICRMISC_GPIO;
1527 intr->mask_misc |= TXGBE_ICRMISC_ANDONE;
1531 txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
1532 uint16_t tx_rate, uint64_t q_msk)
1534 struct txgbe_hw *hw;
1535 struct txgbe_vf_info *vfinfo;
1536 struct rte_eth_link link;
1537 uint8_t nb_q_per_pool;
1538 uint32_t queue_stride;
1539 uint32_t queue_idx, idx = 0, vf_idx;
1541 uint16_t total_rate = 0;
1542 struct rte_pci_device *pci_dev;
1545 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1546 ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
1550 if (vf >= pci_dev->max_vfs)
1553 if (tx_rate > link.link_speed)
1559 hw = TXGBE_DEV_HW(dev);
1560 vfinfo = *(TXGBE_DEV_VFDATA(dev));
1561 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1562 queue_stride = TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1563 queue_idx = vf * queue_stride;
1564 queue_end = queue_idx + nb_q_per_pool - 1;
1565 if (queue_end >= hw->mac.max_tx_queues)
1569 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
1572 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
1574 total_rate += vfinfo[vf_idx].tx_rate[idx];
1580 /* Store tx_rate for this vf. */
1581 for (idx = 0; idx < nb_q_per_pool; idx++) {
1582 if (((uint64_t)0x1 << idx) & q_msk) {
1583 if (vfinfo[vf].tx_rate[idx] != tx_rate)
1584 vfinfo[vf].tx_rate[idx] = tx_rate;
1585 total_rate += tx_rate;
1589 if (total_rate > dev->data->dev_link.link_speed) {
1590 /* Reset stored TX rate of the VF if it causes exceed
1593 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
1597 /* Set ARBTXRATE of each queue/pool for vf X */
1598 for (; queue_idx <= queue_end; queue_idx++) {
1600 txgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
1608 * Configure device link speed and setup link.
1609 * It returns 0 on success.
1612 txgbe_dev_start(struct rte_eth_dev *dev)
1614 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1615 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
1616 struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1617 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1618 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1619 uint32_t intr_vector = 0;
1621 bool link_up = false, negotiate = 0;
1623 uint32_t allowed_speeds = 0;
1627 uint32_t *link_speeds;
1628 struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev);
1630 PMD_INIT_FUNC_TRACE();
1632 /* TXGBE devices don't support:
1633 * - half duplex (checked afterwards for valid speeds)
1634 * - fixed speed: TODO implement
1636 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1638 "Invalid link_speeds for port %u, fix speed not supported",
1639 dev->data->port_id);
1643 /* Stop the link setup handler before resetting the HW. */
1644 rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1646 /* disable uio/vfio intr/eventfd mapping */
1647 rte_intr_disable(intr_handle);
1650 hw->adapter_stopped = 0;
1653 /* reinitialize adapter
1654 * this calls reset and start
1656 hw->nb_rx_queues = dev->data->nb_rx_queues;
1657 hw->nb_tx_queues = dev->data->nb_tx_queues;
1658 status = txgbe_pf_reset_hw(hw);
1661 hw->mac.start_hw(hw);
1662 hw->mac.get_link_status = true;
1664 /* configure PF module if SRIOV enabled */
1665 txgbe_pf_host_configure(dev);
1667 txgbe_dev_phy_intr_setup(dev);
1669 /* check and configure queue intr-vector mapping */
1670 if ((rte_intr_cap_multiple(intr_handle) ||
1671 !RTE_ETH_DEV_SRIOV(dev).active) &&
1672 dev->data->dev_conf.intr_conf.rxq != 0) {
1673 intr_vector = dev->data->nb_rx_queues;
1674 if (rte_intr_efd_enable(intr_handle, intr_vector))
1678 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1679 intr_handle->intr_vec =
1680 rte_zmalloc("intr_vec",
1681 dev->data->nb_rx_queues * sizeof(int), 0);
1682 if (intr_handle->intr_vec == NULL) {
1683 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1684 " intr_vec", dev->data->nb_rx_queues);
1689 /* confiugre msix for sleep until rx interrupt */
1690 txgbe_configure_msix(dev);
1692 /* initialize transmission unit */
1693 txgbe_dev_tx_init(dev);
1695 /* This can fail when allocating mbufs for descriptor rings */
1696 err = txgbe_dev_rx_init(dev);
1698 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1702 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
1703 ETH_VLAN_EXTEND_MASK;
1704 err = txgbe_vlan_offload_config(dev, mask);
1706 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
1710 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1711 /* Enable vlan filtering for VMDq */
1712 txgbe_vmdq_vlan_hw_filter_enable(dev);
1715 /* Configure DCB hw */
1716 txgbe_configure_pb(dev);
1717 txgbe_configure_port(dev);
1718 txgbe_configure_dcb(dev);
1720 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1721 err = txgbe_fdir_configure(dev);
1726 /* Restore vf rate limit */
1727 if (vfinfo != NULL) {
1728 for (vf = 0; vf < pci_dev->max_vfs; vf++)
1729 for (idx = 0; idx < TXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1730 if (vfinfo[vf].tx_rate[idx] != 0)
1731 txgbe_set_vf_rate_limit(dev, vf,
1732 vfinfo[vf].tx_rate[idx],
1736 err = txgbe_dev_rxtx_start(dev);
1738 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1742 /* Skip link setup if loopback mode is enabled. */
1743 if (hw->mac.type == txgbe_mac_raptor &&
1744 dev->data->dev_conf.lpbk_mode)
1745 goto skip_link_setup;
1747 if (txgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1748 err = hw->mac.setup_sfp(hw);
1753 if (hw->phy.media_type == txgbe_media_type_copper) {
1754 /* Turn on the copper */
1755 hw->phy.set_phy_power(hw, true);
1757 /* Turn on the laser */
1758 hw->mac.enable_tx_laser(hw);
1761 if ((hw->subsystem_device_id & 0xFF) != TXGBE_DEV_ID_KR_KX_KX4)
1762 err = hw->mac.check_link(hw, &speed, &link_up, 0);
1765 dev->data->dev_link.link_status = link_up;
1767 err = hw->mac.get_link_capabilities(hw, &speed, &negotiate);
1771 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
1774 link_speeds = &dev->data->dev_conf.link_speeds;
1775 if (*link_speeds & ~allowed_speeds) {
1776 PMD_INIT_LOG(ERR, "Invalid link setting");
1781 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
1782 speed = (TXGBE_LINK_SPEED_100M_FULL |
1783 TXGBE_LINK_SPEED_1GB_FULL |
1784 TXGBE_LINK_SPEED_10GB_FULL);
1786 if (*link_speeds & ETH_LINK_SPEED_10G)
1787 speed |= TXGBE_LINK_SPEED_10GB_FULL;
1788 if (*link_speeds & ETH_LINK_SPEED_5G)
1789 speed |= TXGBE_LINK_SPEED_5GB_FULL;
1790 if (*link_speeds & ETH_LINK_SPEED_2_5G)
1791 speed |= TXGBE_LINK_SPEED_2_5GB_FULL;
1792 if (*link_speeds & ETH_LINK_SPEED_1G)
1793 speed |= TXGBE_LINK_SPEED_1GB_FULL;
1794 if (*link_speeds & ETH_LINK_SPEED_100M)
1795 speed |= TXGBE_LINK_SPEED_100M_FULL;
1798 err = hw->mac.setup_link(hw, speed, link_up);
1804 if (rte_intr_allow_others(intr_handle)) {
1805 txgbe_dev_misc_interrupt_setup(dev);
1806 /* check if lsc interrupt is enabled */
1807 if (dev->data->dev_conf.intr_conf.lsc != 0)
1808 txgbe_dev_lsc_interrupt_setup(dev, TRUE);
1810 txgbe_dev_lsc_interrupt_setup(dev, FALSE);
1811 txgbe_dev_macsec_interrupt_setup(dev);
1812 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
1814 rte_intr_callback_unregister(intr_handle,
1815 txgbe_dev_interrupt_handler, dev);
1816 if (dev->data->dev_conf.intr_conf.lsc != 0)
1817 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1818 " no intr multiplex");
1821 /* check if rxq interrupt is enabled */
1822 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1823 rte_intr_dp_is_en(intr_handle))
1824 txgbe_dev_rxq_interrupt_setup(dev);
1826 /* enable uio/vfio intr/eventfd mapping */
1827 rte_intr_enable(intr_handle);
1829 /* resume enabled intr since hw reset */
1830 txgbe_enable_intr(dev);
1831 txgbe_l2_tunnel_conf(dev);
1832 txgbe_filter_restore(dev);
1834 if (tm_conf->root && !tm_conf->committed)
1835 PMD_DRV_LOG(WARNING,
1836 "please call hierarchy_commit() "
1837 "before starting the port");
1840 * Update link status right before return, because it may
1841 * start link configuration process in a separate thread.
1843 txgbe_dev_link_update(dev, 0);
1845 wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_ORD_MASK);
1847 txgbe_read_stats_registers(hw, hw_stats);
1848 hw->offset_loaded = 1;
1853 PMD_INIT_LOG(ERR, "failure in dev start: %d", err);
1854 txgbe_dev_clear_queues(dev);
1859 * Stop device: disable rx and tx functions to allow for reconfiguring.
1862 txgbe_dev_stop(struct rte_eth_dev *dev)
1864 struct rte_eth_link link;
1865 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1866 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1867 struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1868 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1869 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1871 struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev);
1873 if (hw->adapter_stopped)
1876 PMD_INIT_FUNC_TRACE();
1878 rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1880 /* disable interrupts */
1881 txgbe_disable_intr(hw);
1884 txgbe_pf_reset_hw(hw);
1885 hw->adapter_stopped = 0;
1890 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
1891 vfinfo[vf].clear_to_send = false;
1893 if (hw->phy.media_type == txgbe_media_type_copper) {
1894 /* Turn off the copper */
1895 hw->phy.set_phy_power(hw, false);
1897 /* Turn off the laser */
1898 hw->mac.disable_tx_laser(hw);
1901 txgbe_dev_clear_queues(dev);
1903 /* Clear stored conf */
1904 dev->data->scattered_rx = 0;
1907 /* Clear recorded link status */
1908 memset(&link, 0, sizeof(link));
1909 rte_eth_linkstatus_set(dev, &link);
1911 if (!rte_intr_allow_others(intr_handle))
1912 /* resume to the default handler */
1913 rte_intr_callback_register(intr_handle,
1914 txgbe_dev_interrupt_handler,
1917 /* Clean datapath event and queue/vec mapping */
1918 rte_intr_efd_disable(intr_handle);
1919 if (intr_handle->intr_vec != NULL) {
1920 rte_free(intr_handle->intr_vec);
1921 intr_handle->intr_vec = NULL;
1924 /* reset hierarchy commit */
1925 tm_conf->committed = false;
1927 adapter->rss_reta_updated = 0;
1928 wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_SEL_MASK);
1930 hw->adapter_stopped = true;
1931 dev->data->dev_started = 0;
1937 * Set device link up: enable tx.
1940 txgbe_dev_set_link_up(struct rte_eth_dev *dev)
1942 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1944 if (hw->phy.media_type == txgbe_media_type_copper) {
1945 /* Turn on the copper */
1946 hw->phy.set_phy_power(hw, true);
1948 /* Turn on the laser */
1949 hw->mac.enable_tx_laser(hw);
1950 txgbe_dev_link_update(dev, 0);
1957 * Set device link down: disable tx.
1960 txgbe_dev_set_link_down(struct rte_eth_dev *dev)
1962 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1964 if (hw->phy.media_type == txgbe_media_type_copper) {
1965 /* Turn off the copper */
1966 hw->phy.set_phy_power(hw, false);
1968 /* Turn off the laser */
1969 hw->mac.disable_tx_laser(hw);
1970 txgbe_dev_link_update(dev, 0);
1977 * Reset and stop device.
1980 txgbe_dev_close(struct rte_eth_dev *dev)
1982 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1983 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1984 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1988 PMD_INIT_FUNC_TRACE();
1990 txgbe_pf_reset_hw(hw);
1992 ret = txgbe_dev_stop(dev);
1994 txgbe_dev_free_queues(dev);
1996 /* reprogram the RAR[0] in case user changed it. */
1997 txgbe_set_rar(hw, 0, hw->mac.addr, 0, true);
1999 /* Unlock any pending hardware semaphore */
2000 txgbe_swfw_lock_reset(hw);
2002 /* disable uio intr before callback unregister */
2003 rte_intr_disable(intr_handle);
2006 ret = rte_intr_callback_unregister(intr_handle,
2007 txgbe_dev_interrupt_handler, dev);
2008 if (ret >= 0 || ret == -ENOENT) {
2010 } else if (ret != -EAGAIN) {
2012 "intr callback unregister failed: %d",
2016 } while (retries++ < (10 + TXGBE_LINK_UP_TIME));
2018 /* cancel the delay handler before remove dev */
2019 rte_eal_alarm_cancel(txgbe_dev_interrupt_delayed_handler, dev);
2021 /* uninitialize PF if max_vfs not zero */
2022 txgbe_pf_host_uninit(dev);
2024 rte_free(dev->data->mac_addrs);
2025 dev->data->mac_addrs = NULL;
2027 rte_free(dev->data->hash_mac_addrs);
2028 dev->data->hash_mac_addrs = NULL;
2030 /* remove all the fdir filters & hash */
2031 txgbe_fdir_filter_uninit(dev);
2033 /* remove all the L2 tunnel filters & hash */
2034 txgbe_l2_tn_filter_uninit(dev);
2036 /* Remove all ntuple filters of the device */
2037 txgbe_ntuple_filter_uninit(dev);
2039 /* clear all the filters list */
2040 txgbe_filterlist_flush();
2042 /* Remove all Traffic Manager configuration */
2043 txgbe_tm_conf_uninit(dev);
2045 #ifdef RTE_LIB_SECURITY
2046 rte_free(dev->security_ctx);
2056 txgbe_dev_reset(struct rte_eth_dev *dev)
2060 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2061 * its VF to make them align with it. The detailed notification
2062 * mechanism is PMD specific. As to txgbe PF, it is rather complex.
2063 * To avoid unexpected behavior in VF, currently reset of PF with
2064 * SR-IOV activation is not supported. It might be supported later.
2066 if (dev->data->sriov.active)
2069 ret = eth_txgbe_dev_uninit(dev);
2073 ret = eth_txgbe_dev_init(dev, NULL);
2078 #define UPDATE_QP_COUNTER_32bit(reg, last_counter, counter) \
2080 uint32_t current_counter = rd32(hw, reg); \
2081 if (current_counter < last_counter) \
2082 current_counter += 0x100000000LL; \
2083 if (!hw->offset_loaded) \
2084 last_counter = current_counter; \
2085 counter = current_counter - last_counter; \
2086 counter &= 0xFFFFFFFFLL; \
2089 #define UPDATE_QP_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
2091 uint64_t current_counter_lsb = rd32(hw, reg_lsb); \
2092 uint64_t current_counter_msb = rd32(hw, reg_msb); \
2093 uint64_t current_counter = (current_counter_msb << 32) | \
2094 current_counter_lsb; \
2095 if (current_counter < last_counter) \
2096 current_counter += 0x1000000000LL; \
2097 if (!hw->offset_loaded) \
2098 last_counter = current_counter; \
2099 counter = current_counter - last_counter; \
2100 counter &= 0xFFFFFFFFFLL; \
2104 txgbe_read_stats_registers(struct txgbe_hw *hw,
2105 struct txgbe_hw_stats *hw_stats)
2110 for (i = 0; i < hw->nb_rx_queues; i++) {
2111 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXPKT(i),
2112 hw->qp_last[i].rx_qp_packets,
2113 hw_stats->qp[i].rx_qp_packets);
2114 UPDATE_QP_COUNTER_36bit(TXGBE_QPRXOCTL(i), TXGBE_QPRXOCTH(i),
2115 hw->qp_last[i].rx_qp_bytes,
2116 hw_stats->qp[i].rx_qp_bytes);
2117 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXMPKT(i),
2118 hw->qp_last[i].rx_qp_mc_packets,
2119 hw_stats->qp[i].rx_qp_mc_packets);
2122 for (i = 0; i < hw->nb_tx_queues; i++) {
2123 UPDATE_QP_COUNTER_32bit(TXGBE_QPTXPKT(i),
2124 hw->qp_last[i].tx_qp_packets,
2125 hw_stats->qp[i].tx_qp_packets);
2126 UPDATE_QP_COUNTER_36bit(TXGBE_QPTXOCTL(i), TXGBE_QPTXOCTH(i),
2127 hw->qp_last[i].tx_qp_bytes,
2128 hw_stats->qp[i].tx_qp_bytes);
2131 for (i = 0; i < TXGBE_MAX_UP; i++) {
2132 hw_stats->up[i].rx_up_xon_packets +=
2133 rd32(hw, TXGBE_PBRXUPXON(i));
2134 hw_stats->up[i].rx_up_xoff_packets +=
2135 rd32(hw, TXGBE_PBRXUPXOFF(i));
2136 hw_stats->up[i].tx_up_xon_packets +=
2137 rd32(hw, TXGBE_PBTXUPXON(i));
2138 hw_stats->up[i].tx_up_xoff_packets +=
2139 rd32(hw, TXGBE_PBTXUPXOFF(i));
2140 hw_stats->up[i].tx_up_xon2off_packets +=
2141 rd32(hw, TXGBE_PBTXUPOFF(i));
2142 hw_stats->up[i].rx_up_dropped +=
2143 rd32(hw, TXGBE_PBRXMISS(i));
2145 hw_stats->rx_xon_packets += rd32(hw, TXGBE_PBRXLNKXON);
2146 hw_stats->rx_xoff_packets += rd32(hw, TXGBE_PBRXLNKXOFF);
2147 hw_stats->tx_xon_packets += rd32(hw, TXGBE_PBTXLNKXON);
2148 hw_stats->tx_xoff_packets += rd32(hw, TXGBE_PBTXLNKXOFF);
2151 hw_stats->rx_packets += rd32(hw, TXGBE_DMARXPKT);
2152 hw_stats->tx_packets += rd32(hw, TXGBE_DMATXPKT);
2154 hw_stats->rx_bytes += rd64(hw, TXGBE_DMARXOCTL);
2155 hw_stats->tx_bytes += rd64(hw, TXGBE_DMATXOCTL);
2156 hw_stats->rx_dma_drop += rd32(hw, TXGBE_DMARXDROP);
2157 hw_stats->rx_drop_packets += rd32(hw, TXGBE_PBRXDROP);
2160 hw_stats->rx_crc_errors += rd64(hw, TXGBE_MACRXERRCRCL);
2161 hw_stats->rx_multicast_packets += rd64(hw, TXGBE_MACRXMPKTL);
2162 hw_stats->tx_multicast_packets += rd64(hw, TXGBE_MACTXMPKTL);
2164 hw_stats->rx_total_packets += rd64(hw, TXGBE_MACRXPKTL);
2165 hw_stats->tx_total_packets += rd64(hw, TXGBE_MACTXPKTL);
2166 hw_stats->rx_total_bytes += rd64(hw, TXGBE_MACRXGBOCTL);
2168 hw_stats->rx_broadcast_packets += rd64(hw, TXGBE_MACRXOCTL);
2169 hw_stats->tx_broadcast_packets += rd32(hw, TXGBE_MACTXOCTL);
2171 hw_stats->rx_size_64_packets += rd64(hw, TXGBE_MACRX1TO64L);
2172 hw_stats->rx_size_65_to_127_packets += rd64(hw, TXGBE_MACRX65TO127L);
2173 hw_stats->rx_size_128_to_255_packets += rd64(hw, TXGBE_MACRX128TO255L);
2174 hw_stats->rx_size_256_to_511_packets += rd64(hw, TXGBE_MACRX256TO511L);
2175 hw_stats->rx_size_512_to_1023_packets +=
2176 rd64(hw, TXGBE_MACRX512TO1023L);
2177 hw_stats->rx_size_1024_to_max_packets +=
2178 rd64(hw, TXGBE_MACRX1024TOMAXL);
2179 hw_stats->tx_size_64_packets += rd64(hw, TXGBE_MACTX1TO64L);
2180 hw_stats->tx_size_65_to_127_packets += rd64(hw, TXGBE_MACTX65TO127L);
2181 hw_stats->tx_size_128_to_255_packets += rd64(hw, TXGBE_MACTX128TO255L);
2182 hw_stats->tx_size_256_to_511_packets += rd64(hw, TXGBE_MACTX256TO511L);
2183 hw_stats->tx_size_512_to_1023_packets +=
2184 rd64(hw, TXGBE_MACTX512TO1023L);
2185 hw_stats->tx_size_1024_to_max_packets +=
2186 rd64(hw, TXGBE_MACTX1024TOMAXL);
2188 hw_stats->rx_undersize_errors += rd64(hw, TXGBE_MACRXERRLENL);
2189 hw_stats->rx_oversize_errors += rd32(hw, TXGBE_MACRXOVERSIZE);
2190 hw_stats->rx_jabber_errors += rd32(hw, TXGBE_MACRXJABBER);
2193 hw_stats->mng_bmc2host_packets = rd32(hw, TXGBE_MNGBMC2OS);
2194 hw_stats->mng_host2bmc_packets = rd32(hw, TXGBE_MNGOS2BMC);
2195 hw_stats->rx_management_packets = rd32(hw, TXGBE_DMARXMNG);
2196 hw_stats->tx_management_packets = rd32(hw, TXGBE_DMATXMNG);
2199 hw_stats->rx_fcoe_crc_errors += rd32(hw, TXGBE_FCOECRC);
2200 hw_stats->rx_fcoe_mbuf_allocation_errors += rd32(hw, TXGBE_FCOELAST);
2201 hw_stats->rx_fcoe_dropped += rd32(hw, TXGBE_FCOERPDC);
2202 hw_stats->rx_fcoe_packets += rd32(hw, TXGBE_FCOEPRC);
2203 hw_stats->tx_fcoe_packets += rd32(hw, TXGBE_FCOEPTC);
2204 hw_stats->rx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWRC);
2205 hw_stats->tx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWTC);
2207 /* Flow Director Stats */
2208 hw_stats->flow_director_matched_filters += rd32(hw, TXGBE_FDIRMATCH);
2209 hw_stats->flow_director_missed_filters += rd32(hw, TXGBE_FDIRMISS);
2210 hw_stats->flow_director_added_filters +=
2211 TXGBE_FDIRUSED_ADD(rd32(hw, TXGBE_FDIRUSED));
2212 hw_stats->flow_director_removed_filters +=
2213 TXGBE_FDIRUSED_REM(rd32(hw, TXGBE_FDIRUSED));
2214 hw_stats->flow_director_filter_add_errors +=
2215 TXGBE_FDIRFAIL_ADD(rd32(hw, TXGBE_FDIRFAIL));
2216 hw_stats->flow_director_filter_remove_errors +=
2217 TXGBE_FDIRFAIL_REM(rd32(hw, TXGBE_FDIRFAIL));
2220 hw_stats->tx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECTX_UTPKT);
2221 hw_stats->tx_macsec_pkts_encrypted +=
2222 rd32(hw, TXGBE_LSECTX_ENCPKT);
2223 hw_stats->tx_macsec_pkts_protected +=
2224 rd32(hw, TXGBE_LSECTX_PROTPKT);
2225 hw_stats->tx_macsec_octets_encrypted +=
2226 rd32(hw, TXGBE_LSECTX_ENCOCT);
2227 hw_stats->tx_macsec_octets_protected +=
2228 rd32(hw, TXGBE_LSECTX_PROTOCT);
2229 hw_stats->rx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECRX_UTPKT);
2230 hw_stats->rx_macsec_pkts_badtag += rd32(hw, TXGBE_LSECRX_BTPKT);
2231 hw_stats->rx_macsec_pkts_nosci += rd32(hw, TXGBE_LSECRX_NOSCIPKT);
2232 hw_stats->rx_macsec_pkts_unknownsci += rd32(hw, TXGBE_LSECRX_UNSCIPKT);
2233 hw_stats->rx_macsec_octets_decrypted += rd32(hw, TXGBE_LSECRX_DECOCT);
2234 hw_stats->rx_macsec_octets_validated += rd32(hw, TXGBE_LSECRX_VLDOCT);
2235 hw_stats->rx_macsec_sc_pkts_unchecked +=
2236 rd32(hw, TXGBE_LSECRX_UNCHKPKT);
2237 hw_stats->rx_macsec_sc_pkts_delayed += rd32(hw, TXGBE_LSECRX_DLYPKT);
2238 hw_stats->rx_macsec_sc_pkts_late += rd32(hw, TXGBE_LSECRX_LATEPKT);
2239 for (i = 0; i < 2; i++) {
2240 hw_stats->rx_macsec_sa_pkts_ok +=
2241 rd32(hw, TXGBE_LSECRX_OKPKT(i));
2242 hw_stats->rx_macsec_sa_pkts_invalid +=
2243 rd32(hw, TXGBE_LSECRX_INVPKT(i));
2244 hw_stats->rx_macsec_sa_pkts_notvalid +=
2245 rd32(hw, TXGBE_LSECRX_BADPKT(i));
2247 hw_stats->rx_macsec_sa_pkts_unusedsa +=
2248 rd32(hw, TXGBE_LSECRX_INVSAPKT);
2249 hw_stats->rx_macsec_sa_pkts_notusingsa +=
2250 rd32(hw, TXGBE_LSECRX_BADSAPKT);
2252 hw_stats->rx_total_missed_packets = 0;
2253 for (i = 0; i < TXGBE_MAX_UP; i++) {
2254 hw_stats->rx_total_missed_packets +=
2255 hw_stats->up[i].rx_up_dropped;
2260 txgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2262 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2263 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2264 struct txgbe_stat_mappings *stat_mappings =
2265 TXGBE_DEV_STAT_MAPPINGS(dev);
2268 txgbe_read_stats_registers(hw, hw_stats);
2273 /* Fill out the rte_eth_stats statistics structure */
2274 stats->ipackets = hw_stats->rx_packets;
2275 stats->ibytes = hw_stats->rx_bytes;
2276 stats->opackets = hw_stats->tx_packets;
2277 stats->obytes = hw_stats->tx_bytes;
2279 memset(&stats->q_ipackets, 0, sizeof(stats->q_ipackets));
2280 memset(&stats->q_opackets, 0, sizeof(stats->q_opackets));
2281 memset(&stats->q_ibytes, 0, sizeof(stats->q_ibytes));
2282 memset(&stats->q_obytes, 0, sizeof(stats->q_obytes));
2283 memset(&stats->q_errors, 0, sizeof(stats->q_errors));
2284 for (i = 0; i < TXGBE_MAX_QP; i++) {
2285 uint32_t n = i / NB_QMAP_FIELDS_PER_QSM_REG;
2286 uint32_t offset = (i % NB_QMAP_FIELDS_PER_QSM_REG) * 8;
2289 q_map = (stat_mappings->rqsm[n] >> offset)
2290 & QMAP_FIELD_RESERVED_BITS_MASK;
2291 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2292 ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2293 stats->q_ipackets[j] += hw_stats->qp[i].rx_qp_packets;
2294 stats->q_ibytes[j] += hw_stats->qp[i].rx_qp_bytes;
2296 q_map = (stat_mappings->tqsm[n] >> offset)
2297 & QMAP_FIELD_RESERVED_BITS_MASK;
2298 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2299 ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2300 stats->q_opackets[j] += hw_stats->qp[i].tx_qp_packets;
2301 stats->q_obytes[j] += hw_stats->qp[i].tx_qp_bytes;
2305 stats->imissed = hw_stats->rx_total_missed_packets +
2306 hw_stats->rx_dma_drop;
2307 stats->ierrors = hw_stats->rx_crc_errors +
2308 hw_stats->rx_mac_short_packet_dropped +
2309 hw_stats->rx_length_errors +
2310 hw_stats->rx_undersize_errors +
2311 hw_stats->rx_oversize_errors +
2312 hw_stats->rx_drop_packets +
2313 hw_stats->rx_illegal_byte_errors +
2314 hw_stats->rx_error_bytes +
2315 hw_stats->rx_fragment_errors +
2316 hw_stats->rx_fcoe_crc_errors +
2317 hw_stats->rx_fcoe_mbuf_allocation_errors;
2325 txgbe_dev_stats_reset(struct rte_eth_dev *dev)
2327 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2328 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2330 /* HW registers are cleared on read */
2331 hw->offset_loaded = 0;
2332 txgbe_dev_stats_get(dev, NULL);
2333 hw->offset_loaded = 1;
2335 /* Reset software totals */
2336 memset(hw_stats, 0, sizeof(*hw_stats));
2341 /* This function calculates the number of xstats based on the current config */
2343 txgbe_xstats_calc_num(struct rte_eth_dev *dev)
2345 int nb_queues = max(dev->data->nb_rx_queues, dev->data->nb_tx_queues);
2346 return TXGBE_NB_HW_STATS +
2347 TXGBE_NB_UP_STATS * TXGBE_MAX_UP +
2348 TXGBE_NB_QP_STATS * nb_queues;
2352 txgbe_get_name_by_id(uint32_t id, char *name, uint32_t size)
2356 /* Extended stats from txgbe_hw_stats */
2357 if (id < TXGBE_NB_HW_STATS) {
2358 snprintf(name, size, "[hw]%s",
2359 rte_txgbe_stats_strings[id].name);
2362 id -= TXGBE_NB_HW_STATS;
2364 /* Priority Stats */
2365 if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2366 nb = id / TXGBE_NB_UP_STATS;
2367 st = id % TXGBE_NB_UP_STATS;
2368 snprintf(name, size, "[p%u]%s", nb,
2369 rte_txgbe_up_strings[st].name);
2372 id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2375 if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2376 nb = id / TXGBE_NB_QP_STATS;
2377 st = id % TXGBE_NB_QP_STATS;
2378 snprintf(name, size, "[q%u]%s", nb,
2379 rte_txgbe_qp_strings[st].name);
2382 id -= TXGBE_NB_QP_STATS * TXGBE_MAX_QP;
2384 return -(int)(id + 1);
2388 txgbe_get_offset_by_id(uint32_t id, uint32_t *offset)
2392 /* Extended stats from txgbe_hw_stats */
2393 if (id < TXGBE_NB_HW_STATS) {
2394 *offset = rte_txgbe_stats_strings[id].offset;
2397 id -= TXGBE_NB_HW_STATS;
2399 /* Priority Stats */
2400 if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2401 nb = id / TXGBE_NB_UP_STATS;
2402 st = id % TXGBE_NB_UP_STATS;
2403 *offset = rte_txgbe_up_strings[st].offset +
2404 nb * (TXGBE_NB_UP_STATS * sizeof(uint64_t));
2407 id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2410 if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2411 nb = id / TXGBE_NB_QP_STATS;
2412 st = id % TXGBE_NB_QP_STATS;
2413 *offset = rte_txgbe_qp_strings[st].offset +
2414 nb * (TXGBE_NB_QP_STATS * sizeof(uint64_t));
2421 static int txgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
2422 struct rte_eth_xstat_name *xstats_names, unsigned int limit)
2424 unsigned int i, count;
2426 count = txgbe_xstats_calc_num(dev);
2427 if (xstats_names == NULL)
2430 /* Note: limit >= cnt_stats checked upstream
2431 * in rte_eth_xstats_names()
2433 limit = min(limit, count);
2435 /* Extended stats from txgbe_hw_stats */
2436 for (i = 0; i < limit; i++) {
2437 if (txgbe_get_name_by_id(i, xstats_names[i].name,
2438 sizeof(xstats_names[i].name))) {
2439 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2447 static int txgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
2448 struct rte_eth_xstat_name *xstats_names,
2449 const uint64_t *ids,
2455 return txgbe_dev_xstats_get_names(dev, xstats_names, limit);
2457 for (i = 0; i < limit; i++) {
2458 if (txgbe_get_name_by_id(ids[i], xstats_names[i].name,
2459 sizeof(xstats_names[i].name))) {
2460 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2469 txgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2472 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2473 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2474 unsigned int i, count;
2476 txgbe_read_stats_registers(hw, hw_stats);
2478 /* If this is a reset xstats is NULL, and we have cleared the
2479 * registers by reading them.
2481 count = txgbe_xstats_calc_num(dev);
2485 limit = min(limit, txgbe_xstats_calc_num(dev));
2487 /* Extended stats from txgbe_hw_stats */
2488 for (i = 0; i < limit; i++) {
2489 uint32_t offset = 0;
2491 if (txgbe_get_offset_by_id(i, &offset)) {
2492 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2495 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + offset);
2503 txgbe_dev_xstats_get_(struct rte_eth_dev *dev, uint64_t *values,
2506 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2507 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2508 unsigned int i, count;
2510 txgbe_read_stats_registers(hw, hw_stats);
2512 /* If this is a reset xstats is NULL, and we have cleared the
2513 * registers by reading them.
2515 count = txgbe_xstats_calc_num(dev);
2519 limit = min(limit, txgbe_xstats_calc_num(dev));
2521 /* Extended stats from txgbe_hw_stats */
2522 for (i = 0; i < limit; i++) {
2525 if (txgbe_get_offset_by_id(i, &offset)) {
2526 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2529 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2536 txgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
2537 uint64_t *values, unsigned int limit)
2539 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2543 return txgbe_dev_xstats_get_(dev, values, limit);
2545 for (i = 0; i < limit; i++) {
2548 if (txgbe_get_offset_by_id(ids[i], &offset)) {
2549 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2552 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2559 txgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2561 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2562 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2564 /* HW registers are cleared on read */
2565 hw->offset_loaded = 0;
2566 txgbe_read_stats_registers(hw, hw_stats);
2567 hw->offset_loaded = 1;
2569 /* Reset software totals */
2570 memset(hw_stats, 0, sizeof(*hw_stats));
2576 txgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2578 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2582 hw->phy.get_fw_version(hw, &etrack_id);
2584 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
2586 ret += 1; /* add the size of '\0' */
2587 if (fw_size < (u32)ret)
2594 txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2596 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2597 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2599 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2600 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2601 dev_info->min_rx_bufsize = 1024;
2602 dev_info->max_rx_pktlen = 15872;
2603 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2604 dev_info->max_hash_mac_addrs = TXGBE_VMDQ_NUM_UC_MAC;
2605 dev_info->max_vfs = pci_dev->max_vfs;
2606 dev_info->max_vmdq_pools = ETH_64_POOLS;
2607 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2608 dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev);
2609 dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) |
2610 dev_info->rx_queue_offload_capa);
2611 dev_info->tx_queue_offload_capa = txgbe_get_tx_queue_offloads(dev);
2612 dev_info->tx_offload_capa = txgbe_get_tx_port_offloads(dev);
2614 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2616 .pthresh = TXGBE_DEFAULT_RX_PTHRESH,
2617 .hthresh = TXGBE_DEFAULT_RX_HTHRESH,
2618 .wthresh = TXGBE_DEFAULT_RX_WTHRESH,
2620 .rx_free_thresh = TXGBE_DEFAULT_RX_FREE_THRESH,
2625 dev_info->default_txconf = (struct rte_eth_txconf) {
2627 .pthresh = TXGBE_DEFAULT_TX_PTHRESH,
2628 .hthresh = TXGBE_DEFAULT_TX_HTHRESH,
2629 .wthresh = TXGBE_DEFAULT_TX_WTHRESH,
2631 .tx_free_thresh = TXGBE_DEFAULT_TX_FREE_THRESH,
2635 dev_info->rx_desc_lim = rx_desc_lim;
2636 dev_info->tx_desc_lim = tx_desc_lim;
2638 dev_info->hash_key_size = TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2639 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2640 dev_info->flow_type_rss_offloads = TXGBE_RSS_OFFLOAD_ALL;
2642 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2643 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
2645 /* Driver-preferred Rx/Tx parameters */
2646 dev_info->default_rxportconf.burst_size = 32;
2647 dev_info->default_txportconf.burst_size = 32;
2648 dev_info->default_rxportconf.nb_queues = 1;
2649 dev_info->default_txportconf.nb_queues = 1;
2650 dev_info->default_rxportconf.ring_size = 256;
2651 dev_info->default_txportconf.ring_size = 256;
2657 txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2659 if (dev->rx_pkt_burst == txgbe_recv_pkts ||
2660 dev->rx_pkt_burst == txgbe_recv_pkts_lro_single_alloc ||
2661 dev->rx_pkt_burst == txgbe_recv_pkts_lro_bulk_alloc ||
2662 dev->rx_pkt_burst == txgbe_recv_pkts_bulk_alloc)
2663 return txgbe_get_supported_ptypes();
2669 txgbe_dev_setup_link_alarm_handler(void *param)
2671 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2672 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2673 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2675 bool autoneg = false;
2677 speed = hw->phy.autoneg_advertised;
2679 hw->mac.get_link_capabilities(hw, &speed, &autoneg);
2681 hw->mac.setup_link(hw, speed, true);
2683 intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2686 /* return 0 means link status changed, -1 means not changed */
2688 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
2689 int wait_to_complete)
2691 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2692 struct rte_eth_link link;
2693 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2694 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2699 memset(&link, 0, sizeof(link));
2700 link.link_status = ETH_LINK_DOWN;
2701 link.link_speed = ETH_SPEED_NUM_NONE;
2702 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2703 link.link_autoneg = ETH_LINK_AUTONEG;
2705 hw->mac.get_link_status = true;
2707 if (intr->flags & TXGBE_FLAG_NEED_LINK_CONFIG)
2708 return rte_eth_linkstatus_set(dev, &link);
2710 /* check if it needs to wait to complete, if lsc interrupt is enabled */
2711 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2714 err = hw->mac.check_link(hw, &link_speed, &link_up, wait);
2717 link.link_speed = ETH_SPEED_NUM_100M;
2718 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2719 return rte_eth_linkstatus_set(dev, &link);
2723 if ((hw->subsystem_device_id & 0xFF) ==
2724 TXGBE_DEV_ID_KR_KX_KX4) {
2725 hw->mac.bp_down_event(hw);
2726 } else if (hw->phy.media_type == txgbe_media_type_fiber) {
2727 intr->flags |= TXGBE_FLAG_NEED_LINK_CONFIG;
2728 rte_eal_alarm_set(10,
2729 txgbe_dev_setup_link_alarm_handler, dev);
2731 return rte_eth_linkstatus_set(dev, &link);
2734 intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2735 link.link_status = ETH_LINK_UP;
2736 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2738 switch (link_speed) {
2740 case TXGBE_LINK_SPEED_UNKNOWN:
2741 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2742 link.link_speed = ETH_SPEED_NUM_100M;
2745 case TXGBE_LINK_SPEED_100M_FULL:
2746 link.link_speed = ETH_SPEED_NUM_100M;
2749 case TXGBE_LINK_SPEED_1GB_FULL:
2750 link.link_speed = ETH_SPEED_NUM_1G;
2753 case TXGBE_LINK_SPEED_2_5GB_FULL:
2754 link.link_speed = ETH_SPEED_NUM_2_5G;
2757 case TXGBE_LINK_SPEED_5GB_FULL:
2758 link.link_speed = ETH_SPEED_NUM_5G;
2761 case TXGBE_LINK_SPEED_10GB_FULL:
2762 link.link_speed = ETH_SPEED_NUM_10G;
2766 return rte_eth_linkstatus_set(dev, &link);
2770 txgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2772 return txgbe_dev_link_update_share(dev, wait_to_complete);
2776 txgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2778 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2781 fctrl = rd32(hw, TXGBE_PSRCTL);
2782 fctrl |= (TXGBE_PSRCTL_UCP | TXGBE_PSRCTL_MCP);
2783 wr32(hw, TXGBE_PSRCTL, fctrl);
2789 txgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2791 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2794 fctrl = rd32(hw, TXGBE_PSRCTL);
2795 fctrl &= (~TXGBE_PSRCTL_UCP);
2796 if (dev->data->all_multicast == 1)
2797 fctrl |= TXGBE_PSRCTL_MCP;
2799 fctrl &= (~TXGBE_PSRCTL_MCP);
2800 wr32(hw, TXGBE_PSRCTL, fctrl);
2806 txgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2808 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2811 fctrl = rd32(hw, TXGBE_PSRCTL);
2812 fctrl |= TXGBE_PSRCTL_MCP;
2813 wr32(hw, TXGBE_PSRCTL, fctrl);
2819 txgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2821 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2824 if (dev->data->promiscuous == 1)
2825 return 0; /* must remain in all_multicast mode */
2827 fctrl = rd32(hw, TXGBE_PSRCTL);
2828 fctrl &= (~TXGBE_PSRCTL_MCP);
2829 wr32(hw, TXGBE_PSRCTL, fctrl);
2835 * It clears the interrupt causes and enables the interrupt.
2836 * It will be called once only during nic initialized.
2839 * Pointer to struct rte_eth_dev.
2841 * Enable or Disable.
2844 * - On success, zero.
2845 * - On failure, a negative value.
2848 txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2850 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2852 txgbe_dev_link_status_print(dev);
2854 intr->mask_misc |= TXGBE_ICRMISC_LSC;
2856 intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2862 txgbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev)
2864 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2867 mask = TXGBE_ICR_MASK;
2868 mask &= (1ULL << TXGBE_MISC_VEC_ID);
2870 intr->mask_misc |= TXGBE_ICRMISC_GPIO;
2871 intr->mask_misc |= TXGBE_ICRMISC_ANDONE;
2876 * It clears the interrupt causes and enables the interrupt.
2877 * It will be called once only during nic initialized.
2880 * Pointer to struct rte_eth_dev.
2883 * - On success, zero.
2884 * - On failure, a negative value.
2887 txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2889 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2892 mask = TXGBE_ICR_MASK;
2893 mask &= ~((1ULL << TXGBE_RX_VEC_START) - 1);
2900 * It clears the interrupt causes and enables the interrupt.
2901 * It will be called once only during nic initialized.
2904 * Pointer to struct rte_eth_dev.
2907 * - On success, zero.
2908 * - On failure, a negative value.
2911 txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
2913 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2915 intr->mask_misc |= TXGBE_ICRMISC_LNKSEC;
2921 * It reads ICR and sets flag (TXGBE_ICRMISC_LSC) for the link_update.
2924 * Pointer to struct rte_eth_dev.
2927 * - On success, zero.
2928 * - On failure, a negative value.
2931 txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2934 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2935 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2937 /* clear all cause mask */
2938 txgbe_disable_intr(hw);
2940 /* read-on-clear nic registers here */
2941 eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
2942 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
2946 /* set flag for async link update */
2947 if (eicr & TXGBE_ICRMISC_LSC)
2948 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
2950 if (eicr & TXGBE_ICRMISC_ANDONE)
2951 intr->flags |= TXGBE_FLAG_NEED_AN_CONFIG;
2953 if (eicr & TXGBE_ICRMISC_VFMBX)
2954 intr->flags |= TXGBE_FLAG_MAILBOX;
2956 if (eicr & TXGBE_ICRMISC_LNKSEC)
2957 intr->flags |= TXGBE_FLAG_MACSEC;
2959 if (eicr & TXGBE_ICRMISC_GPIO)
2960 intr->flags |= TXGBE_FLAG_PHY_INTERRUPT;
2966 * It gets and then prints the link status.
2969 * Pointer to struct rte_eth_dev.
2972 * - On success, zero.
2973 * - On failure, a negative value.
2976 txgbe_dev_link_status_print(struct rte_eth_dev *dev)
2978 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2979 struct rte_eth_link link;
2981 rte_eth_linkstatus_get(dev, &link);
2983 if (link.link_status) {
2984 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2985 (int)(dev->data->port_id),
2986 (unsigned int)link.link_speed,
2987 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2988 "full-duplex" : "half-duplex");
2990 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2991 (int)(dev->data->port_id));
2993 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2994 pci_dev->addr.domain,
2996 pci_dev->addr.devid,
2997 pci_dev->addr.function);
3001 * It executes link_update after knowing an interrupt occurred.
3004 * Pointer to struct rte_eth_dev.
3007 * - On success, zero.
3008 * - On failure, a negative value.
3011 txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3012 struct rte_intr_handle *intr_handle)
3014 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
3016 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3018 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3020 if (intr->flags & TXGBE_FLAG_MAILBOX) {
3021 txgbe_pf_mbx_process(dev);
3022 intr->flags &= ~TXGBE_FLAG_MAILBOX;
3025 if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
3026 hw->phy.handle_lasi(hw);
3027 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
3030 if (intr->flags & TXGBE_FLAG_NEED_AN_CONFIG) {
3031 if (hw->devarg.auto_neg == 1 && hw->devarg.poll == 0) {
3032 hw->mac.kr_handle(hw);
3033 intr->flags &= ~TXGBE_FLAG_NEED_AN_CONFIG;
3037 if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
3038 struct rte_eth_link link;
3040 /*get the link status before link update, for predicting later*/
3041 rte_eth_linkstatus_get(dev, &link);
3043 txgbe_dev_link_update(dev, 0);
3046 if (!link.link_status)
3047 /* handle it 1 sec later, wait it being stable */
3048 timeout = TXGBE_LINK_UP_CHECK_TIMEOUT;
3049 /* likely to down */
3050 else if ((hw->subsystem_device_id & 0xFF) ==
3051 TXGBE_DEV_ID_KR_KX_KX4 &&
3052 hw->devarg.auto_neg == 1)
3053 /* handle it 2 sec later for backplane AN73 */
3056 /* handle it 4 sec later, wait it being stable */
3057 timeout = TXGBE_LINK_DOWN_CHECK_TIMEOUT;
3059 txgbe_dev_link_status_print(dev);
3060 if (rte_eal_alarm_set(timeout * 1000,
3061 txgbe_dev_interrupt_delayed_handler,
3063 PMD_DRV_LOG(ERR, "Error setting alarm");
3065 /* only disable lsc interrupt */
3066 intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
3068 intr->mask_orig = intr->mask;
3069 /* only disable all misc interrupts */
3070 intr->mask &= ~(1ULL << TXGBE_MISC_VEC_ID);
3074 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3075 txgbe_enable_intr(dev);
3076 rte_intr_enable(intr_handle);
3082 * Interrupt handler which shall be registered for alarm callback for delayed
3083 * handling specific interrupt to wait for the stable nic state. As the
3084 * NIC interrupt state is not stable for txgbe after link is just down,
3085 * it needs to wait 4 seconds to get the stable status.
3088 * Pointer to interrupt handle.
3090 * The address of parameter (struct rte_eth_dev *) registered before.
3096 txgbe_dev_interrupt_delayed_handler(void *param)
3098 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3099 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3100 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3101 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
3102 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3105 txgbe_disable_intr(hw);
3107 eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
3108 if (eicr & TXGBE_ICRMISC_VFMBX)
3109 txgbe_pf_mbx_process(dev);
3111 if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
3112 hw->phy.handle_lasi(hw);
3113 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
3116 if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
3117 txgbe_dev_link_update(dev, 0);
3118 intr->flags &= ~TXGBE_FLAG_NEED_LINK_UPDATE;
3119 txgbe_dev_link_status_print(dev);
3120 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
3124 if (intr->flags & TXGBE_FLAG_MACSEC) {
3125 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3127 intr->flags &= ~TXGBE_FLAG_MACSEC;
3130 /* restore original mask */
3131 intr->mask_misc |= TXGBE_ICRMISC_LSC;
3133 intr->mask = intr->mask_orig;
3134 intr->mask_orig = 0;
3136 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3137 txgbe_enable_intr(dev);
3138 rte_intr_enable(intr_handle);
3142 * Interrupt handler triggered by NIC for handling
3143 * specific interrupt.
3146 * Pointer to interrupt handle.
3148 * The address of parameter (struct rte_eth_dev *) registered before.
3154 txgbe_dev_interrupt_handler(void *param)
3156 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3158 txgbe_dev_interrupt_get_status(dev);
3159 txgbe_dev_interrupt_action(dev, dev->intr_handle);
3163 txgbe_dev_led_on(struct rte_eth_dev *dev)
3165 struct txgbe_hw *hw;
3167 hw = TXGBE_DEV_HW(dev);
3168 return txgbe_led_on(hw, 4) == 0 ? 0 : -ENOTSUP;
3172 txgbe_dev_led_off(struct rte_eth_dev *dev)
3174 struct txgbe_hw *hw;
3176 hw = TXGBE_DEV_HW(dev);
3177 return txgbe_led_off(hw, 4) == 0 ? 0 : -ENOTSUP;
3181 txgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3183 struct txgbe_hw *hw;
3189 hw = TXGBE_DEV_HW(dev);
3191 fc_conf->pause_time = hw->fc.pause_time;
3192 fc_conf->high_water = hw->fc.high_water[0];
3193 fc_conf->low_water = hw->fc.low_water[0];
3194 fc_conf->send_xon = hw->fc.send_xon;
3195 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3198 * Return rx_pause status according to actual setting of
3201 mflcn_reg = rd32(hw, TXGBE_RXFCCFG);
3202 if (mflcn_reg & (TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC))
3208 * Return tx_pause status according to actual setting of
3211 fccfg_reg = rd32(hw, TXGBE_TXFCCFG);
3212 if (fccfg_reg & (TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC))
3217 if (rx_pause && tx_pause)
3218 fc_conf->mode = RTE_FC_FULL;
3220 fc_conf->mode = RTE_FC_RX_PAUSE;
3222 fc_conf->mode = RTE_FC_TX_PAUSE;
3224 fc_conf->mode = RTE_FC_NONE;
3230 txgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3232 struct txgbe_hw *hw;
3234 uint32_t rx_buf_size;
3235 uint32_t max_high_water;
3236 enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
3243 PMD_INIT_FUNC_TRACE();
3245 hw = TXGBE_DEV_HW(dev);
3246 rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(0));
3247 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3250 * At least reserve one Ethernet frame for watermark
3251 * high_water/low_water in kilo bytes for txgbe
3253 max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
3254 if (fc_conf->high_water > max_high_water ||
3255 fc_conf->high_water < fc_conf->low_water) {
3256 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3257 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3261 hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[fc_conf->mode];
3262 hw->fc.pause_time = fc_conf->pause_time;
3263 hw->fc.high_water[0] = fc_conf->high_water;
3264 hw->fc.low_water[0] = fc_conf->low_water;
3265 hw->fc.send_xon = fc_conf->send_xon;
3266 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3268 err = txgbe_fc_enable(hw);
3270 /* Not negotiated is not an error case */
3271 if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED) {
3272 wr32m(hw, TXGBE_MACRXFLT, TXGBE_MACRXFLT_CTL_MASK,
3273 (fc_conf->mac_ctrl_frame_fwd
3274 ? TXGBE_MACRXFLT_CTL_NOPS : TXGBE_MACRXFLT_CTL_DROP));
3280 PMD_INIT_LOG(ERR, "txgbe_fc_enable = 0x%x", err);
3285 txgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
3286 struct rte_eth_pfc_conf *pfc_conf)
3289 uint32_t rx_buf_size;
3290 uint32_t max_high_water;
3292 uint8_t map[TXGBE_DCB_UP_MAX] = { 0 };
3293 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3294 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
3296 enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
3303 PMD_INIT_FUNC_TRACE();
3305 txgbe_dcb_unpack_map_cee(dcb_config, TXGBE_DCB_RX_CONFIG, map);
3306 tc_num = map[pfc_conf->priority];
3307 rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(tc_num));
3308 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3310 * At least reserve one Ethernet frame for watermark
3311 * high_water/low_water in kilo bytes for txgbe
3313 max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
3314 if (pfc_conf->fc.high_water > max_high_water ||
3315 pfc_conf->fc.high_water <= pfc_conf->fc.low_water) {
3316 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3317 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3321 hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[pfc_conf->fc.mode];
3322 hw->fc.pause_time = pfc_conf->fc.pause_time;
3323 hw->fc.send_xon = pfc_conf->fc.send_xon;
3324 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
3325 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3327 err = txgbe_dcb_pfc_enable(hw, tc_num);
3329 /* Not negotiated is not an error case */
3330 if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED)
3333 PMD_INIT_LOG(ERR, "txgbe_dcb_pfc_enable = 0x%x", err);
3338 txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3339 struct rte_eth_rss_reta_entry64 *reta_conf,
3344 uint16_t idx, shift;
3345 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3346 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3348 PMD_INIT_FUNC_TRACE();
3350 if (!txgbe_rss_update_sp(hw->mac.type)) {
3351 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3356 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3357 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3358 "(%d) doesn't match the number hardware can supported "
3359 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3363 for (i = 0; i < reta_size; i += 4) {
3364 idx = i / RTE_RETA_GROUP_SIZE;
3365 shift = i % RTE_RETA_GROUP_SIZE;
3366 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3370 reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2);
3371 for (j = 0; j < 4; j++) {
3372 if (RS8(mask, j, 0x1)) {
3373 reta &= ~(MS32(8 * j, 0xFF));
3374 reta |= LS32(reta_conf[idx].reta[shift + j],
3378 wr32at(hw, TXGBE_REG_RSSTBL, i >> 2, reta);
3380 adapter->rss_reta_updated = 1;
3386 txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3387 struct rte_eth_rss_reta_entry64 *reta_conf,
3390 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3393 uint16_t idx, shift;
3395 PMD_INIT_FUNC_TRACE();
3397 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3398 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3399 "(%d) doesn't match the number hardware can supported "
3400 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3404 for (i = 0; i < reta_size; i += 4) {
3405 idx = i / RTE_RETA_GROUP_SIZE;
3406 shift = i % RTE_RETA_GROUP_SIZE;
3407 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3411 reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2);
3412 for (j = 0; j < 4; j++) {
3413 if (RS8(mask, j, 0x1))
3414 reta_conf[idx].reta[shift + j] =
3415 (uint16_t)RS32(reta, 8 * j, 0xFF);
3423 txgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3424 uint32_t index, uint32_t pool)
3426 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3427 uint32_t enable_addr = 1;
3429 return txgbe_set_rar(hw, index, mac_addr->addr_bytes,
3434 txgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3436 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3438 txgbe_clear_rar(hw, index);
3442 txgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3444 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3446 txgbe_remove_rar(dev, 0);
3447 txgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
3453 txgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3455 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3456 struct rte_eth_dev_info dev_info;
3457 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
3458 struct rte_eth_dev_data *dev_data = dev->data;
3461 ret = txgbe_dev_info_get(dev, &dev_info);
3465 /* check that mtu is within the allowed range */
3466 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
3469 /* If device is started, refuse mtu that requires the support of
3470 * scattered packets when this feature has not been enabled before.
3472 if (dev_data->dev_started && !dev_data->scattered_rx &&
3473 (frame_size + 2 * TXGBE_VLAN_TAG_SIZE >
3474 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3475 PMD_INIT_LOG(ERR, "Stop port first.");
3479 /* update max frame size */
3480 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3483 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3484 TXGBE_FRAME_SIZE_MAX);
3486 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3487 TXGBE_FRMSZ_MAX(frame_size));
3493 txgbe_uta_vector(struct txgbe_hw *hw, struct rte_ether_addr *uc_addr)
3495 uint32_t vector = 0;
3497 switch (hw->mac.mc_filter_type) {
3498 case 0: /* use bits [47:36] of the address */
3499 vector = ((uc_addr->addr_bytes[4] >> 4) |
3500 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3502 case 1: /* use bits [46:35] of the address */
3503 vector = ((uc_addr->addr_bytes[4] >> 3) |
3504 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3506 case 2: /* use bits [45:34] of the address */
3507 vector = ((uc_addr->addr_bytes[4] >> 2) |
3508 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3510 case 3: /* use bits [43:32] of the address */
3511 vector = ((uc_addr->addr_bytes[4]) |
3512 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3514 default: /* Invalid mc_filter_type */
3518 /* vector can only be 12-bits or boundary will be exceeded */
3524 txgbe_uc_hash_table_set(struct rte_eth_dev *dev,
3525 struct rte_ether_addr *mac_addr, uint8_t on)
3533 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3534 struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3536 /* The UTA table only exists on pf hardware */
3537 if (hw->mac.type < txgbe_mac_raptor)
3540 vector = txgbe_uta_vector(hw, mac_addr);
3541 uta_idx = (vector >> 5) & 0x7F;
3542 uta_mask = 0x1UL << (vector & 0x1F);
3544 if (!!on == !!(uta_info->uta_shadow[uta_idx] & uta_mask))
3547 reg_val = rd32(hw, TXGBE_UCADDRTBL(uta_idx));
3549 uta_info->uta_in_use++;
3550 reg_val |= uta_mask;
3551 uta_info->uta_shadow[uta_idx] |= uta_mask;
3553 uta_info->uta_in_use--;
3554 reg_val &= ~uta_mask;
3555 uta_info->uta_shadow[uta_idx] &= ~uta_mask;
3558 wr32(hw, TXGBE_UCADDRTBL(uta_idx), reg_val);
3560 psrctl = rd32(hw, TXGBE_PSRCTL);
3561 if (uta_info->uta_in_use > 0)
3562 psrctl |= TXGBE_PSRCTL_UCHFENA;
3564 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3566 psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3567 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3568 wr32(hw, TXGBE_PSRCTL, psrctl);
3574 txgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3576 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3577 struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3581 /* The UTA table only exists on pf hardware */
3582 if (hw->mac.type < txgbe_mac_raptor)
3586 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3587 uta_info->uta_shadow[i] = ~0;
3588 wr32(hw, TXGBE_UCADDRTBL(i), ~0);
3591 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3592 uta_info->uta_shadow[i] = 0;
3593 wr32(hw, TXGBE_UCADDRTBL(i), 0);
3597 psrctl = rd32(hw, TXGBE_PSRCTL);
3599 psrctl |= TXGBE_PSRCTL_UCHFENA;
3601 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3603 psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3604 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3605 wr32(hw, TXGBE_PSRCTL, psrctl);
3611 txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3613 uint32_t new_val = orig_val;
3615 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3616 new_val |= TXGBE_POOLETHCTL_UTA;
3617 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3618 new_val |= TXGBE_POOLETHCTL_MCHA;
3619 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3620 new_val |= TXGBE_POOLETHCTL_UCHA;
3621 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3622 new_val |= TXGBE_POOLETHCTL_BCA;
3623 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3624 new_val |= TXGBE_POOLETHCTL_MCP;
3630 txgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
3632 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3633 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3635 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3637 if (queue_id < 32) {
3638 mask = rd32(hw, TXGBE_IMS(0));
3639 mask &= (1 << queue_id);
3640 wr32(hw, TXGBE_IMS(0), mask);
3641 } else if (queue_id < 64) {
3642 mask = rd32(hw, TXGBE_IMS(1));
3643 mask &= (1 << (queue_id - 32));
3644 wr32(hw, TXGBE_IMS(1), mask);
3646 rte_intr_enable(intr_handle);
3652 txgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
3655 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3657 if (queue_id < 32) {
3658 mask = rd32(hw, TXGBE_IMS(0));
3659 mask &= ~(1 << queue_id);
3660 wr32(hw, TXGBE_IMS(0), mask);
3661 } else if (queue_id < 64) {
3662 mask = rd32(hw, TXGBE_IMS(1));
3663 mask &= ~(1 << (queue_id - 32));
3664 wr32(hw, TXGBE_IMS(1), mask);
3671 * set the IVAR registers, mapping interrupt causes to vectors
3673 * pointer to txgbe_hw struct
3675 * 0 for Rx, 1 for Tx, -1 for other causes
3677 * queue to map the corresponding interrupt to
3679 * the vector to map to the corresponding queue
3682 txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
3683 uint8_t queue, uint8_t msix_vector)
3687 if (direction == -1) {
3689 msix_vector |= TXGBE_IVARMISC_VLD;
3691 tmp = rd32(hw, TXGBE_IVARMISC);
3692 tmp &= ~(0xFF << idx);
3693 tmp |= (msix_vector << idx);
3694 wr32(hw, TXGBE_IVARMISC, tmp);
3696 /* rx or tx causes */
3697 /* Workround for ICR lost */
3698 idx = ((16 * (queue & 1)) + (8 * direction));
3699 tmp = rd32(hw, TXGBE_IVAR(queue >> 1));
3700 tmp &= ~(0xFF << idx);
3701 tmp |= (msix_vector << idx);
3702 wr32(hw, TXGBE_IVAR(queue >> 1), tmp);
3707 * Sets up the hardware to properly generate MSI-X interrupts
3709 * board private structure
3712 txgbe_configure_msix(struct rte_eth_dev *dev)
3714 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3715 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3716 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3717 uint32_t queue_id, base = TXGBE_MISC_VEC_ID;
3718 uint32_t vec = TXGBE_MISC_VEC_ID;
3721 /* won't configure msix register if no mapping is done
3722 * between intr vector and event fd
3723 * but if misx has been enabled already, need to configure
3724 * auto clean, auto mask and throttling.
3726 gpie = rd32(hw, TXGBE_GPIE);
3727 if (!rte_intr_dp_is_en(intr_handle) &&
3728 !(gpie & TXGBE_GPIE_MSIX))
3731 if (rte_intr_allow_others(intr_handle)) {
3732 base = TXGBE_RX_VEC_START;
3736 /* setup GPIE for MSI-x mode */
3737 gpie = rd32(hw, TXGBE_GPIE);
3738 gpie |= TXGBE_GPIE_MSIX;
3739 wr32(hw, TXGBE_GPIE, gpie);
3741 /* Populate the IVAR table and set the ITR values to the
3742 * corresponding register.
3744 if (rte_intr_dp_is_en(intr_handle)) {
3745 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
3747 /* by default, 1:1 mapping */
3748 txgbe_set_ivar_map(hw, 0, queue_id, vec);
3749 intr_handle->intr_vec[queue_id] = vec;
3750 if (vec < base + intr_handle->nb_efd - 1)
3754 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
3756 wr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID),
3757 TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
3762 txgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3763 uint16_t queue_idx, uint16_t tx_rate)
3765 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3768 if (queue_idx >= hw->mac.max_tx_queues)
3772 bcnrc_val = TXGBE_ARBTXRATE_MAX(tx_rate);
3773 bcnrc_val |= TXGBE_ARBTXRATE_MIN(tx_rate / 2);
3779 * Set global transmit compensation time to the MMW_SIZE in ARBTXMMW
3780 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
3782 wr32(hw, TXGBE_ARBTXMMW, 0x14);
3784 /* Set ARBTXRATE of queue X */
3785 wr32(hw, TXGBE_ARBPOOLIDX, queue_idx);
3786 wr32(hw, TXGBE_ARBTXRATE, bcnrc_val);
3793 txgbe_syn_filter_set(struct rte_eth_dev *dev,
3794 struct rte_eth_syn_filter *filter,
3797 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3798 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3802 if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
3805 syn_info = filter_info->syn_info;
3808 if (syn_info & TXGBE_SYNCLS_ENA)
3810 synqf = (uint32_t)TXGBE_SYNCLS_QPID(filter->queue);
3811 synqf |= TXGBE_SYNCLS_ENA;
3813 if (filter->hig_pri)
3814 synqf |= TXGBE_SYNCLS_HIPRIO;
3816 synqf &= ~TXGBE_SYNCLS_HIPRIO;
3818 synqf = rd32(hw, TXGBE_SYNCLS);
3819 if (!(syn_info & TXGBE_SYNCLS_ENA))
3821 synqf &= ~(TXGBE_SYNCLS_QPID_MASK | TXGBE_SYNCLS_ENA);
3824 filter_info->syn_info = synqf;
3825 wr32(hw, TXGBE_SYNCLS, synqf);
3830 static inline enum txgbe_5tuple_protocol
3831 convert_protocol_type(uint8_t protocol_value)
3833 if (protocol_value == IPPROTO_TCP)
3834 return TXGBE_5TF_PROT_TCP;
3835 else if (protocol_value == IPPROTO_UDP)
3836 return TXGBE_5TF_PROT_UDP;
3837 else if (protocol_value == IPPROTO_SCTP)
3838 return TXGBE_5TF_PROT_SCTP;
3840 return TXGBE_5TF_PROT_NONE;
3843 /* inject a 5-tuple filter to HW */
3845 txgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
3846 struct txgbe_5tuple_filter *filter)
3848 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3850 uint32_t ftqf, sdpqf;
3851 uint32_t l34timir = 0;
3852 uint32_t mask = TXGBE_5TFCTL0_MASK;
3855 sdpqf = TXGBE_5TFPORT_DST(be_to_le16(filter->filter_info.dst_port));
3856 sdpqf |= TXGBE_5TFPORT_SRC(be_to_le16(filter->filter_info.src_port));
3858 ftqf = TXGBE_5TFCTL0_PROTO(filter->filter_info.proto);
3859 ftqf |= TXGBE_5TFCTL0_PRI(filter->filter_info.priority);
3860 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3861 mask &= ~TXGBE_5TFCTL0_MSADDR;
3862 if (filter->filter_info.dst_ip_mask == 0)
3863 mask &= ~TXGBE_5TFCTL0_MDADDR;
3864 if (filter->filter_info.src_port_mask == 0)
3865 mask &= ~TXGBE_5TFCTL0_MSPORT;
3866 if (filter->filter_info.dst_port_mask == 0)
3867 mask &= ~TXGBE_5TFCTL0_MDPORT;
3868 if (filter->filter_info.proto_mask == 0)
3869 mask &= ~TXGBE_5TFCTL0_MPROTO;
3871 ftqf |= TXGBE_5TFCTL0_MPOOL;
3872 ftqf |= TXGBE_5TFCTL0_ENA;
3874 wr32(hw, TXGBE_5TFDADDR(i), be_to_le32(filter->filter_info.dst_ip));
3875 wr32(hw, TXGBE_5TFSADDR(i), be_to_le32(filter->filter_info.src_ip));
3876 wr32(hw, TXGBE_5TFPORT(i), sdpqf);
3877 wr32(hw, TXGBE_5TFCTL0(i), ftqf);
3879 l34timir |= TXGBE_5TFCTL1_QP(filter->queue);
3880 wr32(hw, TXGBE_5TFCTL1(i), l34timir);
3884 * add a 5tuple filter
3887 * dev: Pointer to struct rte_eth_dev.
3888 * index: the index the filter allocates.
3889 * filter: pointer to the filter that will be added.
3890 * rx_queue: the queue id the filter assigned to.
3893 * - On success, zero.
3894 * - On failure, a negative value.
3897 txgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3898 struct txgbe_5tuple_filter *filter)
3900 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3904 * look for an unused 5tuple filter index,
3905 * and insert the filter to list.
3907 for (i = 0; i < TXGBE_MAX_FTQF_FILTERS; i++) {
3908 idx = i / (sizeof(uint32_t) * NBBY);
3909 shift = i % (sizeof(uint32_t) * NBBY);
3910 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3911 filter_info->fivetuple_mask[idx] |= 1 << shift;
3913 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3919 if (i >= TXGBE_MAX_FTQF_FILTERS) {
3920 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3924 txgbe_inject_5tuple_filter(dev, filter);
3930 * remove a 5tuple filter
3933 * dev: Pointer to struct rte_eth_dev.
3934 * filter: the pointer of the filter will be removed.
3937 txgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3938 struct txgbe_5tuple_filter *filter)
3940 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3941 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3942 uint16_t index = filter->index;
3944 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
3945 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
3946 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3949 wr32(hw, TXGBE_5TFDADDR(index), 0);
3950 wr32(hw, TXGBE_5TFSADDR(index), 0);
3951 wr32(hw, TXGBE_5TFPORT(index), 0);
3952 wr32(hw, TXGBE_5TFCTL0(index), 0);
3953 wr32(hw, TXGBE_5TFCTL1(index), 0);
3956 static inline struct txgbe_5tuple_filter *
3957 txgbe_5tuple_filter_lookup(struct txgbe_5tuple_filter_list *filter_list,
3958 struct txgbe_5tuple_filter_info *key)
3960 struct txgbe_5tuple_filter *it;
3962 TAILQ_FOREACH(it, filter_list, entries) {
3963 if (memcmp(key, &it->filter_info,
3964 sizeof(struct txgbe_5tuple_filter_info)) == 0) {
3971 /* translate elements in struct rte_eth_ntuple_filter
3972 * to struct txgbe_5tuple_filter_info
3975 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
3976 struct txgbe_5tuple_filter_info *filter_info)
3978 if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM ||
3979 filter->priority > TXGBE_5TUPLE_MAX_PRI ||
3980 filter->priority < TXGBE_5TUPLE_MIN_PRI)
3983 switch (filter->dst_ip_mask) {
3985 filter_info->dst_ip_mask = 0;
3986 filter_info->dst_ip = filter->dst_ip;
3989 filter_info->dst_ip_mask = 1;
3992 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3996 switch (filter->src_ip_mask) {
3998 filter_info->src_ip_mask = 0;
3999 filter_info->src_ip = filter->src_ip;
4002 filter_info->src_ip_mask = 1;
4005 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4009 switch (filter->dst_port_mask) {
4011 filter_info->dst_port_mask = 0;
4012 filter_info->dst_port = filter->dst_port;
4015 filter_info->dst_port_mask = 1;
4018 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4022 switch (filter->src_port_mask) {
4024 filter_info->src_port_mask = 0;
4025 filter_info->src_port = filter->src_port;
4028 filter_info->src_port_mask = 1;
4031 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4035 switch (filter->proto_mask) {
4037 filter_info->proto_mask = 0;
4038 filter_info->proto =
4039 convert_protocol_type(filter->proto);
4042 filter_info->proto_mask = 1;
4045 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4049 filter_info->priority = (uint8_t)filter->priority;
4054 * add or delete a ntuple filter
4057 * dev: Pointer to struct rte_eth_dev.
4058 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4059 * add: if true, add filter, if false, remove filter
4062 * - On success, zero.
4063 * - On failure, a negative value.
4066 txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4067 struct rte_eth_ntuple_filter *ntuple_filter,
4070 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4071 struct txgbe_5tuple_filter_info filter_5tuple;
4072 struct txgbe_5tuple_filter *filter;
4075 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4076 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4080 memset(&filter_5tuple, 0, sizeof(struct txgbe_5tuple_filter_info));
4081 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4085 filter = txgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4087 if (filter != NULL && add) {
4088 PMD_DRV_LOG(ERR, "filter exists.");
4091 if (filter == NULL && !add) {
4092 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4097 filter = rte_zmalloc("txgbe_5tuple_filter",
4098 sizeof(struct txgbe_5tuple_filter), 0);
4101 rte_memcpy(&filter->filter_info,
4103 sizeof(struct txgbe_5tuple_filter_info));
4104 filter->queue = ntuple_filter->queue;
4105 ret = txgbe_add_5tuple_filter(dev, filter);
4111 txgbe_remove_5tuple_filter(dev, filter);
4118 txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4119 struct rte_eth_ethertype_filter *filter,
4122 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4123 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4127 struct txgbe_ethertype_filter ethertype_filter;
4129 if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
4132 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4133 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4134 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4135 " ethertype filter.", filter->ether_type);
4139 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4140 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4143 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4144 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4148 ret = txgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4149 if (ret >= 0 && add) {
4150 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4151 filter->ether_type);
4154 if (ret < 0 && !add) {
4155 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4156 filter->ether_type);
4161 etqf = TXGBE_ETFLT_ENA;
4162 etqf |= TXGBE_ETFLT_ETID(filter->ether_type);
4163 etqs |= TXGBE_ETCLS_QPID(filter->queue);
4164 etqs |= TXGBE_ETCLS_QENA;
4166 ethertype_filter.ethertype = filter->ether_type;
4167 ethertype_filter.etqf = etqf;
4168 ethertype_filter.etqs = etqs;
4169 ethertype_filter.conf = FALSE;
4170 ret = txgbe_ethertype_filter_insert(filter_info,
4173 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4177 ret = txgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4181 wr32(hw, TXGBE_ETFLT(ret), etqf);
4182 wr32(hw, TXGBE_ETCLS(ret), etqs);
4189 txgbe_dev_flow_ops_get(__rte_unused struct rte_eth_dev *dev,
4190 const struct rte_flow_ops **ops)
4192 *ops = &txgbe_flow_ops;
4197 txgbe_dev_addr_list_itr(__rte_unused struct txgbe_hw *hw,
4198 u8 **mc_addr_ptr, u32 *vmdq)
4203 mc_addr = *mc_addr_ptr;
4204 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
4209 txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
4210 struct rte_ether_addr *mc_addr_set,
4211 uint32_t nb_mc_addr)
4213 struct txgbe_hw *hw;
4216 hw = TXGBE_DEV_HW(dev);
4217 mc_addr_list = (u8 *)mc_addr_set;
4218 return hw->mac.update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
4219 txgbe_dev_addr_list_itr, TRUE);
4223 txgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
4225 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4226 uint64_t systime_cycles;
4228 systime_cycles = (uint64_t)rd32(hw, TXGBE_TSTIMEL);
4229 systime_cycles |= (uint64_t)rd32(hw, TXGBE_TSTIMEH) << 32;
4231 return systime_cycles;
4235 txgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4237 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4238 uint64_t rx_tstamp_cycles;
4240 /* TSRXSTMPL stores ns and TSRXSTMPH stores seconds. */
4241 rx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSRXSTMPL);
4242 rx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSRXSTMPH) << 32;
4244 return rx_tstamp_cycles;
4248 txgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4250 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4251 uint64_t tx_tstamp_cycles;
4253 /* TSTXSTMPL stores ns and TSTXSTMPH stores seconds. */
4254 tx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSTXSTMPL);
4255 tx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSTXSTMPH) << 32;
4257 return tx_tstamp_cycles;
4261 txgbe_start_timecounters(struct rte_eth_dev *dev)
4263 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4264 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4265 struct rte_eth_link link;
4266 uint32_t incval = 0;
4269 /* Get current link speed. */
4270 txgbe_dev_link_update(dev, 1);
4271 rte_eth_linkstatus_get(dev, &link);
4273 switch (link.link_speed) {
4274 case ETH_SPEED_NUM_100M:
4275 incval = TXGBE_INCVAL_100;
4276 shift = TXGBE_INCVAL_SHIFT_100;
4278 case ETH_SPEED_NUM_1G:
4279 incval = TXGBE_INCVAL_1GB;
4280 shift = TXGBE_INCVAL_SHIFT_1GB;
4282 case ETH_SPEED_NUM_10G:
4284 incval = TXGBE_INCVAL_10GB;
4285 shift = TXGBE_INCVAL_SHIFT_10GB;
4289 wr32(hw, TXGBE_TSTIMEINC, TXGBE_TSTIMEINC_VP(incval, 2));
4291 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4292 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4293 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4295 adapter->systime_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4296 adapter->systime_tc.cc_shift = shift;
4297 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4299 adapter->rx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4300 adapter->rx_tstamp_tc.cc_shift = shift;
4301 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4303 adapter->tx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4304 adapter->tx_tstamp_tc.cc_shift = shift;
4305 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4309 txgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4311 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4313 adapter->systime_tc.nsec += delta;
4314 adapter->rx_tstamp_tc.nsec += delta;
4315 adapter->tx_tstamp_tc.nsec += delta;
4321 txgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4324 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4326 ns = rte_timespec_to_ns(ts);
4327 /* Set the timecounters to a new value. */
4328 adapter->systime_tc.nsec = ns;
4329 adapter->rx_tstamp_tc.nsec = ns;
4330 adapter->tx_tstamp_tc.nsec = ns;
4336 txgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4338 uint64_t ns, systime_cycles;
4339 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4341 systime_cycles = txgbe_read_systime_cyclecounter(dev);
4342 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4343 *ts = rte_ns_to_timespec(ns);
4349 txgbe_timesync_enable(struct rte_eth_dev *dev)
4351 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4354 /* Stop the timesync system time. */
4355 wr32(hw, TXGBE_TSTIMEINC, 0x0);
4356 /* Reset the timesync system time value. */
4357 wr32(hw, TXGBE_TSTIMEL, 0x0);
4358 wr32(hw, TXGBE_TSTIMEH, 0x0);
4360 txgbe_start_timecounters(dev);
4362 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4363 wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588),
4364 RTE_ETHER_TYPE_1588 | TXGBE_ETFLT_ENA | TXGBE_ETFLT_1588);
4366 /* Enable timestamping of received PTP packets. */
4367 tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4368 tsync_ctl |= TXGBE_TSRXCTL_ENA;
4369 wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4371 /* Enable timestamping of transmitted PTP packets. */
4372 tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4373 tsync_ctl |= TXGBE_TSTXCTL_ENA;
4374 wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4382 txgbe_timesync_disable(struct rte_eth_dev *dev)
4384 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4387 /* Disable timestamping of transmitted PTP packets. */
4388 tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4389 tsync_ctl &= ~TXGBE_TSTXCTL_ENA;
4390 wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4392 /* Disable timestamping of received PTP packets. */
4393 tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4394 tsync_ctl &= ~TXGBE_TSRXCTL_ENA;
4395 wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4397 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4398 wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588), 0);
4400 /* Stop incrementating the System Time registers. */
4401 wr32(hw, TXGBE_TSTIMEINC, 0);
4407 txgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4408 struct timespec *timestamp,
4409 uint32_t flags __rte_unused)
4411 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4412 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4413 uint32_t tsync_rxctl;
4414 uint64_t rx_tstamp_cycles;
4417 tsync_rxctl = rd32(hw, TXGBE_TSRXCTL);
4418 if ((tsync_rxctl & TXGBE_TSRXCTL_VLD) == 0)
4421 rx_tstamp_cycles = txgbe_read_rx_tstamp_cyclecounter(dev);
4422 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4423 *timestamp = rte_ns_to_timespec(ns);
4429 txgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4430 struct timespec *timestamp)
4432 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4433 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4434 uint32_t tsync_txctl;
4435 uint64_t tx_tstamp_cycles;
4438 tsync_txctl = rd32(hw, TXGBE_TSTXCTL);
4439 if ((tsync_txctl & TXGBE_TSTXCTL_VLD) == 0)
4442 tx_tstamp_cycles = txgbe_read_tx_tstamp_cyclecounter(dev);
4443 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4444 *timestamp = rte_ns_to_timespec(ns);
4450 txgbe_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4454 const struct reg_info *reg_group;
4455 const struct reg_info **reg_set = txgbe_regs_others;
4457 while ((reg_group = reg_set[g_ind++]))
4458 count += txgbe_regs_group_count(reg_group);
4464 txgbe_get_regs(struct rte_eth_dev *dev,
4465 struct rte_dev_reg_info *regs)
4467 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4468 uint32_t *data = regs->data;
4471 const struct reg_info *reg_group;
4472 const struct reg_info **reg_set = txgbe_regs_others;
4475 regs->length = txgbe_get_reg_length(dev);
4476 regs->width = sizeof(uint32_t);
4480 /* Support only full register dump */
4481 if (regs->length == 0 ||
4482 regs->length == (uint32_t)txgbe_get_reg_length(dev)) {
4483 regs->version = hw->mac.type << 24 |
4484 hw->revision_id << 16 |
4486 while ((reg_group = reg_set[g_ind++]))
4487 count += txgbe_read_regs_group(dev, &data[count],
4496 txgbe_get_eeprom_length(struct rte_eth_dev *dev)
4498 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4500 /* Return unit is byte count */
4501 return hw->rom.word_size * 2;
4505 txgbe_get_eeprom(struct rte_eth_dev *dev,
4506 struct rte_dev_eeprom_info *in_eeprom)
4508 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4509 struct txgbe_rom_info *eeprom = &hw->rom;
4510 uint16_t *data = in_eeprom->data;
4513 first = in_eeprom->offset >> 1;
4514 length = in_eeprom->length >> 1;
4515 if (first > hw->rom.word_size ||
4516 ((first + length) > hw->rom.word_size))
4519 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4521 return eeprom->readw_buffer(hw, first, length, data);
4525 txgbe_set_eeprom(struct rte_eth_dev *dev,
4526 struct rte_dev_eeprom_info *in_eeprom)
4528 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4529 struct txgbe_rom_info *eeprom = &hw->rom;
4530 uint16_t *data = in_eeprom->data;
4533 first = in_eeprom->offset >> 1;
4534 length = in_eeprom->length >> 1;
4535 if (first > hw->rom.word_size ||
4536 ((first + length) > hw->rom.word_size))
4539 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4541 return eeprom->writew_buffer(hw, first, length, data);
4545 txgbe_get_module_info(struct rte_eth_dev *dev,
4546 struct rte_eth_dev_module_info *modinfo)
4548 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4550 uint8_t sff8472_rev, addr_mode;
4551 bool page_swap = false;
4553 /* Check whether we support SFF-8472 or not */
4554 status = hw->phy.read_i2c_eeprom(hw,
4555 TXGBE_SFF_SFF_8472_COMP,
4560 /* addressing mode is not supported */
4561 status = hw->phy.read_i2c_eeprom(hw,
4562 TXGBE_SFF_SFF_8472_SWAP,
4567 if (addr_mode & TXGBE_SFF_ADDRESSING_MODE) {
4569 "Address change required to access page 0xA2, "
4570 "but not supported. Please report the module "
4571 "type to the driver maintainers.");
4575 if (sff8472_rev == TXGBE_SFF_SFF_8472_UNSUP || page_swap) {
4576 /* We have a SFP, but it does not support SFF-8472 */
4577 modinfo->type = RTE_ETH_MODULE_SFF_8079;
4578 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
4580 /* We have a SFP which supports a revision of SFF-8472. */
4581 modinfo->type = RTE_ETH_MODULE_SFF_8472;
4582 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
4589 txgbe_get_module_eeprom(struct rte_eth_dev *dev,
4590 struct rte_dev_eeprom_info *info)
4592 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4593 uint32_t status = TXGBE_ERR_PHY_ADDR_INVALID;
4594 uint8_t databyte = 0xFF;
4595 uint8_t *data = info->data;
4598 if (info->length == 0)
4601 for (i = info->offset; i < info->offset + info->length; i++) {
4602 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
4603 status = hw->phy.read_i2c_eeprom(hw, i, &databyte);
4605 status = hw->phy.read_i2c_sff8472(hw, i, &databyte);
4610 data[i - info->offset] = databyte;
4617 txgbe_rss_update_sp(enum txgbe_mac_type mac_type)
4620 case txgbe_mac_raptor:
4621 case txgbe_mac_raptor_vf:
4629 txgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
4630 struct rte_eth_dcb_info *dcb_info)
4632 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
4633 struct txgbe_dcb_tc_config *tc;
4634 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
4638 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
4639 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
4641 dcb_info->nb_tcs = 1;
4643 tc_queue = &dcb_info->tc_queue;
4644 nb_tcs = dcb_info->nb_tcs;
4646 if (dcb_config->vt_mode) { /* vt is enabled */
4647 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
4648 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
4649 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
4650 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
4651 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
4652 for (j = 0; j < nb_tcs; j++) {
4653 tc_queue->tc_rxq[0][j].base = j;
4654 tc_queue->tc_rxq[0][j].nb_queue = 1;
4655 tc_queue->tc_txq[0][j].base = j;
4656 tc_queue->tc_txq[0][j].nb_queue = 1;
4659 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
4660 for (j = 0; j < nb_tcs; j++) {
4661 tc_queue->tc_rxq[i][j].base =
4663 tc_queue->tc_rxq[i][j].nb_queue = 1;
4664 tc_queue->tc_txq[i][j].base =
4666 tc_queue->tc_txq[i][j].nb_queue = 1;
4670 } else { /* vt is disabled */
4671 struct rte_eth_dcb_rx_conf *rx_conf =
4672 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
4673 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
4674 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
4675 if (dcb_info->nb_tcs == ETH_4_TCS) {
4676 for (i = 0; i < dcb_info->nb_tcs; i++) {
4677 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
4678 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4680 dcb_info->tc_queue.tc_txq[0][0].base = 0;
4681 dcb_info->tc_queue.tc_txq[0][1].base = 64;
4682 dcb_info->tc_queue.tc_txq[0][2].base = 96;
4683 dcb_info->tc_queue.tc_txq[0][3].base = 112;
4684 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
4685 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4686 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4687 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4688 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
4689 for (i = 0; i < dcb_info->nb_tcs; i++) {
4690 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
4691 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4693 dcb_info->tc_queue.tc_txq[0][0].base = 0;
4694 dcb_info->tc_queue.tc_txq[0][1].base = 32;
4695 dcb_info->tc_queue.tc_txq[0][2].base = 64;
4696 dcb_info->tc_queue.tc_txq[0][3].base = 80;
4697 dcb_info->tc_queue.tc_txq[0][4].base = 96;
4698 dcb_info->tc_queue.tc_txq[0][5].base = 104;
4699 dcb_info->tc_queue.tc_txq[0][6].base = 112;
4700 dcb_info->tc_queue.tc_txq[0][7].base = 120;
4701 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
4702 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4703 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4704 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4705 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
4706 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
4707 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
4708 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
4711 for (i = 0; i < dcb_info->nb_tcs; i++) {
4712 tc = &dcb_config->tc_config[i];
4713 dcb_info->tc_bws[i] = tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent;
4718 /* Update e-tag ether type */
4720 txgbe_update_e_tag_eth_type(struct txgbe_hw *hw,
4721 uint16_t ether_type)
4723 uint32_t etag_etype;
4725 etag_etype = rd32(hw, TXGBE_EXTAG);
4726 etag_etype &= ~TXGBE_EXTAG_ETAG_MASK;
4727 etag_etype |= ether_type;
4728 wr32(hw, TXGBE_EXTAG, etag_etype);
4734 /* Enable e-tag tunnel */
4736 txgbe_e_tag_enable(struct txgbe_hw *hw)
4738 uint32_t etag_etype;
4740 etag_etype = rd32(hw, TXGBE_PORTCTL);
4741 etag_etype |= TXGBE_PORTCTL_ETAG;
4742 wr32(hw, TXGBE_PORTCTL, etag_etype);
4749 txgbe_e_tag_filter_del(struct rte_eth_dev *dev,
4750 struct txgbe_l2_tunnel_conf *l2_tunnel)
4753 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4754 uint32_t i, rar_entries;
4755 uint32_t rar_low, rar_high;
4757 rar_entries = hw->mac.num_rar_entries;
4759 for (i = 1; i < rar_entries; i++) {
4760 wr32(hw, TXGBE_ETHADDRIDX, i);
4761 rar_high = rd32(hw, TXGBE_ETHADDRH);
4762 rar_low = rd32(hw, TXGBE_ETHADDRL);
4763 if ((rar_high & TXGBE_ETHADDRH_VLD) &&
4764 (rar_high & TXGBE_ETHADDRH_ETAG) &&
4765 (TXGBE_ETHADDRL_ETAG(rar_low) ==
4766 l2_tunnel->tunnel_id)) {
4767 wr32(hw, TXGBE_ETHADDRL, 0);
4768 wr32(hw, TXGBE_ETHADDRH, 0);
4770 txgbe_clear_vmdq(hw, i, BIT_MASK32);
4780 txgbe_e_tag_filter_add(struct rte_eth_dev *dev,
4781 struct txgbe_l2_tunnel_conf *l2_tunnel)
4784 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4785 uint32_t i, rar_entries;
4786 uint32_t rar_low, rar_high;
4788 /* One entry for one tunnel. Try to remove potential existing entry. */
4789 txgbe_e_tag_filter_del(dev, l2_tunnel);
4791 rar_entries = hw->mac.num_rar_entries;
4793 for (i = 1; i < rar_entries; i++) {
4794 wr32(hw, TXGBE_ETHADDRIDX, i);
4795 rar_high = rd32(hw, TXGBE_ETHADDRH);
4796 if (rar_high & TXGBE_ETHADDRH_VLD) {
4799 txgbe_set_vmdq(hw, i, l2_tunnel->pool);
4800 rar_high = TXGBE_ETHADDRH_VLD | TXGBE_ETHADDRH_ETAG;
4801 rar_low = l2_tunnel->tunnel_id;
4803 wr32(hw, TXGBE_ETHADDRL, rar_low);
4804 wr32(hw, TXGBE_ETHADDRH, rar_high);
4810 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
4811 " Please remove a rule before adding a new one.");
4815 static inline struct txgbe_l2_tn_filter *
4816 txgbe_l2_tn_filter_lookup(struct txgbe_l2_tn_info *l2_tn_info,
4817 struct txgbe_l2_tn_key *key)
4821 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
4825 return l2_tn_info->hash_map[ret];
4829 txgbe_insert_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info,
4830 struct txgbe_l2_tn_filter *l2_tn_filter)
4834 ret = rte_hash_add_key(l2_tn_info->hash_handle,
4835 &l2_tn_filter->key);
4839 "Failed to insert L2 tunnel filter"
4840 " to hash table %d!",
4845 l2_tn_info->hash_map[ret] = l2_tn_filter;
4847 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
4853 txgbe_remove_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info,
4854 struct txgbe_l2_tn_key *key)
4857 struct txgbe_l2_tn_filter *l2_tn_filter;
4859 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
4863 "No such L2 tunnel filter to delete %d!",
4868 l2_tn_filter = l2_tn_info->hash_map[ret];
4869 l2_tn_info->hash_map[ret] = NULL;
4871 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
4872 rte_free(l2_tn_filter);
4877 /* Add l2 tunnel filter */
4879 txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
4880 struct txgbe_l2_tunnel_conf *l2_tunnel,
4884 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
4885 struct txgbe_l2_tn_key key;
4886 struct txgbe_l2_tn_filter *node;
4889 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
4890 key.tn_id = l2_tunnel->tunnel_id;
4892 node = txgbe_l2_tn_filter_lookup(l2_tn_info, &key);
4896 "The L2 tunnel filter already exists!");
4900 node = rte_zmalloc("txgbe_l2_tn",
4901 sizeof(struct txgbe_l2_tn_filter),
4906 rte_memcpy(&node->key,
4908 sizeof(struct txgbe_l2_tn_key));
4909 node->pool = l2_tunnel->pool;
4910 ret = txgbe_insert_l2_tn_filter(l2_tn_info, node);
4917 switch (l2_tunnel->l2_tunnel_type) {
4918 case RTE_L2_TUNNEL_TYPE_E_TAG:
4919 ret = txgbe_e_tag_filter_add(dev, l2_tunnel);
4922 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4927 if (!restore && ret < 0)
4928 (void)txgbe_remove_l2_tn_filter(l2_tn_info, &key);
4933 /* Delete l2 tunnel filter */
4935 txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
4936 struct txgbe_l2_tunnel_conf *l2_tunnel)
4939 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
4940 struct txgbe_l2_tn_key key;
4942 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
4943 key.tn_id = l2_tunnel->tunnel_id;
4944 ret = txgbe_remove_l2_tn_filter(l2_tn_info, &key);
4948 switch (l2_tunnel->l2_tunnel_type) {
4949 case RTE_L2_TUNNEL_TYPE_E_TAG:
4950 ret = txgbe_e_tag_filter_del(dev, l2_tunnel);
4953 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4962 txgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
4966 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4968 ctrl = rd32(hw, TXGBE_POOLCTL);
4969 ctrl &= ~TXGBE_POOLCTL_MODE_MASK;
4971 ctrl |= TXGBE_PSRPOOL_MODE_ETAG;
4972 wr32(hw, TXGBE_POOLCTL, ctrl);
4977 /* Add UDP tunneling port */
4979 txgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4980 struct rte_eth_udp_tunnel *udp_tunnel)
4982 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4985 if (udp_tunnel == NULL)
4988 switch (udp_tunnel->prot_type) {
4989 case RTE_TUNNEL_TYPE_VXLAN:
4990 if (udp_tunnel->udp_port == 0) {
4991 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
4995 wr32(hw, TXGBE_VXLANPORT, udp_tunnel->udp_port);
4996 wr32(hw, TXGBE_VXLANPORTGPE, udp_tunnel->udp_port);
4998 case RTE_TUNNEL_TYPE_GENEVE:
4999 if (udp_tunnel->udp_port == 0) {
5000 PMD_DRV_LOG(ERR, "Add Geneve port 0 is not allowed.");
5004 wr32(hw, TXGBE_GENEVEPORT, udp_tunnel->udp_port);
5006 case RTE_TUNNEL_TYPE_TEREDO:
5007 if (udp_tunnel->udp_port == 0) {
5008 PMD_DRV_LOG(ERR, "Add Teredo port 0 is not allowed.");
5012 wr32(hw, TXGBE_TEREDOPORT, udp_tunnel->udp_port);
5015 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5025 /* Remove UDP tunneling port */
5027 txgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5028 struct rte_eth_udp_tunnel *udp_tunnel)
5030 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5034 if (udp_tunnel == NULL)
5037 switch (udp_tunnel->prot_type) {
5038 case RTE_TUNNEL_TYPE_VXLAN:
5039 cur_port = (uint16_t)rd32(hw, TXGBE_VXLANPORT);
5040 if (cur_port != udp_tunnel->udp_port) {
5041 PMD_DRV_LOG(ERR, "Port %u does not exist.",
5042 udp_tunnel->udp_port);
5046 wr32(hw, TXGBE_VXLANPORT, 0);
5047 wr32(hw, TXGBE_VXLANPORTGPE, 0);
5049 case RTE_TUNNEL_TYPE_GENEVE:
5050 cur_port = (uint16_t)rd32(hw, TXGBE_GENEVEPORT);
5051 if (cur_port != udp_tunnel->udp_port) {
5052 PMD_DRV_LOG(ERR, "Port %u does not exist.",
5053 udp_tunnel->udp_port);
5057 wr32(hw, TXGBE_GENEVEPORT, 0);
5059 case RTE_TUNNEL_TYPE_TEREDO:
5060 cur_port = (uint16_t)rd32(hw, TXGBE_TEREDOPORT);
5061 if (cur_port != udp_tunnel->udp_port) {
5062 PMD_DRV_LOG(ERR, "Port %u does not exist.",
5063 udp_tunnel->udp_port);
5067 wr32(hw, TXGBE_TEREDOPORT, 0);
5070 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5080 /* restore n-tuple filter */
5082 txgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
5084 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5085 struct txgbe_5tuple_filter *node;
5087 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
5088 txgbe_inject_5tuple_filter(dev, node);
5092 /* restore ethernet type filter */
5094 txgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
5096 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5097 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5100 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
5101 if (filter_info->ethertype_mask & (1 << i)) {
5102 wr32(hw, TXGBE_ETFLT(i),
5103 filter_info->ethertype_filters[i].etqf);
5104 wr32(hw, TXGBE_ETCLS(i),
5105 filter_info->ethertype_filters[i].etqs);
5111 /* restore SYN filter */
5113 txgbe_syn_filter_restore(struct rte_eth_dev *dev)
5115 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5116 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5119 synqf = filter_info->syn_info;
5121 if (synqf & TXGBE_SYNCLS_ENA) {
5122 wr32(hw, TXGBE_SYNCLS, synqf);
5127 /* restore L2 tunnel filter */
5129 txgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
5131 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
5132 struct txgbe_l2_tn_filter *node;
5133 struct txgbe_l2_tunnel_conf l2_tn_conf;
5135 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
5136 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
5137 l2_tn_conf.tunnel_id = node->key.tn_id;
5138 l2_tn_conf.pool = node->pool;
5139 (void)txgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
5143 /* restore rss filter */
5145 txgbe_rss_filter_restore(struct rte_eth_dev *dev)
5147 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5149 if (filter_info->rss_info.conf.queue_num)
5150 txgbe_config_rss_filter(dev,
5151 &filter_info->rss_info, TRUE);
5155 txgbe_filter_restore(struct rte_eth_dev *dev)
5157 txgbe_ntuple_filter_restore(dev);
5158 txgbe_ethertype_filter_restore(dev);
5159 txgbe_syn_filter_restore(dev);
5160 txgbe_fdir_filter_restore(dev);
5161 txgbe_l2_tn_filter_restore(dev);
5162 txgbe_rss_filter_restore(dev);
5168 txgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
5170 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
5171 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5173 if (l2_tn_info->e_tag_en)
5174 (void)txgbe_e_tag_enable(hw);
5176 if (l2_tn_info->e_tag_fwd_en)
5177 (void)txgbe_e_tag_forwarding_en_dis(dev, 1);
5179 (void)txgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
5182 /* remove all the n-tuple filters */
5184 txgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
5186 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5187 struct txgbe_5tuple_filter *p_5tuple;
5189 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
5190 txgbe_remove_5tuple_filter(dev, p_5tuple);
5193 /* remove all the ether type filters */
5195 txgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
5197 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5198 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5201 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
5202 if (filter_info->ethertype_mask & (1 << i) &&
5203 !filter_info->ethertype_filters[i].conf) {
5204 (void)txgbe_ethertype_filter_remove(filter_info,
5206 wr32(hw, TXGBE_ETFLT(i), 0);
5207 wr32(hw, TXGBE_ETCLS(i), 0);
5213 /* remove the SYN filter */
5215 txgbe_clear_syn_filter(struct rte_eth_dev *dev)
5217 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5218 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5220 if (filter_info->syn_info & TXGBE_SYNCLS_ENA) {
5221 filter_info->syn_info = 0;
5223 wr32(hw, TXGBE_SYNCLS, 0);
5228 /* remove all the L2 tunnel filters */
5230 txgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
5232 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
5233 struct txgbe_l2_tn_filter *l2_tn_filter;
5234 struct txgbe_l2_tunnel_conf l2_tn_conf;
5237 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
5238 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
5239 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
5240 l2_tn_conf.pool = l2_tn_filter->pool;
5241 ret = txgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
5249 static const struct eth_dev_ops txgbe_eth_dev_ops = {
5250 .dev_configure = txgbe_dev_configure,
5251 .dev_infos_get = txgbe_dev_info_get,
5252 .dev_start = txgbe_dev_start,
5253 .dev_stop = txgbe_dev_stop,
5254 .dev_set_link_up = txgbe_dev_set_link_up,
5255 .dev_set_link_down = txgbe_dev_set_link_down,
5256 .dev_close = txgbe_dev_close,
5257 .dev_reset = txgbe_dev_reset,
5258 .promiscuous_enable = txgbe_dev_promiscuous_enable,
5259 .promiscuous_disable = txgbe_dev_promiscuous_disable,
5260 .allmulticast_enable = txgbe_dev_allmulticast_enable,
5261 .allmulticast_disable = txgbe_dev_allmulticast_disable,
5262 .link_update = txgbe_dev_link_update,
5263 .stats_get = txgbe_dev_stats_get,
5264 .xstats_get = txgbe_dev_xstats_get,
5265 .xstats_get_by_id = txgbe_dev_xstats_get_by_id,
5266 .stats_reset = txgbe_dev_stats_reset,
5267 .xstats_reset = txgbe_dev_xstats_reset,
5268 .xstats_get_names = txgbe_dev_xstats_get_names,
5269 .xstats_get_names_by_id = txgbe_dev_xstats_get_names_by_id,
5270 .queue_stats_mapping_set = txgbe_dev_queue_stats_mapping_set,
5271 .fw_version_get = txgbe_fw_version_get,
5272 .dev_supported_ptypes_get = txgbe_dev_supported_ptypes_get,
5273 .mtu_set = txgbe_dev_mtu_set,
5274 .vlan_filter_set = txgbe_vlan_filter_set,
5275 .vlan_tpid_set = txgbe_vlan_tpid_set,
5276 .vlan_offload_set = txgbe_vlan_offload_set,
5277 .vlan_strip_queue_set = txgbe_vlan_strip_queue_set,
5278 .rx_queue_start = txgbe_dev_rx_queue_start,
5279 .rx_queue_stop = txgbe_dev_rx_queue_stop,
5280 .tx_queue_start = txgbe_dev_tx_queue_start,
5281 .tx_queue_stop = txgbe_dev_tx_queue_stop,
5282 .rx_queue_setup = txgbe_dev_rx_queue_setup,
5283 .rx_queue_intr_enable = txgbe_dev_rx_queue_intr_enable,
5284 .rx_queue_intr_disable = txgbe_dev_rx_queue_intr_disable,
5285 .rx_queue_release = txgbe_dev_rx_queue_release,
5286 .tx_queue_setup = txgbe_dev_tx_queue_setup,
5287 .tx_queue_release = txgbe_dev_tx_queue_release,
5288 .dev_led_on = txgbe_dev_led_on,
5289 .dev_led_off = txgbe_dev_led_off,
5290 .flow_ctrl_get = txgbe_flow_ctrl_get,
5291 .flow_ctrl_set = txgbe_flow_ctrl_set,
5292 .priority_flow_ctrl_set = txgbe_priority_flow_ctrl_set,
5293 .mac_addr_add = txgbe_add_rar,
5294 .mac_addr_remove = txgbe_remove_rar,
5295 .mac_addr_set = txgbe_set_default_mac_addr,
5296 .uc_hash_table_set = txgbe_uc_hash_table_set,
5297 .uc_all_hash_table_set = txgbe_uc_all_hash_table_set,
5298 .set_queue_rate_limit = txgbe_set_queue_rate_limit,
5299 .reta_update = txgbe_dev_rss_reta_update,
5300 .reta_query = txgbe_dev_rss_reta_query,
5301 .rss_hash_update = txgbe_dev_rss_hash_update,
5302 .rss_hash_conf_get = txgbe_dev_rss_hash_conf_get,
5303 .flow_ops_get = txgbe_dev_flow_ops_get,
5304 .set_mc_addr_list = txgbe_dev_set_mc_addr_list,
5305 .rxq_info_get = txgbe_rxq_info_get,
5306 .txq_info_get = txgbe_txq_info_get,
5307 .timesync_enable = txgbe_timesync_enable,
5308 .timesync_disable = txgbe_timesync_disable,
5309 .timesync_read_rx_timestamp = txgbe_timesync_read_rx_timestamp,
5310 .timesync_read_tx_timestamp = txgbe_timesync_read_tx_timestamp,
5311 .get_reg = txgbe_get_regs,
5312 .get_eeprom_length = txgbe_get_eeprom_length,
5313 .get_eeprom = txgbe_get_eeprom,
5314 .set_eeprom = txgbe_set_eeprom,
5315 .get_module_info = txgbe_get_module_info,
5316 .get_module_eeprom = txgbe_get_module_eeprom,
5317 .get_dcb_info = txgbe_dev_get_dcb_info,
5318 .timesync_adjust_time = txgbe_timesync_adjust_time,
5319 .timesync_read_time = txgbe_timesync_read_time,
5320 .timesync_write_time = txgbe_timesync_write_time,
5321 .udp_tunnel_port_add = txgbe_dev_udp_tunnel_port_add,
5322 .udp_tunnel_port_del = txgbe_dev_udp_tunnel_port_del,
5323 .tm_ops_get = txgbe_tm_ops_get,
5324 .tx_done_cleanup = txgbe_dev_tx_done_cleanup,
5327 RTE_PMD_REGISTER_PCI(net_txgbe, rte_txgbe_pmd);
5328 RTE_PMD_REGISTER_PCI_TABLE(net_txgbe, pci_id_txgbe_map);
5329 RTE_PMD_REGISTER_KMOD_DEP(net_txgbe, "* igb_uio | uio_pci_generic | vfio-pci");
5330 RTE_PMD_REGISTER_PARAM_STRING(net_txgbe,
5331 TXGBE_DEVARG_BP_AUTO "=<0|1>"
5332 TXGBE_DEVARG_KR_POLL "=<0|1>"
5333 TXGBE_DEVARG_KR_PRESENT "=<0|1>"
5334 TXGBE_DEVARG_KX_SGMII "=<0|1>"
5335 TXGBE_DEVARG_FFE_SET "=<0-4>"
5336 TXGBE_DEVARG_FFE_MAIN "=<uint16>"
5337 TXGBE_DEVARG_FFE_PRE "=<uint16>"
5338 TXGBE_DEVARG_FFE_POST "=<uint16>");
5340 RTE_LOG_REGISTER(txgbe_logtype_init, pmd.net.txgbe.init, NOTICE);
5341 RTE_LOG_REGISTER(txgbe_logtype_driver, pmd.net.txgbe.driver, NOTICE);
5342 RTE_LOG_REGISTER(txgbe_logtype_bp, pmd.net.txgbe.bp, NOTICE);
5344 #ifdef RTE_LIBRTE_TXGBE_DEBUG_RX
5345 RTE_LOG_REGISTER(txgbe_logtype_rx, pmd.net.txgbe.rx, DEBUG);
5347 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX
5348 RTE_LOG_REGISTER(txgbe_logtype_tx, pmd.net.txgbe.tx, DEBUG);
5351 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX_FREE
5352 RTE_LOG_REGISTER(txgbe_logtype_tx_free, pmd.net.txgbe.tx_free, DEBUG);