1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
5 #ifndef _TXGBE_ETHDEV_H_
6 #define _TXGBE_ETHDEV_H_
10 #include "base/txgbe.h"
11 #include "txgbe_ptypes.h"
13 #include <rte_flow_driver.h>
15 #include <rte_ethdev.h>
16 #include <rte_ethdev_core.h>
18 #include <rte_hash_crc.h>
20 /* need update link, bit flag */
21 #define TXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
22 #define TXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
23 #define TXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
24 #define TXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
25 #define TXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
28 * Defines that were not part of txgbe_type.h as they are not used by the
31 #define TXGBE_VFTA_SIZE 128
32 #define TXGBE_VLAN_TAG_SIZE 4
33 #define TXGBE_HKEY_MAX_INDEX 10
34 /*Default value of Max Rx Queue*/
35 #define TXGBE_MAX_RX_QUEUE_NUM 128
36 #define TXGBE_VMDQ_DCB_NB_QUEUES TXGBE_MAX_RX_QUEUE_NUM
39 #define NBBY 8 /* number of bits in a byte */
41 #define TXGBE_HWSTRIP_BITMAP_SIZE \
42 (TXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
44 #define TXGBE_QUEUE_ITR_INTERVAL_DEFAULT 500 /* 500us */
46 #define TXGBE_MAX_QUEUE_NUM_PER_VF 8
48 #define TXGBE_5TUPLE_MAX_PRI 7
49 #define TXGBE_5TUPLE_MIN_PRI 1
51 #define TXGBE_RSS_OFFLOAD_ALL ( \
53 ETH_RSS_NONFRAG_IPV4_TCP | \
54 ETH_RSS_NONFRAG_IPV4_UDP | \
56 ETH_RSS_NONFRAG_IPV6_TCP | \
57 ETH_RSS_NONFRAG_IPV6_UDP | \
59 ETH_RSS_IPV6_TCP_EX | \
62 #define TXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
63 #define TXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
65 #define TXGBE_MAX_FDIR_FILTER_NUM (1024 * 32)
66 #define TXGBE_MAX_L2_TN_FILTER_NUM 128
69 * Information about the fdir mode.
71 struct txgbe_hw_fdir_mask {
72 uint16_t vlan_tci_mask;
73 uint32_t src_ipv4_mask;
74 uint32_t dst_ipv4_mask;
75 uint16_t src_ipv6_mask;
76 uint16_t dst_ipv6_mask;
77 uint16_t src_port_mask;
78 uint16_t dst_port_mask;
79 uint16_t flex_bytes_mask;
80 uint8_t mac_addr_byte_mask;
81 uint32_t tunnel_id_mask;
82 uint8_t tunnel_type_mask;
85 struct txgbe_fdir_filter {
86 TAILQ_ENTRY(txgbe_fdir_filter) entries;
87 struct txgbe_atr_input input; /* key of fdir filter*/
88 uint32_t fdirflags; /* drop or forward */
89 uint32_t fdirhash; /* hash value for fdir */
90 uint8_t queue; /* assigned rx queue */
93 /* list of fdir filters */
94 TAILQ_HEAD(txgbe_fdir_filter_list, txgbe_fdir_filter);
96 struct txgbe_fdir_rule {
97 struct txgbe_hw_fdir_mask mask;
98 struct txgbe_atr_input input; /* key of fdir filter */
99 bool b_spec; /* If TRUE, input, fdirflags, queue have meaning. */
100 bool b_mask; /* If TRUE, mask has meaning. */
101 enum rte_fdir_mode mode; /* IP, MAC VLAN, Tunnel */
102 uint32_t fdirflags; /* drop or forward */
103 uint32_t soft_id; /* an unique value for this rule */
104 uint8_t queue; /* assigned rx queue */
105 uint8_t flex_bytes_offset;
108 struct txgbe_hw_fdir_info {
109 struct txgbe_hw_fdir_mask mask;
110 uint8_t flex_bytes_offset;
119 struct txgbe_fdir_filter_list fdir_list; /* filter list*/
120 /* store the pointers of the filters, index is the hash value. */
121 struct txgbe_fdir_filter **hash_map;
122 struct rte_hash *hash_handle; /* cuckoo hash handler */
123 bool mask_added; /* If already got mask from consistent filter */
126 struct txgbe_rte_flow_rss_conf {
127 struct rte_flow_action_rss conf; /**< RSS parameters. */
128 uint8_t key[TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t)]; /* Hash key. */
129 uint16_t queue[TXGBE_MAX_RX_QUEUE_NUM]; /**< Queues indices to use. */
132 /* structure for interrupt relative data */
133 struct txgbe_interrupt {
136 /* to save original mask during delayed handler */
137 uint32_t mask_misc_orig;
141 #define TXGBE_NB_STAT_MAPPING 32
142 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
143 #define NB_QMAP_FIELDS_PER_QSM_REG 4
144 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
145 struct txgbe_stat_mappings {
146 uint32_t tqsm[TXGBE_NB_STAT_MAPPING];
147 uint32_t rqsm[TXGBE_NB_STAT_MAPPING];
151 uint32_t vfta[TXGBE_VFTA_SIZE];
154 struct txgbe_hwstrip {
155 uint32_t bitmap[TXGBE_HWSTRIP_BITMAP_SIZE];
159 * VF data which used by PF host only
161 #define TXGBE_MAX_VF_MC_ENTRIES 30
163 struct txgbe_uta_info {
164 uint8_t uc_filter_type;
166 uint32_t uta_shadow[TXGBE_MAX_UTA];
169 #define TXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
171 struct txgbe_mirror_info {
172 struct rte_eth_mirror_conf mr_conf[TXGBE_MAX_MIRROR_RULES];
173 /* store PF mirror rules configuration */
176 struct txgbe_vf_info {
177 uint8_t vf_mac_addresses[RTE_ETHER_ADDR_LEN];
178 uint16_t vf_mc_hashes[TXGBE_MAX_VF_MC_ENTRIES];
179 uint16_t num_vf_mc_hashes;
181 uint16_t tx_rate[TXGBE_MAX_QUEUE_NUM_PER_VF];
184 uint16_t switch_domain_id;
189 TAILQ_HEAD(txgbe_5tuple_filter_list, txgbe_5tuple_filter);
191 struct txgbe_5tuple_filter_info {
196 enum txgbe_5tuple_protocol proto; /* l4 protocol. */
197 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
198 * used when more than one filter matches.
200 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
201 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
202 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
203 src_port_mask:1, /* if mask is 1b, do not compare src port. */
204 proto_mask:1; /* if mask is 1b, do not compare protocol. */
207 /* 5tuple filter structure */
208 struct txgbe_5tuple_filter {
209 TAILQ_ENTRY(txgbe_5tuple_filter) entries;
210 uint16_t index; /* the index of 5tuple filter */
211 struct txgbe_5tuple_filter_info filter_info;
212 uint16_t queue; /* rx queue assigned to */
215 #define TXGBE_5TUPLE_ARRAY_SIZE \
216 (RTE_ALIGN(TXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
217 (sizeof(uint32_t) * NBBY))
219 struct txgbe_ethertype_filter {
224 * If this filter is added by configuration,
225 * it should not be removed.
231 * Structure to store filters' info.
233 struct txgbe_filter_info {
234 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
235 /* store used ethertype filters*/
236 struct txgbe_ethertype_filter ethertype_filters[TXGBE_ETF_ID_MAX];
237 /* Bit mask for every used 5tuple filter */
238 uint32_t fivetuple_mask[TXGBE_5TUPLE_ARRAY_SIZE];
239 struct txgbe_5tuple_filter_list fivetuple_list;
240 /* store the SYN filter info */
242 /* store the rss filter info */
243 struct txgbe_rte_flow_rss_conf rss_info;
246 struct txgbe_l2_tn_key {
247 enum rte_eth_tunnel_type l2_tn_type;
251 struct txgbe_l2_tn_filter {
252 TAILQ_ENTRY(txgbe_l2_tn_filter) entries;
253 struct txgbe_l2_tn_key key;
257 TAILQ_HEAD(txgbe_l2_tn_filter_list, txgbe_l2_tn_filter);
259 struct txgbe_l2_tn_info {
260 struct txgbe_l2_tn_filter_list l2_tn_list;
261 struct txgbe_l2_tn_filter **hash_map;
262 struct rte_hash *hash_handle;
263 bool e_tag_en; /* e-tag enabled */
264 bool e_tag_fwd_en; /* e-tag based forwarding enabled */
265 uint16_t e_tag_ether_type; /* ether type for e-tag */
269 enum rte_filter_type filter_type;
273 /* The configuration of bandwidth */
274 struct txgbe_bw_conf {
275 uint8_t tc_num; /* Number of TCs. */
279 * Structure to store private data for each driver instance (for each port).
281 struct txgbe_adapter {
283 struct txgbe_hw_stats stats;
284 struct txgbe_hw_fdir_info fdir;
285 struct txgbe_interrupt intr;
286 struct txgbe_stat_mappings stat_mappings;
287 struct txgbe_vfta shadow_vfta;
288 struct txgbe_hwstrip hwstrip;
289 struct txgbe_dcb_config dcb_config;
290 struct txgbe_mirror_info mr_data;
291 struct txgbe_vf_info *vfdata;
292 struct txgbe_uta_info uta_info;
293 struct txgbe_filter_info filter;
294 struct txgbe_l2_tn_info l2_tn;
295 struct txgbe_bw_conf bw_conf;
296 bool rx_bulk_alloc_allowed;
297 struct rte_timecounter systime_tc;
298 struct rte_timecounter rx_tstamp_tc;
299 struct rte_timecounter tx_tstamp_tc;
301 /* For RSS reta table update */
302 uint8_t rss_reta_updated;
305 #define TXGBE_DEV_ADAPTER(dev) \
306 ((struct txgbe_adapter *)(dev)->data->dev_private)
308 #define TXGBE_DEV_HW(dev) \
309 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hw)
311 #define TXGBE_DEV_STATS(dev) \
312 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stats)
314 #define TXGBE_DEV_INTR(dev) \
315 (&((struct txgbe_adapter *)(dev)->data->dev_private)->intr)
317 #define TXGBE_DEV_FDIR(dev) \
318 (&((struct txgbe_adapter *)(dev)->data->dev_private)->fdir)
320 #define TXGBE_DEV_STAT_MAPPINGS(dev) \
321 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stat_mappings)
323 #define TXGBE_DEV_VFTA(dev) \
324 (&((struct txgbe_adapter *)(dev)->data->dev_private)->shadow_vfta)
326 #define TXGBE_DEV_HWSTRIP(dev) \
327 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hwstrip)
329 #define TXGBE_DEV_DCB_CONFIG(dev) \
330 (&((struct txgbe_adapter *)(dev)->data->dev_private)->dcb_config)
332 #define TXGBE_DEV_VFDATA(dev) \
333 (&((struct txgbe_adapter *)(dev)->data->dev_private)->vfdata)
335 #define TXGBE_DEV_MR_INFO(dev) \
336 (&((struct txgbe_adapter *)(dev)->data->dev_private)->mr_data)
338 #define TXGBE_DEV_UTA_INFO(dev) \
339 (&((struct txgbe_adapter *)(dev)->data->dev_private)->uta_info)
341 #define TXGBE_DEV_FILTER(dev) \
342 (&((struct txgbe_adapter *)(dev)->data->dev_private)->filter)
344 #define TXGBE_DEV_L2_TN(dev) \
345 (&((struct txgbe_adapter *)(dev)->data->dev_private)->l2_tn)
347 #define TXGBE_DEV_BW_CONF(dev) \
348 (&((struct txgbe_adapter *)(dev)->data->dev_private)->bw_conf)
352 * RX/TX function prototypes
354 void txgbe_dev_clear_queues(struct rte_eth_dev *dev);
356 void txgbe_dev_free_queues(struct rte_eth_dev *dev);
358 void txgbe_dev_rx_queue_release(void *rxq);
360 void txgbe_dev_tx_queue_release(void *txq);
362 int txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
363 uint16_t nb_rx_desc, unsigned int socket_id,
364 const struct rte_eth_rxconf *rx_conf,
365 struct rte_mempool *mb_pool);
367 int txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
368 uint16_t nb_tx_desc, unsigned int socket_id,
369 const struct rte_eth_txconf *tx_conf);
371 uint32_t txgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
372 uint16_t rx_queue_id);
374 int txgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
375 int txgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
377 int txgbe_dev_rx_init(struct rte_eth_dev *dev);
379 void txgbe_dev_tx_init(struct rte_eth_dev *dev);
381 int txgbe_dev_rxtx_start(struct rte_eth_dev *dev);
383 void txgbe_dev_save_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
384 void txgbe_dev_store_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
385 void txgbe_dev_save_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
386 void txgbe_dev_store_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
388 int txgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
390 int txgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
392 int txgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
394 int txgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
396 void txgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
397 struct rte_eth_rxq_info *qinfo);
399 void txgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
400 struct rte_eth_txq_info *qinfo);
402 uint16_t txgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
405 uint16_t txgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
408 uint16_t txgbe_recv_pkts_lro_single_alloc(void *rx_queue,
409 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
410 uint16_t txgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
411 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
413 uint16_t txgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
416 uint16_t txgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
419 uint16_t txgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
422 int txgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
423 struct rte_eth_rss_conf *rss_conf);
425 int txgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
426 struct rte_eth_rss_conf *rss_conf);
428 bool txgbe_rss_update_sp(enum txgbe_mac_type mac_type);
430 int txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
431 struct rte_eth_ntuple_filter *filter,
433 int txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
434 struct rte_eth_ethertype_filter *filter,
436 int txgbe_syn_filter_set(struct rte_eth_dev *dev,
437 struct rte_eth_syn_filter *filter,
441 * l2 tunnel configuration.
443 struct txgbe_l2_tunnel_conf {
444 enum rte_eth_tunnel_type l2_tunnel_type;
445 uint16_t ether_type; /* ether type in l2 header */
446 uint32_t tunnel_id; /* port tag id for e-tag */
447 uint16_t vf_id; /* VF id for tag insertion */
448 uint32_t pool; /* destination pool for tag based forwarding */
452 txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
453 struct txgbe_l2_tunnel_conf *l2_tunnel,
456 txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
457 struct txgbe_l2_tunnel_conf *l2_tunnel);
458 void txgbe_filterlist_init(void);
459 void txgbe_filterlist_flush(void);
461 void txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
462 uint8_t queue, uint8_t msix_vector);
465 * Flow director function prototypes
467 int txgbe_fdir_configure(struct rte_eth_dev *dev);
468 int txgbe_fdir_set_input_mask(struct rte_eth_dev *dev);
469 int txgbe_fdir_set_flexbytes_offset(struct rte_eth_dev *dev,
471 int txgbe_fdir_filter_program(struct rte_eth_dev *dev,
472 struct txgbe_fdir_rule *rule,
473 bool del, bool update);
475 void txgbe_configure_pb(struct rte_eth_dev *dev);
476 void txgbe_configure_port(struct rte_eth_dev *dev);
477 void txgbe_configure_dcb(struct rte_eth_dev *dev);
480 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
481 int wait_to_complete);
482 int txgbe_pf_host_init(struct rte_eth_dev *eth_dev);
484 void txgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
486 void txgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
488 int txgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
490 uint32_t txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
492 void txgbe_fdir_filter_restore(struct rte_eth_dev *dev);
493 int txgbe_clear_all_fdir_filter(struct rte_eth_dev *dev);
495 extern const struct rte_flow_ops txgbe_flow_ops;
497 void txgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev);
498 void txgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev);
499 void txgbe_clear_syn_filter(struct rte_eth_dev *dev);
500 int txgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev);
502 int txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
503 uint16_t tx_rate, uint64_t q_msk);
504 int txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx,
506 int txgbe_rss_conf_init(struct txgbe_rte_flow_rss_conf *out,
507 const struct rte_flow_action_rss *in);
508 int txgbe_action_rss_same(const struct rte_flow_action_rss *comp,
509 const struct rte_flow_action_rss *with);
510 int txgbe_config_rss_filter(struct rte_eth_dev *dev,
511 struct txgbe_rte_flow_rss_conf *conf, bool add);
514 txgbe_ethertype_filter_lookup(struct txgbe_filter_info *filter_info,
519 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
520 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
521 (filter_info->ethertype_mask & (1 << i)))
528 txgbe_ethertype_filter_insert(struct txgbe_filter_info *filter_info,
529 struct txgbe_ethertype_filter *ethertype_filter)
533 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
534 if (filter_info->ethertype_mask & (1 << i))
537 filter_info->ethertype_mask |= 1 << i;
538 filter_info->ethertype_filters[i].ethertype =
539 ethertype_filter->ethertype;
540 filter_info->ethertype_filters[i].etqf =
541 ethertype_filter->etqf;
542 filter_info->ethertype_filters[i].etqs =
543 ethertype_filter->etqs;
544 filter_info->ethertype_filters[i].conf =
545 ethertype_filter->conf;
548 return (i < TXGBE_ETF_ID_MAX ? i : -1);
552 txgbe_ethertype_filter_remove(struct txgbe_filter_info *filter_info,
555 if (idx >= TXGBE_ETF_ID_MAX)
557 filter_info->ethertype_mask &= ~(1 << idx);
558 filter_info->ethertype_filters[idx].ethertype = 0;
559 filter_info->ethertype_filters[idx].etqf = 0;
560 filter_info->ethertype_filters[idx].etqs = 0;
561 filter_info->ethertype_filters[idx].etqs = FALSE;
565 /* High threshold controlling when to start sending XOFF frames. */
566 #define TXGBE_FC_XOFF_HITH 128 /*KB*/
567 /* Low threshold controlling when to start sending XON frames. */
568 #define TXGBE_FC_XON_LOTH 64 /*KB*/
570 /* Timer value included in XOFF frames. */
571 #define TXGBE_FC_PAUSE_TIME 0x680
573 #define TXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
574 #define TXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
575 #define TXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
578 * Default values for RX/TX configuration
580 #define TXGBE_DEFAULT_RX_FREE_THRESH 32
581 #define TXGBE_DEFAULT_RX_PTHRESH 8
582 #define TXGBE_DEFAULT_RX_HTHRESH 8
583 #define TXGBE_DEFAULT_RX_WTHRESH 0
585 #define TXGBE_DEFAULT_TX_FREE_THRESH 32
586 #define TXGBE_DEFAULT_TX_PTHRESH 32
587 #define TXGBE_DEFAULT_TX_HTHRESH 0
588 #define TXGBE_DEFAULT_TX_WTHRESH 0
590 /* Additional timesync values. */
591 #define NSEC_PER_SEC 1000000000L
592 #define TXGBE_INCVAL_10GB 0xCCCCCC
593 #define TXGBE_INCVAL_1GB 0x800000
594 #define TXGBE_INCVAL_100 0xA00000
595 #define TXGBE_INCVAL_10 0xC7F380
596 #define TXGBE_INCVAL_FPGA 0x800000
597 #define TXGBE_INCVAL_SHIFT_10GB 20
598 #define TXGBE_INCVAL_SHIFT_1GB 18
599 #define TXGBE_INCVAL_SHIFT_100 15
600 #define TXGBE_INCVAL_SHIFT_10 12
601 #define TXGBE_INCVAL_SHIFT_FPGA 17
603 #define TXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
605 /* store statistics names and its offset in stats structure */
606 struct rte_txgbe_xstats_name_off {
607 char name[RTE_ETH_XSTATS_NAME_SIZE];
611 const uint32_t *txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
612 int txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
613 struct rte_ether_addr *mc_addr_set,
614 uint32_t nb_mc_addr);
615 int txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
616 struct rte_eth_rss_reta_entry64 *reta_conf,
618 int txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
619 struct rte_eth_rss_reta_entry64 *reta_conf,
621 void txgbe_dev_setup_link_alarm_handler(void *param);
622 void txgbe_read_stats_registers(struct txgbe_hw *hw,
623 struct txgbe_hw_stats *hw_stats);
625 void txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
626 void txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
627 void txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev);
628 void txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
629 uint16_t queue, bool on);
630 void txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
633 #endif /* _TXGBE_ETHDEV_H_ */