1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
5 #ifndef _TXGBE_ETHDEV_H_
6 #define _TXGBE_ETHDEV_H_
10 #include "base/txgbe.h"
11 #include "txgbe_ptypes.h"
13 #include <rte_flow_driver.h>
15 #include <rte_ethdev.h>
16 #include <rte_ethdev_core.h>
18 #include <rte_hash_crc.h>
20 /* need update link, bit flag */
21 #define TXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
22 #define TXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
23 #define TXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
24 #define TXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
25 #define TXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
28 * Defines that were not part of txgbe_type.h as they are not used by the
31 #define TXGBE_VFTA_SIZE 128
32 #define TXGBE_VLAN_TAG_SIZE 4
33 #define TXGBE_HKEY_MAX_INDEX 10
34 /*Default value of Max Rx Queue*/
35 #define TXGBE_MAX_RX_QUEUE_NUM 128
36 #define TXGBE_VMDQ_DCB_NB_QUEUES TXGBE_MAX_RX_QUEUE_NUM
39 #define NBBY 8 /* number of bits in a byte */
41 #define TXGBE_HWSTRIP_BITMAP_SIZE \
42 (TXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
44 #define TXGBE_QUEUE_ITR_INTERVAL_DEFAULT 500 /* 500us */
46 #define TXGBE_MAX_QUEUE_NUM_PER_VF 8
48 #define TXGBE_5TUPLE_MAX_PRI 7
49 #define TXGBE_5TUPLE_MIN_PRI 1
51 #define TXGBE_RSS_OFFLOAD_ALL ( \
53 ETH_RSS_NONFRAG_IPV4_TCP | \
54 ETH_RSS_NONFRAG_IPV4_UDP | \
56 ETH_RSS_NONFRAG_IPV6_TCP | \
57 ETH_RSS_NONFRAG_IPV6_UDP | \
59 ETH_RSS_IPV6_TCP_EX | \
62 #define TXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
63 #define TXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
65 #define TXGBE_MAX_FDIR_FILTER_NUM (1024 * 32)
66 #define TXGBE_MAX_L2_TN_FILTER_NUM 128
69 * Information about the fdir mode.
71 struct txgbe_hw_fdir_mask {
72 uint16_t vlan_tci_mask;
73 uint32_t src_ipv4_mask;
74 uint32_t dst_ipv4_mask;
75 uint16_t src_ipv6_mask;
76 uint16_t dst_ipv6_mask;
77 uint16_t src_port_mask;
78 uint16_t dst_port_mask;
79 uint16_t flex_bytes_mask;
80 uint8_t mac_addr_byte_mask;
81 uint32_t tunnel_id_mask;
82 uint8_t tunnel_type_mask;
85 struct txgbe_fdir_filter {
86 TAILQ_ENTRY(txgbe_fdir_filter) entries;
87 struct txgbe_atr_input input; /* key of fdir filter*/
88 uint32_t fdirflags; /* drop or forward */
89 uint32_t fdirhash; /* hash value for fdir */
90 uint8_t queue; /* assigned rx queue */
93 /* list of fdir filters */
94 TAILQ_HEAD(txgbe_fdir_filter_list, txgbe_fdir_filter);
96 struct txgbe_hw_fdir_info {
97 struct txgbe_hw_fdir_mask mask;
98 uint8_t flex_bytes_offset;
107 struct txgbe_fdir_filter_list fdir_list; /* filter list*/
108 /* store the pointers of the filters, index is the hash value. */
109 struct txgbe_fdir_filter **hash_map;
110 struct rte_hash *hash_handle; /* cuckoo hash handler */
111 bool mask_added; /* If already got mask from consistent filter */
114 /* structure for interrupt relative data */
115 struct txgbe_interrupt {
118 /* to save original mask during delayed handler */
119 uint32_t mask_misc_orig;
123 #define TXGBE_NB_STAT_MAPPING 32
124 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
125 #define NB_QMAP_FIELDS_PER_QSM_REG 4
126 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
127 struct txgbe_stat_mappings {
128 uint32_t tqsm[TXGBE_NB_STAT_MAPPING];
129 uint32_t rqsm[TXGBE_NB_STAT_MAPPING];
133 uint32_t vfta[TXGBE_VFTA_SIZE];
136 struct txgbe_hwstrip {
137 uint32_t bitmap[TXGBE_HWSTRIP_BITMAP_SIZE];
141 * VF data which used by PF host only
143 #define TXGBE_MAX_VF_MC_ENTRIES 30
145 struct txgbe_uta_info {
146 uint8_t uc_filter_type;
148 uint32_t uta_shadow[TXGBE_MAX_UTA];
151 #define TXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
153 struct txgbe_mirror_info {
154 struct rte_eth_mirror_conf mr_conf[TXGBE_MAX_MIRROR_RULES];
155 /* store PF mirror rules configuration */
158 struct txgbe_vf_info {
159 uint8_t vf_mac_addresses[RTE_ETHER_ADDR_LEN];
160 uint16_t vf_mc_hashes[TXGBE_MAX_VF_MC_ENTRIES];
161 uint16_t num_vf_mc_hashes;
163 uint16_t tx_rate[TXGBE_MAX_QUEUE_NUM_PER_VF];
166 uint16_t switch_domain_id;
171 TAILQ_HEAD(txgbe_5tuple_filter_list, txgbe_5tuple_filter);
173 struct txgbe_5tuple_filter_info {
178 enum txgbe_5tuple_protocol proto; /* l4 protocol. */
179 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
180 * used when more than one filter matches.
182 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
183 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
184 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
185 src_port_mask:1, /* if mask is 1b, do not compare src port. */
186 proto_mask:1; /* if mask is 1b, do not compare protocol. */
189 /* 5tuple filter structure */
190 struct txgbe_5tuple_filter {
191 TAILQ_ENTRY(txgbe_5tuple_filter) entries;
192 uint16_t index; /* the index of 5tuple filter */
193 struct txgbe_5tuple_filter_info filter_info;
194 uint16_t queue; /* rx queue assigned to */
197 #define TXGBE_5TUPLE_ARRAY_SIZE \
198 (RTE_ALIGN(TXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
199 (sizeof(uint32_t) * NBBY))
201 struct txgbe_ethertype_filter {
206 * If this filter is added by configuration,
207 * it should not be removed.
213 * Structure to store filters' info.
215 struct txgbe_filter_info {
216 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
217 /* store used ethertype filters*/
218 struct txgbe_ethertype_filter ethertype_filters[TXGBE_ETF_ID_MAX];
219 /* Bit mask for every used 5tuple filter */
220 uint32_t fivetuple_mask[TXGBE_5TUPLE_ARRAY_SIZE];
221 struct txgbe_5tuple_filter_list fivetuple_list;
222 /* store the SYN filter info */
226 struct txgbe_l2_tn_key {
227 enum rte_eth_tunnel_type l2_tn_type;
231 struct txgbe_l2_tn_filter {
232 TAILQ_ENTRY(txgbe_l2_tn_filter) entries;
233 struct txgbe_l2_tn_key key;
237 TAILQ_HEAD(txgbe_l2_tn_filter_list, txgbe_l2_tn_filter);
239 struct txgbe_l2_tn_info {
240 struct txgbe_l2_tn_filter_list l2_tn_list;
241 struct txgbe_l2_tn_filter **hash_map;
242 struct rte_hash *hash_handle;
243 bool e_tag_en; /* e-tag enabled */
244 bool e_tag_fwd_en; /* e-tag based forwarding enabled */
245 uint16_t e_tag_ether_type; /* ether type for e-tag */
248 /* The configuration of bandwidth */
249 struct txgbe_bw_conf {
250 uint8_t tc_num; /* Number of TCs. */
254 * Structure to store private data for each driver instance (for each port).
256 struct txgbe_adapter {
258 struct txgbe_hw_stats stats;
259 struct txgbe_hw_fdir_info fdir;
260 struct txgbe_interrupt intr;
261 struct txgbe_stat_mappings stat_mappings;
262 struct txgbe_vfta shadow_vfta;
263 struct txgbe_hwstrip hwstrip;
264 struct txgbe_dcb_config dcb_config;
265 struct txgbe_mirror_info mr_data;
266 struct txgbe_vf_info *vfdata;
267 struct txgbe_uta_info uta_info;
268 struct txgbe_filter_info filter;
269 struct txgbe_l2_tn_info l2_tn;
270 struct txgbe_bw_conf bw_conf;
271 bool rx_bulk_alloc_allowed;
272 struct rte_timecounter systime_tc;
273 struct rte_timecounter rx_tstamp_tc;
274 struct rte_timecounter tx_tstamp_tc;
276 /* For RSS reta table update */
277 uint8_t rss_reta_updated;
280 #define TXGBE_DEV_ADAPTER(dev) \
281 ((struct txgbe_adapter *)(dev)->data->dev_private)
283 #define TXGBE_DEV_HW(dev) \
284 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hw)
286 #define TXGBE_DEV_STATS(dev) \
287 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stats)
289 #define TXGBE_DEV_INTR(dev) \
290 (&((struct txgbe_adapter *)(dev)->data->dev_private)->intr)
292 #define TXGBE_DEV_FDIR(dev) \
293 (&((struct txgbe_adapter *)(dev)->data->dev_private)->fdir)
295 #define TXGBE_DEV_STAT_MAPPINGS(dev) \
296 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stat_mappings)
298 #define TXGBE_DEV_VFTA(dev) \
299 (&((struct txgbe_adapter *)(dev)->data->dev_private)->shadow_vfta)
301 #define TXGBE_DEV_HWSTRIP(dev) \
302 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hwstrip)
304 #define TXGBE_DEV_DCB_CONFIG(dev) \
305 (&((struct txgbe_adapter *)(dev)->data->dev_private)->dcb_config)
307 #define TXGBE_DEV_VFDATA(dev) \
308 (&((struct txgbe_adapter *)(dev)->data->dev_private)->vfdata)
310 #define TXGBE_DEV_MR_INFO(dev) \
311 (&((struct txgbe_adapter *)(dev)->data->dev_private)->mr_data)
313 #define TXGBE_DEV_UTA_INFO(dev) \
314 (&((struct txgbe_adapter *)(dev)->data->dev_private)->uta_info)
316 #define TXGBE_DEV_FILTER(dev) \
317 (&((struct txgbe_adapter *)(dev)->data->dev_private)->filter)
319 #define TXGBE_DEV_L2_TN(dev) \
320 (&((struct txgbe_adapter *)(dev)->data->dev_private)->l2_tn)
322 #define TXGBE_DEV_BW_CONF(dev) \
323 (&((struct txgbe_adapter *)(dev)->data->dev_private)->bw_conf)
327 * RX/TX function prototypes
329 void txgbe_dev_clear_queues(struct rte_eth_dev *dev);
331 void txgbe_dev_free_queues(struct rte_eth_dev *dev);
333 void txgbe_dev_rx_queue_release(void *rxq);
335 void txgbe_dev_tx_queue_release(void *txq);
337 int txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
338 uint16_t nb_rx_desc, unsigned int socket_id,
339 const struct rte_eth_rxconf *rx_conf,
340 struct rte_mempool *mb_pool);
342 int txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
343 uint16_t nb_tx_desc, unsigned int socket_id,
344 const struct rte_eth_txconf *tx_conf);
346 uint32_t txgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
347 uint16_t rx_queue_id);
349 int txgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
350 int txgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
352 int txgbe_dev_rx_init(struct rte_eth_dev *dev);
354 void txgbe_dev_tx_init(struct rte_eth_dev *dev);
356 int txgbe_dev_rxtx_start(struct rte_eth_dev *dev);
358 void txgbe_dev_save_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
359 void txgbe_dev_store_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
360 void txgbe_dev_save_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
361 void txgbe_dev_store_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
363 int txgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
365 int txgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
367 int txgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
369 int txgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
371 void txgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
372 struct rte_eth_rxq_info *qinfo);
374 void txgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
375 struct rte_eth_txq_info *qinfo);
377 uint16_t txgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
380 uint16_t txgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
383 uint16_t txgbe_recv_pkts_lro_single_alloc(void *rx_queue,
384 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
385 uint16_t txgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
386 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
388 uint16_t txgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
391 uint16_t txgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
394 uint16_t txgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
397 int txgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
398 struct rte_eth_rss_conf *rss_conf);
400 int txgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
401 struct rte_eth_rss_conf *rss_conf);
403 bool txgbe_rss_update_sp(enum txgbe_mac_type mac_type);
405 int txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
406 struct rte_eth_ntuple_filter *filter,
408 int txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
409 struct rte_eth_ethertype_filter *filter,
411 int txgbe_syn_filter_set(struct rte_eth_dev *dev,
412 struct rte_eth_syn_filter *filter,
416 * l2 tunnel configuration.
418 struct txgbe_l2_tunnel_conf {
419 enum rte_eth_tunnel_type l2_tunnel_type;
420 uint16_t ether_type; /* ether type in l2 header */
421 uint32_t tunnel_id; /* port tag id for e-tag */
422 uint16_t vf_id; /* VF id for tag insertion */
423 uint32_t pool; /* destination pool for tag based forwarding */
427 txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
428 struct txgbe_l2_tunnel_conf *l2_tunnel,
431 txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
432 struct txgbe_l2_tunnel_conf *l2_tunnel);
433 void txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
434 uint8_t queue, uint8_t msix_vector);
437 * Flow director function prototypes
439 int txgbe_fdir_configure(struct rte_eth_dev *dev);
440 int txgbe_fdir_set_input_mask(struct rte_eth_dev *dev);
441 int txgbe_fdir_set_flexbytes_offset(struct rte_eth_dev *dev,
443 void txgbe_configure_pb(struct rte_eth_dev *dev);
444 void txgbe_configure_port(struct rte_eth_dev *dev);
445 void txgbe_configure_dcb(struct rte_eth_dev *dev);
448 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
449 int wait_to_complete);
450 int txgbe_pf_host_init(struct rte_eth_dev *eth_dev);
452 void txgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
454 void txgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
456 int txgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
458 uint32_t txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
460 extern const struct rte_flow_ops txgbe_flow_ops;
462 int txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
463 uint16_t tx_rate, uint64_t q_msk);
464 int txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx,
467 txgbe_ethertype_filter_lookup(struct txgbe_filter_info *filter_info,
472 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
473 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
474 (filter_info->ethertype_mask & (1 << i)))
481 txgbe_ethertype_filter_insert(struct txgbe_filter_info *filter_info,
482 struct txgbe_ethertype_filter *ethertype_filter)
486 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
487 if (filter_info->ethertype_mask & (1 << i))
490 filter_info->ethertype_mask |= 1 << i;
491 filter_info->ethertype_filters[i].ethertype =
492 ethertype_filter->ethertype;
493 filter_info->ethertype_filters[i].etqf =
494 ethertype_filter->etqf;
495 filter_info->ethertype_filters[i].etqs =
496 ethertype_filter->etqs;
497 filter_info->ethertype_filters[i].conf =
498 ethertype_filter->conf;
501 return (i < TXGBE_ETF_ID_MAX ? i : -1);
505 txgbe_ethertype_filter_remove(struct txgbe_filter_info *filter_info,
508 if (idx >= TXGBE_ETF_ID_MAX)
510 filter_info->ethertype_mask &= ~(1 << idx);
511 filter_info->ethertype_filters[idx].ethertype = 0;
512 filter_info->ethertype_filters[idx].etqf = 0;
513 filter_info->ethertype_filters[idx].etqs = 0;
514 filter_info->ethertype_filters[idx].etqs = FALSE;
518 /* High threshold controlling when to start sending XOFF frames. */
519 #define TXGBE_FC_XOFF_HITH 128 /*KB*/
520 /* Low threshold controlling when to start sending XON frames. */
521 #define TXGBE_FC_XON_LOTH 64 /*KB*/
523 /* Timer value included in XOFF frames. */
524 #define TXGBE_FC_PAUSE_TIME 0x680
526 #define TXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
527 #define TXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
528 #define TXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
531 * Default values for RX/TX configuration
533 #define TXGBE_DEFAULT_RX_FREE_THRESH 32
534 #define TXGBE_DEFAULT_RX_PTHRESH 8
535 #define TXGBE_DEFAULT_RX_HTHRESH 8
536 #define TXGBE_DEFAULT_RX_WTHRESH 0
538 #define TXGBE_DEFAULT_TX_FREE_THRESH 32
539 #define TXGBE_DEFAULT_TX_PTHRESH 32
540 #define TXGBE_DEFAULT_TX_HTHRESH 0
541 #define TXGBE_DEFAULT_TX_WTHRESH 0
543 /* Additional timesync values. */
544 #define NSEC_PER_SEC 1000000000L
545 #define TXGBE_INCVAL_10GB 0xCCCCCC
546 #define TXGBE_INCVAL_1GB 0x800000
547 #define TXGBE_INCVAL_100 0xA00000
548 #define TXGBE_INCVAL_10 0xC7F380
549 #define TXGBE_INCVAL_FPGA 0x800000
550 #define TXGBE_INCVAL_SHIFT_10GB 20
551 #define TXGBE_INCVAL_SHIFT_1GB 18
552 #define TXGBE_INCVAL_SHIFT_100 15
553 #define TXGBE_INCVAL_SHIFT_10 12
554 #define TXGBE_INCVAL_SHIFT_FPGA 17
556 #define TXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
558 /* store statistics names and its offset in stats structure */
559 struct rte_txgbe_xstats_name_off {
560 char name[RTE_ETH_XSTATS_NAME_SIZE];
564 const uint32_t *txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
565 int txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
566 struct rte_ether_addr *mc_addr_set,
567 uint32_t nb_mc_addr);
568 int txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
569 struct rte_eth_rss_reta_entry64 *reta_conf,
571 int txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
572 struct rte_eth_rss_reta_entry64 *reta_conf,
574 void txgbe_dev_setup_link_alarm_handler(void *param);
575 void txgbe_read_stats_registers(struct txgbe_hw *hw,
576 struct txgbe_hw_stats *hw_stats);
578 void txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
579 void txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
580 void txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev);
581 void txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
582 uint16_t queue, bool on);
583 void txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
586 #endif /* _TXGBE_ETHDEV_H_ */