1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
5 #ifndef _TXGBE_ETHDEV_H_
6 #define _TXGBE_ETHDEV_H_
10 #include "base/txgbe.h"
11 #include "txgbe_ptypes.h"
14 #include <rte_ethdev.h>
15 #include <rte_ethdev_core.h>
17 /* need update link, bit flag */
18 #define TXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
19 #define TXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
20 #define TXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
21 #define TXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
22 #define TXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
25 * Defines that were not part of txgbe_type.h as they are not used by the
28 #define TXGBE_VFTA_SIZE 128
29 #define TXGBE_VLAN_TAG_SIZE 4
30 #define TXGBE_HKEY_MAX_INDEX 10
31 /*Default value of Max Rx Queue*/
32 #define TXGBE_MAX_RX_QUEUE_NUM 128
33 #define TXGBE_VMDQ_DCB_NB_QUEUES TXGBE_MAX_RX_QUEUE_NUM
36 #define NBBY 8 /* number of bits in a byte */
38 #define TXGBE_HWSTRIP_BITMAP_SIZE \
39 (TXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
41 #define TXGBE_QUEUE_ITR_INTERVAL_DEFAULT 500 /* 500us */
43 #define TXGBE_MAX_QUEUE_NUM_PER_VF 8
45 #define TXGBE_RSS_OFFLOAD_ALL ( \
47 ETH_RSS_NONFRAG_IPV4_TCP | \
48 ETH_RSS_NONFRAG_IPV4_UDP | \
50 ETH_RSS_NONFRAG_IPV6_TCP | \
51 ETH_RSS_NONFRAG_IPV6_UDP | \
53 ETH_RSS_IPV6_TCP_EX | \
56 #define TXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
57 #define TXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
59 /* structure for interrupt relative data */
60 struct txgbe_interrupt {
63 /* to save original mask during delayed handler */
64 uint32_t mask_misc_orig;
68 #define TXGBE_NB_STAT_MAPPING 32
69 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
70 #define NB_QMAP_FIELDS_PER_QSM_REG 4
71 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
72 struct txgbe_stat_mappings {
73 uint32_t tqsm[TXGBE_NB_STAT_MAPPING];
74 uint32_t rqsm[TXGBE_NB_STAT_MAPPING];
78 uint32_t vfta[TXGBE_VFTA_SIZE];
81 struct txgbe_hwstrip {
82 uint32_t bitmap[TXGBE_HWSTRIP_BITMAP_SIZE];
86 * VF data which used by PF host only
88 #define TXGBE_MAX_VF_MC_ENTRIES 30
90 struct txgbe_uta_info {
91 uint8_t uc_filter_type;
93 uint32_t uta_shadow[TXGBE_MAX_UTA];
96 #define TXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
98 struct txgbe_mirror_info {
99 struct rte_eth_mirror_conf mr_conf[TXGBE_MAX_MIRROR_RULES];
100 /* store PF mirror rules configuration */
103 struct txgbe_vf_info {
104 uint8_t vf_mac_addresses[RTE_ETHER_ADDR_LEN];
105 uint16_t vf_mc_hashes[TXGBE_MAX_VF_MC_ENTRIES];
106 uint16_t num_vf_mc_hashes;
108 uint16_t tx_rate[TXGBE_MAX_QUEUE_NUM_PER_VF];
111 uint16_t switch_domain_id;
116 struct txgbe_ethertype_filter {
121 * If this filter is added by configuration,
122 * it should not be removed.
128 * Structure to store filters' info.
130 struct txgbe_filter_info {
131 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
132 /* store used ethertype filters*/
133 struct txgbe_ethertype_filter ethertype_filters[TXGBE_ETF_ID_MAX];
136 /* The configuration of bandwidth */
137 struct txgbe_bw_conf {
138 uint8_t tc_num; /* Number of TCs. */
142 * Structure to store private data for each driver instance (for each port).
144 struct txgbe_adapter {
146 struct txgbe_hw_stats stats;
147 struct txgbe_interrupt intr;
148 struct txgbe_stat_mappings stat_mappings;
149 struct txgbe_vfta shadow_vfta;
150 struct txgbe_hwstrip hwstrip;
151 struct txgbe_dcb_config dcb_config;
152 struct txgbe_mirror_info mr_data;
153 struct txgbe_vf_info *vfdata;
154 struct txgbe_uta_info uta_info;
155 struct txgbe_filter_info filter;
156 struct txgbe_bw_conf bw_conf;
157 bool rx_bulk_alloc_allowed;
158 struct rte_timecounter systime_tc;
159 struct rte_timecounter rx_tstamp_tc;
160 struct rte_timecounter tx_tstamp_tc;
162 /* For RSS reta table update */
163 uint8_t rss_reta_updated;
166 #define TXGBE_DEV_ADAPTER(dev) \
167 ((struct txgbe_adapter *)(dev)->data->dev_private)
169 #define TXGBE_DEV_HW(dev) \
170 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hw)
172 #define TXGBE_DEV_STATS(dev) \
173 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stats)
175 #define TXGBE_DEV_INTR(dev) \
176 (&((struct txgbe_adapter *)(dev)->data->dev_private)->intr)
178 #define TXGBE_DEV_STAT_MAPPINGS(dev) \
179 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stat_mappings)
181 #define TXGBE_DEV_VFTA(dev) \
182 (&((struct txgbe_adapter *)(dev)->data->dev_private)->shadow_vfta)
184 #define TXGBE_DEV_HWSTRIP(dev) \
185 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hwstrip)
187 #define TXGBE_DEV_DCB_CONFIG(dev) \
188 (&((struct txgbe_adapter *)(dev)->data->dev_private)->dcb_config)
190 #define TXGBE_DEV_VFDATA(dev) \
191 (&((struct txgbe_adapter *)(dev)->data->dev_private)->vfdata)
193 #define TXGBE_DEV_MR_INFO(dev) \
194 (&((struct txgbe_adapter *)(dev)->data->dev_private)->mr_data)
196 #define TXGBE_DEV_UTA_INFO(dev) \
197 (&((struct txgbe_adapter *)(dev)->data->dev_private)->uta_info)
199 #define TXGBE_DEV_FILTER(dev) \
200 (&((struct txgbe_adapter *)(dev)->data->dev_private)->filter)
201 #define TXGBE_DEV_BW_CONF(dev) \
202 (&((struct txgbe_adapter *)(dev)->data->dev_private)->bw_conf)
206 * RX/TX function prototypes
208 void txgbe_dev_clear_queues(struct rte_eth_dev *dev);
210 void txgbe_dev_free_queues(struct rte_eth_dev *dev);
212 void txgbe_dev_rx_queue_release(void *rxq);
214 void txgbe_dev_tx_queue_release(void *txq);
216 int txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
217 uint16_t nb_rx_desc, unsigned int socket_id,
218 const struct rte_eth_rxconf *rx_conf,
219 struct rte_mempool *mb_pool);
221 int txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
222 uint16_t nb_tx_desc, unsigned int socket_id,
223 const struct rte_eth_txconf *tx_conf);
225 uint32_t txgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
226 uint16_t rx_queue_id);
228 int txgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
229 int txgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
231 int txgbe_dev_rx_init(struct rte_eth_dev *dev);
233 void txgbe_dev_tx_init(struct rte_eth_dev *dev);
235 int txgbe_dev_rxtx_start(struct rte_eth_dev *dev);
237 void txgbe_dev_save_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
238 void txgbe_dev_store_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
239 void txgbe_dev_save_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
240 void txgbe_dev_store_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
242 int txgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
244 int txgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
246 int txgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
248 int txgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
250 void txgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
251 struct rte_eth_rxq_info *qinfo);
253 void txgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
254 struct rte_eth_txq_info *qinfo);
256 uint16_t txgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
259 uint16_t txgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
262 uint16_t txgbe_recv_pkts_lro_single_alloc(void *rx_queue,
263 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
264 uint16_t txgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
265 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
267 uint16_t txgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
270 uint16_t txgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
273 uint16_t txgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
276 int txgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
277 struct rte_eth_rss_conf *rss_conf);
279 int txgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
280 struct rte_eth_rss_conf *rss_conf);
282 bool txgbe_rss_update_sp(enum txgbe_mac_type mac_type);
284 void txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
285 uint8_t queue, uint8_t msix_vector);
287 void txgbe_configure_pb(struct rte_eth_dev *dev);
288 void txgbe_configure_port(struct rte_eth_dev *dev);
289 void txgbe_configure_dcb(struct rte_eth_dev *dev);
292 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
293 int wait_to_complete);
294 int txgbe_pf_host_init(struct rte_eth_dev *eth_dev);
296 void txgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
298 void txgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
300 int txgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
302 uint32_t txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
304 extern const struct rte_flow_ops txgbe_flow_ops;
306 int txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
307 uint16_t tx_rate, uint64_t q_msk);
308 int txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx,
311 txgbe_ethertype_filter_lookup(struct txgbe_filter_info *filter_info,
316 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
317 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
318 (filter_info->ethertype_mask & (1 << i)))
325 txgbe_ethertype_filter_insert(struct txgbe_filter_info *filter_info,
326 struct txgbe_ethertype_filter *ethertype_filter)
330 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
331 if (filter_info->ethertype_mask & (1 << i))
334 filter_info->ethertype_mask |= 1 << i;
335 filter_info->ethertype_filters[i].ethertype =
336 ethertype_filter->ethertype;
337 filter_info->ethertype_filters[i].etqf =
338 ethertype_filter->etqf;
339 filter_info->ethertype_filters[i].etqs =
340 ethertype_filter->etqs;
341 filter_info->ethertype_filters[i].conf =
342 ethertype_filter->conf;
345 return (i < TXGBE_ETF_ID_MAX ? i : -1);
348 /* High threshold controlling when to start sending XOFF frames. */
349 #define TXGBE_FC_XOFF_HITH 128 /*KB*/
350 /* Low threshold controlling when to start sending XON frames. */
351 #define TXGBE_FC_XON_LOTH 64 /*KB*/
353 /* Timer value included in XOFF frames. */
354 #define TXGBE_FC_PAUSE_TIME 0x680
356 #define TXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
357 #define TXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
358 #define TXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
361 * Default values for RX/TX configuration
363 #define TXGBE_DEFAULT_RX_FREE_THRESH 32
364 #define TXGBE_DEFAULT_RX_PTHRESH 8
365 #define TXGBE_DEFAULT_RX_HTHRESH 8
366 #define TXGBE_DEFAULT_RX_WTHRESH 0
368 #define TXGBE_DEFAULT_TX_FREE_THRESH 32
369 #define TXGBE_DEFAULT_TX_PTHRESH 32
370 #define TXGBE_DEFAULT_TX_HTHRESH 0
371 #define TXGBE_DEFAULT_TX_WTHRESH 0
373 /* Additional timesync values. */
374 #define NSEC_PER_SEC 1000000000L
375 #define TXGBE_INCVAL_10GB 0xCCCCCC
376 #define TXGBE_INCVAL_1GB 0x800000
377 #define TXGBE_INCVAL_100 0xA00000
378 #define TXGBE_INCVAL_10 0xC7F380
379 #define TXGBE_INCVAL_FPGA 0x800000
380 #define TXGBE_INCVAL_SHIFT_10GB 20
381 #define TXGBE_INCVAL_SHIFT_1GB 18
382 #define TXGBE_INCVAL_SHIFT_100 15
383 #define TXGBE_INCVAL_SHIFT_10 12
384 #define TXGBE_INCVAL_SHIFT_FPGA 17
386 #define TXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
388 /* store statistics names and its offset in stats structure */
389 struct rte_txgbe_xstats_name_off {
390 char name[RTE_ETH_XSTATS_NAME_SIZE];
394 const uint32_t *txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
395 int txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
396 struct rte_ether_addr *mc_addr_set,
397 uint32_t nb_mc_addr);
398 int txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
399 struct rte_eth_rss_reta_entry64 *reta_conf,
401 int txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
402 struct rte_eth_rss_reta_entry64 *reta_conf,
404 void txgbe_dev_setup_link_alarm_handler(void *param);
405 void txgbe_read_stats_registers(struct txgbe_hw *hw,
406 struct txgbe_hw_stats *hw_stats);
408 void txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
409 void txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
410 void txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev);
411 void txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
412 uint16_t queue, bool on);
413 void txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
416 #endif /* _TXGBE_ETHDEV_H_ */