1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
5 #ifndef _TXGBE_ETHDEV_H_
6 #define _TXGBE_ETHDEV_H_
10 #include "base/txgbe.h"
11 #include "txgbe_ptypes.h"
14 #include <rte_ethdev.h>
15 #include <rte_ethdev_core.h>
17 #include <rte_hash_crc.h>
19 /* need update link, bit flag */
20 #define TXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
21 #define TXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
22 #define TXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
23 #define TXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
24 #define TXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
27 * Defines that were not part of txgbe_type.h as they are not used by the
30 #define TXGBE_VFTA_SIZE 128
31 #define TXGBE_VLAN_TAG_SIZE 4
32 #define TXGBE_HKEY_MAX_INDEX 10
33 /*Default value of Max Rx Queue*/
34 #define TXGBE_MAX_RX_QUEUE_NUM 128
35 #define TXGBE_VMDQ_DCB_NB_QUEUES TXGBE_MAX_RX_QUEUE_NUM
38 #define NBBY 8 /* number of bits in a byte */
40 #define TXGBE_HWSTRIP_BITMAP_SIZE \
41 (TXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
43 #define TXGBE_QUEUE_ITR_INTERVAL_DEFAULT 500 /* 500us */
45 #define TXGBE_MAX_QUEUE_NUM_PER_VF 8
47 #define TXGBE_5TUPLE_MAX_PRI 7
48 #define TXGBE_5TUPLE_MIN_PRI 1
50 #define TXGBE_RSS_OFFLOAD_ALL ( \
52 ETH_RSS_NONFRAG_IPV4_TCP | \
53 ETH_RSS_NONFRAG_IPV4_UDP | \
55 ETH_RSS_NONFRAG_IPV6_TCP | \
56 ETH_RSS_NONFRAG_IPV6_UDP | \
58 ETH_RSS_IPV6_TCP_EX | \
61 #define TXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
62 #define TXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
64 #define TXGBE_MAX_FDIR_FILTER_NUM (1024 * 32)
65 #define TXGBE_MAX_L2_TN_FILTER_NUM 128
68 * Information about the fdir mode.
70 struct txgbe_hw_fdir_mask {
71 uint16_t vlan_tci_mask;
72 uint32_t src_ipv4_mask;
73 uint32_t dst_ipv4_mask;
74 uint16_t src_ipv6_mask;
75 uint16_t dst_ipv6_mask;
76 uint16_t src_port_mask;
77 uint16_t dst_port_mask;
78 uint16_t flex_bytes_mask;
79 uint8_t mac_addr_byte_mask;
80 uint32_t tunnel_id_mask;
81 uint8_t tunnel_type_mask;
84 struct txgbe_fdir_filter {
85 TAILQ_ENTRY(txgbe_fdir_filter) entries;
86 struct txgbe_atr_input input; /* key of fdir filter*/
87 uint32_t fdirflags; /* drop or forward */
88 uint32_t fdirhash; /* hash value for fdir */
89 uint8_t queue; /* assigned rx queue */
92 /* list of fdir filters */
93 TAILQ_HEAD(txgbe_fdir_filter_list, txgbe_fdir_filter);
95 struct txgbe_hw_fdir_info {
96 struct txgbe_hw_fdir_mask mask;
97 uint8_t flex_bytes_offset;
106 struct txgbe_fdir_filter_list fdir_list; /* filter list*/
107 /* store the pointers of the filters, index is the hash value. */
108 struct txgbe_fdir_filter **hash_map;
109 struct rte_hash *hash_handle; /* cuckoo hash handler */
110 bool mask_added; /* If already got mask from consistent filter */
113 /* structure for interrupt relative data */
114 struct txgbe_interrupt {
117 /* to save original mask during delayed handler */
118 uint32_t mask_misc_orig;
122 #define TXGBE_NB_STAT_MAPPING 32
123 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
124 #define NB_QMAP_FIELDS_PER_QSM_REG 4
125 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
126 struct txgbe_stat_mappings {
127 uint32_t tqsm[TXGBE_NB_STAT_MAPPING];
128 uint32_t rqsm[TXGBE_NB_STAT_MAPPING];
132 uint32_t vfta[TXGBE_VFTA_SIZE];
135 struct txgbe_hwstrip {
136 uint32_t bitmap[TXGBE_HWSTRIP_BITMAP_SIZE];
140 * VF data which used by PF host only
142 #define TXGBE_MAX_VF_MC_ENTRIES 30
144 struct txgbe_uta_info {
145 uint8_t uc_filter_type;
147 uint32_t uta_shadow[TXGBE_MAX_UTA];
150 #define TXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
152 struct txgbe_mirror_info {
153 struct rte_eth_mirror_conf mr_conf[TXGBE_MAX_MIRROR_RULES];
154 /* store PF mirror rules configuration */
157 struct txgbe_vf_info {
158 uint8_t vf_mac_addresses[RTE_ETHER_ADDR_LEN];
159 uint16_t vf_mc_hashes[TXGBE_MAX_VF_MC_ENTRIES];
160 uint16_t num_vf_mc_hashes;
162 uint16_t tx_rate[TXGBE_MAX_QUEUE_NUM_PER_VF];
165 uint16_t switch_domain_id;
170 TAILQ_HEAD(txgbe_5tuple_filter_list, txgbe_5tuple_filter);
172 struct txgbe_5tuple_filter_info {
177 enum txgbe_5tuple_protocol proto; /* l4 protocol. */
178 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
179 * used when more than one filter matches.
181 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
182 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
183 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
184 src_port_mask:1, /* if mask is 1b, do not compare src port. */
185 proto_mask:1; /* if mask is 1b, do not compare protocol. */
188 /* 5tuple filter structure */
189 struct txgbe_5tuple_filter {
190 TAILQ_ENTRY(txgbe_5tuple_filter) entries;
191 uint16_t index; /* the index of 5tuple filter */
192 struct txgbe_5tuple_filter_info filter_info;
193 uint16_t queue; /* rx queue assigned to */
196 #define TXGBE_5TUPLE_ARRAY_SIZE \
197 (RTE_ALIGN(TXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
198 (sizeof(uint32_t) * NBBY))
200 struct txgbe_ethertype_filter {
205 * If this filter is added by configuration,
206 * it should not be removed.
212 * Structure to store filters' info.
214 struct txgbe_filter_info {
215 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
216 /* store used ethertype filters*/
217 struct txgbe_ethertype_filter ethertype_filters[TXGBE_ETF_ID_MAX];
218 /* Bit mask for every used 5tuple filter */
219 uint32_t fivetuple_mask[TXGBE_5TUPLE_ARRAY_SIZE];
220 struct txgbe_5tuple_filter_list fivetuple_list;
221 /* store the SYN filter info */
225 struct txgbe_l2_tn_key {
226 enum rte_eth_tunnel_type l2_tn_type;
230 struct txgbe_l2_tn_filter {
231 TAILQ_ENTRY(txgbe_l2_tn_filter) entries;
232 struct txgbe_l2_tn_key key;
236 TAILQ_HEAD(txgbe_l2_tn_filter_list, txgbe_l2_tn_filter);
238 struct txgbe_l2_tn_info {
239 struct txgbe_l2_tn_filter_list l2_tn_list;
240 struct txgbe_l2_tn_filter **hash_map;
241 struct rte_hash *hash_handle;
242 bool e_tag_en; /* e-tag enabled */
243 bool e_tag_fwd_en; /* e-tag based forwarding enabled */
244 uint16_t e_tag_ether_type; /* ether type for e-tag */
247 /* The configuration of bandwidth */
248 struct txgbe_bw_conf {
249 uint8_t tc_num; /* Number of TCs. */
253 * Structure to store private data for each driver instance (for each port).
255 struct txgbe_adapter {
257 struct txgbe_hw_stats stats;
258 struct txgbe_hw_fdir_info fdir;
259 struct txgbe_interrupt intr;
260 struct txgbe_stat_mappings stat_mappings;
261 struct txgbe_vfta shadow_vfta;
262 struct txgbe_hwstrip hwstrip;
263 struct txgbe_dcb_config dcb_config;
264 struct txgbe_mirror_info mr_data;
265 struct txgbe_vf_info *vfdata;
266 struct txgbe_uta_info uta_info;
267 struct txgbe_filter_info filter;
268 struct txgbe_l2_tn_info l2_tn;
269 struct txgbe_bw_conf bw_conf;
270 bool rx_bulk_alloc_allowed;
271 struct rte_timecounter systime_tc;
272 struct rte_timecounter rx_tstamp_tc;
273 struct rte_timecounter tx_tstamp_tc;
275 /* For RSS reta table update */
276 uint8_t rss_reta_updated;
279 #define TXGBE_DEV_ADAPTER(dev) \
280 ((struct txgbe_adapter *)(dev)->data->dev_private)
282 #define TXGBE_DEV_HW(dev) \
283 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hw)
285 #define TXGBE_DEV_STATS(dev) \
286 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stats)
288 #define TXGBE_DEV_INTR(dev) \
289 (&((struct txgbe_adapter *)(dev)->data->dev_private)->intr)
291 #define TXGBE_DEV_FDIR(dev) \
292 (&((struct txgbe_adapter *)(dev)->data->dev_private)->fdir)
294 #define TXGBE_DEV_STAT_MAPPINGS(dev) \
295 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stat_mappings)
297 #define TXGBE_DEV_VFTA(dev) \
298 (&((struct txgbe_adapter *)(dev)->data->dev_private)->shadow_vfta)
300 #define TXGBE_DEV_HWSTRIP(dev) \
301 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hwstrip)
303 #define TXGBE_DEV_DCB_CONFIG(dev) \
304 (&((struct txgbe_adapter *)(dev)->data->dev_private)->dcb_config)
306 #define TXGBE_DEV_VFDATA(dev) \
307 (&((struct txgbe_adapter *)(dev)->data->dev_private)->vfdata)
309 #define TXGBE_DEV_MR_INFO(dev) \
310 (&((struct txgbe_adapter *)(dev)->data->dev_private)->mr_data)
312 #define TXGBE_DEV_UTA_INFO(dev) \
313 (&((struct txgbe_adapter *)(dev)->data->dev_private)->uta_info)
315 #define TXGBE_DEV_FILTER(dev) \
316 (&((struct txgbe_adapter *)(dev)->data->dev_private)->filter)
318 #define TXGBE_DEV_L2_TN(dev) \
319 (&((struct txgbe_adapter *)(dev)->data->dev_private)->l2_tn)
321 #define TXGBE_DEV_BW_CONF(dev) \
322 (&((struct txgbe_adapter *)(dev)->data->dev_private)->bw_conf)
326 * RX/TX function prototypes
328 void txgbe_dev_clear_queues(struct rte_eth_dev *dev);
330 void txgbe_dev_free_queues(struct rte_eth_dev *dev);
332 void txgbe_dev_rx_queue_release(void *rxq);
334 void txgbe_dev_tx_queue_release(void *txq);
336 int txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
337 uint16_t nb_rx_desc, unsigned int socket_id,
338 const struct rte_eth_rxconf *rx_conf,
339 struct rte_mempool *mb_pool);
341 int txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
342 uint16_t nb_tx_desc, unsigned int socket_id,
343 const struct rte_eth_txconf *tx_conf);
345 uint32_t txgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
346 uint16_t rx_queue_id);
348 int txgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
349 int txgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
351 int txgbe_dev_rx_init(struct rte_eth_dev *dev);
353 void txgbe_dev_tx_init(struct rte_eth_dev *dev);
355 int txgbe_dev_rxtx_start(struct rte_eth_dev *dev);
357 void txgbe_dev_save_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
358 void txgbe_dev_store_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
359 void txgbe_dev_save_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
360 void txgbe_dev_store_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
362 int txgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
364 int txgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
366 int txgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
368 int txgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
370 void txgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
371 struct rte_eth_rxq_info *qinfo);
373 void txgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
374 struct rte_eth_txq_info *qinfo);
376 uint16_t txgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
379 uint16_t txgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
382 uint16_t txgbe_recv_pkts_lro_single_alloc(void *rx_queue,
383 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
384 uint16_t txgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
385 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
387 uint16_t txgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
390 uint16_t txgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
393 uint16_t txgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
396 int txgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
397 struct rte_eth_rss_conf *rss_conf);
399 int txgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
400 struct rte_eth_rss_conf *rss_conf);
402 bool txgbe_rss_update_sp(enum txgbe_mac_type mac_type);
404 int txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
405 struct rte_eth_ntuple_filter *filter,
407 int txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
408 struct rte_eth_ethertype_filter *filter,
410 int txgbe_syn_filter_set(struct rte_eth_dev *dev,
411 struct rte_eth_syn_filter *filter,
415 * l2 tunnel configuration.
417 struct txgbe_l2_tunnel_conf {
418 enum rte_eth_tunnel_type l2_tunnel_type;
419 uint16_t ether_type; /* ether type in l2 header */
420 uint32_t tunnel_id; /* port tag id for e-tag */
421 uint16_t vf_id; /* VF id for tag insertion */
422 uint32_t pool; /* destination pool for tag based forwarding */
426 txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
427 struct txgbe_l2_tunnel_conf *l2_tunnel,
430 txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
431 struct txgbe_l2_tunnel_conf *l2_tunnel);
432 void txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
433 uint8_t queue, uint8_t msix_vector);
435 void txgbe_configure_pb(struct rte_eth_dev *dev);
436 void txgbe_configure_port(struct rte_eth_dev *dev);
437 void txgbe_configure_dcb(struct rte_eth_dev *dev);
440 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
441 int wait_to_complete);
442 int txgbe_pf_host_init(struct rte_eth_dev *eth_dev);
444 void txgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
446 void txgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
448 int txgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
450 uint32_t txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
452 extern const struct rte_flow_ops txgbe_flow_ops;
454 int txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
455 uint16_t tx_rate, uint64_t q_msk);
456 int txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx,
459 txgbe_ethertype_filter_lookup(struct txgbe_filter_info *filter_info,
464 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
465 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
466 (filter_info->ethertype_mask & (1 << i)))
473 txgbe_ethertype_filter_insert(struct txgbe_filter_info *filter_info,
474 struct txgbe_ethertype_filter *ethertype_filter)
478 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
479 if (filter_info->ethertype_mask & (1 << i))
482 filter_info->ethertype_mask |= 1 << i;
483 filter_info->ethertype_filters[i].ethertype =
484 ethertype_filter->ethertype;
485 filter_info->ethertype_filters[i].etqf =
486 ethertype_filter->etqf;
487 filter_info->ethertype_filters[i].etqs =
488 ethertype_filter->etqs;
489 filter_info->ethertype_filters[i].conf =
490 ethertype_filter->conf;
493 return (i < TXGBE_ETF_ID_MAX ? i : -1);
497 txgbe_ethertype_filter_remove(struct txgbe_filter_info *filter_info,
500 if (idx >= TXGBE_ETF_ID_MAX)
502 filter_info->ethertype_mask &= ~(1 << idx);
503 filter_info->ethertype_filters[idx].ethertype = 0;
504 filter_info->ethertype_filters[idx].etqf = 0;
505 filter_info->ethertype_filters[idx].etqs = 0;
506 filter_info->ethertype_filters[idx].etqs = FALSE;
510 /* High threshold controlling when to start sending XOFF frames. */
511 #define TXGBE_FC_XOFF_HITH 128 /*KB*/
512 /* Low threshold controlling when to start sending XON frames. */
513 #define TXGBE_FC_XON_LOTH 64 /*KB*/
515 /* Timer value included in XOFF frames. */
516 #define TXGBE_FC_PAUSE_TIME 0x680
518 #define TXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
519 #define TXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
520 #define TXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
523 * Default values for RX/TX configuration
525 #define TXGBE_DEFAULT_RX_FREE_THRESH 32
526 #define TXGBE_DEFAULT_RX_PTHRESH 8
527 #define TXGBE_DEFAULT_RX_HTHRESH 8
528 #define TXGBE_DEFAULT_RX_WTHRESH 0
530 #define TXGBE_DEFAULT_TX_FREE_THRESH 32
531 #define TXGBE_DEFAULT_TX_PTHRESH 32
532 #define TXGBE_DEFAULT_TX_HTHRESH 0
533 #define TXGBE_DEFAULT_TX_WTHRESH 0
535 /* Additional timesync values. */
536 #define NSEC_PER_SEC 1000000000L
537 #define TXGBE_INCVAL_10GB 0xCCCCCC
538 #define TXGBE_INCVAL_1GB 0x800000
539 #define TXGBE_INCVAL_100 0xA00000
540 #define TXGBE_INCVAL_10 0xC7F380
541 #define TXGBE_INCVAL_FPGA 0x800000
542 #define TXGBE_INCVAL_SHIFT_10GB 20
543 #define TXGBE_INCVAL_SHIFT_1GB 18
544 #define TXGBE_INCVAL_SHIFT_100 15
545 #define TXGBE_INCVAL_SHIFT_10 12
546 #define TXGBE_INCVAL_SHIFT_FPGA 17
548 #define TXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
550 /* store statistics names and its offset in stats structure */
551 struct rte_txgbe_xstats_name_off {
552 char name[RTE_ETH_XSTATS_NAME_SIZE];
556 const uint32_t *txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
557 int txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
558 struct rte_ether_addr *mc_addr_set,
559 uint32_t nb_mc_addr);
560 int txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
561 struct rte_eth_rss_reta_entry64 *reta_conf,
563 int txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
564 struct rte_eth_rss_reta_entry64 *reta_conf,
566 void txgbe_dev_setup_link_alarm_handler(void *param);
567 void txgbe_read_stats_registers(struct txgbe_hw *hw,
568 struct txgbe_hw_stats *hw_stats);
570 void txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
571 void txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
572 void txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev);
573 void txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
574 uint16_t queue, bool on);
575 void txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
578 #endif /* _TXGBE_ETHDEV_H_ */