drivers/net/vmxnet3/vmxnet3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2015 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <fcntl.h>
  13 #include <inttypes.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_memzone.h>
  26 #include <rte_eal.h>
  27 #include <rte_alarm.h>
  28 #include <rte_ether.h>
  29 #include <rte_ethdev_driver.h>
  30 #include <rte_ethdev_pci.h>
  31 #include <rte_string_fns.h>
  32 #include <rte_malloc.h>
  33 #include <rte_dev.h>
  34
  35 #include "base/vmxnet3_defs.h"
  36
  37 #include "vmxnet3_ring.h"
  38 #include "vmxnet3_logs.h"
  39 #include "vmxnet3_ethdev.h"
  40
  41 #define PROCESS_SYS_EVENTS 0
  42
  43 #define VMXNET3_TX_MAX_SEG      UINT8_MAX
  44
  45 #define VMXNET3_TX_OFFLOAD_CAP          \
  46         (DEV_TX_OFFLOAD_VLAN_INSERT |   \
  47          DEV_TX_OFFLOAD_IPV4_CKSUM |    \
  48          DEV_TX_OFFLOAD_TCP_CKSUM |     \
  49          DEV_TX_OFFLOAD_UDP_CKSUM |     \
  50          DEV_TX_OFFLOAD_TCP_TSO |       \
  51          DEV_TX_OFFLOAD_MULTI_SEGS)
  52
  53 #define VMXNET3_RX_OFFLOAD_CAP          \
  54         (DEV_RX_OFFLOAD_VLAN_STRIP |    \
  55          DEV_RX_OFFLOAD_SCATTER |       \
  56          DEV_RX_OFFLOAD_IPV4_CKSUM |    \
  57          DEV_RX_OFFLOAD_UDP_CKSUM |     \
  58          DEV_RX_OFFLOAD_TCP_CKSUM |     \
  59          DEV_RX_OFFLOAD_TCP_LRO |       \
  60          DEV_RX_OFFLOAD_JUMBO_FRAME)
  61
  62 static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev);
  63 static int eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev);
  64 static int vmxnet3_dev_configure(struct rte_eth_dev *dev);
  65 static int vmxnet3_dev_start(struct rte_eth_dev *dev);
  66 static void vmxnet3_dev_stop(struct rte_eth_dev *dev);
  67 static void vmxnet3_dev_close(struct rte_eth_dev *dev);
  68 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set);
  69 static void vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev);
  70 static void vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev);
  71 static void vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev);
  72 static void vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev);
  73 static int __vmxnet3_dev_link_update(struct rte_eth_dev *dev,
  74                                      int wait_to_complete);
  75 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev,
  76                                    int wait_to_complete);
  77 static void vmxnet3_hw_stats_save(struct vmxnet3_hw *hw);
  78 static int vmxnet3_dev_stats_get(struct rte_eth_dev *dev,
  79                                   struct rte_eth_stats *stats);
  80 static void vmxnet3_dev_stats_reset(struct rte_eth_dev *dev);
  81 static int vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev,
  82                                         struct rte_eth_xstat_name *xstats,
  83                                         unsigned int n);
  84 static int vmxnet3_dev_xstats_get(struct rte_eth_dev *dev,
  85                                   struct rte_eth_xstat *xstats, unsigned int n);
  86 static void vmxnet3_dev_info_get(struct rte_eth_dev *dev,
  87                                  struct rte_eth_dev_info *dev_info);
  88 static const uint32_t *
  89 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev);
  90 static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev,
  91                                        uint16_t vid, int on);
  92 static int vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  93 static int vmxnet3_mac_addr_set(struct rte_eth_dev *dev,
  94                                  struct ether_addr *mac_addr);
  95 static void vmxnet3_interrupt_handler(void *param);
  96
  97 int vmxnet3_logtype_init;
  98 int vmxnet3_logtype_driver;
  99
 100 /*
 101  * The set of PCI devices this driver supports
 102  */
 103 #define VMWARE_PCI_VENDOR_ID 0x15AD
 104 #define VMWARE_DEV_ID_VMXNET3 0x07B0
 105 static const struct rte_pci_id pci_id_vmxnet3_map[] = {
 106         { RTE_PCI_DEVICE(VMWARE_PCI_VENDOR_ID, VMWARE_DEV_ID_VMXNET3) },
 107         { .vendor_id = 0, /* sentinel */ },
 108 };
 109
 110 static const struct eth_dev_ops vmxnet3_eth_dev_ops = {
 111         .dev_configure        = vmxnet3_dev_configure,
 112         .dev_start            = vmxnet3_dev_start,
 113         .dev_stop             = vmxnet3_dev_stop,
 114         .dev_close            = vmxnet3_dev_close,
 115         .promiscuous_enable   = vmxnet3_dev_promiscuous_enable,
 116         .promiscuous_disable  = vmxnet3_dev_promiscuous_disable,
 117         .allmulticast_enable  = vmxnet3_dev_allmulticast_enable,
 118         .allmulticast_disable = vmxnet3_dev_allmulticast_disable,
 119         .link_update          = vmxnet3_dev_link_update,
 120         .stats_get            = vmxnet3_dev_stats_get,
 121         .xstats_get_names     = vmxnet3_dev_xstats_get_names,
 122         .xstats_get           = vmxnet3_dev_xstats_get,
 123         .stats_reset          = vmxnet3_dev_stats_reset,
 124         .mac_addr_set         = vmxnet3_mac_addr_set,
 125         .dev_infos_get        = vmxnet3_dev_info_get,
 126         .dev_supported_ptypes_get = vmxnet3_dev_supported_ptypes_get,
 127         .vlan_filter_set      = vmxnet3_dev_vlan_filter_set,
 128         .vlan_offload_set     = vmxnet3_dev_vlan_offload_set,
 129         .rx_queue_setup       = vmxnet3_dev_rx_queue_setup,
 130         .rx_queue_release     = vmxnet3_dev_rx_queue_release,
 131         .tx_queue_setup       = vmxnet3_dev_tx_queue_setup,
 132         .tx_queue_release     = vmxnet3_dev_tx_queue_release,
 133 };
 134
 135 struct vmxnet3_xstats_name_off {
 136         char name[RTE_ETH_XSTATS_NAME_SIZE];
 137         unsigned int offset;
 138 };
 139
 140 /* tx_qX_ is prepended to the name string here */
 141 static const struct vmxnet3_xstats_name_off vmxnet3_txq_stat_strings[] = {
 142         {"drop_total",         offsetof(struct vmxnet3_txq_stats, drop_total)},
 143         {"drop_too_many_segs", offsetof(struct vmxnet3_txq_stats, drop_too_many_segs)},
 144         {"drop_tso",           offsetof(struct vmxnet3_txq_stats, drop_tso)},
 145         {"tx_ring_full",       offsetof(struct vmxnet3_txq_stats, tx_ring_full)},
 146 };
 147
 148 /* rx_qX_ is prepended to the name string here */
 149 static const struct vmxnet3_xstats_name_off vmxnet3_rxq_stat_strings[] = {
 150         {"drop_total",           offsetof(struct vmxnet3_rxq_stats, drop_total)},
 151         {"drop_err",             offsetof(struct vmxnet3_rxq_stats, drop_err)},
 152         {"drop_fcs",             offsetof(struct vmxnet3_rxq_stats, drop_fcs)},
 153         {"rx_buf_alloc_failure", offsetof(struct vmxnet3_rxq_stats, rx_buf_alloc_failure)},
 154 };
 155
 156 static const struct rte_memzone *
 157 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size,
 158                  const char *post_string, int socket_id,
 159                  uint16_t align, bool reuse)
 160 {
 161         char z_name[RTE_MEMZONE_NAMESIZE];
 162         const struct rte_memzone *mz;
 163
 164         snprintf(z_name, sizeof(z_name), "eth_p%d_%s",
 165                         dev->data->port_id, post_string);
 166
 167         mz = rte_memzone_lookup(z_name);
 168         if (!reuse) {
 169                 if (mz)
 170                         rte_memzone_free(mz);
 171                 return rte_memzone_reserve_aligned(z_name, size, socket_id,
 172                                 RTE_MEMZONE_IOVA_CONTIG, align);
 173         }
 174
 175         if (mz)
 176                 return mz;
 177
 178         return rte_memzone_reserve_aligned(z_name, size, socket_id,
 179                         RTE_MEMZONE_IOVA_CONTIG, align);
 180 }
 181
 182 /*
 183  * This function is based on vmxnet3_disable_intr()
 184  */
 185 static void
 186 vmxnet3_disable_intr(struct vmxnet3_hw *hw)
 187 {
 188         int i;
 189
 190         PMD_INIT_FUNC_TRACE();
 191
 192         hw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
 193         for (i = 0; i < hw->num_intrs; i++)
 194                 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1);
 195 }
 196
 197 static void
 198 vmxnet3_enable_intr(struct vmxnet3_hw *hw)
 199 {
 200         int i;
 201
 202         PMD_INIT_FUNC_TRACE();
 203
 204         hw->shared->devRead.intrConf.intrCtrl &= ~VMXNET3_IC_DISABLE_ALL;
 205         for (i = 0; i < hw->num_intrs; i++)
 206                 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 0);
 207 }
 208
 209 /*
 210  * Gets tx data ring descriptor size.
 211  */
 212 static uint16_t
 213 eth_vmxnet3_txdata_get(struct vmxnet3_hw *hw)
 214 {
 215         uint16 txdata_desc_size;
 216
 217         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
 218                                VMXNET3_CMD_GET_TXDATA_DESC_SIZE);
 219         txdata_desc_size = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
 220
 221         return (txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE ||
 222                 txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE ||
 223                 txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK) ?
 224                 sizeof(struct Vmxnet3_TxDataDesc) : txdata_desc_size;
 225 }
 226
 227 /*
 228  * It returns 0 on success.
 229  */
 230 static int
 231 eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev)
 232 {
 233         struct rte_pci_device *pci_dev;
 234         struct vmxnet3_hw *hw = eth_dev->data->dev_private;
 235         uint32_t mac_hi, mac_lo, ver;
 236         struct rte_eth_link link;
 237
 238         PMD_INIT_FUNC_TRACE();
 239
 240         eth_dev->dev_ops = &vmxnet3_eth_dev_ops;
 241         eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts;
 242         eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts;
 243         eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts;
 244         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 245
 246         /*
 247          * for secondary processes, we don't initialize any further as primary
 248          * has already done this work.
 249          */
 250         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 251                 return 0;
 252
 253         rte_eth_copy_pci_info(eth_dev, pci_dev);
 254
 255         /* Vendor and Device ID need to be set before init of shared code */
 256         hw->device_id = pci_dev->id.device_id;
 257         hw->vendor_id = pci_dev->id.vendor_id;
 258         hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr;
 259         hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr;
 260
 261         hw->num_rx_queues = 1;
 262         hw->num_tx_queues = 1;
 263         hw->bufs_per_pkt = 1;
 264
 265         /* Check h/w version compatibility with driver. */
 266         ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS);
 267         PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver);
 268
 269         if (ver & (1 << VMXNET3_REV_4)) {
 270                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
 271                                        1 << VMXNET3_REV_4);
 272                 hw->version = VMXNET3_REV_4 + 1;
 273         } else if (ver & (1 << VMXNET3_REV_3)) {
 274                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
 275                                        1 << VMXNET3_REV_3);
 276                 hw->version = VMXNET3_REV_3 + 1;
 277         } else if (ver & (1 << VMXNET3_REV_2)) {
 278                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
 279                                        1 << VMXNET3_REV_2);
 280                 hw->version = VMXNET3_REV_2 + 1;
 281         } else if (ver & (1 << VMXNET3_REV_1)) {
 282                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
 283                                        1 << VMXNET3_REV_1);
 284                 hw->version = VMXNET3_REV_1 + 1;
 285         } else {
 286                 PMD_INIT_LOG(ERR, "Incompatible hardware version: %d", ver);
 287                 return -EIO;
 288         }
 289
 290         PMD_INIT_LOG(DEBUG, "Using device version %d\n", hw->version);
 291
 292         /* Check UPT version compatibility with driver. */
 293         ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS);
 294         PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver);
 295         if (ver & 0x1)
 296                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1);
 297         else {
 298                 PMD_INIT_LOG(ERR, "Incompatible UPT version.");
 299                 return -EIO;
 300         }
 301
 302         /* Getting MAC Address */
 303         mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL);
 304         mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH);
 305         memcpy(hw->perm_addr, &mac_lo, 4);
 306         memcpy(hw->perm_addr + 4, &mac_hi, 2);
 307
 308         /* Allocate memory for storing MAC addresses */
 309         eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", ETHER_ADDR_LEN *
 310                                                VMXNET3_MAX_MAC_ADDRS, 0);
 311         if (eth_dev->data->mac_addrs == NULL) {
 312                 PMD_INIT_LOG(ERR,
 313                              "Failed to allocate %d bytes needed to store MAC addresses",
 314                              ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS);
 315                 return -ENOMEM;
 316         }
 317         /* Copy the permanent MAC address */
 318         ether_addr_copy((struct ether_addr *) hw->perm_addr,
 319                         &eth_dev->data->mac_addrs[0]);
 320
 321         PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
 322                      hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2],
 323                      hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]);
 324
 325         /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
 326         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
 327
 328         /* Put device in Quiesce Mode */
 329         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
 330
 331         /* allow untagged pkts */
 332         VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0);
 333
 334         hw->txdata_desc_size = VMXNET3_VERSION_GE_3(hw) ?
 335                 eth_vmxnet3_txdata_get(hw) : sizeof(struct Vmxnet3_TxDataDesc);
 336
 337         hw->rxdata_desc_size = VMXNET3_VERSION_GE_3(hw) ?
 338                 VMXNET3_DEF_RXDATA_DESC_SIZE : 0;
 339         RTE_ASSERT((hw->rxdata_desc_size & ~VMXNET3_RXDATA_DESC_SIZE_MASK) ==
 340                    hw->rxdata_desc_size);
 341
 342         /* clear shadow stats */
 343         memset(hw->saved_tx_stats, 0, sizeof(hw->saved_tx_stats));
 344         memset(hw->saved_rx_stats, 0, sizeof(hw->saved_rx_stats));
 345
 346         /* clear snapshot stats */
 347         memset(hw->snapshot_tx_stats, 0, sizeof(hw->snapshot_tx_stats));
 348         memset(hw->snapshot_rx_stats, 0, sizeof(hw->snapshot_rx_stats));
 349
 350         /* set the initial link status */
 351         memset(&link, 0, sizeof(link));
 352         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 353         link.link_speed = ETH_SPEED_NUM_10G;
 354         link.link_autoneg = ETH_LINK_FIXED;
 355         rte_eth_linkstatus_set(eth_dev, &link);
 356
 357         return 0;
 358 }
 359
 360 static int
 361 eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev)
 362 {
 363         struct vmxnet3_hw *hw = eth_dev->data->dev_private;
 364
 365         PMD_INIT_FUNC_TRACE();
 366
 367         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 368                 return 0;
 369
 370         if (hw->adapter_stopped == 0) {
 371                 PMD_INIT_LOG(DEBUG, "Device has not been closed.");
 372                 return -EBUSY;
 373         }
 374
 375         eth_dev->dev_ops = NULL;
 376         eth_dev->rx_pkt_burst = NULL;
 377         eth_dev->tx_pkt_burst = NULL;
 378         eth_dev->tx_pkt_prepare = NULL;
 379
 380         return 0;
 381 }
 382
 383 static int eth_vmxnet3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 384         struct rte_pci_device *pci_dev)
 385 {
 386         return rte_eth_dev_pci_generic_probe(pci_dev,
 387                 sizeof(struct vmxnet3_hw), eth_vmxnet3_dev_init);
 388 }
 389
 390 static int eth_vmxnet3_pci_remove(struct rte_pci_device *pci_dev)
 391 {
 392         return rte_eth_dev_pci_generic_remove(pci_dev, eth_vmxnet3_dev_uninit);
 393 }
 394
 395 static struct rte_pci_driver rte_vmxnet3_pmd = {
 396         .id_table = pci_id_vmxnet3_map,
 397         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 398         .probe = eth_vmxnet3_pci_probe,
 399         .remove = eth_vmxnet3_pci_remove,
 400 };
 401
 402 static int
 403 vmxnet3_dev_configure(struct rte_eth_dev *dev)
 404 {
 405         const struct rte_memzone *mz;
 406         struct vmxnet3_hw *hw = dev->data->dev_private;
 407         size_t size;
 408
 409         PMD_INIT_FUNC_TRACE();
 410
 411         if (dev->data->nb_tx_queues > VMXNET3_MAX_TX_QUEUES ||
 412             dev->data->nb_rx_queues > VMXNET3_MAX_RX_QUEUES) {
 413                 PMD_INIT_LOG(ERR, "ERROR: Number of queues not supported");
 414                 return -EINVAL;
 415         }
 416
 417         if (!rte_is_power_of_2(dev->data->nb_rx_queues)) {
 418                 PMD_INIT_LOG(ERR, "ERROR: Number of rx queues not power of 2");
 419                 return -EINVAL;
 420         }
 421
 422         size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
 423                 dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc);
 424
 425         if (size > UINT16_MAX)
 426                 return -EINVAL;
 427
 428         hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues;
 429         hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues;
 430
 431         /*
 432          * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead
 433          * on current socket
 434          */
 435         mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared),
 436                               "shared", rte_socket_id(), 8, 1);
 437
 438         if (mz == NULL) {
 439                 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone");
 440                 return -ENOMEM;
 441         }
 442         memset(mz->addr, 0, mz->len);
 443
 444         hw->shared = mz->addr;
 445         hw->sharedPA = mz->iova;
 446
 447         /*
 448          * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc
 449          * on current socket.
 450          *
 451          * We cannot reuse this memzone from previous allocation as its size
 452          * depends on the number of tx and rx queues, which could be different
 453          * from one config to another.
 454          */
 455         mz = gpa_zone_reserve(dev, size, "queuedesc", rte_socket_id(),
 456                               VMXNET3_QUEUE_DESC_ALIGN, 0);
 457         if (mz == NULL) {
 458                 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone");
 459                 return -ENOMEM;
 460         }
 461         memset(mz->addr, 0, mz->len);
 462
 463         hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr;
 464         hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues);
 465
 466         hw->queueDescPA = mz->iova;
 467         hw->queue_desc_len = (uint16_t)size;
 468
 469         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
 470                 /* Allocate memory structure for UPT1_RSSConf and configure */
 471                 mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf),
 472                                       "rss_conf", rte_socket_id(),
 473                                       RTE_CACHE_LINE_SIZE, 1);
 474                 if (mz == NULL) {
 475                         PMD_INIT_LOG(ERR,
 476                                      "ERROR: Creating rss_conf structure zone");
 477                         return -ENOMEM;
 478                 }
 479                 memset(mz->addr, 0, mz->len);
 480
 481                 hw->rss_conf = mz->addr;
 482                 hw->rss_confPA = mz->iova;
 483         }
 484
 485         return 0;
 486 }
 487
 488 static void
 489 vmxnet3_write_mac(struct vmxnet3_hw *hw, const uint8_t *addr)
 490 {
 491         uint32_t val;
 492
 493         PMD_INIT_LOG(DEBUG,
 494                      "Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
 495                      addr[0], addr[1], addr[2],
 496                      addr[3], addr[4], addr[5]);
 497
 498         memcpy(&val, addr, 4);
 499         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val);
 500
 501         memcpy(&val, addr + 4, 2);
 502         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val);
 503 }
 504
 505 static int
 506 vmxnet3_dev_setup_memreg(struct rte_eth_dev *dev)
 507 {
 508         struct vmxnet3_hw *hw = dev->data->dev_private;
 509         Vmxnet3_DriverShared *shared = hw->shared;
 510         Vmxnet3_CmdInfo *cmdInfo;
 511         struct rte_mempool *mp[VMXNET3_MAX_RX_QUEUES];
 512         uint8_t index[VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES];
 513         uint32_t num, i, j, size;
 514
 515         if (hw->memRegsPA == 0) {
 516                 const struct rte_memzone *mz;
 517
 518                 size = sizeof(Vmxnet3_MemRegs) +
 519                         (VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES) *
 520                         sizeof(Vmxnet3_MemoryRegion);
 521
 522                 mz = gpa_zone_reserve(dev, size, "memRegs", rte_socket_id(), 8,
 523                                       1);
 524                 if (mz == NULL) {
 525                         PMD_INIT_LOG(ERR, "ERROR: Creating memRegs zone");
 526                         return -ENOMEM;
 527                 }
 528                 memset(mz->addr, 0, mz->len);
 529                 hw->memRegs = mz->addr;
 530                 hw->memRegsPA = mz->iova;
 531         }
 532
 533         num = hw->num_rx_queues;
 534
 535         for (i = 0; i < num; i++) {
 536                 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i];
 537
 538                 mp[i] = rxq->mp;
 539                 index[i] = 1 << i;
 540         }
 541
 542         /*
 543          * The same mempool could be used by multiple queues. In such a case,
 544          * remove duplicate mempool entries. Only one entry is kept with
 545          * bitmask indicating queues that are using this mempool.
 546          */
 547         for (i = 1; i < num; i++) {
 548                 for (j = 0; j < i; j++) {
 549                         if (mp[i] == mp[j]) {
 550                                 mp[i] = NULL;
 551                                 index[j] |= 1 << i;
 552                                 break;
 553                         }
 554                 }
 555         }
 556
 557         j = 0;
 558         for (i = 0; i < num; i++) {
 559                 if (mp[i] == NULL)
 560                         continue;
 561
 562                 Vmxnet3_MemoryRegion *mr = &hw->memRegs->memRegs[j];
 563
 564                 mr->startPA =
 565                         (uintptr_t)STAILQ_FIRST(&mp[i]->mem_list)->iova;
 566                 mr->length = STAILQ_FIRST(&mp[i]->mem_list)->len <= INT32_MAX ?
 567                         STAILQ_FIRST(&mp[i]->mem_list)->len : INT32_MAX;
 568                 mr->txQueueBits = index[i];
 569                 mr->rxQueueBits = index[i];
 570
 571                 PMD_INIT_LOG(INFO,
 572                              "index: %u startPA: %" PRIu64 " length: %u, "
 573                              "rxBits: %x",
 574                              j, mr->startPA, mr->length, mr->rxQueueBits);
 575                 j++;
 576         }
 577         hw->memRegs->numRegs = j;
 578         PMD_INIT_LOG(INFO, "numRegs: %u", j);
 579
 580         size = sizeof(Vmxnet3_MemRegs) +
 581                 (j - 1) * sizeof(Vmxnet3_MemoryRegion);
 582
 583         cmdInfo = &shared->cu.cmdInfo;
 584         cmdInfo->varConf.confVer = 1;
 585         cmdInfo->varConf.confLen = size;
 586         cmdInfo->varConf.confPA = hw->memRegsPA;
 587
 588         return 0;
 589 }
 590
 591 static int
 592 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev)
 593 {
 594         struct rte_eth_conf port_conf = dev->data->dev_conf;
 595         struct vmxnet3_hw *hw = dev->data->dev_private;
 596         uint32_t mtu = dev->data->mtu;
 597         Vmxnet3_DriverShared *shared = hw->shared;
 598         Vmxnet3_DSDevRead *devRead = &shared->devRead;
 599         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
 600         uint32_t i;
 601         int ret;
 602
 603         hw->mtu = mtu;
 604
 605         shared->magic = VMXNET3_REV1_MAGIC;
 606         devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM;
 607
 608         /* Setting up Guest OS information */
 609         devRead->misc.driverInfo.gos.gosBits   = sizeof(void *) == 4 ?
 610                 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64;
 611         devRead->misc.driverInfo.gos.gosType   = VMXNET3_GOS_TYPE_LINUX;
 612         devRead->misc.driverInfo.vmxnet3RevSpt = 1;
 613         devRead->misc.driverInfo.uptVerSpt     = 1;
 614
 615         devRead->misc.mtu = rte_le_to_cpu_32(mtu);
 616         devRead->misc.queueDescPA  = hw->queueDescPA;
 617         devRead->misc.queueDescLen = hw->queue_desc_len;
 618         devRead->misc.numTxQueues  = hw->num_tx_queues;
 619         devRead->misc.numRxQueues  = hw->num_rx_queues;
 620
 621         /*
 622          * Set number of interrupts to 1
 623          * PMD by default disables all the interrupts but this is MUST
 624          * to activate device. It needs at least one interrupt for
 625          * link events to handle
 626          */
 627         hw->num_intrs = devRead->intrConf.numIntrs = 1;
 628         devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
 629
 630         for (i = 0; i < hw->num_tx_queues; i++) {
 631                 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i];
 632                 vmxnet3_tx_queue_t *txq  = dev->data->tx_queues[i];
 633
 634                 txq->shared = &hw->tqd_start[i];
 635
 636                 tqd->ctrl.txNumDeferred  = 0;
 637                 tqd->ctrl.txThreshold    = 1;
 638                 tqd->conf.txRingBasePA   = txq->cmd_ring.basePA;
 639                 tqd->conf.compRingBasePA = txq->comp_ring.basePA;
 640                 tqd->conf.dataRingBasePA = txq->data_ring.basePA;
 641
 642                 tqd->conf.txRingSize   = txq->cmd_ring.size;
 643                 tqd->conf.compRingSize = txq->comp_ring.size;
 644                 tqd->conf.dataRingSize = txq->data_ring.size;
 645                 tqd->conf.txDataRingDescSize = txq->txdata_desc_size;
 646                 tqd->conf.intrIdx      = txq->comp_ring.intr_idx;
 647                 tqd->status.stopped    = TRUE;
 648                 tqd->status.error      = 0;
 649                 memset(&tqd->stats, 0, sizeof(tqd->stats));
 650         }
 651
 652         for (i = 0; i < hw->num_rx_queues; i++) {
 653                 Vmxnet3_RxQueueDesc *rqd  = &hw->rqd_start[i];
 654                 vmxnet3_rx_queue_t *rxq   = dev->data->rx_queues[i];
 655
 656                 rxq->shared = &hw->rqd_start[i];
 657
 658                 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA;
 659                 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA;
 660                 rqd->conf.compRingBasePA  = rxq->comp_ring.basePA;
 661
 662                 rqd->conf.rxRingSize[0]   = rxq->cmd_ring[0].size;
 663                 rqd->conf.rxRingSize[1]   = rxq->cmd_ring[1].size;
 664                 rqd->conf.compRingSize    = rxq->comp_ring.size;
 665                 rqd->conf.intrIdx         = rxq->comp_ring.intr_idx;
 666                 if (VMXNET3_VERSION_GE_3(hw)) {
 667                         rqd->conf.rxDataRingBasePA = rxq->data_ring.basePA;
 668                         rqd->conf.rxDataRingDescSize = rxq->data_desc_size;
 669                 }
 670                 rqd->status.stopped       = TRUE;
 671                 rqd->status.error         = 0;
 672                 memset(&rqd->stats, 0, sizeof(rqd->stats));
 673         }
 674
 675         /* RxMode set to 0 of VMXNET3_RXM_xxx */
 676         devRead->rxFilterConf.rxMode = 0;
 677
 678         /* Setting up feature flags */
 679         if (rx_offloads & DEV_RX_OFFLOAD_CHECKSUM)
 680                 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM;
 681
 682         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) {
 683                 devRead->misc.uptFeatures |= VMXNET3_F_LRO;
 684                 devRead->misc.maxNumRxSG = 0;
 685         }
 686
 687         if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
 688                 ret = vmxnet3_rss_configure(dev);
 689                 if (ret != VMXNET3_SUCCESS)
 690                         return ret;
 691
 692                 devRead->misc.uptFeatures |= VMXNET3_F_RSS;
 693                 devRead->rssConfDesc.confVer = 1;
 694                 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf);
 695                 devRead->rssConfDesc.confPA  = hw->rss_confPA;
 696         }
 697
 698         ret = vmxnet3_dev_vlan_offload_set(dev,
 699                         ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK);
 700         if (ret)
 701                 return ret;
 702
 703         vmxnet3_write_mac(hw, dev->data->mac_addrs->addr_bytes);
 704
 705         return VMXNET3_SUCCESS;
 706 }
 707
 708 /*
 709  * Configure device link speed and setup link.
 710  * Must be called after eth_vmxnet3_dev_init. Other wise it might fail
 711  * It returns 0 on success.
 712  */
 713 static int
 714 vmxnet3_dev_start(struct rte_eth_dev *dev)
 715 {
 716         int ret;
 717         struct vmxnet3_hw *hw = dev->data->dev_private;
 718
 719         PMD_INIT_FUNC_TRACE();
 720
 721         /* Save stats before it is reset by CMD_ACTIVATE */
 722         vmxnet3_hw_stats_save(hw);
 723
 724         ret = vmxnet3_setup_driver_shared(dev);
 725         if (ret != VMXNET3_SUCCESS)
 726                 return ret;
 727
 728         /* check if lsc interrupt feature is enabled */
 729         if (dev->data->dev_conf.intr_conf.lsc) {
 730                 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
 731
 732                 /* Setup interrupt callback  */
 733                 rte_intr_callback_register(&pci_dev->intr_handle,
 734                                            vmxnet3_interrupt_handler, dev);
 735
 736                 if (rte_intr_enable(&pci_dev->intr_handle) < 0) {
 737                         PMD_INIT_LOG(ERR, "interrupt enable failed");
 738                         return -EIO;
 739                 }
 740         }
 741
 742         /* Exchange shared data with device */
 743         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL,
 744                                VMXNET3_GET_ADDR_LO(hw->sharedPA));
 745         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH,
 746                                VMXNET3_GET_ADDR_HI(hw->sharedPA));
 747
 748         /* Activate device by register write */
 749         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV);
 750         ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
 751
 752         if (ret != 0) {
 753                 PMD_INIT_LOG(ERR, "Device activation: UNSUCCESSFUL");
 754                 return -EINVAL;
 755         }
 756
 757         /* Setup memory region for rx buffers */
 758         ret = vmxnet3_dev_setup_memreg(dev);
 759         if (ret == 0) {
 760                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
 761                                        VMXNET3_CMD_REGISTER_MEMREGS);
 762                 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
 763                 if (ret != 0)
 764                         PMD_INIT_LOG(DEBUG,
 765                                      "Failed in setup memory region cmd\n");
 766                 ret = 0;
 767         } else {
 768                 PMD_INIT_LOG(DEBUG, "Failed to setup memory region\n");
 769         }
 770
 771         if (VMXNET3_VERSION_GE_4(hw)) {
 772                 /* Check for additional RSS  */
 773                 ret = vmxnet3_v4_rss_configure(dev);
 774                 if (ret != VMXNET3_SUCCESS) {
 775                         PMD_INIT_LOG(ERR, "Failed to configure v4 RSS");
 776                         return ret;
 777                 }
 778         }
 779
 780         /* Disable interrupts */
 781         vmxnet3_disable_intr(hw);
 782
 783         /*
 784          * Load RX queues with blank mbufs and update next2fill index for device
 785          * Update RxMode of the device
 786          */
 787         ret = vmxnet3_dev_rxtx_init(dev);
 788         if (ret != VMXNET3_SUCCESS) {
 789                 PMD_INIT_LOG(ERR, "Device queue init: UNSUCCESSFUL");
 790                 return ret;
 791         }
 792
 793         hw->adapter_stopped = FALSE;
 794
 795         /* Setting proper Rx Mode and issue Rx Mode Update command */
 796         vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1);
 797
 798         if (dev->data->dev_conf.intr_conf.lsc) {
 799                 vmxnet3_enable_intr(hw);
 800
 801                 /*
 802                  * Update link state from device since this won't be
 803                  * done upon starting with lsc in use. This is done
 804                  * only after enabling interrupts to avoid any race
 805                  * where the link state could change without an
 806                  * interrupt being fired.
 807                  */
 808                 __vmxnet3_dev_link_update(dev, 0);
 809         }
 810
 811         return VMXNET3_SUCCESS;
 812 }
 813
 814 /*
 815  * Stop device: disable rx and tx functions to allow for reconfiguring.
 816  */
 817 static void
 818 vmxnet3_dev_stop(struct rte_eth_dev *dev)
 819 {
 820         struct rte_eth_link link;
 821         struct vmxnet3_hw *hw = dev->data->dev_private;
 822
 823         PMD_INIT_FUNC_TRACE();
 824
 825         if (hw->adapter_stopped == 1) {
 826                 PMD_INIT_LOG(DEBUG, "Device already stopped.");
 827                 return;
 828         }
 829
 830         /* disable interrupts */
 831         vmxnet3_disable_intr(hw);
 832
 833         if (dev->data->dev_conf.intr_conf.lsc) {
 834                 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
 835
 836                 rte_intr_disable(&pci_dev->intr_handle);
 837
 838                 rte_intr_callback_unregister(&pci_dev->intr_handle,
 839                                              vmxnet3_interrupt_handler, dev);
 840         }
 841
 842         /* quiesce the device first */
 843         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
 844         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0);
 845         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0);
 846
 847         /* reset the device */
 848         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
 849         PMD_INIT_LOG(DEBUG, "Device reset.");
 850
 851         vmxnet3_dev_clear_queues(dev);
 852
 853         /* Clear recorded link status */
 854         memset(&link, 0, sizeof(link));
 855         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 856         link.link_speed = ETH_SPEED_NUM_10G;
 857         link.link_autoneg = ETH_LINK_FIXED;
 858         rte_eth_linkstatus_set(dev, &link);
 859
 860         hw->adapter_stopped = 1;
 861 }
 862
 863 static void
 864 vmxnet3_free_queues(struct rte_eth_dev *dev)
 865 {
 866         int i;
 867
 868         PMD_INIT_FUNC_TRACE();
 869
 870         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 871                 void *rxq = dev->data->rx_queues[i];
 872
 873                 vmxnet3_dev_rx_queue_release(rxq);
 874         }
 875         dev->data->nb_rx_queues = 0;
 876
 877         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 878                 void *txq = dev->data->tx_queues[i];
 879
 880                 vmxnet3_dev_tx_queue_release(txq);
 881         }
 882         dev->data->nb_tx_queues = 0;
 883 }
 884
 885 /*
 886  * Reset and stop device.
 887  */
 888 static void
 889 vmxnet3_dev_close(struct rte_eth_dev *dev)
 890 {
 891         PMD_INIT_FUNC_TRACE();
 892
 893         vmxnet3_dev_stop(dev);
 894         vmxnet3_free_queues(dev);
 895 }
 896
 897 static void
 898 vmxnet3_hw_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
 899                         struct UPT1_TxStats *res)
 900 {
 901 #define VMXNET3_UPDATE_TX_STAT(h, i, f, r)              \
 902                 ((r)->f = (h)->tqd_start[(i)].stats.f + \
 903                         (h)->saved_tx_stats[(i)].f)
 904
 905         VMXNET3_UPDATE_TX_STAT(hw, q, ucastPktsTxOK, res);
 906         VMXNET3_UPDATE_TX_STAT(hw, q, mcastPktsTxOK, res);
 907         VMXNET3_UPDATE_TX_STAT(hw, q, bcastPktsTxOK, res);
 908         VMXNET3_UPDATE_TX_STAT(hw, q, ucastBytesTxOK, res);
 909         VMXNET3_UPDATE_TX_STAT(hw, q, mcastBytesTxOK, res);
 910         VMXNET3_UPDATE_TX_STAT(hw, q, bcastBytesTxOK, res);
 911         VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxError, res);
 912         VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxDiscard, res);
 913
 914 #undef VMXNET3_UPDATE_TX_STAT
 915 }
 916
 917 static void
 918 vmxnet3_hw_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
 919                         struct UPT1_RxStats *res)
 920 {
 921 #define VMXNET3_UPDATE_RX_STAT(h, i, f, r)              \
 922                 ((r)->f = (h)->rqd_start[(i)].stats.f + \
 923                         (h)->saved_rx_stats[(i)].f)
 924
 925         VMXNET3_UPDATE_RX_STAT(hw, q, ucastPktsRxOK, res);
 926         VMXNET3_UPDATE_RX_STAT(hw, q, mcastPktsRxOK, res);
 927         VMXNET3_UPDATE_RX_STAT(hw, q, bcastPktsRxOK, res);
 928         VMXNET3_UPDATE_RX_STAT(hw, q, ucastBytesRxOK, res);
 929         VMXNET3_UPDATE_RX_STAT(hw, q, mcastBytesRxOK, res);
 930         VMXNET3_UPDATE_RX_STAT(hw, q, bcastBytesRxOK, res);
 931         VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxError, res);
 932         VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxOutOfBuf, res);
 933
 934 #undef VMXNET3_UPDATE_RX_STAT
 935 }
 936
 937 static void
 938 vmxnet3_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
 939                                         struct UPT1_TxStats *res)
 940 {
 941                 vmxnet3_hw_tx_stats_get(hw, q, res);
 942
 943 #define VMXNET3_REDUCE_SNAPSHOT_TX_STAT(h, i, f, r)     \
 944                 ((r)->f -= (h)->snapshot_tx_stats[(i)].f)
 945
 946         VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, ucastPktsTxOK, res);
 947         VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, mcastPktsTxOK, res);
 948         VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, bcastPktsTxOK, res);
 949         VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, ucastBytesTxOK, res);
 950         VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, mcastBytesTxOK, res);
 951         VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, bcastBytesTxOK, res);
 952         VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, pktsTxError, res);
 953         VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, pktsTxDiscard, res);
 954
 955 #undef VMXNET3_REDUCE_SNAPSHOT_TX_STAT
 956 }
 957
 958 static void
 959 vmxnet3_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
 960                                         struct UPT1_RxStats *res)
 961 {
 962                 vmxnet3_hw_rx_stats_get(hw, q, res);
 963
 964 #define VMXNET3_REDUCE_SNAPSHOT_RX_STAT(h, i, f, r)     \
 965                 ((r)->f -= (h)->snapshot_rx_stats[(i)].f)
 966
 967         VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, ucastPktsRxOK, res);
 968         VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, mcastPktsRxOK, res);
 969         VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, bcastPktsRxOK, res);
 970         VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, ucastBytesRxOK, res);
 971         VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, mcastBytesRxOK, res);
 972         VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, bcastBytesRxOK, res);
 973         VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, pktsRxError, res);
 974         VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, pktsRxOutOfBuf, res);
 975
 976 #undef VMXNET3_REDUCE_SNAPSHOT_RX_STAT
 977 }
 978
 979 static void
 980 vmxnet3_hw_stats_save(struct vmxnet3_hw *hw)
 981 {
 982         unsigned int i;
 983
 984         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
 985
 986         RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
 987
 988         for (i = 0; i < hw->num_tx_queues; i++)
 989                 vmxnet3_hw_tx_stats_get(hw, i, &hw->saved_tx_stats[i]);
 990         for (i = 0; i < hw->num_rx_queues; i++)
 991                 vmxnet3_hw_rx_stats_get(hw, i, &hw->saved_rx_stats[i]);
 992 }
 993
 994 static int
 995 vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev,
 996                              struct rte_eth_xstat_name *xstats_names,
 997                              unsigned int n)
 998 {
 999         unsigned int i, t, count = 0;
1000         unsigned int nstats =
1001                 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) +
1002                 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings);
1003
1004         if (!xstats_names || n < nstats)
1005                 return nstats;
1006
1007         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1008                 if (!dev->data->rx_queues[i])
1009                         continue;
1010
1011                 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) {
1012                         snprintf(xstats_names[count].name,
1013                                  sizeof(xstats_names[count].name),
1014                                  "rx_q%u_%s", i,
1015                                  vmxnet3_rxq_stat_strings[t].name);
1016                         count++;
1017                 }
1018         }
1019
1020         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1021                 if (!dev->data->tx_queues[i])
1022                         continue;
1023
1024                 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) {
1025                         snprintf(xstats_names[count].name,
1026                                  sizeof(xstats_names[count].name),
1027                                  "tx_q%u_%s", i,
1028                                  vmxnet3_txq_stat_strings[t].name);
1029                         count++;
1030                 }
1031         }
1032
1033         return count;
1034 }
1035
1036 static int
1037 vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1038                        unsigned int n)
1039 {
1040         unsigned int i, t, count = 0;
1041         unsigned int nstats =
1042                 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) +
1043                 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings);
1044
1045         if (n < nstats)
1046                 return nstats;
1047
1048         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1049                 struct vmxnet3_rx_queue *rxq = dev->data->rx_queues[i];
1050
1051                 if (rxq == NULL)
1052                         continue;
1053
1054                 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) {
1055                         xstats[count].value = *(uint64_t *)(((char *)&rxq->stats) +
1056                                 vmxnet3_rxq_stat_strings[t].offset);
1057                         xstats[count].id = count;
1058                         count++;
1059                 }
1060         }
1061
1062         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1063                 struct vmxnet3_tx_queue *txq = dev->data->tx_queues[i];
1064
1065                 if (txq == NULL)
1066                         continue;
1067
1068                 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) {
1069                         xstats[count].value = *(uint64_t *)(((char *)&txq->stats) +
1070                                 vmxnet3_txq_stat_strings[t].offset);
1071                         xstats[count].id = count;
1072                         count++;
1073                 }
1074         }
1075
1076         return count;
1077 }
1078
1079 static int
1080 vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1081 {
1082         unsigned int i;
1083         struct vmxnet3_hw *hw = dev->data->dev_private;
1084         struct UPT1_TxStats txStats;
1085         struct UPT1_RxStats rxStats;
1086
1087         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
1088
1089         RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
1090         for (i = 0; i < hw->num_tx_queues; i++) {
1091                 vmxnet3_tx_stats_get(hw, i, &txStats);
1092
1093                 stats->q_opackets[i] = txStats.ucastPktsTxOK +
1094                         txStats.mcastPktsTxOK +
1095                         txStats.bcastPktsTxOK;
1096
1097                 stats->q_obytes[i] = txStats.ucastBytesTxOK +
1098                         txStats.mcastBytesTxOK +
1099                         txStats.bcastBytesTxOK;
1100
1101                 stats->opackets += stats->q_opackets[i];
1102                 stats->obytes += stats->q_obytes[i];
1103                 stats->oerrors += txStats.pktsTxError + txStats.pktsTxDiscard;
1104         }
1105
1106         RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES);
1107         for (i = 0; i < hw->num_rx_queues; i++) {
1108                 vmxnet3_rx_stats_get(hw, i, &rxStats);
1109
1110                 stats->q_ipackets[i] = rxStats.ucastPktsRxOK +
1111                         rxStats.mcastPktsRxOK +
1112                         rxStats.bcastPktsRxOK;
1113
1114                 stats->q_ibytes[i] = rxStats.ucastBytesRxOK +
1115                         rxStats.mcastBytesRxOK +
1116                         rxStats.bcastBytesRxOK;
1117
1118                 stats->ipackets += stats->q_ipackets[i];
1119                 stats->ibytes += stats->q_ibytes[i];
1120
1121                 stats->q_errors[i] = rxStats.pktsRxError;
1122                 stats->ierrors += rxStats.pktsRxError;
1123                 stats->imissed += rxStats.pktsRxOutOfBuf;
1124         }
1125
1126         return 0;
1127 }
1128
1129 static void
1130 vmxnet3_dev_stats_reset(struct rte_eth_dev *dev)
1131 {
1132         unsigned int i;
1133         struct vmxnet3_hw *hw = dev->data->dev_private;
1134         struct UPT1_TxStats txStats;
1135         struct UPT1_RxStats rxStats;
1136
1137         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
1138
1139         RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
1140
1141         for (i = 0; i < hw->num_tx_queues; i++) {
1142                 vmxnet3_hw_tx_stats_get(hw, i, &txStats);
1143                 memcpy(&hw->snapshot_tx_stats[i], &txStats,
1144                         sizeof(hw->snapshot_tx_stats[0]));
1145         }
1146         for (i = 0; i < hw->num_rx_queues; i++) {
1147                 vmxnet3_hw_rx_stats_get(hw, i, &rxStats);
1148                 memcpy(&hw->snapshot_rx_stats[i], &rxStats,
1149                         sizeof(hw->snapshot_rx_stats[0]));
1150         }
1151 }
1152
1153 static void
1154 vmxnet3_dev_info_get(struct rte_eth_dev *dev __rte_unused,
1155                      struct rte_eth_dev_info *dev_info)
1156 {
1157         struct vmxnet3_hw *hw = dev->data->dev_private;
1158
1159         dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES;
1160         dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES;
1161         dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM;
1162         dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */
1163         dev_info->speed_capa = ETH_LINK_SPEED_10G;
1164         dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS;
1165
1166         dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL;
1167
1168         if (VMXNET3_VERSION_GE_4(hw)) {
1169                 dev_info->flow_type_rss_offloads |= VMXNET3_V4_RSS_MASK;
1170         }
1171
1172         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1173                 .nb_max = VMXNET3_RX_RING_MAX_SIZE,
1174                 .nb_min = VMXNET3_DEF_RX_RING_SIZE,
1175                 .nb_align = 1,
1176         };
1177
1178         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1179                 .nb_max = VMXNET3_TX_RING_MAX_SIZE,
1180                 .nb_min = VMXNET3_DEF_TX_RING_SIZE,
1181                 .nb_align = 1,
1182                 .nb_seg_max = VMXNET3_TX_MAX_SEG,
1183                 .nb_mtu_seg_max = VMXNET3_MAX_TXD_PER_PKT,
1184         };
1185
1186         dev_info->rx_offload_capa = VMXNET3_RX_OFFLOAD_CAP;
1187         dev_info->rx_queue_offload_capa = 0;
1188         dev_info->tx_offload_capa = VMXNET3_TX_OFFLOAD_CAP;
1189         dev_info->tx_queue_offload_capa = 0;
1190 }
1191
1192 static const uint32_t *
1193 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1194 {
1195         static const uint32_t ptypes[] = {
1196                 RTE_PTYPE_L3_IPV4_EXT,
1197                 RTE_PTYPE_L3_IPV4,
1198                 RTE_PTYPE_UNKNOWN
1199         };
1200
1201         if (dev->rx_pkt_burst == vmxnet3_recv_pkts)
1202                 return ptypes;
1203         return NULL;
1204 }
1205
1206 static int
1207 vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
1208 {
1209         struct vmxnet3_hw *hw = dev->data->dev_private;
1210
1211         ether_addr_copy(mac_addr, (struct ether_addr *)(hw->perm_addr));
1212         vmxnet3_write_mac(hw, mac_addr->addr_bytes);
1213         return 0;
1214 }
1215
1216 /* return 0 means link status changed, -1 means not changed */
1217 static int
1218 __vmxnet3_dev_link_update(struct rte_eth_dev *dev,
1219                           __rte_unused int wait_to_complete)
1220 {
1221         struct vmxnet3_hw *hw = dev->data->dev_private;
1222         struct rte_eth_link link;
1223         uint32_t ret;
1224
1225         memset(&link, 0, sizeof(link));
1226
1227         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
1228         ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
1229
1230         if (ret & 0x1)
1231                 link.link_status = ETH_LINK_UP;
1232         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1233         link.link_speed = ETH_SPEED_NUM_10G;
1234         link.link_autoneg = ETH_LINK_FIXED;
1235
1236         return rte_eth_linkstatus_set(dev, &link);
1237 }
1238
1239 static int
1240 vmxnet3_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1241 {
1242         /* Link status doesn't change for stopped dev */
1243         if (dev->data->dev_started == 0)
1244                 return -1;
1245
1246         return __vmxnet3_dev_link_update(dev, wait_to_complete);
1247 }
1248
1249 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */
1250 static void
1251 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set)
1252 {
1253         struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
1254
1255         if (set)
1256                 rxConf->rxMode = rxConf->rxMode | feature;
1257         else
1258                 rxConf->rxMode = rxConf->rxMode & (~feature);
1259
1260         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE);
1261 }
1262
1263 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
1264 static void
1265 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev)
1266 {
1267         struct vmxnet3_hw *hw = dev->data->dev_private;
1268         uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
1269
1270         memset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE);
1271         vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1);
1272
1273         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1274                                VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1275 }
1276
1277 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
1278 static void
1279 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev)
1280 {
1281         struct vmxnet3_hw *hw = dev->data->dev_private;
1282         uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
1283         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1284
1285         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1286                 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
1287         else
1288                 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE);
1289         vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0);
1290         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1291                                VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1292 }
1293
1294 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
1295 static void
1296 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev)
1297 {
1298         struct vmxnet3_hw *hw = dev->data->dev_private;
1299
1300         vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1);
1301 }
1302
1303 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
1304 static void
1305 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev)
1306 {
1307         struct vmxnet3_hw *hw = dev->data->dev_private;
1308
1309         vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0);
1310 }
1311
1312 /* Enable/disable filter on vlan */
1313 static int
1314 vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on)
1315 {
1316         struct vmxnet3_hw *hw = dev->data->dev_private;
1317         struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
1318         uint32_t *vf_table = rxConf->vfTable;
1319
1320         /* save state for restore */
1321         if (on)
1322                 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid);
1323         else
1324                 VMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid);
1325
1326         /* don't change active filter if in promiscuous mode */
1327         if (rxConf->rxMode & VMXNET3_RXM_PROMISC)
1328                 return 0;
1329
1330         /* set in hardware */
1331         if (on)
1332                 VMXNET3_SET_VFTABLE_ENTRY(vf_table, vid);
1333         else
1334                 VMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid);
1335
1336         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1337                                VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1338         return 0;
1339 }
1340
1341 static int
1342 vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1343 {
1344         struct vmxnet3_hw *hw = dev->data->dev_private;
1345         Vmxnet3_DSDevRead *devRead = &hw->shared->devRead;
1346         uint32_t *vf_table = devRead->rxFilterConf.vfTable;
1347         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1348
1349         if (mask & ETH_VLAN_STRIP_MASK) {
1350                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1351                         devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
1352                 else
1353                         devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN;
1354
1355                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1356                                        VMXNET3_CMD_UPDATE_FEATURE);
1357         }
1358
1359         if (mask & ETH_VLAN_FILTER_MASK) {
1360                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1361                         memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
1362                 else
1363                         memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE);
1364
1365                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1366                                        VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1367         }
1368
1369         return 0;
1370 }
1371
1372 static void
1373 vmxnet3_process_events(struct rte_eth_dev *dev)
1374 {
1375         struct vmxnet3_hw *hw = dev->data->dev_private;
1376         uint32_t events = hw->shared->ecr;
1377
1378         if (!events)
1379                 return;
1380
1381         /*
1382          * ECR bits when written with 1b are cleared. Hence write
1383          * events back to ECR so that the bits which were set will be reset.
1384          */
1385         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events);
1386
1387         /* Check if link state has changed */
1388         if (events & VMXNET3_ECR_LINK) {
1389                 PMD_DRV_LOG(DEBUG, "Process events: VMXNET3_ECR_LINK event");
1390                 if (vmxnet3_dev_link_update(dev, 0) == 0)
1391                         _rte_eth_dev_callback_process(dev,
1392                                                       RTE_ETH_EVENT_INTR_LSC,
1393                                                       NULL);
1394         }
1395
1396         /* Check if there is an error on xmit/recv queues */
1397         if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
1398                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1399                                        VMXNET3_CMD_GET_QUEUE_STATUS);
1400
1401                 if (hw->tqd_start->status.stopped)
1402                         PMD_DRV_LOG(ERR, "tq error 0x%x",
1403                                     hw->tqd_start->status.error);
1404
1405                 if (hw->rqd_start->status.stopped)
1406                         PMD_DRV_LOG(ERR, "rq error 0x%x",
1407                                      hw->rqd_start->status.error);
1408
1409                 /* Reset the device */
1410                 /* Have to reset the device */
1411         }
1412
1413         if (events & VMXNET3_ECR_DIC)
1414                 PMD_DRV_LOG(DEBUG, "Device implementation change event.");
1415
1416         if (events & VMXNET3_ECR_DEBUG)
1417                 PMD_DRV_LOG(DEBUG, "Debug event generated by device.");
1418 }
1419
1420 static void
1421 vmxnet3_interrupt_handler(void *param)
1422 {
1423         struct rte_eth_dev *dev = param;
1424         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1425
1426         vmxnet3_process_events(dev);
1427
1428         if (rte_intr_enable(&pci_dev->intr_handle) < 0)
1429                 PMD_DRV_LOG(ERR, "interrupt enable failed");
1430 }
1431
1432 RTE_PMD_REGISTER_PCI(net_vmxnet3, rte_vmxnet3_pmd);
1433 RTE_PMD_REGISTER_PCI_TABLE(net_vmxnet3, pci_id_vmxnet3_map);
1434 RTE_PMD_REGISTER_KMOD_DEP(net_vmxnet3, "* igb_uio | uio_pci_generic | vfio-pci");
1435
1436 RTE_INIT(vmxnet3_init_log)
1437 {
1438         vmxnet3_logtype_init = rte_log_register("pmd.net.vmxnet3.init");
1439         if (vmxnet3_logtype_init >= 0)
1440                 rte_log_set_level(vmxnet3_logtype_init, RTE_LOG_NOTICE);
1441         vmxnet3_logtype_driver = rte_log_register("pmd.net.vmxnet3.driver");
1442         if (vmxnet3_logtype_driver >= 0)
1443                 rte_log_set_level(vmxnet3_logtype_driver, RTE_LOG_NOTICE);
1444 }