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34 #include <sys/queue.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_string_fns.h>
61 #include <rte_malloc.h>
64 #include "base/vmxnet3_defs.h"
66 #include "vmxnet3_ring.h"
67 #include "vmxnet3_logs.h"
68 #include "vmxnet3_ethdev.h"
70 #define PROCESS_SYS_EVENTS 0
72 static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev);
73 static int vmxnet3_dev_configure(struct rte_eth_dev *dev);
74 static int vmxnet3_dev_start(struct rte_eth_dev *dev);
75 static void vmxnet3_dev_stop(struct rte_eth_dev *dev);
76 static void vmxnet3_dev_close(struct rte_eth_dev *dev);
77 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set);
78 static void vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev);
79 static void vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev);
80 static void vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev);
81 static void vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev);
82 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev,
83 int wait_to_complete);
84 static void vmxnet3_dev_stats_get(struct rte_eth_dev *dev,
85 struct rte_eth_stats *stats);
86 static void vmxnet3_dev_info_get(struct rte_eth_dev *dev,
87 struct rte_eth_dev_info *dev_info);
88 static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev,
89 uint16_t vid, int on);
90 static void vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask);
91 static void vmxnet3_dev_vlan_offload_set_clear(struct rte_eth_dev *dev,
94 #if PROCESS_SYS_EVENTS == 1
95 static void vmxnet3_process_events(struct vmxnet3_hw *);
98 * The set of PCI devices this driver supports
100 static const struct rte_pci_id pci_id_vmxnet3_map[] = {
102 #define RTE_PCI_DEV_ID_DECL_VMXNET3(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
103 #include "rte_pci_dev_ids.h"
105 { .vendor_id = 0, /* sentinel */ },
108 static const struct eth_dev_ops vmxnet3_eth_dev_ops = {
109 .dev_configure = vmxnet3_dev_configure,
110 .dev_start = vmxnet3_dev_start,
111 .dev_stop = vmxnet3_dev_stop,
112 .dev_close = vmxnet3_dev_close,
113 .promiscuous_enable = vmxnet3_dev_promiscuous_enable,
114 .promiscuous_disable = vmxnet3_dev_promiscuous_disable,
115 .allmulticast_enable = vmxnet3_dev_allmulticast_enable,
116 .allmulticast_disable = vmxnet3_dev_allmulticast_disable,
117 .link_update = vmxnet3_dev_link_update,
118 .stats_get = vmxnet3_dev_stats_get,
119 .dev_infos_get = vmxnet3_dev_info_get,
120 .vlan_filter_set = vmxnet3_dev_vlan_filter_set,
121 .vlan_offload_set = vmxnet3_dev_vlan_offload_set,
122 .rx_queue_setup = vmxnet3_dev_rx_queue_setup,
123 .rx_queue_release = vmxnet3_dev_rx_queue_release,
124 .tx_queue_setup = vmxnet3_dev_tx_queue_setup,
125 .tx_queue_release = vmxnet3_dev_tx_queue_release,
128 static const struct rte_memzone *
129 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size,
130 const char *post_string, int socket_id, uint16_t align)
132 char z_name[RTE_MEMZONE_NAMESIZE];
133 const struct rte_memzone *mz;
135 snprintf(z_name, sizeof(z_name), "%s_%d_%s",
136 dev->driver->pci_drv.name, dev->data->port_id, post_string);
138 mz = rte_memzone_lookup(z_name);
142 return rte_memzone_reserve_aligned(z_name, size,
143 socket_id, 0, align);
147 * Atomically reads the link status information from global
148 * structure rte_eth_dev.
151 * - Pointer to the structure rte_eth_dev to read from.
152 * - Pointer to the buffer to be saved with the link status.
155 * - On success, zero.
156 * - On failure, negative value.
160 vmxnet3_dev_atomic_read_link_status(struct rte_eth_dev *dev,
161 struct rte_eth_link *link)
163 struct rte_eth_link *dst = link;
164 struct rte_eth_link *src = &(dev->data->dev_link);
166 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
167 *(uint64_t *)src) == 0)
174 * Atomically writes the link status information into global
175 * structure rte_eth_dev.
178 * - Pointer to the structure rte_eth_dev to write to.
179 * - Pointer to the buffer to be saved with the link status.
182 * - On success, zero.
183 * - On failure, negative value.
186 vmxnet3_dev_atomic_write_link_status(struct rte_eth_dev *dev,
187 struct rte_eth_link *link)
189 struct rte_eth_link *dst = &(dev->data->dev_link);
190 struct rte_eth_link *src = link;
192 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
193 *(uint64_t *)src) == 0)
200 * This function is based on vmxnet3_disable_intr()
203 vmxnet3_disable_intr(struct vmxnet3_hw *hw)
207 PMD_INIT_FUNC_TRACE();
209 hw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
210 for (i = 0; i < VMXNET3_MAX_INTRS; i++)
211 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1);
215 * It returns 0 on success.
218 eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev)
220 struct rte_pci_device *pci_dev;
221 struct vmxnet3_hw *hw = eth_dev->data->dev_private;
222 uint32_t mac_hi, mac_lo, ver;
224 PMD_INIT_FUNC_TRACE();
226 eth_dev->dev_ops = &vmxnet3_eth_dev_ops;
227 eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts;
228 eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts;
229 pci_dev = eth_dev->pci_dev;
232 * for secondary processes, we don't initialize any further as primary
233 * has already done this work.
235 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
238 rte_eth_copy_pci_info(eth_dev, pci_dev);
240 /* Vendor and Device ID need to be set before init of shared code */
241 hw->device_id = pci_dev->id.device_id;
242 hw->vendor_id = pci_dev->id.vendor_id;
243 hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr;
244 hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr;
246 hw->num_rx_queues = 1;
247 hw->num_tx_queues = 1;
248 hw->bufs_per_pkt = 1;
250 /* Check h/w version compatibility with driver. */
251 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS);
252 PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver);
254 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 1);
256 PMD_INIT_LOG(ERR, "Incompatible h/w version, should be 0x1");
260 /* Check UPT version compatibility with driver. */
261 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS);
262 PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver);
264 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1);
266 PMD_INIT_LOG(ERR, "Incompatible UPT version.");
270 /* Getting MAC Address */
271 mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL);
272 mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH);
273 memcpy(hw->perm_addr , &mac_lo, 4);
274 memcpy(hw->perm_addr+4, &mac_hi, 2);
276 /* Allocate memory for storing MAC addresses */
277 eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", ETHER_ADDR_LEN *
278 VMXNET3_MAX_MAC_ADDRS, 0);
279 if (eth_dev->data->mac_addrs == NULL) {
281 "Failed to allocate %d bytes needed to store MAC addresses",
282 ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS);
285 /* Copy the permanent MAC address */
286 ether_addr_copy((struct ether_addr *) hw->perm_addr,
287 ð_dev->data->mac_addrs[0]);
289 PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
290 hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2],
291 hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]);
293 /* Put device in Quiesce Mode */
294 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
299 static struct eth_driver rte_vmxnet3_pmd = {
301 .name = "rte_vmxnet3_pmd",
302 .id_table = pci_id_vmxnet3_map,
303 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
305 .eth_dev_init = eth_vmxnet3_dev_init,
306 .dev_private_size = sizeof(struct vmxnet3_hw),
310 * Driver initialization routine.
311 * Invoked once at EAL init time.
312 * Register itself as the [Poll Mode] Driver of Virtual PCI VMXNET3 devices.
315 rte_vmxnet3_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
317 PMD_INIT_FUNC_TRACE();
319 rte_eth_driver_register(&rte_vmxnet3_pmd);
324 vmxnet3_dev_configure(struct rte_eth_dev *dev)
326 const struct rte_memzone *mz;
327 struct vmxnet3_hw *hw = dev->data->dev_private;
330 PMD_INIT_FUNC_TRACE();
332 if (dev->data->nb_rx_queues > UINT8_MAX ||
333 dev->data->nb_tx_queues > UINT8_MAX)
336 size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
337 dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc);
339 if (size > UINT16_MAX)
342 hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues;
343 hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues;
346 * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead
349 mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared),
350 "shared", rte_socket_id(), 8);
353 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone");
356 memset(mz->addr, 0, mz->len);
358 hw->shared = mz->addr;
359 hw->sharedPA = mz->phys_addr;
362 * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc
365 mz = gpa_zone_reserve(dev, size, "queuedesc",
366 rte_socket_id(), VMXNET3_QUEUE_DESC_ALIGN);
368 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone");
371 memset(mz->addr, 0, mz->len);
373 hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr;
374 hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues);
376 hw->queueDescPA = mz->phys_addr;
377 hw->queue_desc_len = (uint16_t)size;
379 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
381 /* Allocate memory structure for UPT1_RSSConf and configure */
382 mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf), "rss_conf",
383 rte_socket_id(), RTE_CACHE_LINE_SIZE);
386 "ERROR: Creating rss_conf structure zone");
389 memset(mz->addr, 0, mz->len);
391 hw->rss_conf = mz->addr;
392 hw->rss_confPA = mz->phys_addr;
399 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev)
401 struct rte_eth_conf port_conf = dev->data->dev_conf;
402 struct vmxnet3_hw *hw = dev->data->dev_private;
403 Vmxnet3_DriverShared *shared = hw->shared;
404 Vmxnet3_DSDevRead *devRead = &shared->devRead;
409 shared->magic = VMXNET3_REV1_MAGIC;
410 devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM;
412 /* Setting up Guest OS information */
413 devRead->misc.driverInfo.gos.gosBits = sizeof(void *) == 4 ?
414 VMXNET3_GOS_BITS_32 :
416 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
417 devRead->misc.driverInfo.vmxnet3RevSpt = 1;
418 devRead->misc.driverInfo.uptVerSpt = 1;
420 devRead->misc.mtu = rte_le_to_cpu_32(dev->data->mtu);
421 devRead->misc.queueDescPA = hw->queueDescPA;
422 devRead->misc.queueDescLen = hw->queue_desc_len;
423 devRead->misc.numTxQueues = hw->num_tx_queues;
424 devRead->misc.numRxQueues = hw->num_rx_queues;
427 * Set number of interrupts to 1
428 * PMD disables all the interrupts but this is MUST to activate device
429 * It needs at least one interrupt for link events to handle
430 * So we'll disable it later after device activation if needed
432 devRead->intrConf.numIntrs = 1;
433 devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
435 for (i = 0; i < hw->num_tx_queues; i++) {
436 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i];
437 vmxnet3_tx_queue_t *txq = dev->data->tx_queues[i];
439 tqd->ctrl.txNumDeferred = 0;
440 tqd->ctrl.txThreshold = 1;
441 tqd->conf.txRingBasePA = txq->cmd_ring.basePA;
442 tqd->conf.compRingBasePA = txq->comp_ring.basePA;
443 tqd->conf.dataRingBasePA = txq->data_ring.basePA;
445 tqd->conf.txRingSize = txq->cmd_ring.size;
446 tqd->conf.compRingSize = txq->comp_ring.size;
447 tqd->conf.dataRingSize = txq->data_ring.size;
448 tqd->conf.intrIdx = txq->comp_ring.intr_idx;
449 tqd->status.stopped = TRUE;
450 tqd->status.error = 0;
451 memset(&tqd->stats, 0, sizeof(tqd->stats));
454 for (i = 0; i < hw->num_rx_queues; i++) {
455 Vmxnet3_RxQueueDesc *rqd = &hw->rqd_start[i];
456 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i];
458 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA;
459 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA;
460 rqd->conf.compRingBasePA = rxq->comp_ring.basePA;
462 rqd->conf.rxRingSize[0] = rxq->cmd_ring[0].size;
463 rqd->conf.rxRingSize[1] = rxq->cmd_ring[1].size;
464 rqd->conf.compRingSize = rxq->comp_ring.size;
465 rqd->conf.intrIdx = rxq->comp_ring.intr_idx;
466 rqd->status.stopped = TRUE;
467 rqd->status.error = 0;
468 memset(&rqd->stats, 0, sizeof(rqd->stats));
471 /* RxMode set to 0 of VMXNET3_RXM_xxx */
472 devRead->rxFilterConf.rxMode = 0;
474 /* Setting up feature flags */
475 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
476 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM;
478 if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
479 ret = vmxnet3_rss_configure(dev);
480 if (ret != VMXNET3_SUCCESS)
483 devRead->misc.uptFeatures |= VMXNET3_F_RSS;
484 devRead->rssConfDesc.confVer = 1;
485 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf);
486 devRead->rssConfDesc.confPA = hw->rss_confPA;
490 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
491 mask |= ETH_VLAN_STRIP_MASK;
493 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
494 mask |= ETH_VLAN_FILTER_MASK;
496 vmxnet3_dev_vlan_offload_set_clear(dev, mask, 1);
499 "Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
500 hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2],
501 hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]);
503 /* Write MAC Address back to device */
504 mac_ptr = (uint32_t *)hw->perm_addr;
506 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val);
508 val = (hw->perm_addr[5] << 8) | hw->perm_addr[4];
509 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val);
511 return VMXNET3_SUCCESS;
515 * Configure device link speed and setup link.
516 * Must be called after eth_vmxnet3_dev_init. Other wise it might fail
517 * It returns 0 on success.
520 vmxnet3_dev_start(struct rte_eth_dev *dev)
523 struct vmxnet3_hw *hw = dev->data->dev_private;
525 PMD_INIT_FUNC_TRACE();
527 ret = vmxnet3_setup_driver_shared(dev);
528 if (ret != VMXNET3_SUCCESS)
531 /* Exchange shared data with device */
532 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL,
533 VMXNET3_GET_ADDR_LO(hw->sharedPA));
534 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH,
535 VMXNET3_GET_ADDR_HI(hw->sharedPA));
537 /* Activate device by register write */
538 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV);
539 status = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
542 PMD_INIT_LOG(ERR, "Device activation in %s(): UNSUCCESSFUL", __func__);
546 /* Disable interrupts */
547 vmxnet3_disable_intr(hw);
550 * Load RX queues with blank mbufs and update next2fill index for device
551 * Update RxMode of the device
553 ret = vmxnet3_dev_rxtx_init(dev);
554 if (ret != VMXNET3_SUCCESS) {
555 PMD_INIT_LOG(ERR, "Device receive init in %s: UNSUCCESSFUL", __func__);
559 /* Setting proper Rx Mode and issue Rx Mode Update command */
560 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1);
563 * Don't need to handle events for now
565 #if PROCESS_SYS_EVENTS == 1
566 events = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_ECR);
567 PMD_INIT_LOG(DEBUG, "Reading events: 0x%X", events);
568 vmxnet3_process_events(hw);
574 * Stop device: disable rx and tx functions to allow for reconfiguring.
577 vmxnet3_dev_stop(struct rte_eth_dev *dev)
579 struct rte_eth_link link;
580 struct vmxnet3_hw *hw = dev->data->dev_private;
582 PMD_INIT_FUNC_TRACE();
584 if (hw->adapter_stopped == TRUE) {
585 PMD_INIT_LOG(DEBUG, "Device already closed.");
589 /* disable interrupts */
590 vmxnet3_disable_intr(hw);
592 /* quiesce the device first */
593 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
594 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0);
595 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0);
597 /* reset the device */
598 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
599 PMD_INIT_LOG(DEBUG, "Device reset.");
600 hw->adapter_stopped = FALSE;
602 vmxnet3_dev_clear_queues(dev);
604 /* Clear recorded link status */
605 memset(&link, 0, sizeof(link));
606 vmxnet3_dev_atomic_write_link_status(dev, &link);
610 * Reset and stop device.
613 vmxnet3_dev_close(struct rte_eth_dev *dev)
615 struct vmxnet3_hw *hw = dev->data->dev_private;
617 PMD_INIT_FUNC_TRACE();
619 vmxnet3_dev_stop(dev);
620 hw->adapter_stopped = TRUE;
624 vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
627 struct vmxnet3_hw *hw = dev->data->dev_private;
629 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
631 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
632 for (i = 0; i < hw->num_tx_queues; i++) {
633 struct UPT1_TxStats *txStats = &hw->tqd_start[i].stats;
635 stats->q_opackets[i] = txStats->ucastPktsTxOK +
636 txStats->mcastPktsTxOK +
637 txStats->bcastPktsTxOK;
638 stats->q_obytes[i] = txStats->ucastBytesTxOK +
639 txStats->mcastBytesTxOK +
640 txStats->bcastBytesTxOK;
642 stats->opackets += stats->q_opackets[i];
643 stats->obytes += stats->q_obytes[i];
644 stats->oerrors += txStats->pktsTxError +
645 txStats->pktsTxDiscard;
648 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES);
649 for (i = 0; i < hw->num_rx_queues; i++) {
650 struct UPT1_RxStats *rxStats = &hw->rqd_start[i].stats;
652 stats->q_ipackets[i] = rxStats->ucastPktsRxOK +
653 rxStats->mcastPktsRxOK +
654 rxStats->bcastPktsRxOK;
656 stats->q_ibytes[i] = rxStats->ucastBytesRxOK +
657 rxStats->mcastBytesRxOK +
658 rxStats->bcastBytesRxOK;
660 stats->ipackets += stats->q_ipackets[i];
661 stats->ibytes += stats->q_ibytes[i];
663 stats->q_errors[i] = rxStats->pktsRxError;
664 stats->ierrors += rxStats->pktsRxError;
665 stats->imcasts += rxStats->mcastPktsRxOK;
666 stats->rx_nombuf += rxStats->pktsRxOutOfBuf;
671 vmxnet3_dev_info_get(__attribute__((unused))struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
673 dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES;
674 dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES;
675 dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM;
676 dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */
677 dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS;
679 dev_info->default_txconf.txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
680 ETH_TXQ_FLAGS_NOOFFLOADS;
681 dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL;
683 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
684 .nb_max = VMXNET3_RX_RING_MAX_SIZE,
685 .nb_min = VMXNET3_DEF_RX_RING_SIZE,
689 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
690 .nb_max = VMXNET3_TX_RING_MAX_SIZE,
691 .nb_min = VMXNET3_DEF_TX_RING_SIZE,
696 /* return 0 means link status changed, -1 means not changed */
698 vmxnet3_dev_link_update(struct rte_eth_dev *dev, __attribute__((unused)) int wait_to_complete)
700 struct vmxnet3_hw *hw = dev->data->dev_private;
701 struct rte_eth_link old, link;
704 if (dev->data->dev_started == 0)
705 return -1; /* Link status doesn't change for stopped dev */
707 memset(&link, 0, sizeof(link));
708 vmxnet3_dev_atomic_read_link_status(dev, &old);
710 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
711 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
714 link.link_status = 1;
715 link.link_duplex = ETH_LINK_FULL_DUPLEX;
716 link.link_speed = ETH_LINK_SPEED_10000;
719 vmxnet3_dev_atomic_write_link_status(dev, &link);
721 return (old.link_status == link.link_status) ? -1 : 0;
724 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */
726 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set) {
728 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
731 rxConf->rxMode = rxConf->rxMode | feature;
733 rxConf->rxMode = rxConf->rxMode & (~feature);
735 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE);
738 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
740 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev)
742 struct vmxnet3_hw *hw = dev->data->dev_private;
743 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
745 memset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE);
746 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1);
748 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
749 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
752 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
754 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev)
756 struct vmxnet3_hw *hw = dev->data->dev_private;
757 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
759 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
760 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0);
761 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
762 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
765 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
767 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev)
769 struct vmxnet3_hw *hw = dev->data->dev_private;
771 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1);
774 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
776 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev)
778 struct vmxnet3_hw *hw = dev->data->dev_private;
780 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0);
783 /* Enable/disable filter on vlan */
785 vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on)
787 struct vmxnet3_hw *hw = dev->data->dev_private;
788 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
789 uint32_t *vf_table = rxConf->vfTable;
791 /* save state for restore */
793 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid);
795 VMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid);
797 /* don't change active filter if in promiscious mode */
798 if (rxConf->rxMode & VMXNET3_RXM_PROMISC)
801 /* set in hardware */
803 VMXNET3_SET_VFTABLE_ENTRY(vf_table, vid);
805 VMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid);
807 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
808 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
813 vmxnet3_dev_vlan_offload_set_clear(struct rte_eth_dev *dev,
816 struct vmxnet3_hw *hw = dev->data->dev_private;
817 Vmxnet3_DSDevRead *devRead = &hw->shared->devRead;
818 uint32_t *vf_table = devRead->rxFilterConf.vfTable;
820 if (mask & ETH_VLAN_STRIP_MASK)
821 devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
823 devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN;
825 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
826 VMXNET3_CMD_UPDATE_FEATURE);
828 if (mask & ETH_VLAN_FILTER_MASK) {
830 memset(hw->shadow_vfta, 0,
831 VMXNET3_VFT_TABLE_SIZE);
832 /* allow untagged pkts */
833 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0);
835 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
837 /* allow any pkts -- no filtering */
839 memset(hw->shadow_vfta, 0xff, VMXNET3_VFT_TABLE_SIZE);
840 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE);
843 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
844 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
848 vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask)
850 vmxnet3_dev_vlan_offload_set_clear(dev, mask, 0);
853 #if PROCESS_SYS_EVENTS == 1
855 vmxnet3_process_events(struct vmxnet3_hw *hw)
857 uint32_t events = hw->shared->ecr;
860 PMD_INIT_LOG(ERR, "No events to process in %s()", __func__);
865 * ECR bits when written with 1b are cleared. Hence write
866 * events back to ECR so that the bits which were set will be reset.
868 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events);
870 /* Check if link state has changed */
871 if (events & VMXNET3_ECR_LINK)
873 "Process events in %s(): VMXNET3_ECR_LINK event", __func__);
875 /* Check if there is an error on xmit/recv queues */
876 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
877 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_QUEUE_STATUS);
879 if (hw->tqd_start->status.stopped)
880 PMD_INIT_LOG(ERR, "tq error 0x%x",
881 hw->tqd_start->status.error);
883 if (hw->rqd_start->status.stopped)
884 PMD_INIT_LOG(ERR, "rq error 0x%x",
885 hw->rqd_start->status.error);
887 /* Reset the device */
888 /* Have to reset the device */
891 if (events & VMXNET3_ECR_DIC)
892 PMD_INIT_LOG(ERR, "Device implementation change event.");
894 if (events & VMXNET3_ECR_DEBUG)
895 PMD_INIT_LOG(ERR, "Debug event generated by device.");
900 static struct rte_driver rte_vmxnet3_driver = {
902 .init = rte_vmxnet3_pmd_init,
905 PMD_REGISTER_DRIVER(rte_vmxnet3_driver);