4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_string_fns.h>
61 #include <rte_malloc.h>
64 #include "base/vmxnet3_defs.h"
66 #include "vmxnet3_ring.h"
67 #include "vmxnet3_logs.h"
68 #include "vmxnet3_ethdev.h"
70 #define PROCESS_SYS_EVENTS 0
72 static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev);
73 static int vmxnet3_dev_configure(struct rte_eth_dev *dev);
74 static int vmxnet3_dev_start(struct rte_eth_dev *dev);
75 static void vmxnet3_dev_stop(struct rte_eth_dev *dev);
76 static void vmxnet3_dev_close(struct rte_eth_dev *dev);
77 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set);
78 static void vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev);
79 static void vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev);
80 static void vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev);
81 static void vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev);
82 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev,
83 int wait_to_complete);
84 static void vmxnet3_dev_stats_get(struct rte_eth_dev *dev,
85 struct rte_eth_stats *stats);
86 static void vmxnet3_dev_info_get(struct rte_eth_dev *dev,
87 struct rte_eth_dev_info *dev_info);
88 #if PROCESS_SYS_EVENTS == 1
89 static void vmxnet3_process_events(struct vmxnet3_hw *);
92 * The set of PCI devices this driver supports
94 static const struct rte_pci_id pci_id_vmxnet3_map[] = {
96 #define RTE_PCI_DEV_ID_DECL_VMXNET3(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
97 #include "rte_pci_dev_ids.h"
99 { .vendor_id = 0, /* sentinel */ },
102 static const struct eth_dev_ops vmxnet3_eth_dev_ops = {
103 .dev_configure = vmxnet3_dev_configure,
104 .dev_start = vmxnet3_dev_start,
105 .dev_stop = vmxnet3_dev_stop,
106 .dev_close = vmxnet3_dev_close,
107 .promiscuous_enable = vmxnet3_dev_promiscuous_enable,
108 .promiscuous_disable = vmxnet3_dev_promiscuous_disable,
109 .allmulticast_enable = vmxnet3_dev_allmulticast_enable,
110 .allmulticast_disable = vmxnet3_dev_allmulticast_disable,
111 .link_update = vmxnet3_dev_link_update,
112 .stats_get = vmxnet3_dev_stats_get,
113 .dev_infos_get = vmxnet3_dev_info_get,
114 .rx_queue_setup = vmxnet3_dev_rx_queue_setup,
115 .rx_queue_release = vmxnet3_dev_rx_queue_release,
116 .tx_queue_setup = vmxnet3_dev_tx_queue_setup,
117 .tx_queue_release = vmxnet3_dev_tx_queue_release,
120 static const struct rte_memzone *
121 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size,
122 const char *post_string, int socket_id, uint16_t align)
124 char z_name[RTE_MEMZONE_NAMESIZE];
125 const struct rte_memzone *mz;
127 snprintf(z_name, sizeof(z_name), "%s_%d_%s",
128 dev->driver->pci_drv.name, dev->data->port_id, post_string);
130 mz = rte_memzone_lookup(z_name);
134 return rte_memzone_reserve_aligned(z_name, size,
135 socket_id, 0, align);
139 * Atomically reads the link status information from global
140 * structure rte_eth_dev.
143 * - Pointer to the structure rte_eth_dev to read from.
144 * - Pointer to the buffer to be saved with the link status.
147 * - On success, zero.
148 * - On failure, negative value.
151 rte_vmxnet3_dev_atomic_write_link_status(struct rte_eth_dev *dev,
152 struct rte_eth_link *link)
154 struct rte_eth_link *dst = &(dev->data->dev_link);
155 struct rte_eth_link *src = link;
157 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
158 *(uint64_t *)src) == 0)
165 * This function is based on vmxnet3_disable_intr()
168 vmxnet3_disable_intr(struct vmxnet3_hw *hw)
172 PMD_INIT_FUNC_TRACE();
174 hw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
175 for (i = 0; i < VMXNET3_MAX_INTRS; i++)
176 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1);
180 * It returns 0 on success.
183 eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev)
185 struct rte_pci_device *pci_dev;
186 struct vmxnet3_hw *hw = eth_dev->data->dev_private;
187 uint32_t mac_hi, mac_lo, ver;
189 PMD_INIT_FUNC_TRACE();
191 eth_dev->dev_ops = &vmxnet3_eth_dev_ops;
192 eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts;
193 eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts;
194 pci_dev = eth_dev->pci_dev;
197 * for secondary processes, we don't initialize any further as primary
198 * has already done this work.
200 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
203 /* Vendor and Device ID need to be set before init of shared code */
204 hw->device_id = pci_dev->id.device_id;
205 hw->vendor_id = pci_dev->id.vendor_id;
206 hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr;
207 hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr;
209 hw->num_rx_queues = 1;
210 hw->num_tx_queues = 1;
211 hw->cur_mtu = ETHER_MTU;
212 hw->bufs_per_pkt = 1;
214 /* Check h/w version compatibility with driver. */
215 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS);
216 PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver);
218 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 1);
220 PMD_INIT_LOG(ERR, "Incompatible h/w version, should be 0x1");
224 /* Check UPT version compatibility with driver. */
225 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS);
226 PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver);
228 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1);
230 PMD_INIT_LOG(ERR, "Incompatible UPT version.");
234 /* Getting MAC Address */
235 mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL);
236 mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH);
237 memcpy(hw->perm_addr , &mac_lo, 4);
238 memcpy(hw->perm_addr+4, &mac_hi, 2);
240 /* Allocate memory for storing MAC addresses */
241 eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", ETHER_ADDR_LEN *
242 VMXNET3_MAX_MAC_ADDRS, 0);
243 if (eth_dev->data->mac_addrs == NULL) {
245 "Failed to allocate %d bytes needed to store MAC addresses",
246 ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS);
249 /* Copy the permanent MAC address */
250 ether_addr_copy((struct ether_addr *) hw->perm_addr,
251 ð_dev->data->mac_addrs[0]);
253 PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
254 hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2],
255 hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]);
257 /* Put device in Quiesce Mode */
258 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
263 static struct eth_driver rte_vmxnet3_pmd = {
265 .name = "rte_vmxnet3_pmd",
266 .id_table = pci_id_vmxnet3_map,
267 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
269 .eth_dev_init = eth_vmxnet3_dev_init,
270 .dev_private_size = sizeof(struct vmxnet3_hw),
274 * Driver initialization routine.
275 * Invoked once at EAL init time.
276 * Register itself as the [Poll Mode] Driver of Virtual PCI VMXNET3 devices.
279 rte_vmxnet3_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
281 PMD_INIT_FUNC_TRACE();
283 rte_eth_driver_register(&rte_vmxnet3_pmd);
288 vmxnet3_dev_configure(struct rte_eth_dev *dev)
290 const struct rte_memzone *mz;
291 struct vmxnet3_hw *hw = dev->data->dev_private;
294 PMD_INIT_FUNC_TRACE();
296 if (dev->data->nb_rx_queues > UINT8_MAX ||
297 dev->data->nb_tx_queues > UINT8_MAX)
300 size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
301 dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc);
303 if (size > UINT16_MAX)
306 hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues;
307 hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues;
310 * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead
313 mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared),
314 "shared", rte_socket_id(), 8);
317 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone");
320 memset(mz->addr, 0, mz->len);
322 hw->shared = mz->addr;
323 hw->sharedPA = mz->phys_addr;
326 * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc
329 mz = gpa_zone_reserve(dev, size, "queuedesc",
330 rte_socket_id(), VMXNET3_QUEUE_DESC_ALIGN);
332 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone");
335 memset(mz->addr, 0, mz->len);
337 hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr;
338 hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues);
340 hw->queueDescPA = mz->phys_addr;
341 hw->queue_desc_len = (uint16_t)size;
343 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
345 /* Allocate memory structure for UPT1_RSSConf and configure */
346 mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf), "rss_conf",
347 rte_socket_id(), RTE_CACHE_LINE_SIZE);
350 "ERROR: Creating rss_conf structure zone");
353 memset(mz->addr, 0, mz->len);
355 hw->rss_conf = mz->addr;
356 hw->rss_confPA = mz->phys_addr;
363 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev)
365 struct rte_eth_conf port_conf = dev->data->dev_conf;
366 struct vmxnet3_hw *hw = dev->data->dev_private;
367 Vmxnet3_DriverShared *shared = hw->shared;
368 Vmxnet3_DSDevRead *devRead = &shared->devRead;
373 shared->magic = VMXNET3_REV1_MAGIC;
374 devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM;
376 /* Setting up Guest OS information */
377 devRead->misc.driverInfo.gos.gosBits = sizeof(void *) == 4 ?
378 VMXNET3_GOS_BITS_32 :
380 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
381 devRead->misc.driverInfo.vmxnet3RevSpt = 1;
382 devRead->misc.driverInfo.uptVerSpt = 1;
384 devRead->misc.queueDescPA = hw->queueDescPA;
385 devRead->misc.queueDescLen = hw->queue_desc_len;
386 devRead->misc.mtu = hw->cur_mtu;
387 devRead->misc.numTxQueues = hw->num_tx_queues;
388 devRead->misc.numRxQueues = hw->num_rx_queues;
391 * Set number of interrupts to 1
392 * PMD disables all the interrupts but this is MUST to activate device
393 * It needs at least one interrupt for link events to handle
394 * So we'll disable it later after device activation if needed
396 devRead->intrConf.numIntrs = 1;
397 devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
399 for (i = 0; i < hw->num_tx_queues; i++) {
400 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i];
401 vmxnet3_tx_queue_t *txq = dev->data->tx_queues[i];
403 tqd->ctrl.txNumDeferred = 0;
404 tqd->ctrl.txThreshold = 1;
405 tqd->conf.txRingBasePA = txq->cmd_ring.basePA;
406 tqd->conf.compRingBasePA = txq->comp_ring.basePA;
407 tqd->conf.dataRingBasePA = txq->data_ring.basePA;
409 tqd->conf.txRingSize = txq->cmd_ring.size;
410 tqd->conf.compRingSize = txq->comp_ring.size;
411 tqd->conf.dataRingSize = txq->data_ring.size;
412 tqd->conf.intrIdx = txq->comp_ring.intr_idx;
413 tqd->status.stopped = TRUE;
414 tqd->status.error = 0;
415 memset(&tqd->stats, 0, sizeof(tqd->stats));
418 for (i = 0; i < hw->num_rx_queues; i++) {
419 Vmxnet3_RxQueueDesc *rqd = &hw->rqd_start[i];
420 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i];
422 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA;
423 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA;
424 rqd->conf.compRingBasePA = rxq->comp_ring.basePA;
426 rqd->conf.rxRingSize[0] = rxq->cmd_ring[0].size;
427 rqd->conf.rxRingSize[1] = rxq->cmd_ring[1].size;
428 rqd->conf.compRingSize = rxq->comp_ring.size;
429 rqd->conf.intrIdx = rxq->comp_ring.intr_idx;
430 rqd->status.stopped = TRUE;
431 rqd->status.error = 0;
432 memset(&rqd->stats, 0, sizeof(rqd->stats));
435 /* RxMode set to 0 of VMXNET3_RXM_xxx */
436 devRead->rxFilterConf.rxMode = 0;
438 /* Setting up feature flags */
439 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
440 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM;
442 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
443 devRead->misc.uptFeatures |= VMXNET3_F_RXVLAN;
445 if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
446 ret = vmxnet3_rss_configure(dev);
447 if (ret != VMXNET3_SUCCESS)
450 devRead->misc.uptFeatures |= VMXNET3_F_RSS;
451 devRead->rssConfDesc.confVer = 1;
452 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf);
453 devRead->rssConfDesc.confPA = hw->rss_confPA;
456 if (dev->data->dev_conf.rxmode.hw_vlan_filter) {
457 ret = vmxnet3_vlan_configure(dev);
458 if (ret != VMXNET3_SUCCESS)
463 "Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
464 hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2],
465 hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]);
467 /* Write MAC Address back to device */
468 mac_ptr = (uint32_t *)hw->perm_addr;
470 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val);
472 val = (hw->perm_addr[5] << 8) | hw->perm_addr[4];
473 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val);
475 return VMXNET3_SUCCESS;
479 * Configure device link speed and setup link.
480 * Must be called after eth_vmxnet3_dev_init. Other wise it might fail
481 * It returns 0 on success.
484 vmxnet3_dev_start(struct rte_eth_dev *dev)
487 struct vmxnet3_hw *hw = dev->data->dev_private;
489 PMD_INIT_FUNC_TRACE();
491 ret = vmxnet3_setup_driver_shared(dev);
492 if (ret != VMXNET3_SUCCESS)
495 /* Exchange shared data with device */
496 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL,
497 VMXNET3_GET_ADDR_LO(hw->sharedPA));
498 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH,
499 VMXNET3_GET_ADDR_HI(hw->sharedPA));
501 /* Activate device by register write */
502 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV);
503 status = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
506 PMD_INIT_LOG(ERR, "Device activation in %s(): UNSUCCESSFUL", __func__);
510 /* Disable interrupts */
511 vmxnet3_disable_intr(hw);
514 * Load RX queues with blank mbufs and update next2fill index for device
515 * Update RxMode of the device
517 ret = vmxnet3_dev_rxtx_init(dev);
518 if (ret != VMXNET3_SUCCESS) {
519 PMD_INIT_LOG(ERR, "Device receive init in %s: UNSUCCESSFUL", __func__);
523 /* Setting proper Rx Mode and issue Rx Mode Update command */
524 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1);
527 * Don't need to handle events for now
529 #if PROCESS_SYS_EVENTS == 1
530 events = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_ECR);
531 PMD_INIT_LOG(DEBUG, "Reading events: 0x%X", events);
532 vmxnet3_process_events(hw);
538 * Stop device: disable rx and tx functions to allow for reconfiguring.
541 vmxnet3_dev_stop(struct rte_eth_dev *dev)
543 struct rte_eth_link link;
544 struct vmxnet3_hw *hw = dev->data->dev_private;
546 PMD_INIT_FUNC_TRACE();
548 if (hw->adapter_stopped == TRUE) {
549 PMD_INIT_LOG(DEBUG, "Device already closed.");
553 /* disable interrupts */
554 vmxnet3_disable_intr(hw);
556 /* quiesce the device first */
557 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
558 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0);
559 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0);
561 /* reset the device */
562 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
563 PMD_INIT_LOG(DEBUG, "Device reset.");
564 hw->adapter_stopped = FALSE;
566 vmxnet3_dev_clear_queues(dev);
568 /* Clear recorded link status */
569 memset(&link, 0, sizeof(link));
570 rte_vmxnet3_dev_atomic_write_link_status(dev, &link);
574 * Reset and stop device.
577 vmxnet3_dev_close(struct rte_eth_dev *dev)
579 struct vmxnet3_hw *hw = dev->data->dev_private;
581 PMD_INIT_FUNC_TRACE();
583 vmxnet3_dev_stop(dev);
584 hw->adapter_stopped = TRUE;
588 vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
591 struct vmxnet3_hw *hw = dev->data->dev_private;
593 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
595 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
596 for (i = 0; i < hw->num_tx_queues; i++) {
597 struct UPT1_TxStats *txStats = &hw->tqd_start[i].stats;
599 stats->q_opackets[i] = txStats->ucastPktsTxOK +
600 txStats->mcastPktsTxOK +
601 txStats->bcastPktsTxOK;
602 stats->q_obytes[i] = txStats->ucastBytesTxOK +
603 txStats->mcastBytesTxOK +
604 txStats->bcastBytesTxOK;
606 stats->opackets += stats->q_opackets[i];
607 stats->obytes += stats->q_obytes[i];
608 stats->oerrors += txStats->pktsTxError +
609 txStats->pktsTxDiscard;
612 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES);
613 for (i = 0; i < hw->num_rx_queues; i++) {
614 struct UPT1_RxStats *rxStats = &hw->rqd_start[i].stats;
616 stats->q_ipackets[i] = rxStats->ucastPktsRxOK +
617 rxStats->mcastPktsRxOK +
618 rxStats->bcastPktsRxOK;
620 stats->q_ibytes[i] = rxStats->ucastBytesRxOK +
621 rxStats->mcastBytesRxOK +
622 rxStats->bcastBytesRxOK;
624 stats->ipackets += stats->q_ipackets[i];
625 stats->ibytes += stats->q_ibytes[i];
627 stats->q_errors[i] = rxStats->pktsRxError;
628 stats->ierrors += rxStats->pktsRxError;
629 stats->imcasts += rxStats->mcastPktsRxOK;
630 stats->rx_nombuf += rxStats->pktsRxOutOfBuf;
635 vmxnet3_dev_info_get(__attribute__((unused))struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
637 dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES;
638 dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES;
639 dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM;
640 dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */
641 dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS;
643 dev_info->default_txconf.txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
644 ETH_TXQ_FLAGS_NOOFFLOADS;
645 dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL;
648 /* return 0 means link status changed, -1 means not changed */
650 vmxnet3_dev_link_update(struct rte_eth_dev *dev, __attribute__((unused)) int wait_to_complete)
652 struct vmxnet3_hw *hw = dev->data->dev_private;
653 struct rte_eth_link link;
656 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
657 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
660 PMD_INIT_LOG(ERR, "Link Status Negative : %s()", __func__);
665 link.link_status = 1;
666 link.link_duplex = ETH_LINK_FULL_DUPLEX;
667 link.link_speed = ETH_LINK_SPEED_10000;
669 rte_vmxnet3_dev_atomic_write_link_status(dev, &link);
677 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */
679 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set) {
681 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
684 rxConf->rxMode = rxConf->rxMode | feature;
686 rxConf->rxMode = rxConf->rxMode & (~feature);
688 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE);
691 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
693 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev)
695 struct vmxnet3_hw *hw = dev->data->dev_private;
697 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1);
700 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
702 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev)
704 struct vmxnet3_hw *hw = dev->data->dev_private;
706 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0);
709 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
711 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev)
713 struct vmxnet3_hw *hw = dev->data->dev_private;
715 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1);
718 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
720 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev)
722 struct vmxnet3_hw *hw = dev->data->dev_private;
724 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0);
727 #if PROCESS_SYS_EVENTS == 1
729 vmxnet3_process_events(struct vmxnet3_hw *hw)
731 uint32_t events = hw->shared->ecr;
734 PMD_INIT_LOG(ERR, "No events to process in %s()", __func__);
739 * ECR bits when written with 1b are cleared. Hence write
740 * events back to ECR so that the bits which were set will be reset.
742 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events);
744 /* Check if link state has changed */
745 if (events & VMXNET3_ECR_LINK)
747 "Process events in %s(): VMXNET3_ECR_LINK event", __func__);
749 /* Check if there is an error on xmit/recv queues */
750 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
751 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_QUEUE_STATUS);
753 if (hw->tqd_start->status.stopped)
754 PMD_INIT_LOG(ERR, "tq error 0x%x",
755 hw->tqd_start->status.error);
757 if (hw->rqd_start->status.stopped)
758 PMD_INIT_LOG(ERR, "rq error 0x%x",
759 hw->rqd_start->status.error);
761 /* Reset the device */
762 /* Have to reset the device */
765 if (events & VMXNET3_ECR_DIC)
766 PMD_INIT_LOG(ERR, "Device implementation change event.");
768 if (events & VMXNET3_ECR_DEBUG)
769 PMD_INIT_LOG(ERR, "Debug event generated by device.");
774 static struct rte_driver rte_vmxnet3_driver = {
776 .init = rte_vmxnet3_pmd_init,
779 PMD_REGISTER_DRIVER(rte_vmxnet3_driver);