drivers/raw/cnxk_bphy/rte_pmd_bphy.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #ifndef _CNXK_BPHY_H_
   6 #define _CNXK_BPHY_H_
   7
   8 #include "cnxk_bphy_irq.h"
   9
  10 enum cnxk_bphy_cgx_msg_type {
  11         CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO,
  12         CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE,
  13         CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE,
  14         CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE,
  15         CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE,
  16         CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE,
  17         CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE,
  18         CNXK_BPHY_CGX_MSG_TYPE_START_RXTX,
  19         CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX,
  20 };
  21
  22 enum cnxk_bphy_cgx_eth_link_speed {
  23         CNXK_BPHY_CGX_ETH_LINK_SPEED_NONE,
  24         CNXK_BPHY_CGX_ETH_LINK_SPEED_10M,
  25         CNXK_BPHY_CGX_ETH_LINK_SPEED_100M,
  26         CNXK_BPHY_CGX_ETH_LINK_SPEED_1G,
  27         CNXK_BPHY_CGX_ETH_LINK_SPEED_2HG,
  28         CNXK_BPHY_CGX_ETH_LINK_SPEED_5G,
  29         CNXK_BPHY_CGX_ETH_LINK_SPEED_10G,
  30         CNXK_BPHY_CGX_ETH_LINK_SPEED_20G,
  31         CNXK_BPHY_CGX_ETH_LINK_SPEED_25G,
  32         CNXK_BPHY_CGX_ETH_LINK_SPEED_40G,
  33         CNXK_BPHY_CGX_ETH_LINK_SPEED_50G,
  34         CNXK_BPHY_CGX_ETH_LINK_SPEED_80G,
  35         CNXK_BPHY_CGX_ETH_LINK_SPEED_100G,
  36         __CNXK_BPHY_CGX_ETH_LINK_SPEED_MAX
  37 };
  38
  39 enum cnxk_bphy_cgx_eth_link_fec {
  40         CNXK_BPHY_CGX_ETH_LINK_FEC_NONE,
  41         CNXK_BPHY_CGX_ETH_LINK_FEC_BASE_R,
  42         CNXK_BPHY_CGX_ETH_LINK_FEC_RS,
  43         __CNXK_BPHY_CGX_ETH_LINK_FEC_MAX
  44 };
  45
  46 enum cnxk_bphy_cgx_eth_link_mode {
  47         CNXK_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT,
  48         CNXK_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT,
  49         CNXK_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT,
  50         CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT,
  51         CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT,
  52         CNXK_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT,
  53         CNXK_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT,
  54         CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT,
  55         CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT,
  56         CNXK_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT,
  57         CNXK_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT,
  58         CNXK_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT,
  59         CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT,
  60         CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT,
  61         CNXK_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT,
  62         CNXK_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT,
  63         CNXK_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT,
  64         CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT,
  65         CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT,
  66         CNXK_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT,
  67         CNXK_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT,
  68         CNXK_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT,
  69         CNXK_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT,
  70         CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT,
  71         CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT,
  72         CNXK_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,
  73         CNXK_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,
  74         __CNXK_BPHY_CGX_ETH_LINK_MODE_MAX
  75 };
  76
  77 struct cnxk_bphy_cgx_msg_link_mode {
  78         bool full_duplex;
  79         bool autoneg;
  80         enum cnxk_bphy_cgx_eth_link_speed speed;
  81         enum cnxk_bphy_cgx_eth_link_mode mode;
  82 };
  83
  84 struct cnxk_bphy_cgx_msg_link_info {
  85         bool link_up;
  86         bool full_duplex;
  87         enum cnxk_bphy_cgx_eth_link_speed speed;
  88         bool autoneg;
  89         enum cnxk_bphy_cgx_eth_link_fec fec;
  90         enum cnxk_bphy_cgx_eth_link_mode mode;
  91 };
  92
  93 struct cnxk_bphy_cgx_msg_set_link_state {
  94         bool state; /* up or down */
  95 };
  96
  97 struct cnxk_bphy_cgx_msg {
  98         enum cnxk_bphy_cgx_msg_type type;
  99         /*
 100          * data depends on message type and whether
 101          * it's a request or a response
 102          */
 103         void *data;
 104 };
 105
 106 #define CNXK_BPHY_DEF_QUEUE 0
 107
 108 enum cnxk_bphy_irq_msg_type {
 109         CNXK_BPHY_IRQ_MSG_TYPE_INIT,
 110         CNXK_BPHY_IRQ_MSG_TYPE_FINI,
 111         CNXK_BPHY_IRQ_MSG_TYPE_REGISTER,
 112         CNXK_BPHY_IRQ_MSG_TYPE_UNREGISTER,
 113         CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET,
 114 };
 115
 116 struct cnxk_bphy_irq_msg {
 117         enum cnxk_bphy_irq_msg_type type;
 118         void *data;
 119 };
 120
 121 struct cnxk_bphy_irq_info {
 122         int irq_num;
 123         cnxk_bphy_intr_handler_t handler;
 124         void *data;
 125         int cpu;
 126 };
 127
 128 static __rte_always_inline int
 129 rte_pmd_bphy_intr_init(uint16_t dev_id)
 130 {
 131         struct cnxk_bphy_irq_msg msg = {
 132                 .type = CNXK_BPHY_IRQ_MSG_TYPE_INIT,
 133         };
 134         struct rte_rawdev_buf *bufs[1];
 135         struct rte_rawdev_buf buf;
 136
 137         buf.buf_addr = &msg;
 138         bufs[0] = &buf;
 139
 140         return rte_rawdev_enqueue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
 141 }
 142
 143 static __rte_always_inline void
 144 rte_pmd_bphy_intr_fini(uint16_t dev_id)
 145 {
 146         struct cnxk_bphy_irq_msg msg = {
 147                 .type = CNXK_BPHY_IRQ_MSG_TYPE_FINI,
 148         };
 149         struct rte_rawdev_buf *bufs[1];
 150         struct rte_rawdev_buf buf;
 151
 152         buf.buf_addr = &msg;
 153         bufs[0] = &buf;
 154
 155         rte_rawdev_enqueue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
 156 }
 157
 158 #endif /* _CNXK_BPHY_H_ */