drivers/raw/ifpga/ifpga_rawdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2018 Intel Corporation
   3  */
   4
   5 #include <string.h>
   6 #include <dirent.h>
   7 #include <sys/stat.h>
   8 #include <unistd.h>
   9 #include <sys/types.h>
  10 #include <fcntl.h>
  11 #include <sys/ioctl.h>
  12 #include <sys/epoll.h>
  13 #include <rte_log.h>
  14 #include <rte_bus.h>
  15 #include <rte_malloc.h>
  16 #include <rte_devargs.h>
  17 #include <rte_memcpy.h>
  18 #include <rte_pci.h>
  19 #include <rte_bus_pci.h>
  20 #include <rte_kvargs.h>
  21 #include <rte_alarm.h>
  22 #include <rte_interrupts.h>
  23 #include <rte_errno.h>
  24 #include <rte_per_lcore.h>
  25 #include <rte_memory.h>
  26 #include <rte_memzone.h>
  27 #include <rte_eal.h>
  28 #include <rte_common.h>
  29 #include <rte_bus_vdev.h>
  30 #include <rte_string_fns.h>
  31
  32 #include "base/opae_hw_api.h"
  33 #include "base/opae_ifpga_hw_api.h"
  34 #include "base/ifpga_api.h"
  35 #include "rte_rawdev.h"
  36 #include "rte_rawdev_pmd.h"
  37 #include "rte_bus_ifpga.h"
  38 #include "ifpga_common.h"
  39 #include "ifpga_logs.h"
  40 #include "ifpga_rawdev.h"
  41 #include "ipn3ke_rawdev_api.h"
  42
  43 #define RTE_PCI_EXT_CAP_ID_ERR           0x01   /* Advanced Error Reporting */
  44 #define RTE_PCI_CFG_SPACE_SIZE           256
  45 #define RTE_PCI_CFG_SPACE_EXP_SIZE       4096
  46 #define RTE_PCI_EXT_CAP_ID(header)       (int)(header & 0x0000ffff)
  47 #define RTE_PCI_EXT_CAP_NEXT(header)     ((header >> 20) & 0xffc)
  48
  49 int ifpga_rawdev_logtype;
  50
  51 #define PCI_VENDOR_ID_INTEL          0x8086
  52 /* PCI Device ID */
  53 #define PCIE_DEVICE_ID_PF_INT_5_X    0xBCBD
  54 #define PCIE_DEVICE_ID_PF_INT_6_X    0xBCC0
  55 #define PCIE_DEVICE_ID_PF_DSC_1_X    0x09C4
  56 #define PCIE_DEVICE_ID_PAC_N3000     0x0B30
  57 /* VF Device */
  58 #define PCIE_DEVICE_ID_VF_INT_5_X    0xBCBF
  59 #define PCIE_DEVICE_ID_VF_INT_6_X    0xBCC1
  60 #define PCIE_DEVICE_ID_VF_DSC_1_X    0x09C5
  61 #define PCIE_DEVICE_ID_VF_PAC_N3000  0x0B31
  62 #define RTE_MAX_RAW_DEVICE           10
  63
  64 static const struct rte_pci_id pci_ifpga_map[] = {
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PAC_N3000),},
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_PAC_N3000),},
  73         { .vendor_id = 0, /* sentinel */ },
  74 };
  75
  76 static struct ifpga_rawdev ifpga_rawdevices[IFPGA_RAWDEV_NUM];
  77
  78 static int ifpga_monitor_start;
  79 static pthread_t ifpga_monitor_start_thread;
  80
  81 static struct ifpga_rawdev *
  82 ifpga_rawdev_allocate(struct rte_rawdev *rawdev);
  83 static int set_surprise_link_check_aer(
  84                 struct ifpga_rawdev *ifpga_rdev, int force_disable);
  85 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
  86                 int start, int cap);
  87 static int ifpga_pci_find_ext_capability(unsigned int fd, int cap);
  88
  89 struct ifpga_rawdev *
  90 ifpga_rawdev_get(const struct rte_rawdev *rawdev)
  91 {
  92         struct ifpga_rawdev *dev;
  93         unsigned int i;
  94
  95         if (rawdev == NULL)
  96                 return NULL;
  97
  98         for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
  99                 dev = &ifpga_rawdevices[i];
 100                 if (dev->rawdev == rawdev)
 101                         return dev;
 102         }
 103
 104         return NULL;
 105 }
 106
 107 static inline uint8_t
 108 ifpga_rawdev_find_free_device_index(void)
 109 {
 110         uint16_t dev_id;
 111
 112         for (dev_id = 0; dev_id < IFPGA_RAWDEV_NUM; dev_id++) {
 113                 if (ifpga_rawdevices[dev_id].rawdev == NULL)
 114                         return dev_id;
 115         }
 116
 117         return IFPGA_RAWDEV_NUM;
 118 }
 119 static struct ifpga_rawdev *
 120 ifpga_rawdev_allocate(struct rte_rawdev *rawdev)
 121 {
 122         struct ifpga_rawdev *dev;
 123         uint16_t dev_id;
 124
 125         dev = ifpga_rawdev_get(rawdev);
 126         if (dev != NULL) {
 127                 IFPGA_RAWDEV_PMD_ERR("Event device already allocated!");
 128                 return NULL;
 129         }
 130
 131         dev_id = ifpga_rawdev_find_free_device_index();
 132         if (dev_id == IFPGA_RAWDEV_NUM) {
 133                 IFPGA_RAWDEV_PMD_ERR("Reached maximum number of raw devices");
 134                 return NULL;
 135         }
 136
 137         dev = &ifpga_rawdevices[dev_id];
 138         dev->rawdev = rawdev;
 139         dev->dev_id = dev_id;
 140
 141         return dev;
 142 }
 143
 144 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
 145 int start, int cap)
 146 {
 147         uint32_t header;
 148         int ttl;
 149         int pos = RTE_PCI_CFG_SPACE_SIZE;
 150         int ret;
 151
 152         /* minimum 8 bytes per capability */
 153         ttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8;
 154
 155         if (start)
 156                 pos = start;
 157         ret = pread(fd, &header, sizeof(header), pos);
 158         if (ret == -1)
 159                 return -1;
 160
 161         /*
 162          * If we have no capabilities, this is indicated by cap ID,
 163          * cap version and next pointer all being 0.
 164          */
 165         if (header == 0)
 166                 return 0;
 167
 168         while (ttl-- > 0) {
 169                 if (RTE_PCI_EXT_CAP_ID(header) == cap && pos != start)
 170                         return pos;
 171
 172                 pos = RTE_PCI_EXT_CAP_NEXT(header);
 173                 if (pos < RTE_PCI_CFG_SPACE_SIZE)
 174                         break;
 175                 ret = pread(fd, &header, sizeof(header), pos);
 176                 if (ret == -1)
 177                         return -1;
 178         }
 179
 180         return 0;
 181 }
 182
 183 static int ifpga_pci_find_ext_capability(unsigned int fd, int cap)
 184 {
 185         return ifpga_pci_find_next_ext_capability(fd, 0, cap);
 186 }
 187
 188 static int ifpga_get_dev_vendor_id(const char *bdf,
 189         uint32_t *dev_id, uint32_t *vendor_id)
 190 {
 191         int fd;
 192         char path[1024];
 193         int ret;
 194         uint32_t header;
 195
 196         strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
 197         strlcat(path, bdf, sizeof(path));
 198         strlcat(path, "/config", sizeof(path));
 199         fd = open(path, O_RDWR);
 200         if (fd < 0)
 201                 return -1;
 202         ret = pread(fd, &header, sizeof(header), 0);
 203         if (ret == -1) {
 204                 close(fd);
 205                 return -1;
 206         }
 207         (*vendor_id) = header & 0xffff;
 208         (*dev_id) = (header >> 16) & 0xffff;
 209         close(fd);
 210
 211         return 0;
 212 }
 213 static int ifpga_rawdev_fill_info(struct ifpga_rawdev *ifpga_dev,
 214         const char *bdf)
 215 {
 216         char path[1024] = "/sys/bus/pci/devices/0000:";
 217         char link[1024], link1[1024];
 218         char dir[1024] = "/sys/devices/";
 219         char *c;
 220         int ret;
 221         char sub_brg_bdf[4][16];
 222         int point;
 223         DIR *dp = NULL;
 224         struct dirent *entry;
 225         int i, j;
 226
 227         unsigned int dom, bus, dev;
 228         int func;
 229         uint32_t dev_id, vendor_id;
 230
 231         strlcat(path, bdf, sizeof(path));
 232         memset(link, 0, sizeof(link));
 233         memset(link1, 0, sizeof(link1));
 234         ret = readlink(path, link, (sizeof(link)-1));
 235         if (ret == -1)
 236                 return -1;
 237         strlcpy(link1, link, sizeof(link1));
 238         memset(ifpga_dev->parent_bdf, 0, 16);
 239         point = strlen(link);
 240         if (point < 39)
 241                 return -1;
 242         point -= 39;
 243         link[point] = 0;
 244         if (point < 12)
 245                 return -1;
 246         point -= 12;
 247         rte_memcpy(ifpga_dev->parent_bdf, &link[point], 12);
 248
 249         point = strlen(link1);
 250         if (point < 26)
 251                 return -1;
 252         point -= 26;
 253         link1[point] = 0;
 254         if (point < 12)
 255                 return -1;
 256         point -= 12;
 257         c = strchr(link1, 'p');
 258         if (!c)
 259                 return -1;
 260         strlcat(dir, c, sizeof(dir));
 261
 262         /* scan folder */
 263         dp = opendir(dir);
 264         if (dp == NULL)
 265                 return -1;
 266         i = 0;
 267         while ((entry = readdir(dp)) != NULL) {
 268                 if (i >= 4)
 269                         break;
 270                 if (entry->d_name[0] == '.')
 271                         continue;
 272                 if (strlen(entry->d_name) > 12)
 273                         continue;
 274                 if (sscanf(entry->d_name, "%x:%x:%x.%d",
 275                         &dom, &bus, &dev, &func) < 4)
 276                         continue;
 277                 else {
 278                         strlcpy(sub_brg_bdf[i],
 279                                 entry->d_name,
 280                                 sizeof(sub_brg_bdf[i]));
 281                         i++;
 282                 }
 283         }
 284         closedir(dp);
 285
 286         /* get fpga and fvl */
 287         j = 0;
 288         for (i = 0; i < 4; i++) {
 289                 strlcpy(link, dir, sizeof(link));
 290                 strlcat(link, "/", sizeof(link));
 291                 strlcat(link, sub_brg_bdf[i], sizeof(link));
 292                 dp = opendir(link);
 293                 if (dp == NULL)
 294                         return -1;
 295                 while ((entry = readdir(dp)) != NULL) {
 296                         if (j >= 8)
 297                                 break;
 298                         if (entry->d_name[0] == '.')
 299                                 continue;
 300
 301                         if (strlen(entry->d_name) > 12)
 302                                 continue;
 303                         if (sscanf(entry->d_name, "%x:%x:%x.%d",
 304                                 &dom, &bus, &dev, &func) < 4)
 305                                 continue;
 306                         else {
 307                                 if (ifpga_get_dev_vendor_id(entry->d_name,
 308                                         &dev_id, &vendor_id))
 309                                         continue;
 310                                 if (vendor_id == 0x8086 &&
 311                                         (dev_id == 0x0CF8 ||
 312                                         dev_id == 0x0D58 ||
 313                                         dev_id == 0x1580)) {
 314                                         strlcpy(ifpga_dev->fvl_bdf[j],
 315                                                 entry->d_name,
 316                                                 sizeof(ifpga_dev->fvl_bdf[j]));
 317                                         j++;
 318                                 }
 319                         }
 320                 }
 321                 closedir(dp);
 322         }
 323
 324         return 0;
 325 }
 326
 327 #define HIGH_FATAL(_sens, value)\
 328         (((_sens)->flags & OPAE_SENSOR_HIGH_FATAL_VALID) &&\
 329          (value > (_sens)->high_fatal))
 330
 331 #define HIGH_WARN(_sens, value)\
 332         (((_sens)->flags & OPAE_SENSOR_HIGH_WARN_VALID) &&\
 333          (value > (_sens)->high_warn))
 334
 335 #define LOW_FATAL(_sens, value)\
 336         (((_sens)->flags & OPAE_SENSOR_LOW_FATAL_VALID) &&\
 337          (value > (_sens)->low_fatal))
 338
 339 #define LOW_WARN(_sens, value)\
 340         (((_sens)->flags & OPAE_SENSOR_LOW_WARN_VALID) &&\
 341          (value > (_sens)->low_warn))
 342
 343 #define AUX_VOLTAGE_WARN 11400
 344
 345 static int
 346 ifpga_monitor_sensor(struct rte_rawdev *raw_dev,
 347                bool *gsd_start)
 348 {
 349         struct opae_adapter *adapter;
 350         struct opae_manager *mgr;
 351         struct opae_sensor_info *sensor;
 352         unsigned int value;
 353         int ret;
 354
 355         adapter = ifpga_rawdev_get_priv(raw_dev);
 356         if (!adapter)
 357                 return -ENODEV;
 358
 359         mgr = opae_adapter_get_mgr(adapter);
 360         if (!mgr)
 361                 return -ENODEV;
 362
 363         opae_mgr_for_each_sensor(sensor) {
 364                 if (!(sensor->flags & OPAE_SENSOR_VALID))
 365                         goto fail;
 366
 367                 ret = opae_mgr_get_sensor_value(mgr, sensor, &value);
 368                 if (ret)
 369                         goto fail;
 370
 371                 if (value == 0xdeadbeef) {
 372                         IFPGA_RAWDEV_PMD_ERR("sensor %s is invalid value %x\n",
 373                                         sensor->name, value);
 374                         continue;
 375                 }
 376
 377                 /* monitor temperature sensors */
 378                 if (!strcmp(sensor->name, "Board Temperature") ||
 379                                 !strcmp(sensor->name, "FPGA Die Temperature")) {
 380                         IFPGA_RAWDEV_PMD_INFO("read sensor %s %d %d %d\n",
 381                                         sensor->name, value, sensor->high_warn,
 382                                         sensor->high_fatal);
 383
 384                         if (HIGH_WARN(sensor, value) ||
 385                                 LOW_WARN(sensor, value)) {
 386                                 IFPGA_RAWDEV_PMD_INFO("%s reach theshold %d\n",
 387                                         sensor->name, value);
 388                                 *gsd_start = true;
 389                                 break;
 390                         }
 391                 }
 392
 393                 /* monitor 12V AUX sensor */
 394                 if (!strcmp(sensor->name, "12V AUX Voltage")) {
 395                         if (value < AUX_VOLTAGE_WARN) {
 396                                 IFPGA_RAWDEV_PMD_INFO("%s reach theshold %d\n",
 397                                                 sensor->name, value);
 398                                 *gsd_start = true;
 399                                 break;
 400                         }
 401                 }
 402         }
 403
 404         return 0;
 405 fail:
 406         return -EFAULT;
 407 }
 408
 409 static int set_surprise_link_check_aer(
 410         struct ifpga_rawdev *ifpga_rdev, int force_disable)
 411 {
 412         struct rte_rawdev *rdev;
 413         int fd = -1;
 414         char path[1024];
 415         int pos;
 416         int ret;
 417         uint32_t data;
 418         bool enable = 0;
 419         uint32_t aer_new0, aer_new1;
 420
 421         if (!ifpga_rdev) {
 422                 printf("\n device does not exist\n");
 423                 return -EFAULT;
 424         }
 425
 426         rdev = ifpga_rdev->rawdev;
 427         if (ifpga_rdev->aer_enable)
 428                 return -EFAULT;
 429         if (ifpga_monitor_sensor(rdev, &enable))
 430                 return -EFAULT;
 431         if (enable || force_disable) {
 432                 IFPGA_RAWDEV_PMD_ERR("Set AER, pls graceful shutdown\n");
 433                 ifpga_rdev->aer_enable = 1;
 434                 /* get bridge fd */
 435                 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
 436                 strlcat(path, ifpga_rdev->parent_bdf, sizeof(path));
 437                 strlcat(path, "/config", sizeof(path));
 438                 fd = open(path, O_RDWR);
 439                 if (fd < 0)
 440                         goto end;
 441                 pos = ifpga_pci_find_ext_capability(fd, RTE_PCI_EXT_CAP_ID_ERR);
 442                 if (!pos)
 443                         goto end;
 444                 /* save previout ECAP_AER+0x08 */
 445                 ret = pread(fd, &data, sizeof(data), pos+0x08);
 446                 if (ret == -1)
 447                         goto end;
 448                 ifpga_rdev->aer_old[0] = data;
 449                 /* save previout ECAP_AER+0x14 */
 450                 ret = pread(fd, &data, sizeof(data), pos+0x14);
 451                 if (ret == -1)
 452                         goto end;
 453                 ifpga_rdev->aer_old[1] = data;
 454
 455                 /* set ECAP_AER+0x08 to 0xFFFFFFFF */
 456                 data = 0xffffffff;
 457                 ret = pwrite(fd, &data, 4, pos+0x08);
 458                 if (ret == -1)
 459                         goto end;
 460                 /* set ECAP_AER+0x14 to 0xFFFFFFFF */
 461                 ret = pwrite(fd, &data, 4, pos+0x14);
 462                 if (ret == -1)
 463                         goto end;
 464
 465                 /* read current ECAP_AER+0x08 */
 466                 ret = pread(fd, &data, sizeof(data), pos+0x08);
 467                 if (ret == -1)
 468                         goto end;
 469                 aer_new0 = data;
 470                 /* read current ECAP_AER+0x14 */
 471                 ret = pread(fd, &data, sizeof(data), pos+0x14);
 472                 if (ret == -1)
 473                         goto end;
 474                 aer_new1 = data;
 475
 476                 if (fd != -1)
 477                         close(fd);
 478
 479                 printf(">>>>>>Set AER %x,%x %x,%x\n",
 480                         ifpga_rdev->aer_old[0], ifpga_rdev->aer_old[1],
 481                         aer_new0, aer_new1);
 482
 483                 return 1;
 484                 }
 485
 486 end:
 487         if (fd != -1)
 488                 close(fd);
 489         return -EFAULT;
 490 }
 491
 492 static void *
 493 ifpga_rawdev_gsd_handle(__rte_unused void *param)
 494 {
 495         struct ifpga_rawdev *ifpga_rdev;
 496         int i;
 497         int gsd_enable, ret;
 498 #define MS 1000
 499
 500         while (1) {
 501                 gsd_enable = 0;
 502                 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
 503                         ifpga_rdev = &ifpga_rawdevices[i];
 504                         if (ifpga_rdev->rawdev) {
 505                                 ret = set_surprise_link_check_aer(ifpga_rdev,
 506                                         gsd_enable);
 507                                 if (ret == 1 && !gsd_enable) {
 508                                         gsd_enable = 1;
 509                                         i = -1;
 510                                 }
 511                         }
 512                 }
 513
 514                 if (gsd_enable)
 515                         printf(">>>>>>Pls Shutdown APP\n");
 516
 517                 rte_delay_us(100 * MS);
 518         }
 519
 520         return NULL;
 521 }
 522
 523 static int
 524 ifpga_monitor_start_func(void)
 525 {
 526         int ret;
 527
 528         if (ifpga_monitor_start == 0) {
 529                 ret = pthread_create(&ifpga_monitor_start_thread,
 530                         NULL,
 531                         ifpga_rawdev_gsd_handle, NULL);
 532                 if (ret) {
 533                         IFPGA_RAWDEV_PMD_ERR(
 534                                 "Fail to create ifpga nonitor thread");
 535                         return -1;
 536                 }
 537                 ifpga_monitor_start = 1;
 538         }
 539
 540         return 0;
 541 }
 542 static int
 543 ifpga_monitor_stop_func(void)
 544 {
 545         int ret;
 546
 547         if (ifpga_monitor_start == 1) {
 548                 ret = pthread_cancel(ifpga_monitor_start_thread);
 549                 if (ret)
 550                         IFPGA_RAWDEV_PMD_ERR("Can't cancel the thread");
 551
 552                 ret = pthread_join(ifpga_monitor_start_thread, NULL);
 553                 if (ret)
 554                         IFPGA_RAWDEV_PMD_ERR("Can't join the thread");
 555
 556                 ifpga_monitor_start = 0;
 557
 558                 return ret;
 559         }
 560
 561         return 0;
 562 }
 563
 564 static int
 565 ifpga_fill_afu_dev(struct opae_accelerator *acc,
 566                 struct rte_afu_device *afu_dev)
 567 {
 568         struct rte_mem_resource *res = afu_dev->mem_resource;
 569         struct opae_acc_region_info region_info;
 570         struct opae_acc_info info;
 571         unsigned long i;
 572         int ret;
 573
 574         ret = opae_acc_get_info(acc, &info);
 575         if (ret)
 576                 return ret;
 577
 578         if (info.num_regions > PCI_MAX_RESOURCE)
 579                 return -EFAULT;
 580
 581         afu_dev->num_region = info.num_regions;
 582
 583         for (i = 0; i < info.num_regions; i++) {
 584                 region_info.index = i;
 585                 ret = opae_acc_get_region_info(acc, &region_info);
 586                 if (ret)
 587                         return ret;
 588
 589                 if ((region_info.flags & ACC_REGION_MMIO) &&
 590                     (region_info.flags & ACC_REGION_READ) &&
 591                     (region_info.flags & ACC_REGION_WRITE)) {
 592                         res[i].phys_addr = region_info.phys_addr;
 593                         res[i].len = region_info.len;
 594                         res[i].addr = region_info.addr;
 595                 } else
 596                         return -EFAULT;
 597         }
 598
 599         return 0;
 600 }
 601
 602 static void
 603 ifpga_rawdev_info_get(struct rte_rawdev *dev,
 604                                      rte_rawdev_obj_t dev_info)
 605 {
 606         struct opae_adapter *adapter;
 607         struct opae_accelerator *acc;
 608         struct rte_afu_device *afu_dev;
 609         struct opae_manager *mgr = NULL;
 610         struct opae_eth_group_region_info opae_lside_eth_info;
 611         struct opae_eth_group_region_info opae_nside_eth_info;
 612         int lside_bar_idx, nside_bar_idx;
 613
 614         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 615
 616         if (!dev_info) {
 617                 IFPGA_RAWDEV_PMD_ERR("Invalid request");
 618                 return;
 619         }
 620
 621         adapter = ifpga_rawdev_get_priv(dev);
 622         if (!adapter)
 623                 return;
 624
 625         afu_dev = dev_info;
 626         afu_dev->rawdev = dev;
 627
 628         /* find opae_accelerator and fill info into afu_device */
 629         opae_adapter_for_each_acc(adapter, acc) {
 630                 if (acc->index != afu_dev->id.port)
 631                         continue;
 632
 633                 if (ifpga_fill_afu_dev(acc, afu_dev)) {
 634                         IFPGA_RAWDEV_PMD_ERR("cannot get info\n");
 635                         return;
 636                 }
 637         }
 638
 639         /* get opae_manager to rawdev */
 640         mgr = opae_adapter_get_mgr(adapter);
 641         if (mgr) {
 642                 /* get LineSide BAR Index */
 643                 if (opae_manager_get_eth_group_region_info(mgr, 0,
 644                         &opae_lside_eth_info)) {
 645                         return;
 646                 }
 647                 lside_bar_idx = opae_lside_eth_info.mem_idx;
 648
 649                 /* get NICSide BAR Index */
 650                 if (opae_manager_get_eth_group_region_info(mgr, 1,
 651                         &opae_nside_eth_info)) {
 652                         return;
 653                 }
 654                 nside_bar_idx = opae_nside_eth_info.mem_idx;
 655
 656                 if (lside_bar_idx >= PCI_MAX_RESOURCE ||
 657                         nside_bar_idx >= PCI_MAX_RESOURCE ||
 658                         lside_bar_idx == nside_bar_idx)
 659                         return;
 660
 661                 /* fill LineSide BAR Index */
 662                 afu_dev->mem_resource[lside_bar_idx].phys_addr =
 663                         opae_lside_eth_info.phys_addr;
 664                 afu_dev->mem_resource[lside_bar_idx].len =
 665                         opae_lside_eth_info.len;
 666                 afu_dev->mem_resource[lside_bar_idx].addr =
 667                         opae_lside_eth_info.addr;
 668
 669                 /* fill NICSide BAR Index */
 670                 afu_dev->mem_resource[nside_bar_idx].phys_addr =
 671                         opae_nside_eth_info.phys_addr;
 672                 afu_dev->mem_resource[nside_bar_idx].len =
 673                         opae_nside_eth_info.len;
 674                 afu_dev->mem_resource[nside_bar_idx].addr =
 675                         opae_nside_eth_info.addr;
 676         }
 677 }
 678
 679 static int
 680 ifpga_rawdev_configure(const struct rte_rawdev *dev,
 681                 rte_rawdev_obj_t config)
 682 {
 683         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 684
 685         RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
 686
 687         return config ? 0 : 1;
 688 }
 689
 690 static int
 691 ifpga_rawdev_start(struct rte_rawdev *dev)
 692 {
 693         int ret = 0;
 694         struct opae_adapter *adapter;
 695
 696         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 697
 698         RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
 699
 700         adapter = ifpga_rawdev_get_priv(dev);
 701         if (!adapter)
 702                 return -ENODEV;
 703
 704         return ret;
 705 }
 706
 707 static void
 708 ifpga_rawdev_stop(struct rte_rawdev *dev)
 709 {
 710         dev->started = 0;
 711 }
 712
 713 static int
 714 ifpga_rawdev_close(struct rte_rawdev *dev)
 715 {
 716         return dev ? 0:1;
 717 }
 718
 719 static int
 720 ifpga_rawdev_reset(struct rte_rawdev *dev)
 721 {
 722         return dev ? 0:1;
 723 }
 724
 725 static int
 726 fpga_pr(struct rte_rawdev *raw_dev, u32 port_id, const char *buffer, u32 size,
 727                         u64 *status)
 728 {
 729
 730         struct opae_adapter *adapter;
 731         struct opae_manager *mgr;
 732         struct opae_accelerator *acc;
 733         struct opae_bridge *br;
 734         int ret;
 735
 736         adapter = ifpga_rawdev_get_priv(raw_dev);
 737         if (!adapter)
 738                 return -ENODEV;
 739
 740         mgr = opae_adapter_get_mgr(adapter);
 741         if (!mgr)
 742                 return -ENODEV;
 743
 744         acc = opae_adapter_get_acc(adapter, port_id);
 745         if (!acc)
 746                 return -ENODEV;
 747
 748         br = opae_acc_get_br(acc);
 749         if (!br)
 750                 return -ENODEV;
 751
 752         ret = opae_manager_flash(mgr, port_id, buffer, size, status);
 753         if (ret) {
 754                 IFPGA_RAWDEV_PMD_ERR("%s pr error %d\n", __func__, ret);
 755                 return ret;
 756         }
 757
 758         ret = opae_bridge_reset(br);
 759         if (ret) {
 760                 IFPGA_RAWDEV_PMD_ERR("%s reset port:%d error %d\n",
 761                                 __func__, port_id, ret);
 762                 return ret;
 763         }
 764
 765         return ret;
 766 }
 767
 768 static int
 769 rte_fpga_do_pr(struct rte_rawdev *rawdev, int port_id,
 770                 const char *file_name)
 771 {
 772         struct stat file_stat;
 773         int file_fd;
 774         int ret = 0;
 775         ssize_t buffer_size;
 776         void *buffer;
 777         u64 pr_error;
 778
 779         if (!file_name)
 780                 return -EINVAL;
 781
 782         file_fd = open(file_name, O_RDONLY);
 783         if (file_fd < 0) {
 784                 IFPGA_RAWDEV_PMD_ERR("%s: open file error: %s\n",
 785                                 __func__, file_name);
 786                 IFPGA_RAWDEV_PMD_ERR("Message : %s\n", strerror(errno));
 787                 return -EINVAL;
 788         }
 789         ret = stat(file_name, &file_stat);
 790         if (ret) {
 791                 IFPGA_RAWDEV_PMD_ERR("stat on bitstream file failed: %s\n",
 792                                 file_name);
 793                 ret = -EINVAL;
 794                 goto close_fd;
 795         }
 796         buffer_size = file_stat.st_size;
 797         if (buffer_size <= 0) {
 798                 ret = -EINVAL;
 799                 goto close_fd;
 800         }
 801
 802         IFPGA_RAWDEV_PMD_INFO("bitstream file size: %zu\n", buffer_size);
 803         buffer = rte_malloc(NULL, buffer_size, 0);
 804         if (!buffer) {
 805                 ret = -ENOMEM;
 806                 goto close_fd;
 807         }
 808
 809         /*read the raw data*/
 810         if (buffer_size != read(file_fd, (void *)buffer, buffer_size)) {
 811                 ret = -EINVAL;
 812                 goto free_buffer;
 813         }
 814
 815         /*do PR now*/
 816         ret = fpga_pr(rawdev, port_id, buffer, buffer_size, &pr_error);
 817         IFPGA_RAWDEV_PMD_INFO("downloading to device port %d....%s.\n", port_id,
 818                 ret ? "failed" : "success");
 819         if (ret) {
 820                 ret = -EINVAL;
 821                 goto free_buffer;
 822         }
 823
 824 free_buffer:
 825         if (buffer)
 826                 rte_free(buffer);
 827 close_fd:
 828         close(file_fd);
 829         file_fd = 0;
 830         return ret;
 831 }
 832
 833 static int
 834 ifpga_rawdev_pr(struct rte_rawdev *dev,
 835         rte_rawdev_obj_t pr_conf)
 836 {
 837         struct opae_adapter *adapter;
 838         struct rte_afu_pr_conf *afu_pr_conf;
 839         int ret;
 840         struct uuid uuid;
 841         struct opae_accelerator *acc;
 842
 843         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 844
 845         adapter = ifpga_rawdev_get_priv(dev);
 846         if (!adapter)
 847                 return -ENODEV;
 848
 849         if (!pr_conf)
 850                 return -EINVAL;
 851
 852         afu_pr_conf = pr_conf;
 853
 854         if (afu_pr_conf->pr_enable) {
 855                 ret = rte_fpga_do_pr(dev,
 856                                 afu_pr_conf->afu_id.port,
 857                                 afu_pr_conf->bs_path);
 858                 if (ret) {
 859                         IFPGA_RAWDEV_PMD_ERR("do pr error %d\n", ret);
 860                         return ret;
 861                 }
 862         }
 863
 864         acc = opae_adapter_get_acc(adapter, afu_pr_conf->afu_id.port);
 865         if (!acc)
 866                 return -ENODEV;
 867
 868         ret = opae_acc_get_uuid(acc, &uuid);
 869         if (ret)
 870                 return ret;
 871
 872         rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_low, uuid.b, sizeof(u64));
 873         rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_high,
 874                 uuid.b + 8, sizeof(u64));
 875
 876         IFPGA_RAWDEV_PMD_INFO("%s: uuid_l=0x%lx, uuid_h=0x%lx\n", __func__,
 877                 (unsigned long)afu_pr_conf->afu_id.uuid.uuid_low,
 878                 (unsigned long)afu_pr_conf->afu_id.uuid.uuid_high);
 879
 880         return 0;
 881 }
 882
 883 static int
 884 ifpga_rawdev_get_attr(struct rte_rawdev *dev,
 885         const char *attr_name, uint64_t *attr_value)
 886 {
 887         struct opae_adapter *adapter;
 888         struct opae_manager *mgr;
 889         struct opae_retimer_info opae_rtm_info;
 890         struct opae_retimer_status opae_rtm_status;
 891         struct opae_eth_group_info opae_eth_grp_info;
 892         struct opae_eth_group_region_info opae_eth_grp_reg_info;
 893         int eth_group_num = 0;
 894         uint64_t port_link_bitmap = 0, port_link_bit;
 895         uint32_t i, j, p, q;
 896
 897 #define MAX_PORT_PER_RETIMER    4
 898
 899         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 900
 901         if (!dev || !attr_name || !attr_value) {
 902                 IFPGA_RAWDEV_PMD_ERR("Invalid arguments for getting attributes");
 903                 return -1;
 904         }
 905
 906         adapter = ifpga_rawdev_get_priv(dev);
 907         if (!adapter) {
 908                 IFPGA_RAWDEV_PMD_ERR("Adapter of dev %s is NULL", dev->name);
 909                 return -1;
 910         }
 911
 912         mgr = opae_adapter_get_mgr(adapter);
 913         if (!mgr) {
 914                 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
 915                 return -1;
 916         }
 917
 918         /* currently, eth_group_num is always 2 */
 919         eth_group_num = opae_manager_get_eth_group_nums(mgr);
 920         if (eth_group_num < 0)
 921                 return -1;
 922
 923         if (!strcmp(attr_name, "LineSideBaseMAC")) {
 924                 /* Currently FPGA not implement, so just set all zeros*/
 925                 *attr_value = (uint64_t)0;
 926                 return 0;
 927         }
 928         if (!strcmp(attr_name, "LineSideMACType")) {
 929                 /* eth_group 0 on FPGA connect to LineSide */
 930                 if (opae_manager_get_eth_group_info(mgr, 0,
 931                         &opae_eth_grp_info))
 932                         return -1;
 933                 switch (opae_eth_grp_info.speed) {
 934                 case ETH_SPEED_10G:
 935                         *attr_value =
 936                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI);
 937                         break;
 938                 case ETH_SPEED_25G:
 939                         *attr_value =
 940                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI);
 941                         break;
 942                 default:
 943                         *attr_value =
 944                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_UNKNOWN);
 945                         break;
 946                 }
 947                 return 0;
 948         }
 949         if (!strcmp(attr_name, "LineSideLinkSpeed")) {
 950                 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
 951                         return -1;
 952                 switch (opae_rtm_status.speed) {
 953                 case MXD_1GB:
 954                         *attr_value =
 955                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 956                         break;
 957                 case MXD_2_5GB:
 958                         *attr_value =
 959                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 960                         break;
 961                 case MXD_5GB:
 962                         *attr_value =
 963                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 964                         break;
 965                 case MXD_10GB:
 966                         *attr_value =
 967                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_10GB);
 968                         break;
 969                 case MXD_25GB:
 970                         *attr_value =
 971                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_25GB);
 972                         break;
 973                 case MXD_40GB:
 974                         *attr_value =
 975                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_40GB);
 976                         break;
 977                 case MXD_100GB:
 978                         *attr_value =
 979                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 980                         break;
 981                 case MXD_SPEED_UNKNOWN:
 982                         *attr_value =
 983                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 984                         break;
 985                 default:
 986                         *attr_value =
 987                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 988                         break;
 989                 }
 990                 return 0;
 991         }
 992         if (!strcmp(attr_name, "LineSideLinkRetimerNum")) {
 993                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
 994                         return -1;
 995                 *attr_value = (uint64_t)(opae_rtm_info.nums_retimer);
 996                 return 0;
 997         }
 998         if (!strcmp(attr_name, "LineSideLinkPortNum")) {
 999                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1000                         return -1;
1001                 uint64_t tmp = (uint64_t)opae_rtm_info.ports_per_retimer *
1002                                         (uint64_t)opae_rtm_info.nums_retimer;
1003                 *attr_value = tmp;
1004                 return 0;
1005         }
1006         if (!strcmp(attr_name, "LineSideLinkStatus")) {
1007                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1008                         return -1;
1009                 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
1010                         return -1;
1011                 (*attr_value) = 0;
1012                 q = 0;
1013                 port_link_bitmap = (uint64_t)(opae_rtm_status.line_link_bitmap);
1014                 for (i = 0; i < opae_rtm_info.nums_retimer; i++) {
1015                         p = i * MAX_PORT_PER_RETIMER;
1016                         for (j = 0; j < opae_rtm_info.ports_per_retimer; j++) {
1017                                 port_link_bit = 0;
1018                                 IFPGA_BIT_SET(port_link_bit, (p+j));
1019                                 port_link_bit &= port_link_bitmap;
1020                                 if (port_link_bit)
1021                                         IFPGA_BIT_SET((*attr_value), q);
1022                                 q++;
1023                         }
1024                 }
1025                 return 0;
1026         }
1027         if (!strcmp(attr_name, "LineSideBARIndex")) {
1028                 /* eth_group 0 on FPGA connect to LineSide */
1029                 if (opae_manager_get_eth_group_region_info(mgr, 0,
1030                         &opae_eth_grp_reg_info))
1031                         return -1;
1032                 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1033                 return 0;
1034         }
1035         if (!strcmp(attr_name, "NICSideMACType")) {
1036                 /* eth_group 1 on FPGA connect to NicSide */
1037                 if (opae_manager_get_eth_group_info(mgr, 1,
1038                         &opae_eth_grp_info))
1039                         return -1;
1040                 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1041                 return 0;
1042         }
1043         if (!strcmp(attr_name, "NICSideLinkSpeed")) {
1044                 /* eth_group 1 on FPGA connect to NicSide */
1045                 if (opae_manager_get_eth_group_info(mgr, 1,
1046                         &opae_eth_grp_info))
1047                         return -1;
1048                 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1049                 return 0;
1050         }
1051         if (!strcmp(attr_name, "NICSideLinkPortNum")) {
1052                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1053                         return -1;
1054                 uint64_t tmp = (uint64_t)opae_rtm_info.nums_fvl *
1055                                         (uint64_t)opae_rtm_info.ports_per_fvl;
1056                 *attr_value = tmp;
1057                 return 0;
1058         }
1059         if (!strcmp(attr_name, "NICSideLinkStatus"))
1060                 return 0;
1061         if (!strcmp(attr_name, "NICSideBARIndex")) {
1062                 /* eth_group 1 on FPGA connect to NicSide */
1063                 if (opae_manager_get_eth_group_region_info(mgr, 1,
1064                         &opae_eth_grp_reg_info))
1065                         return -1;
1066                 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1067                 return 0;
1068         }
1069
1070         IFPGA_RAWDEV_PMD_ERR("%s not support", attr_name);
1071         return -1;
1072 }
1073
1074 static const struct rte_rawdev_ops ifpga_rawdev_ops = {
1075         .dev_info_get = ifpga_rawdev_info_get,
1076         .dev_configure = ifpga_rawdev_configure,
1077         .dev_start = ifpga_rawdev_start,
1078         .dev_stop = ifpga_rawdev_stop,
1079         .dev_close = ifpga_rawdev_close,
1080         .dev_reset = ifpga_rawdev_reset,
1081
1082         .queue_def_conf = NULL,
1083         .queue_setup = NULL,
1084         .queue_release = NULL,
1085
1086         .attr_get = ifpga_rawdev_get_attr,
1087         .attr_set = NULL,
1088
1089         .enqueue_bufs = NULL,
1090         .dequeue_bufs = NULL,
1091
1092         .dump = NULL,
1093
1094         .xstats_get = NULL,
1095         .xstats_get_names = NULL,
1096         .xstats_get_by_name = NULL,
1097         .xstats_reset = NULL,
1098
1099         .firmware_status_get = NULL,
1100         .firmware_version_get = NULL,
1101         .firmware_load = ifpga_rawdev_pr,
1102         .firmware_unload = NULL,
1103
1104         .dev_selftest = NULL,
1105 };
1106
1107 static int
1108 ifpga_get_fme_error_prop(struct opae_manager *mgr,
1109                 u64 prop_id, u64 *val)
1110 {
1111         struct feature_prop prop;
1112
1113         prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1114         prop.prop_id = prop_id;
1115
1116         if (opae_manager_ifpga_get_prop(mgr, &prop))
1117                 return -EINVAL;
1118
1119         *val = prop.data;
1120
1121         return 0;
1122 }
1123
1124 static int
1125 ifpga_set_fme_error_prop(struct opae_manager *mgr,
1126                 u64 prop_id, u64 val)
1127 {
1128         struct feature_prop prop;
1129
1130         prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1131         prop.prop_id = prop_id;
1132
1133         prop.data = val;
1134
1135         if (opae_manager_ifpga_set_prop(mgr, &prop))
1136                 return -EINVAL;
1137
1138         return 0;
1139 }
1140
1141 static int
1142 fme_err_read_seu_emr(struct opae_manager *mgr)
1143 {
1144         u64 val;
1145         int ret;
1146
1147         ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_LOW, &val);
1148         if (ret)
1149                 return -EINVAL;
1150
1151         IFPGA_RAWDEV_PMD_INFO("seu emr low: 0x%" PRIx64 "\n", val);
1152
1153         ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_HIGH, &val);
1154         if (ret)
1155                 return -EINVAL;
1156
1157         IFPGA_RAWDEV_PMD_INFO("seu emr high: 0x%" PRIx64 "\n", val);
1158
1159         return 0;
1160 }
1161
1162 static int fme_clear_warning_intr(struct opae_manager *mgr)
1163 {
1164         u64 val;
1165
1166         if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_INJECT_ERRORS, 0))
1167                 return -EINVAL;
1168
1169         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1170                 return -EINVAL;
1171         if ((val & 0x40) != 0)
1172                 IFPGA_RAWDEV_PMD_INFO("clean not done\n");
1173
1174         return 0;
1175 }
1176
1177 static int
1178 fme_err_handle_error0(struct opae_manager *mgr)
1179 {
1180         struct feature_fme_error0 fme_error0;
1181         u64 val;
1182
1183         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1184                 return -EINVAL;
1185
1186         fme_error0.csr = val;
1187
1188         if (fme_error0.fabric_err)
1189                 IFPGA_RAWDEV_PMD_ERR("Fabric error\n");
1190         else if (fme_error0.fabfifo_overflow)
1191                 IFPGA_RAWDEV_PMD_ERR("Fabric fifo under/overflow error\n");
1192         else if (fme_error0.afu_acc_mode_err)
1193                 IFPGA_RAWDEV_PMD_ERR("AFU PF/VF access mismatch detected\n");
1194         else if (fme_error0.pcie0cdc_parity_err)
1195                 IFPGA_RAWDEV_PMD_ERR("PCIe0 CDC Parity Error\n");
1196         else if (fme_error0.cvlcdc_parity_err)
1197                 IFPGA_RAWDEV_PMD_ERR("CVL CDC Parity Error\n");
1198         else if (fme_error0.fpgaseuerr)
1199                 fme_err_read_seu_emr(mgr);
1200
1201         /* clean the errors */
1202         if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, val))
1203                 return -EINVAL;
1204
1205         return 0;
1206 }
1207
1208 static int
1209 fme_err_handle_catfatal_error(struct opae_manager *mgr)
1210 {
1211         struct feature_fme_ras_catfaterror fme_catfatal;
1212         u64 val;
1213
1214         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_CATFATAL_ERRORS, &val))
1215                 return -EINVAL;
1216
1217         fme_catfatal.csr = val;
1218
1219         if (fme_catfatal.cci_fatal_err)
1220                 IFPGA_RAWDEV_PMD_ERR("CCI error detected\n");
1221         else if (fme_catfatal.fabric_fatal_err)
1222                 IFPGA_RAWDEV_PMD_ERR("Fabric fatal error detected\n");
1223         else if (fme_catfatal.pcie_poison_err)
1224                 IFPGA_RAWDEV_PMD_ERR("Poison error from PCIe ports\n");
1225         else if (fme_catfatal.inject_fata_err)
1226                 IFPGA_RAWDEV_PMD_ERR("Injected Fatal Error\n");
1227         else if (fme_catfatal.crc_catast_err)
1228                 IFPGA_RAWDEV_PMD_ERR("a catastrophic EDCRC error\n");
1229         else if (fme_catfatal.injected_catast_err)
1230                 IFPGA_RAWDEV_PMD_ERR("Injected Catastrophic Error\n");
1231         else if (fme_catfatal.bmc_seu_catast_err)
1232                 fme_err_read_seu_emr(mgr);
1233
1234         return 0;
1235 }
1236
1237 static int
1238 fme_err_handle_nonfaterror(struct opae_manager *mgr)
1239 {
1240         struct feature_fme_ras_nonfaterror nonfaterr;
1241         u64 val;
1242
1243         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1244                 return -EINVAL;
1245
1246         nonfaterr.csr = val;
1247
1248         if (nonfaterr.temp_thresh_ap1)
1249                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP1\n");
1250         else if (nonfaterr.temp_thresh_ap2)
1251                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP2\n");
1252         else if (nonfaterr.pcie_error)
1253                 IFPGA_RAWDEV_PMD_INFO("an error has occurred in pcie\n");
1254         else if (nonfaterr.portfatal_error)
1255                 IFPGA_RAWDEV_PMD_INFO("fatal error occurred in AFU port.\n");
1256         else if (nonfaterr.proc_hot)
1257                 IFPGA_RAWDEV_PMD_INFO("a ProcHot event\n");
1258         else if (nonfaterr.afu_acc_mode_err)
1259                 IFPGA_RAWDEV_PMD_INFO("an AFU PF/VF access mismatch\n");
1260         else if (nonfaterr.injected_nonfata_err) {
1261                 IFPGA_RAWDEV_PMD_INFO("Injected Warning Error\n");
1262                 fme_clear_warning_intr(mgr);
1263         } else if (nonfaterr.temp_thresh_AP6)
1264                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP6\n");
1265         else if (nonfaterr.power_thresh_AP1)
1266                 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP1\n");
1267         else if (nonfaterr.power_thresh_AP2)
1268                 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP2\n");
1269         else if (nonfaterr.mbp_err)
1270                 IFPGA_RAWDEV_PMD_INFO("an MBP event\n");
1271
1272         return 0;
1273 }
1274
1275 static void
1276 fme_interrupt_handler(void *param)
1277 {
1278         struct opae_manager *mgr = (struct opae_manager *)param;
1279
1280         IFPGA_RAWDEV_PMD_INFO("%s interrupt occurred\n", __func__);
1281
1282         fme_err_handle_error0(mgr);
1283         fme_err_handle_nonfaterror(mgr);
1284         fme_err_handle_catfatal_error(mgr);
1285 }
1286
1287 static struct rte_intr_handle fme_intr_handle;
1288
1289 static int ifpga_register_fme_interrupt(struct opae_manager *mgr)
1290 {
1291         int ret;
1292         struct fpga_fme_err_irq_set err_irq_set;
1293
1294         fme_intr_handle.type = RTE_INTR_HANDLE_VFIO_MSIX;
1295
1296         ret = rte_intr_efd_enable(&fme_intr_handle, 1);
1297         if (ret)
1298                 return -EINVAL;
1299
1300         fme_intr_handle.fd = fme_intr_handle.efds[0];
1301
1302         IFPGA_RAWDEV_PMD_DEBUG("vfio_dev_fd=%d, efd=%d, fd=%d\n",
1303                         fme_intr_handle.vfio_dev_fd,
1304                         fme_intr_handle.efds[0], fme_intr_handle.fd);
1305
1306         err_irq_set.evtfd = fme_intr_handle.efds[0];
1307         ret = opae_manager_ifpga_set_err_irq(mgr, &err_irq_set);
1308         if (ret)
1309                 return -EINVAL;
1310
1311         /* register FME interrupt using DPDK API */
1312         ret = rte_intr_callback_register(&fme_intr_handle,
1313                         fme_interrupt_handler,
1314                         (void *)mgr);
1315         if (ret)
1316                 return -EINVAL;
1317
1318         IFPGA_RAWDEV_PMD_INFO("success register fme interrupt\n");
1319
1320         return 0;
1321 }
1322
1323 static int
1324 ifpga_unregister_fme_interrupt(struct opae_manager *mgr)
1325 {
1326         rte_intr_efd_disable(&fme_intr_handle);
1327
1328         return rte_intr_callback_unregister(&fme_intr_handle,
1329                         fme_interrupt_handler,
1330                         (void *)mgr);
1331 }
1332
1333 static int
1334 ifpga_rawdev_create(struct rte_pci_device *pci_dev,
1335                         int socket_id)
1336 {
1337         int ret = 0;
1338         struct rte_rawdev *rawdev = NULL;
1339         struct ifpga_rawdev *dev = NULL;
1340         struct opae_adapter *adapter = NULL;
1341         struct opae_manager *mgr = NULL;
1342         struct opae_adapter_data_pci *data = NULL;
1343         char name[RTE_RAWDEV_NAME_MAX_LEN];
1344         int i;
1345
1346         if (!pci_dev) {
1347                 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1348                 ret = -EINVAL;
1349                 goto cleanup;
1350         }
1351
1352         memset(name, 0, sizeof(name));
1353         snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%02x:%02x.%x",
1354                 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1355
1356         IFPGA_RAWDEV_PMD_INFO("Init %s on NUMA node %d", name, rte_socket_id());
1357
1358         /* Allocate device structure */
1359         rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct opae_adapter),
1360                                          socket_id);
1361         if (rawdev == NULL) {
1362                 IFPGA_RAWDEV_PMD_ERR("Unable to allocate rawdevice");
1363                 ret = -EINVAL;
1364                 goto cleanup;
1365         }
1366
1367         dev = ifpga_rawdev_allocate(rawdev);
1368         if (dev == NULL) {
1369                 IFPGA_RAWDEV_PMD_ERR("Unable to allocate ifpga_rawdevice");
1370                 ret = -EINVAL;
1371                 goto cleanup;
1372         }
1373         dev->aer_enable = 0;
1374
1375         /* alloc OPAE_FPGA_PCI data to register to OPAE hardware level API */
1376         data = opae_adapter_data_alloc(OPAE_FPGA_PCI);
1377         if (!data) {
1378                 ret = -ENOMEM;
1379                 goto cleanup;
1380         }
1381
1382         /* init opae_adapter_data_pci for device specific information */
1383         for (i = 0; i < PCI_MAX_RESOURCE; i++) {
1384                 data->region[i].phys_addr = pci_dev->mem_resource[i].phys_addr;
1385                 data->region[i].len = pci_dev->mem_resource[i].len;
1386                 data->region[i].addr = pci_dev->mem_resource[i].addr;
1387         }
1388         data->device_id = pci_dev->id.device_id;
1389         data->vendor_id = pci_dev->id.vendor_id;
1390         data->vfio_dev_fd = pci_dev->intr_handle.vfio_dev_fd;
1391
1392         adapter = rawdev->dev_private;
1393         /* create a opae_adapter based on above device data */
1394         ret = opae_adapter_init(adapter, pci_dev->device.name, data);
1395         if (ret) {
1396                 ret = -ENOMEM;
1397                 goto free_adapter_data;
1398         }
1399
1400         rawdev->dev_ops = &ifpga_rawdev_ops;
1401         rawdev->device = &pci_dev->device;
1402         rawdev->driver_name = pci_dev->driver->driver.name;
1403
1404         /* must enumerate the adapter before use it */
1405         ret = opae_adapter_enumerate(adapter);
1406         if (ret)
1407                 goto free_adapter_data;
1408
1409         /* get opae_manager to rawdev */
1410         mgr = opae_adapter_get_mgr(adapter);
1411         if (mgr) {
1412                 /* PF function */
1413                 IFPGA_RAWDEV_PMD_INFO("this is a PF function");
1414         }
1415
1416         ret = ifpga_register_fme_interrupt(mgr);
1417         if (ret)
1418                 goto free_adapter_data;
1419
1420         return ret;
1421
1422 free_adapter_data:
1423         if (data)
1424                 opae_adapter_data_free(data);
1425 cleanup:
1426         if (rawdev)
1427                 rte_rawdev_pmd_release(rawdev);
1428
1429         return ret;
1430 }
1431
1432 static int
1433 ifpga_rawdev_destroy(struct rte_pci_device *pci_dev)
1434 {
1435         int ret;
1436         struct rte_rawdev *rawdev;
1437         char name[RTE_RAWDEV_NAME_MAX_LEN];
1438         struct opae_adapter *adapter;
1439         struct opae_manager *mgr;
1440
1441         if (!pci_dev) {
1442                 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1443                 ret = -EINVAL;
1444                 return ret;
1445         }
1446
1447         memset(name, 0, sizeof(name));
1448         snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%x:%02x.%x",
1449                 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1450
1451         IFPGA_RAWDEV_PMD_INFO("Closing %s on NUMA node %d",
1452                 name, rte_socket_id());
1453
1454         rawdev = rte_rawdev_pmd_get_named_dev(name);
1455         if (!rawdev) {
1456                 IFPGA_RAWDEV_PMD_ERR("Invalid device name (%s)", name);
1457                 return -EINVAL;
1458         }
1459
1460         adapter = ifpga_rawdev_get_priv(rawdev);
1461         if (!adapter)
1462                 return -ENODEV;
1463
1464         mgr = opae_adapter_get_mgr(adapter);
1465         if (!mgr)
1466                 return -ENODEV;
1467
1468         if (ifpga_unregister_fme_interrupt(mgr))
1469                 return -EINVAL;
1470
1471         opae_adapter_data_free(adapter->data);
1472         opae_adapter_free(adapter);
1473
1474         /* rte_rawdev_close is called by pmd_release */
1475         ret = rte_rawdev_pmd_release(rawdev);
1476         if (ret)
1477                 IFPGA_RAWDEV_PMD_DEBUG("Device cleanup failed");
1478
1479         return ret;
1480 }
1481
1482 static int
1483 ifpga_rawdev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1484         struct rte_pci_device *pci_dev)
1485 {
1486         IFPGA_RAWDEV_PMD_FUNC_TRACE();
1487         return ifpga_rawdev_create(pci_dev, rte_socket_id());
1488 }
1489
1490 static int
1491 ifpga_rawdev_pci_remove(struct rte_pci_device *pci_dev)
1492 {
1493         ifpga_monitor_stop_func();
1494         return ifpga_rawdev_destroy(pci_dev);
1495 }
1496
1497 static struct rte_pci_driver rte_ifpga_rawdev_pmd = {
1498         .id_table  = pci_ifpga_map,
1499         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1500         .probe     = ifpga_rawdev_pci_probe,
1501         .remove    = ifpga_rawdev_pci_remove,
1502 };
1503
1504 RTE_PMD_REGISTER_PCI(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1505 RTE_PMD_REGISTER_PCI_TABLE(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1506 RTE_PMD_REGISTER_KMOD_DEP(ifpga_rawdev_pci_driver, "* igb_uio | uio_pci_generic | vfio-pci");
1507
1508 RTE_INIT(ifpga_rawdev_init_log)
1509 {
1510         ifpga_rawdev_logtype = rte_log_register("driver.raw.init");
1511         if (ifpga_rawdev_logtype >= 0)
1512                 rte_log_set_level(ifpga_rawdev_logtype, RTE_LOG_NOTICE);
1513 }
1514
1515 static const char * const valid_args[] = {
1516 #define IFPGA_ARG_NAME         "ifpga"
1517         IFPGA_ARG_NAME,
1518 #define IFPGA_ARG_PORT         "port"
1519         IFPGA_ARG_PORT,
1520 #define IFPGA_AFU_BTS          "afu_bts"
1521         IFPGA_AFU_BTS,
1522         NULL
1523 };
1524
1525 static int ifpga_rawdev_get_string_arg(const char *key __rte_unused,
1526         const char *value, void *extra_args)
1527 {
1528         int size;
1529         if (!value || !extra_args)
1530                 return -EINVAL;
1531
1532         size = strlen(value) + 1;
1533         *(char **)extra_args = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
1534         if (!*(char **)extra_args)
1535                 return -ENOMEM;
1536
1537         strlcpy(*(char **)extra_args, value, size);
1538
1539         return 0;
1540 }
1541 static int
1542 ifpga_cfg_probe(struct rte_vdev_device *dev)
1543 {
1544         struct rte_devargs *devargs;
1545         struct rte_kvargs *kvlist = NULL;
1546         struct rte_rawdev *rawdev = NULL;
1547         struct ifpga_rawdev *ifpga_dev;
1548         int port;
1549         char *name = NULL;
1550         const char *bdf;
1551         char dev_name[RTE_RAWDEV_NAME_MAX_LEN];
1552         int ret = -1;
1553
1554         devargs = dev->device.devargs;
1555
1556         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1557         if (!kvlist) {
1558                 IFPGA_RAWDEV_PMD_LOG(ERR, "error when parsing param");
1559                 goto end;
1560         }
1561
1562         if (rte_kvargs_count(kvlist, IFPGA_ARG_NAME) == 1) {
1563                 if (rte_kvargs_process(kvlist, IFPGA_ARG_NAME,
1564                                        &ifpga_rawdev_get_string_arg,
1565                                        &name) < 0) {
1566                         IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1567                                      IFPGA_ARG_NAME);
1568                         goto end;
1569                 }
1570         } else {
1571                 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1572                           IFPGA_ARG_NAME);
1573                 goto end;
1574         }
1575
1576         if (rte_kvargs_count(kvlist, IFPGA_ARG_PORT) == 1) {
1577                 if (rte_kvargs_process(kvlist,
1578                         IFPGA_ARG_PORT,
1579                         &rte_ifpga_get_integer32_arg,
1580                         &port) < 0) {
1581                         IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1582                                 IFPGA_ARG_PORT);
1583                         goto end;
1584                 }
1585         } else {
1586                 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1587                           IFPGA_ARG_PORT);
1588                 goto end;
1589         }
1590
1591         memset(dev_name, 0, sizeof(dev_name));
1592         snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%s", name);
1593         rawdev = rte_rawdev_pmd_get_named_dev(dev_name);
1594         if (!rawdev)
1595                 goto end;
1596         ifpga_dev = ifpga_rawdev_get(rawdev);
1597         if (!ifpga_dev)
1598                 goto end;
1599         bdf = name;
1600         ifpga_rawdev_fill_info(ifpga_dev, bdf);
1601
1602         ifpga_monitor_start_func();
1603
1604         memset(dev_name, 0, sizeof(dev_name));
1605         snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "%d|%s",
1606         port, name);
1607
1608         ret = rte_eal_hotplug_add(RTE_STR(IFPGA_BUS_NAME),
1609                         dev_name, devargs->args);
1610 end:
1611         if (kvlist)
1612                 rte_kvargs_free(kvlist);
1613         if (name)
1614                 free(name);
1615
1616         return ret;
1617 }
1618
1619 static int
1620 ifpga_cfg_remove(struct rte_vdev_device *vdev)
1621 {
1622         IFPGA_RAWDEV_PMD_INFO("Remove ifpga_cfg %p",
1623                 vdev);
1624
1625         return 0;
1626 }
1627
1628 static struct rte_vdev_driver ifpga_cfg_driver = {
1629         .probe = ifpga_cfg_probe,
1630         .remove = ifpga_cfg_remove,
1631 };
1632
1633 RTE_PMD_REGISTER_VDEV(ifpga_rawdev_cfg, ifpga_cfg_driver);
1634 RTE_PMD_REGISTER_ALIAS(ifpga_rawdev_cfg, ifpga_cfg);
1635 RTE_PMD_REGISTER_PARAM_STRING(ifpga_rawdev_cfg,
1636         "ifpga=<string> "
1637         "port=<int> "
1638         "afu_bts=<path>");