drivers/raw/ifpga/ifpga_rawdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2018 Intel Corporation
   3  */
   4
   5 #include <string.h>
   6 #include <dirent.h>
   7 #include <sys/stat.h>
   8 #include <unistd.h>
   9 #include <sys/types.h>
  10 #include <fcntl.h>
  11 #include <rte_log.h>
  12 #include <rte_bus.h>
  13 #include <rte_malloc.h>
  14 #include <rte_devargs.h>
  15 #include <rte_memcpy.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_kvargs.h>
  19 #include <rte_alarm.h>
  20
  21 #include <rte_errno.h>
  22 #include <rte_per_lcore.h>
  23 #include <rte_memory.h>
  24 #include <rte_memzone.h>
  25 #include <rte_eal.h>
  26 #include <rte_common.h>
  27 #include <rte_bus_vdev.h>
  28
  29 #include "base/opae_hw_api.h"
  30 #include "base/opae_ifpga_hw_api.h"
  31 #include "base/ifpga_api.h"
  32 #include "rte_rawdev.h"
  33 #include "rte_rawdev_pmd.h"
  34 #include "rte_bus_ifpga.h"
  35 #include "ifpga_common.h"
  36 #include "ifpga_logs.h"
  37 #include "ifpga_rawdev.h"
  38 #include "ipn3ke_rawdev_api.h"
  39
  40 int ifpga_rawdev_logtype;
  41
  42 #define PCI_VENDOR_ID_INTEL          0x8086
  43 /* PCI Device ID */
  44 #define PCIE_DEVICE_ID_PF_INT_5_X    0xBCBD
  45 #define PCIE_DEVICE_ID_PF_INT_6_X    0xBCC0
  46 #define PCIE_DEVICE_ID_PF_DSC_1_X    0x09C4
  47 #define PCIE_DEVICE_ID_PAC_N3000     0x0B30
  48 /* VF Device */
  49 #define PCIE_DEVICE_ID_VF_INT_5_X    0xBCBF
  50 #define PCIE_DEVICE_ID_VF_INT_6_X    0xBCC1
  51 #define PCIE_DEVICE_ID_VF_DSC_1_X    0x09C5
  52 #define PCIE_DEVICE_ID_VF_PAC_N3000  0x0B31
  53 #define RTE_MAX_RAW_DEVICE           10
  54
  55 static const struct rte_pci_id pci_ifpga_map[] = {
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PAC_N3000),},
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_PAC_N3000),},
  64         { .vendor_id = 0, /* sentinel */ },
  65 };
  66
  67 static int
  68 ifpga_fill_afu_dev(struct opae_accelerator *acc,
  69                 struct rte_afu_device *afu_dev)
  70 {
  71         struct rte_mem_resource *res = afu_dev->mem_resource;
  72         struct opae_acc_region_info region_info;
  73         struct opae_acc_info info;
  74         unsigned long i;
  75         int ret;
  76
  77         ret = opae_acc_get_info(acc, &info);
  78         if (ret)
  79                 return ret;
  80
  81         if (info.num_regions > PCI_MAX_RESOURCE)
  82                 return -EFAULT;
  83
  84         afu_dev->num_region = info.num_regions;
  85
  86         for (i = 0; i < info.num_regions; i++) {
  87                 region_info.index = i;
  88                 ret = opae_acc_get_region_info(acc, &region_info);
  89                 if (ret)
  90                         return ret;
  91
  92                 if ((region_info.flags & ACC_REGION_MMIO) &&
  93                     (region_info.flags & ACC_REGION_READ) &&
  94                     (region_info.flags & ACC_REGION_WRITE)) {
  95                         res[i].phys_addr = region_info.phys_addr;
  96                         res[i].len = region_info.len;
  97                         res[i].addr = region_info.addr;
  98                 } else
  99                         return -EFAULT;
 100         }
 101
 102         return 0;
 103 }
 104
 105 static void
 106 ifpga_rawdev_info_get(struct rte_rawdev *dev,
 107                                      rte_rawdev_obj_t dev_info)
 108 {
 109         struct opae_adapter *adapter;
 110         struct opae_accelerator *acc;
 111         struct rte_afu_device *afu_dev;
 112         struct opae_manager *mgr = NULL;
 113         struct opae_eth_group_region_info opae_lside_eth_info;
 114         struct opae_eth_group_region_info opae_nside_eth_info;
 115         int lside_bar_idx, nside_bar_idx;
 116
 117         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 118
 119         if (!dev_info) {
 120                 IFPGA_RAWDEV_PMD_ERR("Invalid request");
 121                 return;
 122         }
 123
 124         adapter = ifpga_rawdev_get_priv(dev);
 125         if (!adapter)
 126                 return;
 127
 128         afu_dev = dev_info;
 129         afu_dev->rawdev = dev;
 130
 131         /* find opae_accelerator and fill info into afu_device */
 132         opae_adapter_for_each_acc(adapter, acc) {
 133                 if (acc->index != afu_dev->id.port)
 134                         continue;
 135
 136                 if (ifpga_fill_afu_dev(acc, afu_dev)) {
 137                         IFPGA_RAWDEV_PMD_ERR("cannot get info\n");
 138                         return;
 139                 }
 140         }
 141
 142         /* get opae_manager to rawdev */
 143         mgr = opae_adapter_get_mgr(adapter);
 144         if (mgr) {
 145                 /* get LineSide BAR Index */
 146                 if (opae_manager_get_eth_group_region_info(mgr, 0,
 147                         &opae_lside_eth_info)) {
 148                         return;
 149                 }
 150                 lside_bar_idx = opae_lside_eth_info.mem_idx;
 151
 152                 /* get NICSide BAR Index */
 153                 if (opae_manager_get_eth_group_region_info(mgr, 1,
 154                         &opae_nside_eth_info)) {
 155                         return;
 156                 }
 157                 nside_bar_idx = opae_nside_eth_info.mem_idx;
 158
 159                 if (lside_bar_idx >= PCI_MAX_RESOURCE ||
 160                         nside_bar_idx >= PCI_MAX_RESOURCE ||
 161                         lside_bar_idx == nside_bar_idx)
 162                         return;
 163
 164                 /* fill LineSide BAR Index */
 165                 afu_dev->mem_resource[lside_bar_idx].phys_addr =
 166                         opae_lside_eth_info.phys_addr;
 167                 afu_dev->mem_resource[lside_bar_idx].len =
 168                         opae_lside_eth_info.len;
 169                 afu_dev->mem_resource[lside_bar_idx].addr =
 170                         opae_lside_eth_info.addr;
 171
 172                 /* fill NICSide BAR Index */
 173                 afu_dev->mem_resource[nside_bar_idx].phys_addr =
 174                         opae_nside_eth_info.phys_addr;
 175                 afu_dev->mem_resource[nside_bar_idx].len =
 176                         opae_nside_eth_info.len;
 177                 afu_dev->mem_resource[nside_bar_idx].addr =
 178                         opae_nside_eth_info.addr;
 179         }
 180 }
 181
 182 static int
 183 ifpga_rawdev_configure(const struct rte_rawdev *dev,
 184                 rte_rawdev_obj_t config)
 185 {
 186         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 187
 188         RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
 189
 190         return config ? 0 : 1;
 191 }
 192
 193 static int
 194 ifpga_rawdev_start(struct rte_rawdev *dev)
 195 {
 196         int ret = 0;
 197         struct opae_adapter *adapter;
 198
 199         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 200
 201         RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
 202
 203         adapter = ifpga_rawdev_get_priv(dev);
 204         if (!adapter)
 205                 return -ENODEV;
 206
 207         return ret;
 208 }
 209
 210 static void
 211 ifpga_rawdev_stop(struct rte_rawdev *dev)
 212 {
 213         dev->started = 0;
 214 }
 215
 216 static int
 217 ifpga_rawdev_close(struct rte_rawdev *dev)
 218 {
 219         return dev ? 0:1;
 220 }
 221
 222 static int
 223 ifpga_rawdev_reset(struct rte_rawdev *dev)
 224 {
 225         return dev ? 0:1;
 226 }
 227
 228 static int
 229 fpga_pr(struct rte_rawdev *raw_dev, u32 port_id, const char *buffer, u32 size,
 230                         u64 *status)
 231 {
 232
 233         struct opae_adapter *adapter;
 234         struct opae_manager *mgr;
 235         struct opae_accelerator *acc;
 236         struct opae_bridge *br;
 237         int ret;
 238
 239         adapter = ifpga_rawdev_get_priv(raw_dev);
 240         if (!adapter)
 241                 return -ENODEV;
 242
 243         mgr = opae_adapter_get_mgr(adapter);
 244         if (!mgr)
 245                 return -ENODEV;
 246
 247         acc = opae_adapter_get_acc(adapter, port_id);
 248         if (!acc)
 249                 return -ENODEV;
 250
 251         br = opae_acc_get_br(acc);
 252         if (!br)
 253                 return -ENODEV;
 254
 255         ret = opae_manager_flash(mgr, port_id, buffer, size, status);
 256         if (ret) {
 257                 IFPGA_RAWDEV_PMD_ERR("%s pr error %d\n", __func__, ret);
 258                 return ret;
 259         }
 260
 261         ret = opae_bridge_reset(br);
 262         if (ret) {
 263                 IFPGA_RAWDEV_PMD_ERR("%s reset port:%d error %d\n",
 264                                 __func__, port_id, ret);
 265                 return ret;
 266         }
 267
 268         return ret;
 269 }
 270
 271 static int
 272 rte_fpga_do_pr(struct rte_rawdev *rawdev, int port_id,
 273                 const char *file_name)
 274 {
 275         struct stat file_stat;
 276         int file_fd;
 277         int ret = 0;
 278         ssize_t buffer_size;
 279         void *buffer;
 280         u64 pr_error;
 281
 282         if (!file_name)
 283                 return -EINVAL;
 284
 285         file_fd = open(file_name, O_RDONLY);
 286         if (file_fd < 0) {
 287                 IFPGA_RAWDEV_PMD_ERR("%s: open file error: %s\n",
 288                                 __func__, file_name);
 289                 IFPGA_RAWDEV_PMD_ERR("Message : %s\n", strerror(errno));
 290                 return -EINVAL;
 291         }
 292         ret = stat(file_name, &file_stat);
 293         if (ret) {
 294                 IFPGA_RAWDEV_PMD_ERR("stat on bitstream file failed: %s\n",
 295                                 file_name);
 296                 ret = -EINVAL;
 297                 goto close_fd;
 298         }
 299         buffer_size = file_stat.st_size;
 300         if (buffer_size <= 0) {
 301                 ret = -EINVAL;
 302                 goto close_fd;
 303         }
 304
 305         IFPGA_RAWDEV_PMD_INFO("bitstream file size: %zu\n", buffer_size);
 306         buffer = rte_malloc(NULL, buffer_size, 0);
 307         if (!buffer) {
 308                 ret = -ENOMEM;
 309                 goto close_fd;
 310         }
 311
 312         /*read the raw data*/
 313         if (buffer_size != read(file_fd, (void *)buffer, buffer_size)) {
 314                 ret = -EINVAL;
 315                 goto free_buffer;
 316         }
 317
 318         /*do PR now*/
 319         ret = fpga_pr(rawdev, port_id, buffer, buffer_size, &pr_error);
 320         IFPGA_RAWDEV_PMD_INFO("downloading to device port %d....%s.\n", port_id,
 321                 ret ? "failed" : "success");
 322         if (ret) {
 323                 ret = -EINVAL;
 324                 goto free_buffer;
 325         }
 326
 327 free_buffer:
 328         if (buffer)
 329                 rte_free(buffer);
 330 close_fd:
 331         close(file_fd);
 332         file_fd = 0;
 333         return ret;
 334 }
 335
 336 static int
 337 ifpga_rawdev_pr(struct rte_rawdev *dev,
 338         rte_rawdev_obj_t pr_conf)
 339 {
 340         struct opae_adapter *adapter;
 341         struct rte_afu_pr_conf *afu_pr_conf;
 342         int ret;
 343         struct uuid uuid;
 344         struct opae_accelerator *acc;
 345
 346         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 347
 348         adapter = ifpga_rawdev_get_priv(dev);
 349         if (!adapter)
 350                 return -ENODEV;
 351
 352         if (!pr_conf)
 353                 return -EINVAL;
 354
 355         afu_pr_conf = pr_conf;
 356
 357         if (afu_pr_conf->pr_enable) {
 358                 ret = rte_fpga_do_pr(dev,
 359                                 afu_pr_conf->afu_id.port,
 360                                 afu_pr_conf->bs_path);
 361                 if (ret) {
 362                         IFPGA_RAWDEV_PMD_ERR("do pr error %d\n", ret);
 363                         return ret;
 364                 }
 365         }
 366
 367         acc = opae_adapter_get_acc(adapter, afu_pr_conf->afu_id.port);
 368         if (!acc)
 369                 return -ENODEV;
 370
 371         ret = opae_acc_get_uuid(acc, &uuid);
 372         if (ret)
 373                 return ret;
 374
 375         memcpy(&afu_pr_conf->afu_id.uuid.uuid_low, uuid.b, sizeof(u64));
 376         memcpy(&afu_pr_conf->afu_id.uuid.uuid_high, uuid.b + 8, sizeof(u64));
 377
 378         IFPGA_RAWDEV_PMD_INFO("%s: uuid_l=0x%lx, uuid_h=0x%lx\n", __func__,
 379                 (unsigned long)afu_pr_conf->afu_id.uuid.uuid_low,
 380                 (unsigned long)afu_pr_conf->afu_id.uuid.uuid_high);
 381
 382         return 0;
 383 }
 384
 385 static int
 386 ifpga_rawdev_get_attr(struct rte_rawdev *dev,
 387         const char *attr_name, uint64_t *attr_value)
 388 {
 389         struct opae_adapter *adapter;
 390         struct opae_manager *mgr;
 391         struct opae_retimer_info opae_rtm_info;
 392         struct opae_retimer_status opae_rtm_status;
 393         struct opae_eth_group_info opae_eth_grp_info;
 394         struct opae_eth_group_region_info opae_eth_grp_reg_info;
 395         int eth_group_num = 0;
 396         uint64_t port_link_bitmap = 0, port_link_bit;
 397         uint32_t i, j, p, q;
 398
 399 #define MAX_PORT_PER_RETIMER    4
 400
 401         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 402
 403         if (!dev || !attr_name || !attr_value) {
 404                 IFPGA_RAWDEV_PMD_ERR("Invalid arguments for getting attributes");
 405                 return -1;
 406         }
 407
 408         adapter = ifpga_rawdev_get_priv(dev);
 409         if (!adapter) {
 410                 IFPGA_RAWDEV_PMD_ERR("Adapter of dev %s is NULL", dev->name);
 411                 return -1;
 412         }
 413
 414         mgr = opae_adapter_get_mgr(adapter);
 415         if (!mgr) {
 416                 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
 417                 return -1;
 418         }
 419
 420         /* currently, eth_group_num is always 2 */
 421         eth_group_num = opae_manager_get_eth_group_nums(mgr);
 422         if (eth_group_num < 0)
 423                 return -1;
 424
 425         if (!strcmp(attr_name, "LineSideBaseMAC")) {
 426                 /* Currently FPGA not implement, so just set all zeros*/
 427                 *attr_value = (uint64_t)0;
 428                 return 0;
 429         }
 430         if (!strcmp(attr_name, "LineSideMACType")) {
 431                 /* eth_group 0 on FPGA connect to LineSide */
 432                 if (opae_manager_get_eth_group_info(mgr, 0,
 433                         &opae_eth_grp_info))
 434                         return -1;
 435                 switch (opae_eth_grp_info.speed) {
 436                 case ETH_SPEED_10G:
 437                         *attr_value =
 438                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI);
 439                         break;
 440                 case ETH_SPEED_25G:
 441                         *attr_value =
 442                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI);
 443                         break;
 444                 default:
 445                         *attr_value =
 446                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_UNKNOWN);
 447                         break;
 448                 }
 449                 return 0;
 450         }
 451         if (!strcmp(attr_name, "LineSideLinkSpeed")) {
 452                 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
 453                         return -1;
 454                 switch (opae_rtm_status.speed) {
 455                 case MXD_1GB:
 456                         *attr_value =
 457                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 458                         break;
 459                 case MXD_2_5GB:
 460                         *attr_value =
 461                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 462                         break;
 463                 case MXD_5GB:
 464                         *attr_value =
 465                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 466                         break;
 467                 case MXD_10GB:
 468                         *attr_value =
 469                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_10GB);
 470                         break;
 471                 case MXD_25GB:
 472                         *attr_value =
 473                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_25GB);
 474                         break;
 475                 case MXD_40GB:
 476                         *attr_value =
 477                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_40GB);
 478                         break;
 479                 case MXD_100GB:
 480                         *attr_value =
 481                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 482                         break;
 483                 case MXD_SPEED_UNKNOWN:
 484                         *attr_value =
 485                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 486                         break;
 487                 default:
 488                         *attr_value =
 489                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 490                         break;
 491                 }
 492                 return 0;
 493         }
 494         if (!strcmp(attr_name, "LineSideLinkRetimerNum")) {
 495                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
 496                         return -1;
 497                 *attr_value = (uint64_t)(opae_rtm_info.nums_retimer);
 498                 return 0;
 499         }
 500         if (!strcmp(attr_name, "LineSideLinkPortNum")) {
 501                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
 502                         return -1;
 503                 uint64_t tmp = (uint64_t)opae_rtm_info.ports_per_retimer *
 504                                         (uint64_t)opae_rtm_info.nums_retimer;
 505                 *attr_value = tmp;
 506                 return 0;
 507         }
 508         if (!strcmp(attr_name, "LineSideLinkStatus")) {
 509                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
 510                         return -1;
 511                 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
 512                         return -1;
 513                 (*attr_value) = 0;
 514                 q = 0;
 515                 port_link_bitmap = (uint64_t)(opae_rtm_status.line_link_bitmap);
 516                 for (i = 0; i < opae_rtm_info.nums_retimer; i++) {
 517                         p = i * MAX_PORT_PER_RETIMER;
 518                         for (j = 0; j < opae_rtm_info.ports_per_retimer; j++) {
 519                                 port_link_bit = 0;
 520                                 IFPGA_BIT_SET(port_link_bit, (p+j));
 521                                 port_link_bit &= port_link_bitmap;
 522                                 if (port_link_bit)
 523                                         IFPGA_BIT_SET((*attr_value), q);
 524                                 q++;
 525                         }
 526                 }
 527                 return 0;
 528         }
 529         if (!strcmp(attr_name, "LineSideBARIndex")) {
 530                 /* eth_group 0 on FPGA connect to LineSide */
 531                 if (opae_manager_get_eth_group_region_info(mgr, 0,
 532                         &opae_eth_grp_reg_info))
 533                         return -1;
 534                 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
 535                 return 0;
 536         }
 537         if (!strcmp(attr_name, "NICSideMACType")) {
 538                 /* eth_group 1 on FPGA connect to NicSide */
 539                 if (opae_manager_get_eth_group_info(mgr, 1,
 540                         &opae_eth_grp_info))
 541                         return -1;
 542                 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
 543                 return 0;
 544         }
 545         if (!strcmp(attr_name, "NICSideLinkSpeed")) {
 546                 /* eth_group 1 on FPGA connect to NicSide */
 547                 if (opae_manager_get_eth_group_info(mgr, 1,
 548                         &opae_eth_grp_info))
 549                         return -1;
 550                 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
 551                 return 0;
 552         }
 553         if (!strcmp(attr_name, "NICSideLinkPortNum")) {
 554                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
 555                         return -1;
 556                 uint64_t tmp = (uint64_t)opae_rtm_info.nums_fvl *
 557                                         (uint64_t)opae_rtm_info.ports_per_fvl;
 558                 *attr_value = tmp;
 559                 return 0;
 560         }
 561         if (!strcmp(attr_name, "NICSideLinkStatus"))
 562                 return 0;
 563         if (!strcmp(attr_name, "NICSideBARIndex")) {
 564                 /* eth_group 1 on FPGA connect to NicSide */
 565                 if (opae_manager_get_eth_group_region_info(mgr, 1,
 566                         &opae_eth_grp_reg_info))
 567                         return -1;
 568                 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
 569                 return 0;
 570         }
 571
 572         IFPGA_RAWDEV_PMD_ERR("%s not support", attr_name);
 573         return -1;
 574 }
 575
 576 static const struct rte_rawdev_ops ifpga_rawdev_ops = {
 577         .dev_info_get = ifpga_rawdev_info_get,
 578         .dev_configure = ifpga_rawdev_configure,
 579         .dev_start = ifpga_rawdev_start,
 580         .dev_stop = ifpga_rawdev_stop,
 581         .dev_close = ifpga_rawdev_close,
 582         .dev_reset = ifpga_rawdev_reset,
 583
 584         .queue_def_conf = NULL,
 585         .queue_setup = NULL,
 586         .queue_release = NULL,
 587
 588         .attr_get = ifpga_rawdev_get_attr,
 589         .attr_set = NULL,
 590
 591         .enqueue_bufs = NULL,
 592         .dequeue_bufs = NULL,
 593
 594         .dump = NULL,
 595
 596         .xstats_get = NULL,
 597         .xstats_get_names = NULL,
 598         .xstats_get_by_name = NULL,
 599         .xstats_reset = NULL,
 600
 601         .firmware_status_get = NULL,
 602         .firmware_version_get = NULL,
 603         .firmware_load = ifpga_rawdev_pr,
 604         .firmware_unload = NULL,
 605
 606         .dev_selftest = NULL,
 607 };
 608
 609 static int
 610 ifpga_get_fme_error_prop(struct opae_manager *mgr,
 611                 u64 prop_id, u64 *val)
 612 {
 613         struct feature_prop prop;
 614
 615         prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
 616         prop.prop_id = prop_id;
 617
 618         if (opae_manager_ifpga_get_prop(mgr, &prop))
 619                 return -EINVAL;
 620
 621         *val = prop.data;
 622
 623         return 0;
 624 }
 625
 626 static int
 627 ifpga_set_fme_error_prop(struct opae_manager *mgr,
 628                 u64 prop_id, u64 val)
 629 {
 630         struct feature_prop prop;
 631
 632         prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
 633         prop.prop_id = prop_id;
 634
 635         prop.data = val;
 636
 637         if (opae_manager_ifpga_set_prop(mgr, &prop))
 638                 return -EINVAL;
 639
 640         return 0;
 641 }
 642
 643 static int
 644 fme_err_read_seu_emr(struct opae_manager *mgr)
 645 {
 646         u64 val;
 647         int ret;
 648
 649         ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_LOW, &val);
 650         if (ret)
 651                 return -EINVAL;
 652
 653         IFPGA_RAWDEV_PMD_INFO("seu emr low: 0x%" PRIx64 "\n", val);
 654
 655         ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_HIGH, &val);
 656         if (ret)
 657                 return -EINVAL;
 658
 659         IFPGA_RAWDEV_PMD_INFO("seu emr high: 0x%" PRIx64 "\n", val);
 660
 661         return 0;
 662 }
 663
 664 static int fme_clear_warning_intr(struct opae_manager *mgr)
 665 {
 666         u64 val;
 667
 668         if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_INJECT_ERRORS, 0))
 669                 return -EINVAL;
 670
 671         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
 672                 return -EINVAL;
 673         if ((val & 0x40) != 0)
 674                 IFPGA_RAWDEV_PMD_INFO("clean not done\n");
 675
 676         return 0;
 677 }
 678
 679 static int
 680 fme_err_handle_error0(struct opae_manager *mgr)
 681 {
 682         struct feature_fme_error0 fme_error0;
 683         u64 val;
 684
 685         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
 686                 return -EINVAL;
 687
 688         fme_error0.csr = val;
 689
 690         if (fme_error0.fabric_err)
 691                 IFPGA_RAWDEV_PMD_ERR("Fabric error\n");
 692         else if (fme_error0.fabfifo_overflow)
 693                 IFPGA_RAWDEV_PMD_ERR("Fabric fifo under/overflow error\n");
 694         else if (fme_error0.afu_acc_mode_err)
 695                 IFPGA_RAWDEV_PMD_ERR("AFU PF/VF access mismatch detected\n");
 696         else if (fme_error0.pcie0cdc_parity_err)
 697                 IFPGA_RAWDEV_PMD_ERR("PCIe0 CDC Parity Error\n");
 698         else if (fme_error0.cvlcdc_parity_err)
 699                 IFPGA_RAWDEV_PMD_ERR("CVL CDC Parity Error\n");
 700         else if (fme_error0.fpgaseuerr)
 701                 fme_err_read_seu_emr(mgr);
 702
 703         /* clean the errors */
 704         if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, val))
 705                 return -EINVAL;
 706
 707         return 0;
 708 }
 709
 710 static int
 711 fme_err_handle_catfatal_error(struct opae_manager *mgr)
 712 {
 713         struct feature_fme_ras_catfaterror fme_catfatal;
 714         u64 val;
 715
 716         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_CATFATAL_ERRORS, &val))
 717                 return -EINVAL;
 718
 719         fme_catfatal.csr = val;
 720
 721         if (fme_catfatal.cci_fatal_err)
 722                 IFPGA_RAWDEV_PMD_ERR("CCI error detected\n");
 723         else if (fme_catfatal.fabric_fatal_err)
 724                 IFPGA_RAWDEV_PMD_ERR("Fabric fatal error detected\n");
 725         else if (fme_catfatal.pcie_poison_err)
 726                 IFPGA_RAWDEV_PMD_ERR("Poison error from PCIe ports\n");
 727         else if (fme_catfatal.inject_fata_err)
 728                 IFPGA_RAWDEV_PMD_ERR("Injected Fatal Error\n");
 729         else if (fme_catfatal.crc_catast_err)
 730                 IFPGA_RAWDEV_PMD_ERR("a catastrophic EDCRC error\n");
 731         else if (fme_catfatal.injected_catast_err)
 732                 IFPGA_RAWDEV_PMD_ERR("Injected Catastrophic Error\n");
 733         else if (fme_catfatal.bmc_seu_catast_err)
 734                 fme_err_read_seu_emr(mgr);
 735
 736         return 0;
 737 }
 738
 739 static int
 740 fme_err_handle_nonfaterror(struct opae_manager *mgr)
 741 {
 742         struct feature_fme_ras_nonfaterror nonfaterr;
 743         u64 val;
 744
 745         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
 746                 return -EINVAL;
 747
 748         nonfaterr.csr = val;
 749
 750         if (nonfaterr.temp_thresh_ap1)
 751                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP1\n");
 752         else if (nonfaterr.temp_thresh_ap2)
 753                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP2\n");
 754         else if (nonfaterr.pcie_error)
 755                 IFPGA_RAWDEV_PMD_INFO("an error has occurred in pcie\n");
 756         else if (nonfaterr.portfatal_error)
 757                 IFPGA_RAWDEV_PMD_INFO("fatal error occurred in AFU port.\n");
 758         else if (nonfaterr.proc_hot)
 759                 IFPGA_RAWDEV_PMD_INFO("a ProcHot event\n");
 760         else if (nonfaterr.afu_acc_mode_err)
 761                 IFPGA_RAWDEV_PMD_INFO("an AFU PF/VF access mismatch\n");
 762         else if (nonfaterr.injected_nonfata_err) {
 763                 IFPGA_RAWDEV_PMD_INFO("Injected Warning Error\n");
 764                 fme_clear_warning_intr(mgr);
 765         } else if (nonfaterr.temp_thresh_AP6)
 766                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP6\n");
 767         else if (nonfaterr.power_thresh_AP1)
 768                 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP1\n");
 769         else if (nonfaterr.power_thresh_AP2)
 770                 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP2\n");
 771         else if (nonfaterr.mbp_err)
 772                 IFPGA_RAWDEV_PMD_INFO("an MBP event\n");
 773
 774         return 0;
 775 }
 776
 777 static void
 778 fme_interrupt_handler(void *param)
 779 {
 780         struct opae_manager *mgr = (struct opae_manager *)param;
 781
 782         IFPGA_RAWDEV_PMD_INFO("%s interrupt occurred\n", __func__);
 783
 784         fme_err_handle_error0(mgr);
 785         fme_err_handle_nonfaterror(mgr);
 786         fme_err_handle_catfatal_error(mgr);
 787 }
 788
 789 static struct rte_intr_handle fme_intr_handle;
 790
 791 static int ifpga_register_fme_interrupt(struct opae_manager *mgr)
 792 {
 793         int ret;
 794         struct fpga_fme_err_irq_set err_irq_set;
 795
 796         fme_intr_handle.type = RTE_INTR_HANDLE_VFIO_MSIX;
 797
 798         ret = rte_intr_efd_enable(&fme_intr_handle, 1);
 799         if (ret)
 800                 return -EINVAL;
 801
 802         fme_intr_handle.fd = fme_intr_handle.efds[0];
 803
 804         IFPGA_RAWDEV_PMD_DEBUG("vfio_dev_fd=%d, efd=%d, fd=%d\n",
 805                         fme_intr_handle.vfio_dev_fd,
 806                         fme_intr_handle.efds[0], fme_intr_handle.fd);
 807
 808         err_irq_set.evtfd = fme_intr_handle.efds[0];
 809         ret = opae_manager_ifpga_set_err_irq(mgr, &err_irq_set);
 810         if (ret)
 811                 return -EINVAL;
 812
 813         /* register FME interrupt using DPDK API */
 814         ret = rte_intr_callback_register(&fme_intr_handle,
 815                         fme_interrupt_handler,
 816                         (void *)mgr);
 817         if (ret)
 818                 return -EINVAL;
 819
 820         IFPGA_RAWDEV_PMD_INFO("success register fme interrupt\n");
 821
 822         return 0;
 823 }
 824
 825 static int
 826 ifpga_unregister_fme_interrupt(struct opae_manager *mgr)
 827 {
 828         rte_intr_efd_disable(&fme_intr_handle);
 829
 830         return rte_intr_callback_unregister(&fme_intr_handle,
 831                         fme_interrupt_handler,
 832                         (void *)mgr);
 833 }
 834
 835 static int
 836 ifpga_rawdev_create(struct rte_pci_device *pci_dev,
 837                         int socket_id)
 838 {
 839         int ret = 0;
 840         struct rte_rawdev *rawdev = NULL;
 841         struct opae_adapter *adapter = NULL;
 842         struct opae_manager *mgr = NULL;
 843         struct opae_adapter_data_pci *data = NULL;
 844         char name[RTE_RAWDEV_NAME_MAX_LEN];
 845         int i;
 846
 847         if (!pci_dev) {
 848                 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
 849                 ret = -EINVAL;
 850                 goto cleanup;
 851         }
 852
 853         memset(name, 0, sizeof(name));
 854         snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%x:%02x.%x",
 855                 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
 856
 857         IFPGA_RAWDEV_PMD_INFO("Init %s on NUMA node %d", name, rte_socket_id());
 858
 859         /* Allocate device structure */
 860         rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct opae_adapter),
 861                                          socket_id);
 862         if (rawdev == NULL) {
 863                 IFPGA_RAWDEV_PMD_ERR("Unable to allocate rawdevice");
 864                 ret = -EINVAL;
 865                 goto cleanup;
 866         }
 867
 868         /* alloc OPAE_FPGA_PCI data to register to OPAE hardware level API */
 869         data = opae_adapter_data_alloc(OPAE_FPGA_PCI);
 870         if (!data) {
 871                 ret = -ENOMEM;
 872                 goto cleanup;
 873         }
 874
 875         /* init opae_adapter_data_pci for device specific information */
 876         for (i = 0; i < PCI_MAX_RESOURCE; i++) {
 877                 data->region[i].phys_addr = pci_dev->mem_resource[i].phys_addr;
 878                 data->region[i].len = pci_dev->mem_resource[i].len;
 879                 data->region[i].addr = pci_dev->mem_resource[i].addr;
 880         }
 881         data->device_id = pci_dev->id.device_id;
 882         data->vendor_id = pci_dev->id.vendor_id;
 883         data->vfio_dev_fd = pci_dev->intr_handle.vfio_dev_fd;
 884
 885         adapter = rawdev->dev_private;
 886         /* create a opae_adapter based on above device data */
 887         ret = opae_adapter_init(adapter, pci_dev->device.name, data);
 888         if (ret) {
 889                 ret = -ENOMEM;
 890                 goto free_adapter_data;
 891         }
 892
 893         rawdev->dev_ops = &ifpga_rawdev_ops;
 894         rawdev->device = &pci_dev->device;
 895         rawdev->driver_name = pci_dev->driver->driver.name;
 896
 897         /* must enumerate the adapter before use it */
 898         ret = opae_adapter_enumerate(adapter);
 899         if (ret)
 900                 goto free_adapter_data;
 901
 902         /* get opae_manager to rawdev */
 903         mgr = opae_adapter_get_mgr(adapter);
 904         if (mgr) {
 905                 /* PF function */
 906                 IFPGA_RAWDEV_PMD_INFO("this is a PF function");
 907         }
 908
 909         ret = ifpga_register_fme_interrupt(mgr);
 910         if (ret)
 911                 goto free_adapter_data;
 912
 913         return ret;
 914
 915 free_adapter_data:
 916         if (data)
 917                 opae_adapter_data_free(data);
 918 cleanup:
 919         if (rawdev)
 920                 rte_rawdev_pmd_release(rawdev);
 921
 922         return ret;
 923 }
 924
 925 static int
 926 ifpga_rawdev_destroy(struct rte_pci_device *pci_dev)
 927 {
 928         int ret;
 929         struct rte_rawdev *rawdev;
 930         char name[RTE_RAWDEV_NAME_MAX_LEN];
 931         struct opae_adapter *adapter;
 932         struct opae_manager *mgr;
 933
 934         if (!pci_dev) {
 935                 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
 936                 ret = -EINVAL;
 937                 return ret;
 938         }
 939
 940         memset(name, 0, sizeof(name));
 941         snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%x:%02x.%x",
 942                 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
 943
 944         IFPGA_RAWDEV_PMD_INFO("Closing %s on NUMA node %d",
 945                 name, rte_socket_id());
 946
 947         rawdev = rte_rawdev_pmd_get_named_dev(name);
 948         if (!rawdev) {
 949                 IFPGA_RAWDEV_PMD_ERR("Invalid device name (%s)", name);
 950                 return -EINVAL;
 951         }
 952
 953         adapter = ifpga_rawdev_get_priv(rawdev);
 954         if (!adapter)
 955                 return -ENODEV;
 956
 957         mgr = opae_adapter_get_mgr(adapter);
 958         if (!mgr)
 959                 return -ENODEV;
 960
 961         if (ifpga_unregister_fme_interrupt(mgr))
 962                 return -EINVAL;
 963
 964         opae_adapter_data_free(adapter->data);
 965         opae_adapter_free(adapter);
 966
 967         /* rte_rawdev_close is called by pmd_release */
 968         ret = rte_rawdev_pmd_release(rawdev);
 969         if (ret)
 970                 IFPGA_RAWDEV_PMD_DEBUG("Device cleanup failed");
 971
 972         return ret;
 973 }
 974
 975 static int
 976 ifpga_rawdev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 977         struct rte_pci_device *pci_dev)
 978 {
 979         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 980         return ifpga_rawdev_create(pci_dev, rte_socket_id());
 981 }
 982
 983 static int
 984 ifpga_rawdev_pci_remove(struct rte_pci_device *pci_dev)
 985 {
 986         return ifpga_rawdev_destroy(pci_dev);
 987 }
 988
 989 static struct rte_pci_driver rte_ifpga_rawdev_pmd = {
 990         .id_table  = pci_ifpga_map,
 991         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 992         .probe     = ifpga_rawdev_pci_probe,
 993         .remove    = ifpga_rawdev_pci_remove,
 994 };
 995
 996 RTE_PMD_REGISTER_PCI(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
 997 RTE_PMD_REGISTER_PCI_TABLE(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
 998 RTE_PMD_REGISTER_KMOD_DEP(ifpga_rawdev_pci_driver, "* igb_uio | uio_pci_generic | vfio-pci");
 999
1000 RTE_INIT(ifpga_rawdev_init_log)
1001 {
1002         ifpga_rawdev_logtype = rte_log_register("driver.raw.init");
1003         if (ifpga_rawdev_logtype >= 0)
1004                 rte_log_set_level(ifpga_rawdev_logtype, RTE_LOG_NOTICE);
1005 }
1006
1007 static const char * const valid_args[] = {
1008 #define IFPGA_ARG_NAME         "ifpga"
1009         IFPGA_ARG_NAME,
1010 #define IFPGA_ARG_PORT         "port"
1011         IFPGA_ARG_PORT,
1012 #define IFPGA_AFU_BTS          "afu_bts"
1013         IFPGA_AFU_BTS,
1014         NULL
1015 };
1016
1017 static int
1018 ifpga_cfg_probe(struct rte_vdev_device *dev)
1019 {
1020         struct rte_devargs *devargs;
1021         struct rte_kvargs *kvlist = NULL;
1022         int port;
1023         char *name = NULL;
1024         char dev_name[RTE_RAWDEV_NAME_MAX_LEN];
1025         int ret = -1;
1026
1027         devargs = dev->device.devargs;
1028
1029         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1030         if (!kvlist) {
1031                 IFPGA_RAWDEV_PMD_LOG(ERR, "error when parsing param");
1032                 goto end;
1033         }
1034
1035         if (rte_kvargs_count(kvlist, IFPGA_ARG_NAME) == 1) {
1036                 if (rte_kvargs_process(kvlist, IFPGA_ARG_NAME,
1037                                        &rte_ifpga_get_string_arg, &name) < 0) {
1038                         IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1039                                      IFPGA_ARG_NAME);
1040                         goto end;
1041                 }
1042         } else {
1043                 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1044                           IFPGA_ARG_NAME);
1045                 goto end;
1046         }
1047
1048         if (rte_kvargs_count(kvlist, IFPGA_ARG_PORT) == 1) {
1049                 if (rte_kvargs_process(kvlist,
1050                         IFPGA_ARG_PORT,
1051                         &rte_ifpga_get_integer32_arg,
1052                         &port) < 0) {
1053                         IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1054                                 IFPGA_ARG_PORT);
1055                         goto end;
1056                 }
1057         } else {
1058                 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1059                           IFPGA_ARG_PORT);
1060                 goto end;
1061         }
1062
1063         memset(dev_name, 0, sizeof(dev_name));
1064         snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "%d|%s",
1065         port, name);
1066
1067         ret = rte_eal_hotplug_add(RTE_STR(IFPGA_BUS_NAME),
1068                         dev_name, devargs->args);
1069 end:
1070         if (kvlist)
1071                 rte_kvargs_free(kvlist);
1072         if (name)
1073                 free(name);
1074
1075         return ret;
1076 }
1077
1078 static int
1079 ifpga_cfg_remove(struct rte_vdev_device *vdev)
1080 {
1081         IFPGA_RAWDEV_PMD_INFO("Remove ifpga_cfg %p",
1082                 vdev);
1083
1084         return 0;
1085 }
1086
1087 static struct rte_vdev_driver ifpga_cfg_driver = {
1088         .probe = ifpga_cfg_probe,
1089         .remove = ifpga_cfg_remove,
1090 };
1091
1092 RTE_PMD_REGISTER_VDEV(ifpga_rawdev_cfg, ifpga_cfg_driver);
1093 RTE_PMD_REGISTER_ALIAS(ifpga_rawdev_cfg, ifpga_cfg);
1094 RTE_PMD_REGISTER_PARAM_STRING(ifpga_rawdev_cfg,
1095         "ifpga=<string> "
1096         "port=<int> "
1097         "afu_bts=<path>");