drivers/raw/ifpga/ifpga_rawdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2018 Intel Corporation
   3  */
   4
   5 #include <string.h>
   6 #include <dirent.h>
   7 #include <sys/stat.h>
   8 #include <unistd.h>
   9 #include <sys/types.h>
  10 #include <fcntl.h>
  11 #include <sys/ioctl.h>
  12 #include <sys/epoll.h>
  13 #include <rte_log.h>
  14 #include <rte_bus.h>
  15 #include <rte_malloc.h>
  16 #include <rte_devargs.h>
  17 #include <rte_memcpy.h>
  18 #include <rte_pci.h>
  19 #include <rte_bus_pci.h>
  20 #include <rte_kvargs.h>
  21 #include <rte_alarm.h>
  22 #include <rte_interrupts.h>
  23 #include <rte_errno.h>
  24 #include <rte_per_lcore.h>
  25 #include <rte_memory.h>
  26 #include <rte_memzone.h>
  27 #include <rte_eal.h>
  28 #include <rte_common.h>
  29 #include <rte_bus_vdev.h>
  30 #include <rte_string_fns.h>
  31 #include <rte_pmd_i40e.h>
  32
  33 #include "base/opae_hw_api.h"
  34 #include "base/opae_ifpga_hw_api.h"
  35 #include "base/ifpga_api.h"
  36 #include "rte_rawdev.h"
  37 #include "rte_rawdev_pmd.h"
  38 #include "rte_bus_ifpga.h"
  39 #include "ifpga_common.h"
  40 #include "ifpga_logs.h"
  41 #include "ifpga_rawdev.h"
  42 #include "ipn3ke_rawdev_api.h"
  43
  44 #define PCI_VENDOR_ID_INTEL          0x8086
  45 /* PCI Device ID */
  46 #define PCIE_DEVICE_ID_PF_INT_5_X    0xBCBD
  47 #define PCIE_DEVICE_ID_PF_INT_6_X    0xBCC0
  48 #define PCIE_DEVICE_ID_PF_DSC_1_X    0x09C4
  49 #define PCIE_DEVICE_ID_PAC_N3000     0x0B30
  50 /* VF Device */
  51 #define PCIE_DEVICE_ID_VF_INT_5_X    0xBCBF
  52 #define PCIE_DEVICE_ID_VF_INT_6_X    0xBCC1
  53 #define PCIE_DEVICE_ID_VF_DSC_1_X    0x09C5
  54 #define PCIE_DEVICE_ID_VF_PAC_N3000  0x0B31
  55 #define RTE_MAX_RAW_DEVICE           10
  56
  57 static const struct rte_pci_id pci_ifpga_map[] = {
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PAC_N3000),},
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_PAC_N3000),},
  66         { .vendor_id = 0, /* sentinel */ },
  67 };
  68
  69 static struct ifpga_rawdev ifpga_rawdevices[IFPGA_RAWDEV_NUM];
  70
  71 static int ifpga_monitor_start;
  72 static pthread_t ifpga_monitor_start_thread;
  73
  74 #define IFPGA_MAX_IRQ 12
  75 /* 0 for FME interrupt, others are reserved for AFU irq */
  76 static struct rte_intr_handle ifpga_irq_handle[IFPGA_MAX_IRQ];
  77
  78 static struct ifpga_rawdev *
  79 ifpga_rawdev_allocate(struct rte_rawdev *rawdev);
  80 static int set_surprise_link_check_aer(
  81                 struct ifpga_rawdev *ifpga_rdev, int force_disable);
  82 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
  83                                               int start, uint32_t cap);
  84 static int ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap);
  85
  86 struct ifpga_rawdev *
  87 ifpga_rawdev_get(const struct rte_rawdev *rawdev)
  88 {
  89         struct ifpga_rawdev *dev;
  90         unsigned int i;
  91
  92         if (rawdev == NULL)
  93                 return NULL;
  94
  95         for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
  96                 dev = &ifpga_rawdevices[i];
  97                 if (dev->rawdev == rawdev)
  98                         return dev;
  99         }
 100
 101         return NULL;
 102 }
 103
 104 static inline uint8_t
 105 ifpga_rawdev_find_free_device_index(void)
 106 {
 107         uint16_t dev_id;
 108
 109         for (dev_id = 0; dev_id < IFPGA_RAWDEV_NUM; dev_id++) {
 110                 if (ifpga_rawdevices[dev_id].rawdev == NULL)
 111                         return dev_id;
 112         }
 113
 114         return IFPGA_RAWDEV_NUM;
 115 }
 116 static struct ifpga_rawdev *
 117 ifpga_rawdev_allocate(struct rte_rawdev *rawdev)
 118 {
 119         struct ifpga_rawdev *dev;
 120         uint16_t dev_id;
 121
 122         dev = ifpga_rawdev_get(rawdev);
 123         if (dev != NULL) {
 124                 IFPGA_RAWDEV_PMD_ERR("Event device already allocated!");
 125                 return NULL;
 126         }
 127
 128         dev_id = ifpga_rawdev_find_free_device_index();
 129         if (dev_id == IFPGA_RAWDEV_NUM) {
 130                 IFPGA_RAWDEV_PMD_ERR("Reached maximum number of raw devices");
 131                 return NULL;
 132         }
 133
 134         dev = &ifpga_rawdevices[dev_id];
 135         dev->rawdev = rawdev;
 136         dev->dev_id = dev_id;
 137
 138         return dev;
 139 }
 140
 141 static int
 142 ifpga_pci_find_next_ext_capability(unsigned int fd, int start, uint32_t cap)
 143 {
 144         uint32_t header;
 145         int ttl;
 146         int pos = RTE_PCI_CFG_SPACE_SIZE;
 147         int ret;
 148
 149         /* minimum 8 bytes per capability */
 150         ttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8;
 151
 152         if (start)
 153                 pos = start;
 154         ret = pread(fd, &header, sizeof(header), pos);
 155         if (ret == -1)
 156                 return -1;
 157
 158         /*
 159          * If we have no capabilities, this is indicated by cap ID,
 160          * cap version and next pointer all being 0.
 161          */
 162         if (header == 0)
 163                 return 0;
 164
 165         while (ttl-- > 0) {
 166                 if (RTE_PCI_EXT_CAP_ID(header) == cap && pos != start)
 167                         return pos;
 168
 169                 pos = RTE_PCI_EXT_CAP_NEXT(header);
 170                 if (pos < RTE_PCI_CFG_SPACE_SIZE)
 171                         break;
 172                 ret = pread(fd, &header, sizeof(header), pos);
 173                 if (ret == -1)
 174                         return -1;
 175         }
 176
 177         return 0;
 178 }
 179
 180 static int
 181 ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap)
 182 {
 183         return ifpga_pci_find_next_ext_capability(fd, 0, cap);
 184 }
 185
 186 static int ifpga_get_dev_vendor_id(const char *bdf,
 187         uint32_t *dev_id, uint32_t *vendor_id)
 188 {
 189         int fd;
 190         char path[1024];
 191         int ret;
 192         uint32_t header;
 193
 194         strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
 195         strlcat(path, bdf, sizeof(path));
 196         strlcat(path, "/config", sizeof(path));
 197         fd = open(path, O_RDWR);
 198         if (fd < 0)
 199                 return -1;
 200         ret = pread(fd, &header, sizeof(header), 0);
 201         if (ret == -1) {
 202                 close(fd);
 203                 return -1;
 204         }
 205         (*vendor_id) = header & 0xffff;
 206         (*dev_id) = (header >> 16) & 0xffff;
 207         close(fd);
 208
 209         return 0;
 210 }
 211 static int ifpga_rawdev_fill_info(struct ifpga_rawdev *ifpga_dev,
 212         const char *bdf)
 213 {
 214         char path[1024] = "/sys/bus/pci/devices/0000:";
 215         char link[1024], link1[1024];
 216         char dir[1024] = "/sys/devices/";
 217         char *c;
 218         int ret;
 219         char sub_brg_bdf[4][16];
 220         int point;
 221         DIR *dp = NULL;
 222         struct dirent *entry;
 223         int i, j;
 224
 225         unsigned int dom, bus, dev;
 226         int func;
 227         uint32_t dev_id, vendor_id;
 228
 229         strlcat(path, bdf, sizeof(path));
 230         memset(link, 0, sizeof(link));
 231         memset(link1, 0, sizeof(link1));
 232         ret = readlink(path, link, (sizeof(link)-1));
 233         if (ret == -1)
 234                 return -1;
 235         strlcpy(link1, link, sizeof(link1));
 236         memset(ifpga_dev->parent_bdf, 0, 16);
 237         point = strlen(link);
 238         if (point < 39)
 239                 return -1;
 240         point -= 39;
 241         link[point] = 0;
 242         if (point < 12)
 243                 return -1;
 244         point -= 12;
 245         rte_memcpy(ifpga_dev->parent_bdf, &link[point], 12);
 246
 247         point = strlen(link1);
 248         if (point < 26)
 249                 return -1;
 250         point -= 26;
 251         link1[point] = 0;
 252         if (point < 12)
 253                 return -1;
 254         point -= 12;
 255         c = strchr(link1, 'p');
 256         if (!c)
 257                 return -1;
 258         strlcat(dir, c, sizeof(dir));
 259
 260         /* scan folder */
 261         dp = opendir(dir);
 262         if (dp == NULL)
 263                 return -1;
 264         i = 0;
 265         while ((entry = readdir(dp)) != NULL) {
 266                 if (i >= 4)
 267                         break;
 268                 if (entry->d_name[0] == '.')
 269                         continue;
 270                 if (strlen(entry->d_name) > 12)
 271                         continue;
 272                 if (sscanf(entry->d_name, "%x:%x:%x.%d",
 273                         &dom, &bus, &dev, &func) < 4)
 274                         continue;
 275                 else {
 276                         strlcpy(sub_brg_bdf[i],
 277                                 entry->d_name,
 278                                 sizeof(sub_brg_bdf[i]));
 279                         i++;
 280                 }
 281         }
 282         closedir(dp);
 283
 284         /* get fpga and fvl */
 285         j = 0;
 286         for (i = 0; i < 4; i++) {
 287                 strlcpy(link, dir, sizeof(link));
 288                 strlcat(link, "/", sizeof(link));
 289                 strlcat(link, sub_brg_bdf[i], sizeof(link));
 290                 dp = opendir(link);
 291                 if (dp == NULL)
 292                         return -1;
 293                 while ((entry = readdir(dp)) != NULL) {
 294                         if (j >= 8)
 295                                 break;
 296                         if (entry->d_name[0] == '.')
 297                                 continue;
 298
 299                         if (strlen(entry->d_name) > 12)
 300                                 continue;
 301                         if (sscanf(entry->d_name, "%x:%x:%x.%d",
 302                                 &dom, &bus, &dev, &func) < 4)
 303                                 continue;
 304                         else {
 305                                 if (ifpga_get_dev_vendor_id(entry->d_name,
 306                                         &dev_id, &vendor_id))
 307                                         continue;
 308                                 if (vendor_id == 0x8086 &&
 309                                         (dev_id == 0x0CF8 ||
 310                                         dev_id == 0x0D58 ||
 311                                         dev_id == 0x1580)) {
 312                                         strlcpy(ifpga_dev->fvl_bdf[j],
 313                                                 entry->d_name,
 314                                                 sizeof(ifpga_dev->fvl_bdf[j]));
 315                                         j++;
 316                                 }
 317                         }
 318                 }
 319                 closedir(dp);
 320         }
 321
 322         return 0;
 323 }
 324
 325 #define HIGH_FATAL(_sens, value)\
 326         (((_sens)->flags & OPAE_SENSOR_HIGH_FATAL_VALID) &&\
 327          (value > (_sens)->high_fatal))
 328
 329 #define HIGH_WARN(_sens, value)\
 330         (((_sens)->flags & OPAE_SENSOR_HIGH_WARN_VALID) &&\
 331          (value > (_sens)->high_warn))
 332
 333 #define LOW_FATAL(_sens, value)\
 334         (((_sens)->flags & OPAE_SENSOR_LOW_FATAL_VALID) &&\
 335          (value > (_sens)->low_fatal))
 336
 337 #define LOW_WARN(_sens, value)\
 338         (((_sens)->flags & OPAE_SENSOR_LOW_WARN_VALID) &&\
 339          (value > (_sens)->low_warn))
 340
 341 #define AUX_VOLTAGE_WARN 11400
 342
 343 static int
 344 ifpga_monitor_sensor(struct rte_rawdev *raw_dev,
 345                bool *gsd_start)
 346 {
 347         struct opae_adapter *adapter;
 348         struct opae_manager *mgr;
 349         struct opae_sensor_info *sensor;
 350         unsigned int value;
 351         int ret;
 352
 353         adapter = ifpga_rawdev_get_priv(raw_dev);
 354         if (!adapter)
 355                 return -ENODEV;
 356
 357         mgr = opae_adapter_get_mgr(adapter);
 358         if (!mgr)
 359                 return -ENODEV;
 360
 361         opae_mgr_for_each_sensor(mgr, sensor) {
 362                 if (!(sensor->flags & OPAE_SENSOR_VALID))
 363                         goto fail;
 364
 365                 ret = opae_mgr_get_sensor_value(mgr, sensor, &value);
 366                 if (ret)
 367                         goto fail;
 368
 369                 if (value == 0xdeadbeef) {
 370                         IFPGA_RAWDEV_PMD_ERR("dev_id %d sensor %s value %x\n",
 371                                         raw_dev->dev_id, sensor->name, value);
 372                         continue;
 373                 }
 374
 375                 /* monitor temperature sensors */
 376                 if (!strcmp(sensor->name, "Board Temperature") ||
 377                                 !strcmp(sensor->name, "FPGA Die Temperature")) {
 378                         IFPGA_RAWDEV_PMD_INFO("read sensor %s %d %d %d\n",
 379                                         sensor->name, value, sensor->high_warn,
 380                                         sensor->high_fatal);
 381
 382                         if (HIGH_WARN(sensor, value) ||
 383                                 LOW_WARN(sensor, value)) {
 384                                 IFPGA_RAWDEV_PMD_INFO("%s reach theshold %d\n",
 385                                         sensor->name, value);
 386                                 *gsd_start = true;
 387                                 break;
 388                         }
 389                 }
 390
 391                 /* monitor 12V AUX sensor */
 392                 if (!strcmp(sensor->name, "12V AUX Voltage")) {
 393                         if (value < AUX_VOLTAGE_WARN) {
 394                                 IFPGA_RAWDEV_PMD_INFO(
 395                                         "%s reach theshold %d mV\n",
 396                                         sensor->name, value);
 397                                 *gsd_start = true;
 398                                 break;
 399                         }
 400                 }
 401         }
 402
 403         return 0;
 404 fail:
 405         return -EFAULT;
 406 }
 407
 408 static int set_surprise_link_check_aer(
 409         struct ifpga_rawdev *ifpga_rdev, int force_disable)
 410 {
 411         struct rte_rawdev *rdev;
 412         int fd = -1;
 413         char path[1024];
 414         int pos;
 415         int ret;
 416         uint32_t data;
 417         bool enable = 0;
 418         uint32_t aer_new0, aer_new1;
 419
 420         if (!ifpga_rdev) {
 421                 printf("\n device does not exist\n");
 422                 return -EFAULT;
 423         }
 424
 425         rdev = ifpga_rdev->rawdev;
 426         if (ifpga_rdev->aer_enable)
 427                 return -EFAULT;
 428         if (ifpga_monitor_sensor(rdev, &enable))
 429                 return -EFAULT;
 430         if (enable || force_disable) {
 431                 IFPGA_RAWDEV_PMD_ERR("Set AER, pls graceful shutdown\n");
 432                 ifpga_rdev->aer_enable = 1;
 433                 /* get bridge fd */
 434                 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
 435                 strlcat(path, ifpga_rdev->parent_bdf, sizeof(path));
 436                 strlcat(path, "/config", sizeof(path));
 437                 fd = open(path, O_RDWR);
 438                 if (fd < 0)
 439                         goto end;
 440                 pos = ifpga_pci_find_ext_capability(fd, RTE_PCI_EXT_CAP_ID_ERR);
 441                 if (!pos)
 442                         goto end;
 443                 /* save previout ECAP_AER+0x08 */
 444                 ret = pread(fd, &data, sizeof(data), pos+0x08);
 445                 if (ret == -1)
 446                         goto end;
 447                 ifpga_rdev->aer_old[0] = data;
 448                 /* save previout ECAP_AER+0x14 */
 449                 ret = pread(fd, &data, sizeof(data), pos+0x14);
 450                 if (ret == -1)
 451                         goto end;
 452                 ifpga_rdev->aer_old[1] = data;
 453
 454                 /* set ECAP_AER+0x08 to 0xFFFFFFFF */
 455                 data = 0xffffffff;
 456                 ret = pwrite(fd, &data, 4, pos+0x08);
 457                 if (ret == -1)
 458                         goto end;
 459                 /* set ECAP_AER+0x14 to 0xFFFFFFFF */
 460                 ret = pwrite(fd, &data, 4, pos+0x14);
 461                 if (ret == -1)
 462                         goto end;
 463
 464                 /* read current ECAP_AER+0x08 */
 465                 ret = pread(fd, &data, sizeof(data), pos+0x08);
 466                 if (ret == -1)
 467                         goto end;
 468                 aer_new0 = data;
 469                 /* read current ECAP_AER+0x14 */
 470                 ret = pread(fd, &data, sizeof(data), pos+0x14);
 471                 if (ret == -1)
 472                         goto end;
 473                 aer_new1 = data;
 474
 475                 if (fd != -1)
 476                         close(fd);
 477
 478                 printf(">>>>>>Set AER %x,%x %x,%x\n",
 479                         ifpga_rdev->aer_old[0], ifpga_rdev->aer_old[1],
 480                         aer_new0, aer_new1);
 481
 482                 return 1;
 483                 }
 484
 485 end:
 486         if (fd != -1)
 487                 close(fd);
 488         return -EFAULT;
 489 }
 490
 491 static void *
 492 ifpga_rawdev_gsd_handle(__rte_unused void *param)
 493 {
 494         struct ifpga_rawdev *ifpga_rdev;
 495         int i;
 496         int gsd_enable, ret;
 497 #define MS 1000
 498
 499         while (1) {
 500                 gsd_enable = 0;
 501                 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
 502                         ifpga_rdev = &ifpga_rawdevices[i];
 503                         if (ifpga_rdev->rawdev) {
 504                                 ret = set_surprise_link_check_aer(ifpga_rdev,
 505                                         gsd_enable);
 506                                 if (ret == 1 && !gsd_enable) {
 507                                         gsd_enable = 1;
 508                                         i = -1;
 509                                 }
 510                         }
 511                 }
 512
 513                 if (gsd_enable)
 514                         printf(">>>>>>Pls Shutdown APP\n");
 515
 516                 rte_delay_us(100 * MS);
 517         }
 518
 519         return NULL;
 520 }
 521
 522 static int
 523 ifpga_monitor_start_func(void)
 524 {
 525         int ret;
 526
 527         if (ifpga_monitor_start == 0) {
 528                 ret = pthread_create(&ifpga_monitor_start_thread,
 529                         NULL,
 530                         ifpga_rawdev_gsd_handle, NULL);
 531                 if (ret) {
 532                         IFPGA_RAWDEV_PMD_ERR(
 533                                 "Fail to create ifpga nonitor thread");
 534                         return -1;
 535                 }
 536                 ifpga_monitor_start = 1;
 537         }
 538
 539         return 0;
 540 }
 541 static int
 542 ifpga_monitor_stop_func(void)
 543 {
 544         int ret;
 545
 546         if (ifpga_monitor_start == 1) {
 547                 ret = pthread_cancel(ifpga_monitor_start_thread);
 548                 if (ret)
 549                         IFPGA_RAWDEV_PMD_ERR("Can't cancel the thread");
 550
 551                 ret = pthread_join(ifpga_monitor_start_thread, NULL);
 552                 if (ret)
 553                         IFPGA_RAWDEV_PMD_ERR("Can't join the thread");
 554
 555                 ifpga_monitor_start = 0;
 556
 557                 return ret;
 558         }
 559
 560         return 0;
 561 }
 562
 563 static int
 564 ifpga_fill_afu_dev(struct opae_accelerator *acc,
 565                 struct rte_afu_device *afu_dev)
 566 {
 567         struct rte_mem_resource *res = afu_dev->mem_resource;
 568         struct opae_acc_region_info region_info;
 569         struct opae_acc_info info;
 570         unsigned long i;
 571         int ret;
 572
 573         ret = opae_acc_get_info(acc, &info);
 574         if (ret)
 575                 return ret;
 576
 577         if (info.num_regions > PCI_MAX_RESOURCE)
 578                 return -EFAULT;
 579
 580         afu_dev->num_region = info.num_regions;
 581
 582         for (i = 0; i < info.num_regions; i++) {
 583                 region_info.index = i;
 584                 ret = opae_acc_get_region_info(acc, &region_info);
 585                 if (ret)
 586                         return ret;
 587
 588                 if ((region_info.flags & ACC_REGION_MMIO) &&
 589                     (region_info.flags & ACC_REGION_READ) &&
 590                     (region_info.flags & ACC_REGION_WRITE)) {
 591                         res[i].phys_addr = region_info.phys_addr;
 592                         res[i].len = region_info.len;
 593                         res[i].addr = region_info.addr;
 594                 } else
 595                         return -EFAULT;
 596         }
 597
 598         return 0;
 599 }
 600
 601 static int
 602 ifpga_rawdev_info_get(struct rte_rawdev *dev,
 603                       rte_rawdev_obj_t dev_info,
 604                       size_t dev_info_size)
 605 {
 606         struct opae_adapter *adapter;
 607         struct opae_accelerator *acc;
 608         struct rte_afu_device *afu_dev;
 609         struct opae_manager *mgr = NULL;
 610         struct opae_eth_group_region_info opae_lside_eth_info;
 611         struct opae_eth_group_region_info opae_nside_eth_info;
 612         int lside_bar_idx, nside_bar_idx;
 613
 614         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 615
 616         if (!dev_info || dev_info_size != sizeof(*afu_dev)) {
 617                 IFPGA_RAWDEV_PMD_ERR("Invalid request");
 618                 return -EINVAL;
 619         }
 620
 621         adapter = ifpga_rawdev_get_priv(dev);
 622         if (!adapter)
 623                 return -ENOENT;
 624
 625         afu_dev = dev_info;
 626         afu_dev->rawdev = dev;
 627
 628         /* find opae_accelerator and fill info into afu_device */
 629         opae_adapter_for_each_acc(adapter, acc) {
 630                 if (acc->index != afu_dev->id.port)
 631                         continue;
 632
 633                 if (ifpga_fill_afu_dev(acc, afu_dev)) {
 634                         IFPGA_RAWDEV_PMD_ERR("cannot get info\n");
 635                         return -ENOENT;
 636                 }
 637         }
 638
 639         /* get opae_manager to rawdev */
 640         mgr = opae_adapter_get_mgr(adapter);
 641         if (mgr) {
 642                 /* get LineSide BAR Index */
 643                 if (opae_manager_get_eth_group_region_info(mgr, 0,
 644                         &opae_lside_eth_info)) {
 645                         return -ENOENT;
 646                 }
 647                 lside_bar_idx = opae_lside_eth_info.mem_idx;
 648
 649                 /* get NICSide BAR Index */
 650                 if (opae_manager_get_eth_group_region_info(mgr, 1,
 651                         &opae_nside_eth_info)) {
 652                         return -ENOENT;
 653                 }
 654                 nside_bar_idx = opae_nside_eth_info.mem_idx;
 655
 656                 if (lside_bar_idx >= PCI_MAX_RESOURCE ||
 657                         nside_bar_idx >= PCI_MAX_RESOURCE ||
 658                         lside_bar_idx == nside_bar_idx)
 659                         return -ENOENT;
 660
 661                 /* fill LineSide BAR Index */
 662                 afu_dev->mem_resource[lside_bar_idx].phys_addr =
 663                         opae_lside_eth_info.phys_addr;
 664                 afu_dev->mem_resource[lside_bar_idx].len =
 665                         opae_lside_eth_info.len;
 666                 afu_dev->mem_resource[lside_bar_idx].addr =
 667                         opae_lside_eth_info.addr;
 668
 669                 /* fill NICSide BAR Index */
 670                 afu_dev->mem_resource[nside_bar_idx].phys_addr =
 671                         opae_nside_eth_info.phys_addr;
 672                 afu_dev->mem_resource[nside_bar_idx].len =
 673                         opae_nside_eth_info.len;
 674                 afu_dev->mem_resource[nside_bar_idx].addr =
 675                         opae_nside_eth_info.addr;
 676         }
 677         return 0;
 678 }
 679
 680 static int
 681 ifpga_rawdev_configure(const struct rte_rawdev *dev,
 682                 rte_rawdev_obj_t config,
 683                 size_t config_size __rte_unused)
 684 {
 685         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 686
 687         RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
 688
 689         return config ? 0 : 1;
 690 }
 691
 692 static int
 693 ifpga_rawdev_start(struct rte_rawdev *dev)
 694 {
 695         int ret = 0;
 696         struct opae_adapter *adapter;
 697
 698         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 699
 700         RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
 701
 702         adapter = ifpga_rawdev_get_priv(dev);
 703         if (!adapter)
 704                 return -ENODEV;
 705
 706         return ret;
 707 }
 708
 709 static void
 710 ifpga_rawdev_stop(struct rte_rawdev *dev)
 711 {
 712         dev->started = 0;
 713 }
 714
 715 static int
 716 ifpga_rawdev_close(struct rte_rawdev *dev)
 717 {
 718         return dev ? 0:1;
 719 }
 720
 721 static int
 722 ifpga_rawdev_reset(struct rte_rawdev *dev)
 723 {
 724         return dev ? 0:1;
 725 }
 726
 727 static int
 728 fpga_pr(struct rte_rawdev *raw_dev, u32 port_id, const char *buffer, u32 size,
 729                         u64 *status)
 730 {
 731
 732         struct opae_adapter *adapter;
 733         struct opae_manager *mgr;
 734         struct opae_accelerator *acc;
 735         struct opae_bridge *br;
 736         int ret;
 737
 738         adapter = ifpga_rawdev_get_priv(raw_dev);
 739         if (!adapter)
 740                 return -ENODEV;
 741
 742         mgr = opae_adapter_get_mgr(adapter);
 743         if (!mgr)
 744                 return -ENODEV;
 745
 746         acc = opae_adapter_get_acc(adapter, port_id);
 747         if (!acc)
 748                 return -ENODEV;
 749
 750         br = opae_acc_get_br(acc);
 751         if (!br)
 752                 return -ENODEV;
 753
 754         ret = opae_manager_flash(mgr, port_id, buffer, size, status);
 755         if (ret) {
 756                 IFPGA_RAWDEV_PMD_ERR("%s pr error %d\n", __func__, ret);
 757                 return ret;
 758         }
 759
 760         ret = opae_bridge_reset(br);
 761         if (ret) {
 762                 IFPGA_RAWDEV_PMD_ERR("%s reset port:%d error %d\n",
 763                                 __func__, port_id, ret);
 764                 return ret;
 765         }
 766
 767         return ret;
 768 }
 769
 770 static int
 771 rte_fpga_do_pr(struct rte_rawdev *rawdev, int port_id,
 772                 const char *file_name)
 773 {
 774         struct stat file_stat;
 775         int file_fd;
 776         int ret = 0;
 777         ssize_t buffer_size;
 778         void *buffer;
 779         u64 pr_error;
 780
 781         if (!file_name)
 782                 return -EINVAL;
 783
 784         file_fd = open(file_name, O_RDONLY);
 785         if (file_fd < 0) {
 786                 IFPGA_RAWDEV_PMD_ERR("%s: open file error: %s\n",
 787                                 __func__, file_name);
 788                 IFPGA_RAWDEV_PMD_ERR("Message : %s\n", strerror(errno));
 789                 return -EINVAL;
 790         }
 791         ret = stat(file_name, &file_stat);
 792         if (ret) {
 793                 IFPGA_RAWDEV_PMD_ERR("stat on bitstream file failed: %s\n",
 794                                 file_name);
 795                 ret = -EINVAL;
 796                 goto close_fd;
 797         }
 798         buffer_size = file_stat.st_size;
 799         if (buffer_size <= 0) {
 800                 ret = -EINVAL;
 801                 goto close_fd;
 802         }
 803
 804         IFPGA_RAWDEV_PMD_INFO("bitstream file size: %zu\n", buffer_size);
 805         buffer = rte_malloc(NULL, buffer_size, 0);
 806         if (!buffer) {
 807                 ret = -ENOMEM;
 808                 goto close_fd;
 809         }
 810
 811         /*read the raw data*/
 812         if (buffer_size != read(file_fd, (void *)buffer, buffer_size)) {
 813                 ret = -EINVAL;
 814                 goto free_buffer;
 815         }
 816
 817         /*do PR now*/
 818         ret = fpga_pr(rawdev, port_id, buffer, buffer_size, &pr_error);
 819         IFPGA_RAWDEV_PMD_INFO("downloading to device port %d....%s.\n", port_id,
 820                 ret ? "failed" : "success");
 821         if (ret) {
 822                 ret = -EINVAL;
 823                 goto free_buffer;
 824         }
 825
 826 free_buffer:
 827         if (buffer)
 828                 rte_free(buffer);
 829 close_fd:
 830         close(file_fd);
 831         file_fd = 0;
 832         return ret;
 833 }
 834
 835 static int
 836 ifpga_rawdev_pr(struct rte_rawdev *dev,
 837         rte_rawdev_obj_t pr_conf)
 838 {
 839         struct opae_adapter *adapter;
 840         struct opae_manager *mgr;
 841         struct opae_board_info *info;
 842         struct rte_afu_pr_conf *afu_pr_conf;
 843         int ret;
 844         struct uuid uuid;
 845         struct opae_accelerator *acc;
 846
 847         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 848
 849         adapter = ifpga_rawdev_get_priv(dev);
 850         if (!adapter)
 851                 return -ENODEV;
 852
 853         if (!pr_conf)
 854                 return -EINVAL;
 855
 856         afu_pr_conf = pr_conf;
 857
 858         if (afu_pr_conf->pr_enable) {
 859                 ret = rte_fpga_do_pr(dev,
 860                                 afu_pr_conf->afu_id.port,
 861                                 afu_pr_conf->bs_path);
 862                 if (ret) {
 863                         IFPGA_RAWDEV_PMD_ERR("do pr error %d\n", ret);
 864                         return ret;
 865                 }
 866         }
 867
 868         mgr = opae_adapter_get_mgr(adapter);
 869         if (!mgr) {
 870                 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
 871                 return -1;
 872         }
 873
 874         if (ifpga_mgr_ops.get_board_info(mgr, &info)) {
 875                 IFPGA_RAWDEV_PMD_ERR("ifpga manager get_board_info fail!");
 876                 return -1;
 877         }
 878
 879         if (info->lightweight) {
 880                 /* set uuid to all 0, when fpga is lightweight image */
 881                 memset(&afu_pr_conf->afu_id.uuid.uuid_low, 0, sizeof(u64));
 882                 memset(&afu_pr_conf->afu_id.uuid.uuid_high, 0, sizeof(u64));
 883         } else {
 884                 acc = opae_adapter_get_acc(adapter, afu_pr_conf->afu_id.port);
 885                 if (!acc)
 886                         return -ENODEV;
 887
 888                 ret = opae_acc_get_uuid(acc, &uuid);
 889                 if (ret)
 890                         return ret;
 891
 892                 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_low, uuid.b,
 893                         sizeof(u64));
 894                 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_high, uuid.b + 8,
 895                         sizeof(u64));
 896
 897                 IFPGA_RAWDEV_PMD_INFO("%s: uuid_l=0x%lx, uuid_h=0x%lx\n",
 898                         __func__,
 899                         (unsigned long)afu_pr_conf->afu_id.uuid.uuid_low,
 900                         (unsigned long)afu_pr_conf->afu_id.uuid.uuid_high);
 901                 }
 902         return 0;
 903 }
 904
 905 static int
 906 ifpga_rawdev_get_attr(struct rte_rawdev *dev,
 907         const char *attr_name, uint64_t *attr_value)
 908 {
 909         struct opae_adapter *adapter;
 910         struct opae_manager *mgr;
 911         struct opae_retimer_info opae_rtm_info;
 912         struct opae_retimer_status opae_rtm_status;
 913         struct opae_eth_group_info opae_eth_grp_info;
 914         struct opae_eth_group_region_info opae_eth_grp_reg_info;
 915         int eth_group_num = 0;
 916         uint64_t port_link_bitmap = 0, port_link_bit;
 917         uint32_t i, j, p, q;
 918
 919 #define MAX_PORT_PER_RETIMER    4
 920
 921         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 922
 923         if (!dev || !attr_name || !attr_value) {
 924                 IFPGA_RAWDEV_PMD_ERR("Invalid arguments for getting attributes");
 925                 return -1;
 926         }
 927
 928         adapter = ifpga_rawdev_get_priv(dev);
 929         if (!adapter) {
 930                 IFPGA_RAWDEV_PMD_ERR("Adapter of dev %s is NULL", dev->name);
 931                 return -1;
 932         }
 933
 934         mgr = opae_adapter_get_mgr(adapter);
 935         if (!mgr) {
 936                 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
 937                 return -1;
 938         }
 939
 940         /* currently, eth_group_num is always 2 */
 941         eth_group_num = opae_manager_get_eth_group_nums(mgr);
 942         if (eth_group_num < 0)
 943                 return -1;
 944
 945         if (!strcmp(attr_name, "LineSideBaseMAC")) {
 946                 /* Currently FPGA not implement, so just set all zeros*/
 947                 *attr_value = (uint64_t)0;
 948                 return 0;
 949         }
 950         if (!strcmp(attr_name, "LineSideMACType")) {
 951                 /* eth_group 0 on FPGA connect to LineSide */
 952                 if (opae_manager_get_eth_group_info(mgr, 0,
 953                         &opae_eth_grp_info))
 954                         return -1;
 955                 switch (opae_eth_grp_info.speed) {
 956                 case ETH_SPEED_10G:
 957                         *attr_value =
 958                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI);
 959                         break;
 960                 case ETH_SPEED_25G:
 961                         *attr_value =
 962                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI);
 963                         break;
 964                 default:
 965                         *attr_value =
 966                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_UNKNOWN);
 967                         break;
 968                 }
 969                 return 0;
 970         }
 971         if (!strcmp(attr_name, "LineSideLinkSpeed")) {
 972                 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
 973                         return -1;
 974                 switch (opae_rtm_status.speed) {
 975                 case MXD_1GB:
 976                         *attr_value =
 977                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 978                         break;
 979                 case MXD_2_5GB:
 980                         *attr_value =
 981                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 982                         break;
 983                 case MXD_5GB:
 984                         *attr_value =
 985                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 986                         break;
 987                 case MXD_10GB:
 988                         *attr_value =
 989                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_10GB);
 990                         break;
 991                 case MXD_25GB:
 992                         *attr_value =
 993                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_25GB);
 994                         break;
 995                 case MXD_40GB:
 996                         *attr_value =
 997                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_40GB);
 998                         break;
 999                 case MXD_100GB:
1000                         *attr_value =
1001                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1002                         break;
1003                 case MXD_SPEED_UNKNOWN:
1004                         *attr_value =
1005                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1006                         break;
1007                 default:
1008                         *attr_value =
1009                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1010                         break;
1011                 }
1012                 return 0;
1013         }
1014         if (!strcmp(attr_name, "LineSideLinkRetimerNum")) {
1015                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1016                         return -1;
1017                 *attr_value = (uint64_t)(opae_rtm_info.nums_retimer);
1018                 return 0;
1019         }
1020         if (!strcmp(attr_name, "LineSideLinkPortNum")) {
1021                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1022                         return -1;
1023                 uint64_t tmp = (uint64_t)opae_rtm_info.ports_per_retimer *
1024                                         (uint64_t)opae_rtm_info.nums_retimer;
1025                 *attr_value = tmp;
1026                 return 0;
1027         }
1028         if (!strcmp(attr_name, "LineSideLinkStatus")) {
1029                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1030                         return -1;
1031                 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
1032                         return -1;
1033                 (*attr_value) = 0;
1034                 q = 0;
1035                 port_link_bitmap = (uint64_t)(opae_rtm_status.line_link_bitmap);
1036                 for (i = 0; i < opae_rtm_info.nums_retimer; i++) {
1037                         p = i * MAX_PORT_PER_RETIMER;
1038                         for (j = 0; j < opae_rtm_info.ports_per_retimer; j++) {
1039                                 port_link_bit = 0;
1040                                 IFPGA_BIT_SET(port_link_bit, (p+j));
1041                                 port_link_bit &= port_link_bitmap;
1042                                 if (port_link_bit)
1043                                         IFPGA_BIT_SET((*attr_value), q);
1044                                 q++;
1045                         }
1046                 }
1047                 return 0;
1048         }
1049         if (!strcmp(attr_name, "LineSideBARIndex")) {
1050                 /* eth_group 0 on FPGA connect to LineSide */
1051                 if (opae_manager_get_eth_group_region_info(mgr, 0,
1052                         &opae_eth_grp_reg_info))
1053                         return -1;
1054                 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1055                 return 0;
1056         }
1057         if (!strcmp(attr_name, "NICSideMACType")) {
1058                 /* eth_group 1 on FPGA connect to NicSide */
1059                 if (opae_manager_get_eth_group_info(mgr, 1,
1060                         &opae_eth_grp_info))
1061                         return -1;
1062                 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1063                 return 0;
1064         }
1065         if (!strcmp(attr_name, "NICSideLinkSpeed")) {
1066                 /* eth_group 1 on FPGA connect to NicSide */
1067                 if (opae_manager_get_eth_group_info(mgr, 1,
1068                         &opae_eth_grp_info))
1069                         return -1;
1070                 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1071                 return 0;
1072         }
1073         if (!strcmp(attr_name, "NICSideLinkPortNum")) {
1074                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1075                         return -1;
1076                 uint64_t tmp = (uint64_t)opae_rtm_info.nums_fvl *
1077                                         (uint64_t)opae_rtm_info.ports_per_fvl;
1078                 *attr_value = tmp;
1079                 return 0;
1080         }
1081         if (!strcmp(attr_name, "NICSideLinkStatus"))
1082                 return 0;
1083         if (!strcmp(attr_name, "NICSideBARIndex")) {
1084                 /* eth_group 1 on FPGA connect to NicSide */
1085                 if (opae_manager_get_eth_group_region_info(mgr, 1,
1086                         &opae_eth_grp_reg_info))
1087                         return -1;
1088                 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1089                 return 0;
1090         }
1091
1092         IFPGA_RAWDEV_PMD_ERR("%s not support", attr_name);
1093         return -1;
1094 }
1095
1096 static const struct rte_rawdev_ops ifpga_rawdev_ops = {
1097         .dev_info_get = ifpga_rawdev_info_get,
1098         .dev_configure = ifpga_rawdev_configure,
1099         .dev_start = ifpga_rawdev_start,
1100         .dev_stop = ifpga_rawdev_stop,
1101         .dev_close = ifpga_rawdev_close,
1102         .dev_reset = ifpga_rawdev_reset,
1103
1104         .queue_def_conf = NULL,
1105         .queue_setup = NULL,
1106         .queue_release = NULL,
1107
1108         .attr_get = ifpga_rawdev_get_attr,
1109         .attr_set = NULL,
1110
1111         .enqueue_bufs = NULL,
1112         .dequeue_bufs = NULL,
1113
1114         .dump = NULL,
1115
1116         .xstats_get = NULL,
1117         .xstats_get_names = NULL,
1118         .xstats_get_by_name = NULL,
1119         .xstats_reset = NULL,
1120
1121         .firmware_status_get = NULL,
1122         .firmware_version_get = NULL,
1123         .firmware_load = ifpga_rawdev_pr,
1124         .firmware_unload = NULL,
1125
1126         .dev_selftest = NULL,
1127 };
1128
1129 static int
1130 ifpga_get_fme_error_prop(struct opae_manager *mgr,
1131                 u64 prop_id, u64 *val)
1132 {
1133         struct feature_prop prop;
1134
1135         prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1136         prop.prop_id = prop_id;
1137
1138         if (opae_manager_ifpga_get_prop(mgr, &prop))
1139                 return -EINVAL;
1140
1141         *val = prop.data;
1142
1143         return 0;
1144 }
1145
1146 static int
1147 ifpga_set_fme_error_prop(struct opae_manager *mgr,
1148                 u64 prop_id, u64 val)
1149 {
1150         struct feature_prop prop;
1151
1152         prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1153         prop.prop_id = prop_id;
1154
1155         prop.data = val;
1156
1157         if (opae_manager_ifpga_set_prop(mgr, &prop))
1158                 return -EINVAL;
1159
1160         return 0;
1161 }
1162
1163 static int
1164 fme_err_read_seu_emr(struct opae_manager *mgr)
1165 {
1166         u64 val;
1167         int ret;
1168
1169         ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_LOW, &val);
1170         if (ret)
1171                 return -EINVAL;
1172
1173         IFPGA_RAWDEV_PMD_INFO("seu emr low: 0x%" PRIx64 "\n", val);
1174
1175         ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_HIGH, &val);
1176         if (ret)
1177                 return -EINVAL;
1178
1179         IFPGA_RAWDEV_PMD_INFO("seu emr high: 0x%" PRIx64 "\n", val);
1180
1181         return 0;
1182 }
1183
1184 static int fme_clear_warning_intr(struct opae_manager *mgr)
1185 {
1186         u64 val;
1187
1188         if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_INJECT_ERRORS, 0))
1189                 return -EINVAL;
1190
1191         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1192                 return -EINVAL;
1193         if ((val & 0x40) != 0)
1194                 IFPGA_RAWDEV_PMD_INFO("clean not done\n");
1195
1196         return 0;
1197 }
1198
1199 static int fme_clean_fme_error(struct opae_manager *mgr)
1200 {
1201         u64 val;
1202
1203         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1204                 return -EINVAL;
1205
1206         IFPGA_RAWDEV_PMD_DEBUG("before clean 0x%" PRIx64 "\n", val);
1207
1208         ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_CLEAR, val);
1209
1210         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1211                 return -EINVAL;
1212
1213         IFPGA_RAWDEV_PMD_DEBUG("after clean 0x%" PRIx64 "\n", val);
1214
1215         return 0;
1216 }
1217
1218 static int
1219 fme_err_handle_error0(struct opae_manager *mgr)
1220 {
1221         struct feature_fme_error0 fme_error0;
1222         u64 val;
1223
1224         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1225                 return -EINVAL;
1226
1227         if (fme_clean_fme_error(mgr))
1228                 return -EINVAL;
1229
1230         fme_error0.csr = val;
1231
1232         if (fme_error0.fabric_err)
1233                 IFPGA_RAWDEV_PMD_ERR("Fabric error\n");
1234         else if (fme_error0.fabfifo_overflow)
1235                 IFPGA_RAWDEV_PMD_ERR("Fabric fifo under/overflow error\n");
1236         else if (fme_error0.afu_acc_mode_err)
1237                 IFPGA_RAWDEV_PMD_ERR("AFU PF/VF access mismatch detected\n");
1238         else if (fme_error0.pcie0cdc_parity_err)
1239                 IFPGA_RAWDEV_PMD_ERR("PCIe0 CDC Parity Error\n");
1240         else if (fme_error0.cvlcdc_parity_err)
1241                 IFPGA_RAWDEV_PMD_ERR("CVL CDC Parity Error\n");
1242         else if (fme_error0.fpgaseuerr)
1243                 fme_err_read_seu_emr(mgr);
1244
1245         /* clean the errors */
1246         if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, val))
1247                 return -EINVAL;
1248
1249         return 0;
1250 }
1251
1252 static int
1253 fme_err_handle_catfatal_error(struct opae_manager *mgr)
1254 {
1255         struct feature_fme_ras_catfaterror fme_catfatal;
1256         u64 val;
1257
1258         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_CATFATAL_ERRORS, &val))
1259                 return -EINVAL;
1260
1261         fme_catfatal.csr = val;
1262
1263         if (fme_catfatal.cci_fatal_err)
1264                 IFPGA_RAWDEV_PMD_ERR("CCI error detected\n");
1265         else if (fme_catfatal.fabric_fatal_err)
1266                 IFPGA_RAWDEV_PMD_ERR("Fabric fatal error detected\n");
1267         else if (fme_catfatal.pcie_poison_err)
1268                 IFPGA_RAWDEV_PMD_ERR("Poison error from PCIe ports\n");
1269         else if (fme_catfatal.inject_fata_err)
1270                 IFPGA_RAWDEV_PMD_ERR("Injected Fatal Error\n");
1271         else if (fme_catfatal.crc_catast_err)
1272                 IFPGA_RAWDEV_PMD_ERR("a catastrophic EDCRC error\n");
1273         else if (fme_catfatal.injected_catast_err)
1274                 IFPGA_RAWDEV_PMD_ERR("Injected Catastrophic Error\n");
1275         else if (fme_catfatal.bmc_seu_catast_err)
1276                 fme_err_read_seu_emr(mgr);
1277
1278         return 0;
1279 }
1280
1281 static int
1282 fme_err_handle_nonfaterror(struct opae_manager *mgr)
1283 {
1284         struct feature_fme_ras_nonfaterror nonfaterr;
1285         u64 val;
1286
1287         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1288                 return -EINVAL;
1289
1290         nonfaterr.csr = val;
1291
1292         if (nonfaterr.temp_thresh_ap1)
1293                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP1\n");
1294         else if (nonfaterr.temp_thresh_ap2)
1295                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP2\n");
1296         else if (nonfaterr.pcie_error)
1297                 IFPGA_RAWDEV_PMD_INFO("an error has occurred in pcie\n");
1298         else if (nonfaterr.portfatal_error)
1299                 IFPGA_RAWDEV_PMD_INFO("fatal error occurred in AFU port.\n");
1300         else if (nonfaterr.proc_hot)
1301                 IFPGA_RAWDEV_PMD_INFO("a ProcHot event\n");
1302         else if (nonfaterr.afu_acc_mode_err)
1303                 IFPGA_RAWDEV_PMD_INFO("an AFU PF/VF access mismatch\n");
1304         else if (nonfaterr.injected_nonfata_err) {
1305                 IFPGA_RAWDEV_PMD_INFO("Injected Warning Error\n");
1306                 fme_clear_warning_intr(mgr);
1307         } else if (nonfaterr.temp_thresh_AP6)
1308                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP6\n");
1309         else if (nonfaterr.power_thresh_AP1)
1310                 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP1\n");
1311         else if (nonfaterr.power_thresh_AP2)
1312                 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP2\n");
1313         else if (nonfaterr.mbp_err)
1314                 IFPGA_RAWDEV_PMD_INFO("an MBP event\n");
1315
1316         return 0;
1317 }
1318
1319 static void
1320 fme_interrupt_handler(void *param)
1321 {
1322         struct opae_manager *mgr = (struct opae_manager *)param;
1323
1324         IFPGA_RAWDEV_PMD_INFO("%s interrupt occurred\n", __func__);
1325
1326         fme_err_handle_error0(mgr);
1327         fme_err_handle_nonfaterror(mgr);
1328         fme_err_handle_catfatal_error(mgr);
1329 }
1330
1331 int
1332 ifpga_unregister_msix_irq(enum ifpga_irq_type type,
1333                 int vec_start, rte_intr_callback_fn handler, void *arg)
1334 {
1335         struct rte_intr_handle *intr_handle;
1336
1337         if (type == IFPGA_FME_IRQ)
1338                 intr_handle = &ifpga_irq_handle[0];
1339         else if (type == IFPGA_AFU_IRQ)
1340                 intr_handle = &ifpga_irq_handle[vec_start + 1];
1341         else
1342                 return 0;
1343
1344         rte_intr_efd_disable(intr_handle);
1345
1346         return rte_intr_callback_unregister(intr_handle, handler, arg);
1347 }
1348
1349 int
1350 ifpga_register_msix_irq(struct rte_rawdev *dev, int port_id,
1351                 enum ifpga_irq_type type, int vec_start, int count,
1352                 rte_intr_callback_fn handler, const char *name,
1353                 void *arg)
1354 {
1355         int ret;
1356         struct rte_intr_handle *intr_handle;
1357         struct opae_adapter *adapter;
1358         struct opae_manager *mgr;
1359         struct opae_accelerator *acc;
1360
1361         adapter = ifpga_rawdev_get_priv(dev);
1362         if (!adapter)
1363                 return -ENODEV;
1364
1365         mgr = opae_adapter_get_mgr(adapter);
1366         if (!mgr)
1367                 return -ENODEV;
1368
1369         if (type == IFPGA_FME_IRQ) {
1370                 intr_handle = &ifpga_irq_handle[0];
1371                 count = 1;
1372         } else if (type == IFPGA_AFU_IRQ) {
1373                 intr_handle = &ifpga_irq_handle[vec_start + 1];
1374         } else {
1375                 return -EINVAL;
1376         }
1377
1378         intr_handle->type = RTE_INTR_HANDLE_VFIO_MSIX;
1379
1380         ret = rte_intr_efd_enable(intr_handle, count);
1381         if (ret)
1382                 return -ENODEV;
1383
1384         intr_handle->fd = intr_handle->efds[0];
1385
1386         IFPGA_RAWDEV_PMD_DEBUG("register %s irq, vfio_fd=%d, fd=%d\n",
1387                         name, intr_handle->vfio_dev_fd,
1388                         intr_handle->fd);
1389
1390         if (type == IFPGA_FME_IRQ) {
1391                 struct fpga_fme_err_irq_set err_irq_set;
1392                 err_irq_set.evtfd = intr_handle->efds[0];
1393
1394                 ret = opae_manager_ifpga_set_err_irq(mgr, &err_irq_set);
1395                 if (ret)
1396                         return -EINVAL;
1397         } else if (type == IFPGA_AFU_IRQ) {
1398                 acc = opae_adapter_get_acc(adapter, port_id);
1399                 if (!acc)
1400                         return -EINVAL;
1401
1402                 ret = opae_acc_set_irq(acc, vec_start, count,
1403                                 intr_handle->efds);
1404                 if (ret)
1405                         return -EINVAL;
1406         }
1407
1408         /* register interrupt handler using DPDK API */
1409         ret = rte_intr_callback_register(intr_handle,
1410                         handler, (void *)arg);
1411         if (ret)
1412                 return -EINVAL;
1413
1414         IFPGA_RAWDEV_PMD_INFO("success register %s interrupt\n", name);
1415
1416         return 0;
1417 }
1418
1419 static int
1420 ifpga_rawdev_create(struct rte_pci_device *pci_dev,
1421                         int socket_id)
1422 {
1423         int ret = 0;
1424         struct rte_rawdev *rawdev = NULL;
1425         struct ifpga_rawdev *dev = NULL;
1426         struct opae_adapter *adapter = NULL;
1427         struct opae_manager *mgr = NULL;
1428         struct opae_adapter_data_pci *data = NULL;
1429         char name[RTE_RAWDEV_NAME_MAX_LEN];
1430         int i;
1431
1432         if (!pci_dev) {
1433                 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1434                 ret = -EINVAL;
1435                 goto cleanup;
1436         }
1437
1438         memset(name, 0, sizeof(name));
1439         snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%02x:%02x.%x",
1440                 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1441
1442         IFPGA_RAWDEV_PMD_INFO("Init %s on NUMA node %d", name, rte_socket_id());
1443
1444         /* Allocate device structure */
1445         rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct opae_adapter),
1446                                          socket_id);
1447         if (rawdev == NULL) {
1448                 IFPGA_RAWDEV_PMD_ERR("Unable to allocate rawdevice");
1449                 ret = -EINVAL;
1450                 goto cleanup;
1451         }
1452
1453         ipn3ke_bridge_func.get_ifpga_rawdev = ifpga_rawdev_get;
1454         ipn3ke_bridge_func.set_i40e_sw_dev = rte_pmd_i40e_set_switch_dev;
1455
1456         dev = ifpga_rawdev_allocate(rawdev);
1457         if (dev == NULL) {
1458                 IFPGA_RAWDEV_PMD_ERR("Unable to allocate ifpga_rawdevice");
1459                 ret = -EINVAL;
1460                 goto cleanup;
1461         }
1462         dev->aer_enable = 0;
1463
1464         /* alloc OPAE_FPGA_PCI data to register to OPAE hardware level API */
1465         data = opae_adapter_data_alloc(OPAE_FPGA_PCI);
1466         if (!data) {
1467                 ret = -ENOMEM;
1468                 goto cleanup;
1469         }
1470
1471         /* init opae_adapter_data_pci for device specific information */
1472         for (i = 0; i < PCI_MAX_RESOURCE; i++) {
1473                 data->region[i].phys_addr = pci_dev->mem_resource[i].phys_addr;
1474                 data->region[i].len = pci_dev->mem_resource[i].len;
1475                 data->region[i].addr = pci_dev->mem_resource[i].addr;
1476         }
1477         data->device_id = pci_dev->id.device_id;
1478         data->vendor_id = pci_dev->id.vendor_id;
1479         data->bus = pci_dev->addr.bus;
1480         data->devid = pci_dev->addr.devid;
1481         data->function = pci_dev->addr.function;
1482         data->vfio_dev_fd = pci_dev->intr_handle.vfio_dev_fd;
1483
1484         adapter = rawdev->dev_private;
1485         /* create a opae_adapter based on above device data */
1486         ret = opae_adapter_init(adapter, pci_dev->device.name, data);
1487         if (ret) {
1488                 ret = -ENOMEM;
1489                 goto free_adapter_data;
1490         }
1491
1492         rawdev->dev_ops = &ifpga_rawdev_ops;
1493         rawdev->device = &pci_dev->device;
1494         rawdev->driver_name = pci_dev->driver->driver.name;
1495
1496         /* must enumerate the adapter before use it */
1497         ret = opae_adapter_enumerate(adapter);
1498         if (ret)
1499                 goto free_adapter_data;
1500
1501         /* get opae_manager to rawdev */
1502         mgr = opae_adapter_get_mgr(adapter);
1503         if (mgr) {
1504                 /* PF function */
1505                 IFPGA_RAWDEV_PMD_INFO("this is a PF function");
1506         }
1507
1508         ret = ifpga_register_msix_irq(rawdev, 0, IFPGA_FME_IRQ, 0, 0,
1509                         fme_interrupt_handler, "fme_irq", mgr);
1510         if (ret)
1511                 goto free_adapter_data;
1512
1513         return ret;
1514
1515 free_adapter_data:
1516         if (data)
1517                 opae_adapter_data_free(data);
1518 cleanup:
1519         if (rawdev)
1520                 rte_rawdev_pmd_release(rawdev);
1521
1522         return ret;
1523 }
1524
1525 static int
1526 ifpga_rawdev_destroy(struct rte_pci_device *pci_dev)
1527 {
1528         int ret;
1529         struct rte_rawdev *rawdev;
1530         char name[RTE_RAWDEV_NAME_MAX_LEN];
1531         struct opae_adapter *adapter;
1532         struct opae_manager *mgr;
1533
1534         if (!pci_dev) {
1535                 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1536                 ret = -EINVAL;
1537                 return ret;
1538         }
1539
1540         memset(name, 0, sizeof(name));
1541         snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%x:%02x.%x",
1542                 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1543
1544         IFPGA_RAWDEV_PMD_INFO("Closing %s on NUMA node %d",
1545                 name, rte_socket_id());
1546
1547         rawdev = rte_rawdev_pmd_get_named_dev(name);
1548         if (!rawdev) {
1549                 IFPGA_RAWDEV_PMD_ERR("Invalid device name (%s)", name);
1550                 return -EINVAL;
1551         }
1552
1553         adapter = ifpga_rawdev_get_priv(rawdev);
1554         if (!adapter)
1555                 return -ENODEV;
1556
1557         mgr = opae_adapter_get_mgr(adapter);
1558         if (!mgr)
1559                 return -ENODEV;
1560
1561         if (ifpga_unregister_msix_irq(IFPGA_FME_IRQ, 0,
1562                                 fme_interrupt_handler, mgr) < 0)
1563                 return -EINVAL;
1564
1565         opae_adapter_data_free(adapter->data);
1566         opae_adapter_free(adapter);
1567
1568         /* rte_rawdev_close is called by pmd_release */
1569         ret = rte_rawdev_pmd_release(rawdev);
1570         if (ret)
1571                 IFPGA_RAWDEV_PMD_DEBUG("Device cleanup failed");
1572
1573         return ret;
1574 }
1575
1576 static int
1577 ifpga_rawdev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1578         struct rte_pci_device *pci_dev)
1579 {
1580         IFPGA_RAWDEV_PMD_FUNC_TRACE();
1581         return ifpga_rawdev_create(pci_dev, rte_socket_id());
1582 }
1583
1584 static int
1585 ifpga_rawdev_pci_remove(struct rte_pci_device *pci_dev)
1586 {
1587         ifpga_monitor_stop_func();
1588         return ifpga_rawdev_destroy(pci_dev);
1589 }
1590
1591 static struct rte_pci_driver rte_ifpga_rawdev_pmd = {
1592         .id_table  = pci_ifpga_map,
1593         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1594         .probe     = ifpga_rawdev_pci_probe,
1595         .remove    = ifpga_rawdev_pci_remove,
1596 };
1597
1598 RTE_PMD_REGISTER_PCI(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1599 RTE_PMD_REGISTER_PCI_TABLE(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1600 RTE_PMD_REGISTER_KMOD_DEP(ifpga_rawdev_pci_driver, "* igb_uio | uio_pci_generic | vfio-pci");
1601 RTE_LOG_REGISTER(ifpga_rawdev_logtype, driver.raw.init, NOTICE);
1602
1603 static const char * const valid_args[] = {
1604 #define IFPGA_ARG_NAME         "ifpga"
1605         IFPGA_ARG_NAME,
1606 #define IFPGA_ARG_PORT         "port"
1607         IFPGA_ARG_PORT,
1608 #define IFPGA_AFU_BTS          "afu_bts"
1609         IFPGA_AFU_BTS,
1610         NULL
1611 };
1612
1613 static int ifpga_rawdev_get_string_arg(const char *key __rte_unused,
1614         const char *value, void *extra_args)
1615 {
1616         int size;
1617         if (!value || !extra_args)
1618                 return -EINVAL;
1619
1620         size = strlen(value) + 1;
1621         *(char **)extra_args = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
1622         if (!*(char **)extra_args)
1623                 return -ENOMEM;
1624
1625         strlcpy(*(char **)extra_args, value, size);
1626
1627         return 0;
1628 }
1629 static int
1630 ifpga_cfg_probe(struct rte_vdev_device *dev)
1631 {
1632         struct rte_devargs *devargs;
1633         struct rte_kvargs *kvlist = NULL;
1634         struct rte_rawdev *rawdev = NULL;
1635         struct ifpga_rawdev *ifpga_dev;
1636         int port;
1637         char *name = NULL;
1638         const char *bdf;
1639         char dev_name[RTE_RAWDEV_NAME_MAX_LEN];
1640         int ret = -1;
1641
1642         devargs = dev->device.devargs;
1643
1644         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1645         if (!kvlist) {
1646                 IFPGA_RAWDEV_PMD_LOG(ERR, "error when parsing param");
1647                 goto end;
1648         }
1649
1650         if (rte_kvargs_count(kvlist, IFPGA_ARG_NAME) == 1) {
1651                 if (rte_kvargs_process(kvlist, IFPGA_ARG_NAME,
1652                                        &ifpga_rawdev_get_string_arg,
1653                                        &name) < 0) {
1654                         IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1655                                      IFPGA_ARG_NAME);
1656                         goto end;
1657                 }
1658         } else {
1659                 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1660                           IFPGA_ARG_NAME);
1661                 goto end;
1662         }
1663
1664         if (rte_kvargs_count(kvlist, IFPGA_ARG_PORT) == 1) {
1665                 if (rte_kvargs_process(kvlist,
1666                         IFPGA_ARG_PORT,
1667                         &rte_ifpga_get_integer32_arg,
1668                         &port) < 0) {
1669                         IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1670                                 IFPGA_ARG_PORT);
1671                         goto end;
1672                 }
1673         } else {
1674                 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1675                           IFPGA_ARG_PORT);
1676                 goto end;
1677         }
1678
1679         memset(dev_name, 0, sizeof(dev_name));
1680         snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%s", name);
1681         rawdev = rte_rawdev_pmd_get_named_dev(dev_name);
1682         if (!rawdev)
1683                 goto end;
1684         ifpga_dev = ifpga_rawdev_get(rawdev);
1685         if (!ifpga_dev)
1686                 goto end;
1687         bdf = name;
1688         ifpga_rawdev_fill_info(ifpga_dev, bdf);
1689
1690         ifpga_monitor_start_func();
1691
1692         memset(dev_name, 0, sizeof(dev_name));
1693         snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "%d|%s",
1694         port, name);
1695
1696         ret = rte_eal_hotplug_add(RTE_STR(IFPGA_BUS_NAME),
1697                         dev_name, devargs->args);
1698 end:
1699         if (kvlist)
1700                 rte_kvargs_free(kvlist);
1701         if (name)
1702                 free(name);
1703
1704         return ret;
1705 }
1706
1707 static int
1708 ifpga_cfg_remove(struct rte_vdev_device *vdev)
1709 {
1710         IFPGA_RAWDEV_PMD_INFO("Remove ifpga_cfg %p",
1711                 vdev);
1712
1713         return 0;
1714 }
1715
1716 static struct rte_vdev_driver ifpga_cfg_driver = {
1717         .probe = ifpga_cfg_probe,
1718         .remove = ifpga_cfg_remove,
1719 };
1720
1721 RTE_PMD_REGISTER_VDEV(ifpga_rawdev_cfg, ifpga_cfg_driver);
1722 RTE_PMD_REGISTER_ALIAS(ifpga_rawdev_cfg, ifpga_cfg);
1723 RTE_PMD_REGISTER_PARAM_STRING(ifpga_rawdev_cfg,
1724         "ifpga=<string> "
1725         "port=<int> "
1726         "afu_bts=<path>");