drivers/raw/ifpga_rawdev/base/ifpga_defines.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2018 Intel Corporation
   3  */
   4
   5 #ifndef _IFPGA_DEFINES_H_
   6 #define _IFPGA_DEFINES_H_
   7
   8 #include "ifpga_compat.h"
   9
  10 #define MAX_FPGA_PORT_NUM  4
  11
  12 #define FME_FEATURE_HEADER          "fme_hdr"
  13 #define FME_FEATURE_THERMAL_MGMT    "fme_thermal"
  14 #define FME_FEATURE_POWER_MGMT      "fme_power"
  15 #define FME_FEATURE_GLOBAL_IPERF    "fme_iperf"
  16 #define FME_FEATURE_GLOBAL_ERR      "fme_error"
  17 #define FME_FEATURE_PR_MGMT         "fme_pr"
  18 #define FME_FEATURE_EMIF_MGMT       "fme_emif"
  19 #define FME_FEATURE_HSSI_ETH        "fme_hssi"
  20 #define FME_FEATURE_GLOBAL_DPERF    "fme_dperf"
  21 #define FME_FEATURE_QSPI_FLASH      "fme_qspi_flash"
  22
  23 #define PORT_FEATURE_HEADER         "port_hdr"
  24 #define PORT_FEATURE_UAFU           "port_uafu"
  25 #define PORT_FEATURE_ERR            "port_err"
  26 #define PORT_FEATURE_UMSG           "port_umsg"
  27 #define PORT_FEATURE_PR             "port_pr"
  28 #define PORT_FEATURE_UINT           "port_uint"
  29 #define PORT_FEATURE_STP            "port_stp"
  30
  31 /*
  32  * do not check the revision id as id may be dynamic under
  33  * some cases, e.g, UAFU.
  34  */
  35 #define SKIP_REVISION_CHECK             0xff
  36
  37 #define FME_HEADER_REVISION             1
  38 #define FME_THERMAL_MGMT_REVISION       0
  39 #define FME_POWER_MGMT_REVISION         1
  40 #define FME_GLOBAL_IPERF_REVISION       1
  41 #define FME_GLOBAL_ERR_REVISION         1
  42 #define FME_PR_MGMT_REVISION            2
  43 #define FME_HSSI_ETH_REVISION           0
  44 #define FME_GLOBAL_DPERF_REVISION       0
  45 #define FME_QSPI_REVISION               0
  46
  47 #define PORT_HEADER_REVISION            0
  48 /* UAFU's header info depends on the downloaded GBS */
  49 #define PORT_UAFU_REVISION              SKIP_REVISION_CHECK
  50 #define PORT_ERR_REVISION               1
  51 #define PORT_UMSG_REVISION              0
  52 #define PORT_UINT_REVISION              0
  53 #define PORT_STP_REVISION               1
  54
  55 #define FEATURE_TYPE_AFU        0x1
  56 #define FEATURE_TYPE_BBB        0x2
  57 #define FEATURE_TYPE_PRIVATE    0x3
  58 #define FEATURE_TYPE_FIU        0x4
  59
  60 #define FEATURE_FIU_ID_FME      0x0
  61 #define FEATURE_FIU_ID_PORT     0x1
  62
  63 /* Reserved 0xfe for Header, 0xff for AFU*/
  64 #define FEATURE_ID_FIU_HEADER   0xfe
  65 #define FEATURE_ID_AFU          0xff
  66
  67 enum fpga_id_type {
  68         FME_ID,
  69         PORT_ID,
  70         FPGA_ID_MAX,
  71 };
  72
  73 #define FME_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
  74 #define FME_FEATURE_ID_THERMAL_MGMT 0x1
  75 #define FME_FEATURE_ID_POWER_MGMT 0x2
  76 #define FME_FEATURE_ID_GLOBAL_IPERF 0x3
  77 #define FME_FEATURE_ID_GLOBAL_ERR 0x4
  78 #define FME_FEATURE_ID_PR_MGMT 0x5
  79 #define FME_FEATURE_ID_HSSI_ETH 0x6
  80 #define FME_FEATURE_ID_GLOBAL_DPERF 0x7
  81 #define FME_FEATURE_ID_QSPI_FLASH 0x8
  82 #define FME_FEATURE_ID_EMIF_MGMT  0x9
  83
  84 #define PORT_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
  85 #define PORT_FEATURE_ID_ERROR 0x10
  86 #define PORT_FEATURE_ID_UMSG 0x12
  87 #define PORT_FEATURE_ID_UINT 0x13
  88 #define PORT_FEATURE_ID_STP 0x14
  89 #define PORT_FEATURE_ID_UAFU FEATURE_ID_AFU
  90
  91 /*
  92  * All headers and structures must be byte-packed to match the spec.
  93  */
  94 #pragma pack(push, 1)
  95
  96 struct feature_header {
  97         union {
  98                 u64 csr;
  99                 struct {
 100                         u16 id:12;
 101                         u8  revision:4;
 102                         u32 next_header_offset:24;
 103                         u8  end_of_list:1;
 104                         u32 reserved:19;
 105                         u8  type:4;
 106                 };
 107         };
 108 };
 109
 110 struct feature_bbb_header {
 111         struct uuid guid;
 112 };
 113
 114 struct feature_afu_header {
 115         struct uuid guid;
 116         union {
 117                 u64 csr;
 118                 struct {
 119                         u64 next_afu:24;
 120                         u64 reserved:40;
 121                 };
 122         };
 123 };
 124
 125 struct feature_fiu_header {
 126         struct uuid guid;
 127         union {
 128                 u64 csr;
 129                 struct {
 130                         u64 next_afu:24;
 131                         u64 reserved:40;
 132                 };
 133         };
 134 };
 135
 136 struct feature_fme_capability {
 137         union {
 138                 u64 csr;
 139                 struct {
 140                         u8  fabric_verid;       /* Fabric version ID */
 141                         u8  socket_id:1;        /* Socket id */
 142                         u8  rsvd1:3;            /* Reserved */
 143                         /* pci0 link available yes /no */
 144                         u8  pci0_link_avile:1;
 145                         /* pci1 link available yes /no */
 146                         u8  pci1_link_avile:1;
 147                         /* Coherent (QPI/UPI) link available yes /no */
 148                         u8  qpi_link_avile:1;
 149                         u8  rsvd2:1;            /* Reserved */
 150                         /* IOMMU or VT-d supported  yes/no */
 151                         u8  iommu_support:1;
 152                         u8  num_ports:3;        /* Number of ports */
 153                         u8  sf_fab_ctl:1;       /* Internal validation bit */
 154                         u8  rsvd3:3;            /* Reserved */
 155                         /*
 156                          * Address width supported in bits
 157                          * BXT -0x26 , SKX -0x30
 158                          */
 159                         u8  address_width_bits:6;
 160                         u8  rsvd4:2;            /* Reserved */
 161                         /* Size of cache supported in kb */
 162                         u16 cache_size:12;
 163                         u8  cache_assoc:4;      /* Cache Associativity */
 164                         u16 rsvd5:15;           /* Reserved */
 165                         u8  lock_bit:1;         /* Lock bit */
 166                 };
 167         };
 168 };
 169
 170 #define FME_AFU_ACCESS_PF               0
 171 #define FME_AFU_ACCESS_VF               1
 172
 173 struct feature_fme_port {
 174         union {
 175                 u64 csr;
 176                 struct {
 177                         u32 port_offset:24;
 178                         u8  reserved1;
 179                         u8  port_bar:3;
 180                         u32 reserved2:20;
 181                         u8  afu_access_control:1;
 182                         u8  reserved3:4;
 183                         u8  port_implemented:1;
 184                         u8  reserved4:3;
 185                 };
 186         };
 187 };
 188
 189 struct feature_fme_fab_status {
 190         union {
 191                 u64 csr;
 192                 struct {
 193                         u8  upilink_status:4;   /* UPI Link Status */
 194                         u8  rsvd1:4;            /* Reserved */
 195                         u8  pci0link_status:1;  /* pci0 link status */
 196                         u8  rsvd2:3;            /* Reserved */
 197                         u8  pci1link_status:1;  /* pci1 link status */
 198                         u64 rsvd3:51;           /* Reserved */
 199                 };
 200         };
 201 };
 202
 203 struct feature_fme_genprotrange2_base {
 204         union {
 205                 u64 csr;
 206                 struct {
 207                         u16 rsvd1;           /* Reserved */
 208                         /* Base Address of memory range */
 209                         u8  protected_base_addrss:4;
 210                         u64 rsvd2:44;           /* Reserved */
 211                 };
 212         };
 213 };
 214
 215 struct feature_fme_genprotrange2_limit {
 216         union {
 217                 u64 csr;
 218                 struct {
 219                         u16 rsvd1;           /* Reserved */
 220                         /* Limit Address of memory range */
 221                         u8  protected_limit_addrss:4;
 222                         u16 rsvd2:11;           /* Reserved */
 223                         u8  enable:1;        /* Enable GENPROTRANGE check */
 224                         u32 rsvd3;           /* Reserved */
 225                 };
 226         };
 227 };
 228
 229 struct feature_fme_dxe_lock {
 230         union {
 231                 u64 csr;
 232                 struct {
 233                         /*
 234                          * Determines write access to the DXE region CSRs
 235                          * 1 - CSR region is locked;
 236                          * 0 - it is open for write access.
 237                          */
 238                         u8  dxe_early_lock:1;
 239                         /*
 240                          * Determines write access to the HSSI CSR
 241                          * 1 - CSR region is locked;
 242                          * 0 - it is open for write access.
 243                          */
 244                         u8  dxe_late_lock:1;
 245                         u64 rsvd:62;
 246                 };
 247         };
 248 };
 249
 250 #define HSSI_ID_NO_HASSI        0
 251 #define HSSI_ID_PCIE_RP         1
 252 #define HSSI_ID_ETHERNET        2
 253
 254 struct feature_fme_bitstream_id {
 255         union {
 256                 u64 csr;
 257                 struct {
 258                         u32 gitrepo_hash:32;    /* GIT repository hash */
 259                         /*
 260                          * HSSI configuration identifier:
 261                          * 0 - No HSSI
 262                          * 1 - PCIe-RP
 263                          * 2 - Ethernet
 264                          */
 265                         u8  hssi_id:4;
 266                         u16 rsvd1:12;           /* Reserved */
 267                         /* Bitstream version patch number */
 268                         u8  bs_verpatch:4;
 269                         /* Bitstream version minor number */
 270                         u8  bs_verminor:4;
 271                         /* Bitstream version major number */
 272                         u8  bs_vermajor:4;
 273                         /* Bitstream version debug number */
 274                         u8  bs_verdebug:4;
 275                 };
 276         };
 277 };
 278
 279 struct feature_fme_bitstream_md {
 280         union {
 281                 u64 csr;
 282                 struct {
 283                         /* Seed number userd for synthesis flow */
 284                         u8  synth_seed:4;
 285                         /* Synthesis date(day number - 2 digits) */
 286                         u8  synth_day:8;
 287                         /* Synthesis date(month number - 2 digits) */
 288                         u8  synth_month:8;
 289                         /* Synthesis date(year number - 2 digits) */
 290                         u8  synth_year:8;
 291                         u64 rsvd:36;            /* Reserved */
 292                 };
 293         };
 294 };
 295
 296 struct feature_fme_iommu_ctrl {
 297         union {
 298                 u64 csr;
 299                 struct {
 300                         /* Disables IOMMU prefetcher for C0 channel */
 301                         u8 prefetch_disableC0:1;
 302                         /* Disables IOMMU prefetcher for C1 channel */
 303                         u8 prefetch_disableC1:1;
 304                         /* Disables IOMMU partial cache line writes */
 305                         u8 prefetch_wrdisable:1;
 306                         u8 rsvd1:1;             /* Reserved */
 307                         /*
 308                          * Select counter and read value from register
 309                          * iommu_stat.dbg_counters
 310                          * 0 - Number of 4K page translation response
 311                          * 1 - Number of 2M page translation response
 312                          * 2 - Number of 1G page translation response
 313                          */
 314                         u8 counter_sel:2;
 315                         u32 rsvd2:26;           /* Reserved */
 316                         /* Connected to IOMMU SIP Capabilities */
 317                         u32 capecap_defeature;
 318                 };
 319         };
 320 };
 321
 322 struct feature_fme_iommu_stat {
 323         union {
 324                 u64 csr;
 325                 struct {
 326                         /* Translation Enable bit from IOMMU SIP */
 327                         u8 translation_enable:1;
 328                         /* Drain request in progress */
 329                         u8 drain_req_inprog:1;
 330                         /* Invalidation current state */
 331                         u8 inv_state:3;
 332                         /* C0 Response Buffer current state */
 333                         u8 respbuffer_stateC0:3;
 334                         /* C1 Response Buffer current state */
 335                         u8 respbuffer_stateC1:3;
 336                         /* Last request ID to IOMMU SIP */
 337                         u8 last_reqID:4;
 338                         /* Last IOMMU SIP response ID value */
 339                         u8 last_respID:4;
 340                         /* Last IOMMU SIP response status value */
 341                         u8 last_respstatus:3;
 342                         /* C0 Transaction Buffer is not empty */
 343                         u8 transbuf_notEmptyC0:1;
 344                         /* C1 Transaction Buffer is not empty */
 345                         u8 transbuf_notEmptyC1:1;
 346                         /* C0 Request FIFO is not empty */
 347                         u8 reqFIFO_notemptyC0:1;
 348                         /* C1 Request FIFO is not empty */
 349                         u8 reqFIFO_notemptyC1:1;
 350                         /* C0 Response FIFO is not empty */
 351                         u8 respFIFO_notemptyC0:1;
 352                         /* C1 Response FIFO is not empty */
 353                         u8 respFIFO_notemptyC1:1;
 354                         /* C0 Response FIFO overflow detected */
 355                         u8 respFIFO_overflowC0:1;
 356                         /* C1 Response FIFO overflow detected */
 357                         u8 respFIFO_overflowC1:1;
 358                         /* C0 Transaction Buffer overflow detected */
 359                         u8 tranbuf_overflowC0:1;
 360                         /* C1 Transaction Buffer overflow detected */
 361                         u8 tranbuf_overflowC1:1;
 362                         /* Request FIFO overflow detected */
 363                         u8 reqFIFO_overflow:1;
 364                         /* IOMMU memory read in progress */
 365                         u8 memrd_inprog:1;
 366                         /* IOMMU memory write in progress */
 367                         u8 memwr_inprog:1;
 368                         u8 rsvd1:1;     /* Reserved */
 369                         /* Value of counter selected by iommu_ctl.counter_sel */
 370                         u16 dbg_counters:16;
 371                         u16 rsvd2:12;   /* Reserved */
 372                 };
 373         };
 374 };
 375
 376 struct feature_fme_pcie0_ctrl {
 377         union {
 378                 u64 csr;
 379                 struct {
 380                         u64 vtd_bar_lock:1;     /* Lock VT-D BAR register */
 381                         u64 rsvd1:3;
 382                         u64 rciep:1;            /* Configure PCIE0 as RCiEP */
 383                         u64 rsvd2:59;
 384                 };
 385         };
 386 };
 387
 388 struct feature_fme_llpr_smrr_base {
 389         union {
 390                 u64 csr;
 391                 struct {
 392                         u64 rsvd1:12;
 393                         u64 base:20;    /* SMRR2 memory range base address */
 394                         u64 rsvd2:32;
 395                 };
 396         };
 397 };
 398
 399 struct feature_fme_llpr_smrr_mask {
 400         union {
 401                 u64 csr;
 402                 struct {
 403                         u64 rsvd1:11;
 404                         u64 valid:1;    /* LLPR_SMRR rule is valid or not */
 405                         /*
 406                          * SMRR memory range mask which determines the range
 407                          * of region being mapped
 408                          */
 409                         u64 phys_mask:20;
 410                         u64 rsvd2:32;
 411                 };
 412         };
 413 };
 414
 415 struct feature_fme_llpr_smrr2_base {
 416         union {
 417                 u64 csr;
 418                 struct {
 419                         u64 rsvd1:12;
 420                         u64 base:20;    /* SMRR2 memory range base address */
 421                         u64 rsvd2:32;
 422                 };
 423         };
 424 };
 425
 426 struct feature_fme_llpr_smrr2_mask {
 427         union {
 428                 u64 csr;
 429                 struct {
 430                         u64 rsvd1:11;
 431                         u64 valid:1;    /* LLPR_SMRR2 rule is valid or not */
 432                         /*
 433                          * SMRR2 memory range mask which determines the range
 434                          * of region being mapped
 435                          */
 436                         u64 phys_mask:20;
 437                         u64 rsvd2:32;
 438                 };
 439         };
 440 };
 441
 442 struct feature_fme_llpr_meseg_base {
 443         union {
 444                 u64 csr;
 445                 struct {
 446                         /* A[45:19] of base address memory range */
 447                         u64 me_base:27;
 448                         u64 rsvd:37;
 449                 };
 450         };
 451 };
 452
 453 struct feature_fme_llpr_meseg_limit {
 454         union {
 455                 u64 csr;
 456                 struct {
 457                         /* A[45:19] of limit address memory range */
 458                         u64 me_limit:27;
 459                         u64 rsvd1:4;
 460                         u64 enable:1;   /* Enable LLPR MESEG rule */
 461                         u64 rsvd2:32;
 462                 };
 463         };
 464 };
 465
 466 struct feature_fme_header {
 467         struct feature_header header;
 468         struct feature_afu_header afu_header;
 469         u64 reserved;
 470         u64 scratchpad;
 471         struct feature_fme_capability capability;
 472         struct feature_fme_port port[MAX_FPGA_PORT_NUM];
 473         struct feature_fme_fab_status fab_status;
 474         struct feature_fme_bitstream_id bitstream_id;
 475         struct feature_fme_bitstream_md bitstream_md;
 476         struct feature_fme_genprotrange2_base genprotrange2_base;
 477         struct feature_fme_genprotrange2_limit genprotrange2_limit;
 478         struct feature_fme_dxe_lock dxe_lock;
 479         struct feature_fme_iommu_ctrl iommu_ctrl;
 480         struct feature_fme_iommu_stat iommu_stat;
 481         struct feature_fme_pcie0_ctrl pcie0_control;
 482         struct feature_fme_llpr_smrr_base smrr_base;
 483         struct feature_fme_llpr_smrr_mask smrr_mask;
 484         struct feature_fme_llpr_smrr2_base smrr2_base;
 485         struct feature_fme_llpr_smrr2_mask smrr2_mask;
 486         struct feature_fme_llpr_meseg_base meseg_base;
 487         struct feature_fme_llpr_meseg_limit meseg_limit;
 488 };
 489
 490 struct feature_port_capability {
 491         union {
 492                 u64 csr;
 493                 struct {
 494                         u8 port_number:2;       /* Port Number 0-3 */
 495                         u8 rsvd1:6;             /* Reserved */
 496                         u16 mmio_size;          /* User MMIO size in KB */
 497                         u8 rsvd2;               /* Reserved */
 498                         u8 sp_intr_num:4;       /* Supported interrupts num */
 499                         u32 rsvd3:28;           /* Reserved */
 500                 };
 501         };
 502 };
 503
 504 struct feature_port_control {
 505         union {
 506                 u64 csr;
 507                 struct {
 508                         u8 port_sftrst:1;       /* Port Soft Reset */
 509                         u8 rsvd1:1;             /* Reserved */
 510                         u8 latency_tolerance:1;/* '1' >= 40us, '0' < 40us */
 511                         u8 rsvd2:1;             /* Reserved */
 512                         u8 port_sftrst_ack:1;   /* HW ACK for Soft Reset */
 513                         u64 rsvd3:59;           /* Reserved */
 514                 };
 515         };
 516 };
 517
 518 #define PORT_POWER_STATE_NORMAL         0
 519 #define PORT_POWER_STATE_AP1            1
 520 #define PORT_POWER_STATE_AP2            2
 521 #define PORT_POWER_STATE_AP6            6
 522
 523 struct feature_port_status {
 524         union {
 525                 u64 csr;
 526                 struct {
 527                         u8 port_freeze:1;       /* '1' - freezed '0' - normal */
 528                         u8 rsvd1:7;             /* Reserved */
 529                         u8 power_state:4;       /* Power State */
 530                         u8 ap1_event:1;         /* AP1 event was detected  */
 531                         u8 ap2_event:1;         /* AP2 event was detected  */
 532                         u64 rsvd2:50;           /* Reserved */
 533                 };
 534         };
 535 };
 536
 537 /* Port Header Register Set */
 538 struct feature_port_header {
 539         struct feature_header header;
 540         struct feature_afu_header afu_header;
 541         u64 port_mailbox;
 542         u64 scratchpad;
 543         struct feature_port_capability capability;
 544         struct feature_port_control control;
 545         struct feature_port_status status;
 546         u64 rsvd2;
 547         u64 user_clk_freq_cmd0;
 548         u64 user_clk_freq_cmd1;
 549         u64 user_clk_freq_sts0;
 550         u64 user_clk_freq_sts1;
 551 };
 552
 553 struct feature_fme_tmp_threshold {
 554         union {
 555                 u64 csr;
 556                 struct {
 557                         u8  tmp_thshold1:7;       /* temperature Threshold 1 */
 558                         /* temperature Threshold 1 enable/disable */
 559                         u8  tmp_thshold1_enable:1;
 560                         u8  tmp_thshold2:7;       /* temperature Threshold 2 */
 561                         /* temperature Threshold 2 enable /disable */
 562                         u8  tmp_thshold2_enable:1;
 563                         u8  pro_hot_setpoint:7;   /* Proc Hot set point */
 564                         u8  rsvd4:1;              /* Reserved */
 565                         u8  therm_trip_thshold:7; /* Thermeal Trip Threshold */
 566                         u8  rsvd3:1;              /* Reserved */
 567                         u8  thshold1_status:1;    /* Threshold 1 Status */
 568                         u8  thshold2_status:1;    /* Threshold 2 Status */
 569                         u8  rsvd5:1;              /* Reserved */
 570                         /* Thermeal Trip Threshold status */
 571                         u8  therm_trip_thshold_status:1;
 572                         u8  rsvd6:4;              /* Reserved */
 573                         /* Validation mode- Force Proc Hot */
 574                         u8  valmodeforce:1;
 575                         /* Validation mode - Therm trip Hot */
 576                         u8  valmodetherm:1;
 577                         u8  rsvd2:2;              /* Reserved */
 578                         u8  thshold_policy:1;     /* threshold policy */
 579                         u32 rsvd:19;              /* Reserved */
 580                 };
 581         };
 582 };
 583
 584 /* Temperature Sensor Read values format 1 */
 585 struct feature_fme_temp_rdsensor_fmt1 {
 586         union {
 587                 u64 csr;
 588                 struct {
 589                         /* Reads out FPGA temperature in celsius */
 590                         u8  fpga_temp:7;
 591                         u8  rsvd0:1;                    /* Reserved */
 592                         /* Temperature reading sequence number */
 593                         u16 tmp_reading_seq_num;
 594                         /* Temperature reading is valid */
 595                         u8  tmp_reading_valid:1;
 596                         u8  rsvd1:7;                    /* Reserved */
 597                         u16 dbg_mode:10;                /* Debug mode */
 598                         u32 rsvd2:22;                   /* Reserved */
 599                 };
 600         };
 601 };
 602
 603 /* Temperature sensor read values format 2 */
 604 struct feature_fme_temp_rdsensor_fmt2 {
 605         u64 rsvd;       /* Reserved */
 606 };
 607
 608 /* Temperature Threshold Capability Register */
 609 struct feature_fme_tmp_threshold_cap {
 610         union {
 611                 u64 csr;
 612                 struct {
 613                         /* Temperature Threshold Unsupported */
 614                         u8  tmp_thshold_disabled:1;
 615                         u64 rsvd:63;                    /* Reserved */
 616                 };
 617         };
 618 };
 619
 620 /* FME THERNAL FEATURE */
 621 struct feature_fme_thermal {
 622         struct feature_header header;
 623         struct feature_fme_tmp_threshold threshold;
 624         struct feature_fme_temp_rdsensor_fmt1 rdsensor_fm1;
 625         struct feature_fme_temp_rdsensor_fmt2 rdsensor_fm2;
 626         struct feature_fme_tmp_threshold_cap threshold_cap;
 627 };
 628
 629 /* Power Status register */
 630 struct feature_fme_pm_status {
 631         union {
 632                 u64 csr;
 633                 struct {
 634                         /* FPGA Power consumed, The format is to be defined */
 635                         u32 pwr_consumed:18;
 636                         /* FPGA Latency Tolerance Reporting */
 637                         u8  fpga_latency_report:1;
 638                         u64 rsvd:45;                    /* Reserved */
 639                 };
 640         };
 641 };
 642
 643 /* AP Thresholds */
 644 struct feature_fme_pm_ap_threshold {
 645         union {
 646                 u64 csr;
 647                 struct {
 648                         /*
 649                          * Number of clocks (5ns period) for assertion
 650                          * of FME_data
 651                          */
 652                         u8  threshold1:7;
 653                         u8  rsvd1:1;
 654                         u8  threshold2:7;
 655                         u8  rsvd2:1;
 656                         u8  threshold1_status:1;
 657                         u8  threshold2_status:1;
 658                         u64 rsvd3:46;           /* Reserved */
 659                 };
 660         };
 661 };
 662
 663 /* Xeon Power Limit */
 664 struct feature_fme_pm_xeon_limit {
 665         union {
 666                 u64 csr;
 667                 struct {
 668                         /* Power limit in Watts in 12.3 format */
 669                         u16 pwr_limit:15;
 670                         /* Indicates that power limit has been written */
 671                         u8  enable:1;
 672                         /* 0 - Turbe range, 1 - Entire range */
 673                         u8  clamping:1;
 674                         /* Time constant in XXYYY format */
 675                         u8  time:7;
 676                         u64 rsvd:40;            /* Reserved */
 677                 };
 678         };
 679 };
 680
 681 /* FPGA Power Limit */
 682 struct feature_fme_pm_fpga_limit {
 683         union {
 684                 u64 csr;
 685                 struct {
 686                         /* Power limit in Watts in 12.3 format */
 687                         u16 pwr_limit:15;
 688                         /* Indicates that power limit has been written */
 689                         u8  enable:1;
 690                         /* 0 - Turbe range, 1 - Entire range */
 691                         u8  clamping:1;
 692                         /* Time constant in XXYYY format */
 693                         u8  time:7;
 694                         u64 rsvd:40;            /* Reserved */
 695                 };
 696         };
 697 };
 698
 699 /* FME POWER FEATURE */
 700 struct feature_fme_power {
 701         struct feature_header header;
 702         struct feature_fme_pm_status status;
 703         struct feature_fme_pm_ap_threshold threshold;
 704         struct feature_fme_pm_xeon_limit xeon_limit;
 705         struct feature_fme_pm_fpga_limit fpga_limit;
 706 };
 707
 708 #define CACHE_CHANNEL_RD        0
 709 #define CACHE_CHANNEL_WR        1
 710
 711 enum iperf_cache_events {
 712         IPERF_CACHE_RD_HIT,
 713         IPERF_CACHE_WR_HIT,
 714         IPERF_CACHE_RD_MISS,
 715         IPERF_CACHE_WR_MISS,
 716         IPERF_CACHE_RSVD, /* reserved */
 717         IPERF_CACHE_HOLD_REQ,
 718         IPERF_CACHE_DATA_WR_PORT_CONTEN,
 719         IPERF_CACHE_TAG_WR_PORT_CONTEN,
 720         IPERF_CACHE_TX_REQ_STALL,
 721         IPERF_CACHE_RX_REQ_STALL,
 722         IPERF_CACHE_EVICTIONS,
 723 };
 724
 725 /* FPMON Cache Control */
 726 struct feature_fme_ifpmon_ch_ctl {
 727         union {
 728                 u64 csr;
 729                 struct {
 730                         u8  reset_counters:1;   /* Reset Counters */
 731                         u8  rsvd1:7;            /* Reserved */
 732                         u8  freeze:1;           /* Freeze if set to 1 */
 733                         u8  rsvd2:7;            /* Reserved */
 734                         u8  cache_event:4;      /* Select the cache event */
 735                         u8  cci_chsel:1;        /* Select the channel */
 736                         u64 rsvd3:43;           /* Reserved */
 737                 };
 738         };
 739 };
 740
 741 /* FPMON Cache Counter */
 742 struct feature_fme_ifpmon_ch_ctr {
 743         union {
 744                 u64 csr;
 745                 struct {
 746                         /* Cache Counter for even addresse */
 747                         u64 cache_counter:48;
 748                         u16 rsvd:12;            /* Reserved */
 749                         /* Cache Event being reported */
 750                         u8  event_code:4;
 751                 };
 752         };
 753 };
 754
 755 enum iperf_fab_events {
 756         IPERF_FAB_PCIE0_RD,
 757         IPERF_FAB_PCIE0_WR,
 758         IPERF_FAB_PCIE1_RD,
 759         IPERF_FAB_PCIE1_WR,
 760         IPERF_FAB_UPI_RD,
 761         IPERF_FAB_UPI_WR,
 762         IPERF_FAB_MMIO_RD,
 763         IPERF_FAB_MMIO_WR,
 764 };
 765
 766 #define FAB_DISABLE_FILTER     0
 767 #define FAB_ENABLE_FILTER      1
 768
 769 /* FPMON FAB Control */
 770 struct feature_fme_ifpmon_fab_ctl {
 771         union {
 772                 u64 csr;
 773                 struct {
 774                         u8  reset_counters:1;   /* Reset Counters */
 775                         u8  rsvd:7;             /* Reserved */
 776                         u8  freeze:1;           /* Set to 1 frozen counter */
 777                         u8  rsvd1:7;            /* Reserved */
 778                         u8  fab_evtcode:4;      /* Fabric Event Code */
 779                         u8  port_id:2;          /* Port ID */
 780                         u8  rsvd2:1;            /* Reserved */
 781                         u8  port_filter:1;      /* Port Filter */
 782                         u64 rsvd3:40;           /* Reserved */
 783                 };
 784         };
 785 };
 786
 787 /* FPMON Event Counter */
 788 struct feature_fme_ifpmon_fab_ctr {
 789         union {
 790                 u64 csr;
 791                 struct {
 792                         u64 fab_cnt:60; /* Fabric event counter */
 793                         /* Fabric event code being reported */
 794                         u8  event_code:4;
 795                 };
 796         };
 797 };
 798
 799 /* FPMON Clock Counter */
 800 struct feature_fme_ifpmon_clk_ctr {
 801         u64 afu_interf_clock;           /* Clk_16UI (AFU clock) counter. */
 802 };
 803
 804 enum iperf_vtd_events {
 805         IPERF_VTD_AFU_MEM_RD_TRANS,
 806         IPERF_VTD_AFU_MEM_WR_TRANS,
 807         IPERF_VTD_AFU_DEVTLB_RD_HIT,
 808         IPERF_VTD_AFU_DEVTLB_WR_HIT,
 809         IPERF_VTD_DEVTLB_4K_FILL,
 810         IPERF_VTD_DEVTLB_2M_FILL,
 811         IPERF_VTD_DEVTLB_1G_FILL,
 812 };
 813
 814 /* VT-d control register */
 815 struct feature_fme_ifpmon_vtd_ctl {
 816         union {
 817                 u64 csr;
 818                 struct {
 819                         u8  reset_counters:1;   /* Reset Counters */
 820                         u8  rsvd:7;             /* Reserved */
 821                         u8  freeze:1;           /* Set to 1 frozen counter */
 822                         u8  rsvd1:7;            /* Reserved */
 823                         u8  vtd_evtcode:4;      /* VTd and TLB event code */
 824                         u64 rsvd2:44;           /* Reserved */
 825                 };
 826         };
 827 };
 828
 829 /* VT-d event counter */
 830 struct feature_fme_ifpmon_vtd_ctr {
 831         union {
 832                 u64 csr;
 833                 struct {
 834                         u64 vtd_counter:48;     /* VTd event counter */
 835                         u16 rsvd:12;            /* Reserved */
 836                         u8  event_code:4;       /* VTd event code */
 837                 };
 838         };
 839 };
 840
 841 enum iperf_vtd_sip_events {
 842         IPERF_VTD_SIP_IOTLB_4K_HIT,
 843         IPERF_VTD_SIP_IOTLB_2M_HIT,
 844         IPERF_VTD_SIP_IOTLB_1G_HIT,
 845         IPERF_VTD_SIP_SLPWC_L3_HIT,
 846         IPERF_VTD_SIP_SLPWC_L4_HIT,
 847         IPERF_VTD_SIP_RCC_HIT,
 848         IPERF_VTD_SIP_IOTLB_4K_MISS,
 849         IPERF_VTD_SIP_IOTLB_2M_MISS,
 850         IPERF_VTD_SIP_IOTLB_1G_MISS,
 851         IPERF_VTD_SIP_SLPWC_L3_MISS,
 852         IPERF_VTD_SIP_SLPWC_L4_MISS,
 853         IPERF_VTD_SIP_RCC_MISS,
 854 };
 855
 856 /* VT-d SIP control register */
 857 struct feature_fme_ifpmon_vtd_sip_ctl {
 858         union {
 859                 u64 csr;
 860                 struct {
 861                         u8  reset_counters:1;   /* Reset Counters */
 862                         u8  rsvd:7;             /* Reserved */
 863                         u8  freeze:1;           /* Set to 1 frozen counter */
 864                         u8  rsvd1:7;            /* Reserved */
 865                         u8  vtd_evtcode:4;      /* VTd and TLB event code */
 866                         u64 rsvd2:44;           /* Reserved */
 867                 };
 868         };
 869 };
 870
 871 /* VT-d SIP event counter */
 872 struct feature_fme_ifpmon_vtd_sip_ctr {
 873         union {
 874                 u64 csr;
 875                 struct {
 876                         u64 vtd_counter:48;     /* VTd event counter */
 877                         u16 rsvd:12;            /* Reserved */
 878                         u8 event_code:4;        /* VTd event code */
 879                 };
 880         };
 881 };
 882
 883 /* FME IPERF FEATURE */
 884 struct feature_fme_iperf {
 885         struct feature_header header;
 886         struct feature_fme_ifpmon_ch_ctl ch_ctl;
 887         struct feature_fme_ifpmon_ch_ctr ch_ctr0;
 888         struct feature_fme_ifpmon_ch_ctr ch_ctr1;
 889         struct feature_fme_ifpmon_fab_ctl fab_ctl;
 890         struct feature_fme_ifpmon_fab_ctr fab_ctr;
 891         struct feature_fme_ifpmon_clk_ctr clk;
 892         struct feature_fme_ifpmon_vtd_ctl vtd_ctl;
 893         struct feature_fme_ifpmon_vtd_ctr vtd_ctr;
 894         struct feature_fme_ifpmon_vtd_sip_ctl vtd_sip_ctl;
 895         struct feature_fme_ifpmon_vtd_sip_ctr vtd_sip_ctr;
 896 };
 897
 898 enum dperf_fab_events {
 899         DPERF_FAB_PCIE0_RD,
 900         DPERF_FAB_PCIE0_WR,
 901         DPERF_FAB_MMIO_RD = 6,
 902         DPERF_FAB_MMIO_WR,
 903 };
 904
 905 /* FPMON FAB Control */
 906 struct feature_fme_dfpmon_fab_ctl {
 907         union {
 908                 u64 csr;
 909                 struct {
 910                         u8  reset_counters:1;   /* Reset Counters */
 911                         u8  rsvd:7;             /* Reserved */
 912                         u8  freeze:1;           /* Set to 1 frozen counter */
 913                         u8  rsvd1:7;            /* Reserved */
 914                         u8  fab_evtcode:4;      /* Fabric Event Code */
 915                         u8  port_id:2;          /* Port ID */
 916                         u8  rsvd2:1;            /* Reserved */
 917                         u8  port_filter:1;      /* Port Filter */
 918                         u64 rsvd3:40;           /* Reserved */
 919                 };
 920         };
 921 };
 922
 923 /* FPMON Event Counter */
 924 struct feature_fme_dfpmon_fab_ctr {
 925         union {
 926                 u64 csr;
 927                 struct {
 928                         u64 fab_cnt:60; /* Fabric event counter */
 929                         /* Fabric event code being reported */
 930                         u8  event_code:4;
 931                 };
 932         };
 933 };
 934
 935 /* FPMON Clock Counter */
 936 struct feature_fme_dfpmon_clk_ctr {
 937         u64 afu_interf_clock;           /* Clk_16UI (AFU clock) counter. */
 938 };
 939
 940 /* FME DPERF FEATURE */
 941 struct feature_fme_dperf {
 942         struct feature_header header;
 943         u64 rsvd[3];
 944         struct feature_fme_dfpmon_fab_ctl fab_ctl;
 945         struct feature_fme_dfpmon_fab_ctr fab_ctr;
 946         struct feature_fme_dfpmon_clk_ctr clk;
 947 };
 948
 949 struct feature_fme_error0 {
 950 #define FME_ERROR0_MASK        0xFFUL
 951 #define FME_ERROR0_MASK_DEFAULT 0x40UL  /* pcode workaround */
 952         union {
 953                 u64 csr;
 954                 struct {
 955                         u8  fabric_err:1;       /* Fabric error */
 956                         u8  fabfifo_overflow:1; /* Fabric fifo overflow */
 957                         u8  kticdc_parity_err:2;/* KTI CDC Parity Error */
 958                         u8  iommu_parity_err:1; /* IOMMU Parity error */
 959                         /* AFU PF/VF access mismatch detected */
 960                         u8  afu_acc_mode_err:1;
 961                         u8  mbp_err:1;          /* Indicates an MBP event */
 962                         /* PCIE0 CDC Parity Error */
 963                         u8  pcie0cdc_parity_err:5;
 964                         /* PCIE1 CDC Parity Error */
 965                         u8  pcie1cdc_parity_err:5;
 966                         /* CVL CDC Parity Error */
 967                         u8  cvlcdc_parity_err:3;
 968                         u64 rsvd:44;            /* Reserved */
 969                 };
 970         };
 971 };
 972
 973 /* PCIe0 Error Status register */
 974 struct feature_fme_pcie0_error {
 975 #define FME_PCIE0_ERROR_MASK   0xFFUL
 976         union {
 977                 u64 csr;
 978                 struct {
 979                         u8  formattype_err:1;   /* TLP format/type error */
 980                         u8  MWAddr_err:1;       /* TLP MW address error */
 981                         u8  MWAddrLength_err:1; /* TLP MW length error */
 982                         u8  MRAddr_err:1;       /* TLP MR address error */
 983                         u8  MRAddrLength_err:1; /* TLP MR length error */
 984                         u8  cpl_tag_err:1;      /* TLP CPL tag error */
 985                         u8  cpl_status_err:1;   /* TLP CPL status error */
 986                         u8  cpl_timeout_err:1;  /* TLP CPL timeout */
 987                         u8  cci_parity_err:1;   /* CCI bridge parity error */
 988                         u8  rxpoison_tlp_err:1; /* Received a TLP with EP set */
 989                         u64 rsvd:52;            /* Reserved */
 990                         u8  vfnumb_err:1;       /* Number of error VF */
 991                         u8  funct_type_err:1;   /* Virtual (1) or Physical */
 992                 };
 993         };
 994 };
 995
 996 /* PCIe1 Error Status register */
 997 struct feature_fme_pcie1_error {
 998 #define FME_PCIE1_ERROR_MASK   0xFFUL
 999         union {
1000                 u64 csr;
1001                 struct {
1002                         u8  formattype_err:1;   /* TLP format/type error */
1003                         u8  MWAddr_err:1;       /* TLP MW address error */
1004                         u8  MWAddrLength_err:1; /* TLP MW length error */
1005                         u8  MRAddr_err:1;       /* TLP MR address error */
1006                         u8  MRAddrLength_err:1; /* TLP MR length error */
1007                         u8  cpl_tag_err:1;      /* TLP CPL tag error */
1008                         u8  cpl_status_err:1;   /* TLP CPL status error */
1009                         u8  cpl_timeout_err:1;  /* TLP CPL timeout */
1010                         u8  cci_parity_err:1;   /* CCI bridge parity error */
1011                         u8  rxpoison_tlp_err:1; /* Received a TLP with EP set */
1012                         u64 rsvd:54;            /* Reserved */
1013                 };
1014         };
1015 };
1016
1017 /* FME First Error register */
1018 struct feature_fme_first_error {
1019 #define FME_FIRST_ERROR_MASK   ((1ULL << 60) - 1)
1020         union {
1021                 u64 csr;
1022                 struct {
1023                         /*
1024                          * Indicates the Error Register that was
1025                          * triggered first
1026                          */
1027                         u64 err_reg_status:60;
1028                         /*
1029                          * Holds 60 LSBs from the Error register that was
1030                          * triggered first
1031                          */
1032                         u8 errReg_id:4;
1033                 };
1034         };
1035 };
1036
1037 /* FME Next Error register */
1038 struct feature_fme_next_error {
1039 #define FME_NEXT_ERROR_MASK    ((1ULL << 60) - 1)
1040         union {
1041                 u64 csr;
1042                 struct {
1043                         /*
1044                          * Indicates the Error Register that was
1045                          * triggered second
1046                          */
1047                         u64 err_reg_status:60;
1048                         /*
1049                          * Holds 60 LSBs from the Error register that was
1050                          * triggered second
1051                          */
1052                         u8  errReg_id:4;
1053                 };
1054         };
1055 };
1056
1057 /* RAS Non Fatal Error Status register */
1058 struct feature_fme_ras_nonfaterror {
1059         union {
1060                 u64 csr;
1061                 struct {
1062                         /* thremal threshold AP1 */
1063                         u8  temp_thresh_ap1:1;
1064                         /* thremal threshold AP2 */
1065                         u8  temp_thresh_ap2:1;
1066                         u8  pcie_error:1;       /* pcie Error */
1067                         u8  portfatal_error:1;  /* port fatal error */
1068                         u8  proc_hot:1;         /* Indicates a ProcHot event */
1069                         /* Indicates an AFU PF/VF access mismatch */
1070                         u8  afu_acc_mode_err:1;
1071                         /* Injected nonfata Error */
1072                         u8  injected_nonfata_err:1;
1073                         u8  rsvd1:2;
1074                         /* Temperature threshold triggered AP6*/
1075                         u8  temp_thresh_AP6:1;
1076                         /* Power threshold triggered AP1 */
1077                         u8  power_thresh_AP1:1;
1078                         /* Power threshold triggered AP2 */
1079                         u8  power_thresh_AP2:1;
1080                         /* Indicates a MBP event */
1081                         u8  mbp_err:1;
1082                         u64 rsvd2:51;           /* Reserved */
1083                 };
1084         };
1085 };
1086
1087 /* RAS Catastrophic Fatal Error Status register */
1088 struct feature_fme_ras_catfaterror {
1089         union {
1090                 u64 csr;
1091                 struct {
1092                         /* KTI Link layer error detected */
1093                         u8  ktilink_fatal_err:1;
1094                         /* tag-n-cache error detected */
1095                         u8  tagcch_fatal_err:1;
1096                         /* CCI error detected */
1097                         u8  cci_fatal_err:1;
1098                         /* KTI Protocol error detected */
1099                         u8  ktiprpto_fatal_err:1;
1100                         /* Fatal DRAM error detected */
1101                         u8  dram_fatal_err:1;
1102                         /* IOMMU detected */
1103                         u8  iommu_fatal_err:1;
1104                         /* Fabric Fatal Error */
1105                         u8  fabric_fatal_err:1;
1106                         /* PCIe possion Error */
1107                         u8  pcie_poison_err:1;
1108                         /* Injected fatal Error */
1109                         u8  inject_fata_err:1;
1110                         /* Catastrophic CRC Error */
1111                         u8  crc_catast_err:1;
1112                         /* Catastrophic Thermal Error */
1113                         u8  therm_catast_err:1;
1114                         /* Injected Catastrophic Error */
1115                         u8  injected_catast_err:1;
1116                         u64 rsvd:52;
1117                 };
1118         };
1119 };
1120
1121 /* RAS Error injection register */
1122 struct feature_fme_ras_error_inj {
1123 #define FME_RAS_ERROR_INJ_MASK      0x7UL
1124         union {
1125                 u64 csr;
1126                 struct {
1127                         u8  catast_error:1;     /* Catastrophic error flag */
1128                         u8  fatal_error:1;      /* Fatal error flag */
1129                         u8  nonfatal_error:1;   /* NonFatal error flag */
1130                         u64 rsvd:61;            /* Reserved */
1131                 };
1132         };
1133 };
1134
1135 /* FME error capabilities */
1136 struct feature_fme_error_capability {
1137         union {
1138         u64 csr;
1139                 struct {
1140                         u8 support_intr:1;
1141                         /* MSI-X vector table entry number */
1142                         u16 intr_vector_num:12;
1143                         u64 rsvd:51;    /* Reserved */
1144                 };
1145         };
1146 };
1147
1148 /* FME ERR FEATURE */
1149 struct feature_fme_err {
1150         struct feature_header header;
1151         struct feature_fme_error0 fme_err_mask;
1152         struct feature_fme_error0 fme_err;
1153         struct feature_fme_pcie0_error pcie0_err_mask;
1154         struct feature_fme_pcie0_error pcie0_err;
1155         struct feature_fme_pcie1_error pcie1_err_mask;
1156         struct feature_fme_pcie1_error pcie1_err;
1157         struct feature_fme_first_error fme_first_err;
1158         struct feature_fme_next_error fme_next_err;
1159         struct feature_fme_ras_nonfaterror ras_nonfat_mask;
1160         struct feature_fme_ras_nonfaterror ras_nonfaterr;
1161         struct feature_fme_ras_catfaterror ras_catfat_mask;
1162         struct feature_fme_ras_catfaterror ras_catfaterr;
1163         struct feature_fme_ras_error_inj ras_error_inj;
1164         struct feature_fme_error_capability fme_err_capability;
1165 };
1166
1167 /* FME Partial Reconfiguration Control */
1168 struct feature_fme_pr_ctl {
1169         union {
1170                 u64 csr;
1171                 struct {
1172                         u8  pr_reset:1;         /* Reset PR Engine */
1173                         u8  rsvd3:3;            /* Reserved */
1174                         u8  pr_reset_ack:1;     /* Reset PR Engine Ack */
1175                         u8  rsvd4:3;            /* Reserved */
1176                         u8  pr_regionid:2;      /* PR Region ID */
1177                         u8  rsvd1:2;            /* Reserved */
1178                         u8  pr_start_req:1;     /* PR Start Request */
1179                         u8  pr_push_complete:1; /* PR Data push complete */
1180                         u8  pr_kind:1;          /* PR Data push complete */
1181                         u32 rsvd:17;            /* Reserved */
1182                         u32 config_data;        /* Config data TBD */
1183                 };
1184         };
1185 };
1186
1187 /* FME Partial Reconfiguration Status */
1188 struct feature_fme_pr_status {
1189         union {
1190                 u64 csr;
1191                 struct {
1192                         u16 pr_credit:9;        /* PR Credits */
1193                         u8  rsvd2:7;            /* Reserved */
1194                         u8  pr_status:1;        /* PR status */
1195                         u8  rsvd:3;             /* Reserved */
1196                         /* Altra PR Controller Block status */
1197                         u8  pr_controller_status:3;
1198                         u8  rsvd1:1;            /* Reserved */
1199                         u8  pr_host_status:4;   /* PR Host status */
1200                         u8  rsvd3:4;            /* Reserved */
1201                         /* Security Block Status fields (TBD) */
1202                         u32 security_bstatus;
1203                 };
1204         };
1205 };
1206
1207 /* FME Partial Reconfiguration Data */
1208 struct feature_fme_pr_data {
1209         union {
1210                 u64 csr;        /* PR data from the raw-binary file */
1211                 struct {
1212                         /* PR data from the raw-binary file */
1213                         u32 pr_data_raw;
1214                         u32 rsvd;
1215                 };
1216         };
1217 };
1218
1219 /* FME PR Public Key */
1220 struct feature_fme_pr_key {
1221         u64 key;                /* FME PR Public Hash */
1222 };
1223
1224 /* FME PR FEATURE */
1225 struct feature_fme_pr {
1226         struct feature_header header;
1227         /*Partial Reconfiguration control */
1228         struct feature_fme_pr_ctl       ccip_fme_pr_control;
1229
1230         /* Partial Reconfiguration Status */
1231         struct feature_fme_pr_status    ccip_fme_pr_status;
1232
1233         /* Partial Reconfiguration data */
1234         struct feature_fme_pr_data      ccip_fme_pr_data;
1235
1236         /* Partial Reconfiguration data */
1237         u64                             ccip_fme_pr_err;
1238
1239         u64 rsvd1[3];
1240
1241         /* Partial Reconfiguration data registers */
1242         u64 fme_pr_data1;
1243         u64 fme_pr_data2;
1244         u64 fme_pr_data3;
1245         u64 fme_pr_data4;
1246         u64 fme_pr_data5;
1247         u64 fme_pr_data6;
1248         u64 fme_pr_data7;
1249         u64 fme_pr_data8;
1250
1251         u64 rsvd2[5];
1252
1253         /* PR Interface ID */
1254         u64 fme_pr_intfc_id_l;
1255         u64 fme_pr_intfc_id_h;
1256
1257         /* MSIX filed to be Added */
1258 };
1259
1260 /* FME HSSI Control */
1261 struct feature_fme_hssi_eth_ctrl {
1262         union {
1263                 u64 csr;
1264                 struct {
1265                         u32 data:32;            /* HSSI data */
1266                         u16 address:16;         /* HSSI address */
1267                         /*
1268                          * HSSI comamnd
1269                          * 0x0 - No request
1270                          * 0x08 - SW register RD request
1271                          * 0x10 - SW register WR request
1272                          * 0x40 - Auxiliar bus RD request
1273                          * 0x80 - Auxiliar bus WR request
1274                          */
1275                         u16 cmd:16;
1276                 };
1277         };
1278 };
1279
1280 /* FME HSSI Status */
1281 struct feature_fme_hssi_eth_stat {
1282         union {
1283                 u64 csr;
1284                 struct {
1285                         u32 data:32;            /* HSSI data */
1286                         u8  acknowledge:1;      /* HSSI acknowledge */
1287                         u8  spare:1;            /* HSSI spare */
1288                         u32 rsvd:30;            /* Reserved */
1289                 };
1290         };
1291 };
1292
1293 /* FME HSSI FEATURE */
1294 struct feature_fme_hssi {
1295         struct feature_header header;
1296         struct feature_fme_hssi_eth_ctrl        hssi_control;
1297         struct feature_fme_hssi_eth_stat        hssi_status;
1298 };
1299
1300 #define PORT_ERR_MASK           0xfff0703ff001f
1301 struct feature_port_err_key {
1302         union {
1303                 u64 csr;
1304                 struct {
1305                         /* Tx Channel0: Overflow */
1306                         u8 tx_ch0_overflow:1;
1307                         /* Tx Channel0: Invalid request encoding */
1308                         u8 tx_ch0_invaldreq :1;
1309                         /* Tx Channel0: Request with cl_len=3 not supported */
1310                         u8 tx_ch0_cl_len3:1;
1311                         /* Tx Channel0: Request with cl_len=2 not aligned 2CL */
1312                         u8 tx_ch0_cl_len2:1;
1313                         /* Tx Channel0: Request with cl_len=4 not aligned 4CL */
1314                         u8 tx_ch0_cl_len4:1;
1315
1316                         u16 rsvd1:4;                    /* Reserved */
1317
1318                         /* AFU MMIO RD received while PORT is in reset */
1319                         u8 mmio_rd_whilerst:1;
1320                         /* AFU MMIO WR received while PORT is in reset */
1321                         u8 mmio_wr_whilerst:1;
1322
1323                         u16 rsvd2:5;                    /* Reserved */
1324
1325                         /* Tx Channel1: Overflow */
1326                         u8 tx_ch1_overflow:1;
1327                         /* Tx Channel1: Invalid request encoding */
1328                         u8 tx_ch1_invaldreq:1;
1329                         /* Tx Channel1: Request with cl_len=3 not supported */
1330                         u8 tx_ch1_cl_len3:1;
1331                         /* Tx Channel1: Request with cl_len=2 not aligned 2CL */
1332                         u8 tx_ch1_cl_len2:1;
1333                         /* Tx Channel1: Request with cl_len=4 not aligned 4CL */
1334                         u8 tx_ch1_cl_len4:1;
1335
1336                         /* Tx Channel1: Insufficient data payload */
1337                         u8 tx_ch1_insuff_data:1;
1338                         /* Tx Channel1: Data payload overrun */
1339                         u8 tx_ch1_data_overrun:1;
1340                         /* Tx Channel1 : Incorrect address */
1341                         u8 tx_ch1_incorr_addr:1;
1342                         /* Tx Channel1 : NON-Zero SOP Detected */
1343                         u8 tx_ch1_nzsop:1;
1344                         /* Tx Channel1 : Illegal VC_SEL, atomic request VLO */
1345                         u8 tx_ch1_illegal_vcsel:1;
1346
1347                         u8 rsvd3:6;                     /* Reserved */
1348
1349                         /* MMIO Read Timeout in AFU */
1350                         u8 mmioread_timeout:1;
1351
1352                         /* Tx Channel2: FIFO Overflow */
1353                         u8 tx_ch2_fifo_overflow:1;
1354
1355                         /* MMIO read is not matching pending request */
1356                         u8 unexp_mmio_resp:1;
1357
1358                         u8 rsvd4:5;                     /* Reserved */
1359
1360                         /* Number of pending Requests: counter overflow */
1361                         u8 tx_req_counter_overflow:1;
1362                         /* Req with Address violating SMM Range */
1363                         u8 llpr_smrr_err:1;
1364                         /* Req with Address violating second SMM Range */
1365                         u8 llpr_smrr2_err:1;
1366                         /* Req with Address violating ME Stolen message */
1367                         u8 llpr_mesg_err:1;
1368                         /* Req with Address violating Generic Protected Range */
1369                         u8 genprot_range_err:1;
1370                         /* Req with Address violating Legacy Range low */
1371                         u8 legrange_low_err:1;
1372                         /* Req with Address violating Legacy Range High */
1373                         u8 legrange_high_err:1;
1374                         /* Req with Address violating VGA memory range */
1375                         u8 vgmem_range_err:1;
1376                         u8 page_fault_err:1;            /* Page fault */
1377                         u8 pmr_err:1;                   /* PMR Error */
1378                         u8 ap6_event:1;                 /* AP6 event */
1379                         /* VF FLR detected on Port with PF access control */
1380                         u8 vfflr_access_err:1;
1381                         u16 rsvd5:12;                   /* Reserved */
1382                 };
1383         };
1384 };
1385
1386 /* Port first error register, not contain all error bits in error register. */
1387 struct feature_port_first_err_key {
1388         union {
1389                 u64 csr;
1390                 struct {
1391                         u8 tx_ch0_overflow:1;
1392                         u8 tx_ch0_invaldreq :1;
1393                         u8 tx_ch0_cl_len3:1;
1394                         u8 tx_ch0_cl_len2:1;
1395                         u8 tx_ch0_cl_len4:1;
1396                         u8 rsvd1:4;                     /* Reserved */
1397                         u8 mmio_rd_whilerst:1;
1398                         u8 mmio_wr_whilerst:1;
1399                         u8 rsvd2:5;                     /* Reserved */
1400                         u8 tx_ch1_overflow:1;
1401                         u8 tx_ch1_invaldreq:1;
1402                         u8 tx_ch1_cl_len3:1;
1403                         u8 tx_ch1_cl_len2:1;
1404                         u8 tx_ch1_cl_len4:1;
1405                         u8 tx_ch1_insuff_data:1;
1406                         u8 tx_ch1_data_overrun:1;
1407                         u8 tx_ch1_incorr_addr:1;
1408                         u8 tx_ch1_nzsop:1;
1409                         u8 tx_ch1_illegal_vcsel:1;
1410                         u8 rsvd3:6;                     /* Reserved */
1411                         u8 mmioread_timeout:1;
1412                         u8 tx_ch2_fifo_overflow:1;
1413                         u8 rsvd4:6;                     /* Reserved */
1414                         u8 tx_req_counter_overflow:1;
1415                         u32 rsvd5:23;                   /* Reserved */
1416                 };
1417         };
1418 };
1419
1420 /* Port malformed Req0 */
1421 struct feature_port_malformed_req0 {
1422         u64 header_lsb;
1423 };
1424
1425 /* Port malformed Req1 */
1426 struct feature_port_malformed_req1 {
1427         u64 header_msb;
1428 };
1429
1430 /* Port debug register */
1431 struct feature_port_debug {
1432         u64 port_debug;
1433 };
1434
1435 /* Port error capabilities */
1436 struct feature_port_err_capability {
1437         union {
1438                 u64 csr;
1439                 struct {
1440                         u8  support_intr:1;
1441                         /* MSI-X vector table entry number */
1442                         u16 intr_vector_num:12;
1443                         u64 rsvd:51;            /* Reserved */
1444                 };
1445         };
1446 };
1447
1448 /* PORT FEATURE ERROR */
1449 struct feature_port_error {
1450         struct feature_header header;
1451         struct feature_port_err_key error_mask;
1452         struct feature_port_err_key port_error;
1453         struct feature_port_first_err_key port_first_error;
1454         struct feature_port_malformed_req0 malreq0;
1455         struct feature_port_malformed_req1 malreq1;
1456         struct feature_port_debug port_debug;
1457         struct feature_port_err_capability error_capability;
1458 };
1459
1460 /* Port UMSG Capability */
1461 struct feature_port_umsg_cap {
1462         union {
1463                 u64 csr;
1464                 struct {
1465                         /* Number of umsg allocated to this port */
1466                         u8 umsg_allocated;
1467                         /* Enable / Disable UMsg engine for this port */
1468                         u8 umsg_enable:1;
1469                         /* Usmg initialization status */
1470                         u8 umsg_init_complete:1;
1471                         /* IOMMU can not translate the umsg base address */
1472                         u8 umsg_trans_error:1;
1473                         u64 rsvd:53;            /* Reserved */
1474                 };
1475         };
1476 };
1477
1478 /* Port UMSG base address */
1479 struct feature_port_umsg_baseaddr {
1480         union {
1481                 u64 csr;
1482                 struct {
1483                         u64 base_addr:48;       /* 48 bit physical address */
1484                         u16 rsvd;               /* Reserved */
1485                 };
1486         };
1487 };
1488
1489 struct feature_port_umsg_mode {
1490         union {
1491                 u64 csr;
1492                 struct {
1493                         u32 umsg_hint_enable;   /* UMSG hint enable/disable */
1494                         u32 rsvd;               /* Reserved */
1495                 };
1496         };
1497 };
1498
1499 /* PORT FEATURE UMSG */
1500 struct feature_port_umsg {
1501         struct feature_header header;
1502         struct feature_port_umsg_cap capability;
1503         struct feature_port_umsg_baseaddr baseaddr;
1504         struct feature_port_umsg_mode mode;
1505 };
1506
1507 #define UMSG_EN_POLL_INVL 10 /* us */
1508 #define UMSG_EN_POLL_TIMEOUT 1000 /* us */
1509
1510 /* Port UINT Capability */
1511 struct feature_port_uint_cap {
1512         union {
1513                 u64 csr;
1514                 struct {
1515                         u16 intr_num:12;        /* Supported interrupts num */
1516                         /* First MSI-X vector table entry number */
1517                         u16 first_vec_num:12;
1518                         u64 rsvd:40;
1519                 };
1520         };
1521 };
1522
1523 /* PORT FEATURE UINT */
1524 struct feature_port_uint {
1525         struct feature_header header;
1526         struct feature_port_uint_cap capability;
1527 };
1528
1529 /* STP region supports mmap operation, so use page aligned size. */
1530 #define PORT_FEATURE_STP_REGION_SIZE \
1531         IFPGA_PAGE_ALIGN(sizeof(struct feature_port_stp))
1532
1533 /* Port STP status register (for debug only)*/
1534 struct feature_port_stp_status {
1535         union {
1536                 u64 csr;
1537                 struct {
1538                         /* SLD Hub end-point read/write timeout */
1539                         u8 sld_ep_timeout:1;
1540                         /* Remote STP in reset/disable */
1541                         u8 rstp_disabled:1;
1542                         u8 unsupported_read:1;
1543                         /* MMIO timeout detected and faked with a response */
1544                         u8 mmio_timeout:1;
1545                         u8 txfifo_count:4;
1546                         u8 rxfifo_count:4;
1547                         u8 txfifo_overflow:1;
1548                         u8 txfifo_underflow:1;
1549                         u8 rxfifo_overflow:1;
1550                         u8 rxfifo_underflow:1;
1551                         /* Number of MMIO write requests */
1552                         u16 write_requests;
1553                         /* Number of MMIO read requests */
1554                         u16 read_requests;
1555                         /* Number of MMIO read responses */
1556                         u16 read_responses;
1557                 };
1558         };
1559 };
1560
1561 /*
1562  * PORT FEATURE STP
1563  * Most registers in STP region are not touched by driver, but mmapped to user
1564  * space. So they are not defined in below data structure, as its actual size
1565  * is 0x18c per spec.
1566  */
1567 struct feature_port_stp {
1568         struct feature_header header;
1569         struct feature_port_stp_status stp_status;
1570 };
1571
1572 /**
1573  * enum fpga_pr_states - fpga PR states
1574  * @FPGA_PR_STATE_UNKNOWN: can't determine state
1575  * @FPGA_PR_STATE_WRITE_INIT: preparing FPGA for programming
1576  * @FPGA_PR_STATE_WRITE_INIT_ERR: Error during WRITE_INIT stage
1577  * @FPGA_PR_STATE_WRITE: writing image to FPGA
1578  * @FPGA_PR_STATE_WRITE_ERR: Error while writing FPGA
1579  * @FPGA_PR_STATE_WRITE_COMPLETE: Doing post programming steps
1580  * @FPGA_PR_STATE_WRITE_COMPLETE_ERR: Error during WRITE_COMPLETE
1581  * @FPGA_PR_STATE_OPERATING: FPGA PR done
1582  */
1583 enum fpga_pr_states {
1584         /* canot determine state states */
1585         FPGA_PR_STATE_UNKNOWN,
1586
1587         /* write sequence: init, write, complete */
1588         FPGA_PR_STATE_WRITE_INIT,
1589         FPGA_PR_STATE_WRITE_INIT_ERR,
1590         FPGA_PR_STATE_WRITE,
1591         FPGA_PR_STATE_WRITE_ERR,
1592         FPGA_PR_STATE_WRITE_COMPLETE,
1593         FPGA_PR_STATE_WRITE_COMPLETE_ERR,
1594
1595         /* FPGA PR done */
1596         FPGA_PR_STATE_DONE,
1597 };
1598
1599 /*
1600  * FPGA Manager flags
1601  * FPGA_MGR_PARTIAL_RECONFIG: do partial reconfiguration if supported
1602  */
1603 #define FPGA_MGR_PARTIAL_RECONFIG       BIT(0)
1604
1605 /**
1606  * struct fpga_pr_info - specific information to a FPGA PR
1607  * @flags: boolean flags as defined above
1608  * @pr_err: PR error code
1609  * @state: fpga manager state
1610  * @port_id: port id
1611  */
1612 struct fpga_pr_info {
1613         u32 flags;
1614         u64 pr_err;
1615         enum fpga_pr_states state;
1616         int port_id;
1617 };
1618
1619 #define DEFINE_FPGA_PR_ERR_MSG(_name_)                  \
1620 static const char * const _name_[] = {                  \
1621         "PR operation error detected",                  \
1622         "PR CRC error detected",                        \
1623         "PR incompatiable bitstream error detected",    \
1624         "PR IP protocol error detected",                \
1625         "PR FIFO overflow error detected",              \
1626         "PR timeout error detected",                    \
1627         "PR secure load error detected",                \
1628 }
1629
1630 #define RST_POLL_INVL 10 /* us */
1631 #define RST_POLL_TIMEOUT 1000 /* us */
1632
1633 #define PR_WAIT_TIMEOUT   15000000
1634
1635 #define PR_HOST_STATUS_IDLE     0
1636 #define PR_MAX_ERR_NUM  7
1637
1638 DEFINE_FPGA_PR_ERR_MSG(pr_err_msg);
1639
1640 /*
1641  * green bitstream header must be byte-packed to match the
1642  * real file format.
1643  */
1644 struct bts_header {
1645         u64 guid_h;
1646         u64 guid_l;
1647         u32 metadata_len;
1648 };
1649
1650 #define GBS_GUID_H              0x414750466e6f6558
1651 #define GBS_GUID_L              0x31303076534247b7
1652 #define is_valid_bts(bts_hdr)                           \
1653         (((bts_hdr)->guid_h == GBS_GUID_H) &&           \
1654         ((bts_hdr)->guid_l == GBS_GUID_L))
1655
1656 #pragma pack(pop)
1657 #endif /* _BASE_IFPGA_DEFINES_H_ */