drivers/raw/ifpga_rawdev/base/ifpga_fme.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2018 Intel Corporation
   3  */
   4
   5 #include "ifpga_feature_dev.h"
   6 #include "opae_spi.h"
   7 #include "opae_intel_max10.h"
   8
   9 #define PWR_THRESHOLD_MAX       0x7F
  10
  11 int fme_get_prop(struct ifpga_fme_hw *fme, struct feature_prop *prop)
  12 {
  13         struct feature *feature;
  14
  15         if (!fme)
  16                 return -ENOENT;
  17
  18         feature = get_fme_feature_by_id(fme, prop->feature_id);
  19
  20         if (feature && feature->ops && feature->ops->get_prop)
  21                 return feature->ops->get_prop(feature, prop);
  22
  23         return -ENOENT;
  24 }
  25
  26 int fme_set_prop(struct ifpga_fme_hw *fme, struct feature_prop *prop)
  27 {
  28         struct feature *feature;
  29
  30         if (!fme)
  31                 return -ENOENT;
  32
  33         feature = get_fme_feature_by_id(fme, prop->feature_id);
  34
  35         if (feature && feature->ops && feature->ops->set_prop)
  36                 return feature->ops->set_prop(feature, prop);
  37
  38         return -ENOENT;
  39 }
  40
  41 int fme_set_irq(struct ifpga_fme_hw *fme, u32 feature_id, void *irq_set)
  42 {
  43         struct feature *feature;
  44
  45         if (!fme)
  46                 return -ENOENT;
  47
  48         feature = get_fme_feature_by_id(fme, feature_id);
  49
  50         if (feature && feature->ops && feature->ops->set_irq)
  51                 return feature->ops->set_irq(feature, irq_set);
  52
  53         return -ENOENT;
  54 }
  55
  56 /* fme private feature head */
  57 static int fme_hdr_init(struct feature *feature)
  58 {
  59         struct feature_fme_header *fme_hdr;
  60
  61         fme_hdr = (struct feature_fme_header *)feature->addr;
  62
  63         dev_info(NULL, "FME HDR Init.\n");
  64         dev_info(NULL, "FME cap %llx.\n",
  65                  (unsigned long long)fme_hdr->capability.csr);
  66
  67         return 0;
  68 }
  69
  70 static void fme_hdr_uinit(struct feature *feature)
  71 {
  72         UNUSED(feature);
  73
  74         dev_info(NULL, "FME HDR UInit.\n");
  75 }
  76
  77 static int fme_hdr_get_revision(struct ifpga_fme_hw *fme, u64 *revision)
  78 {
  79         struct feature_fme_header *fme_hdr
  80                 = get_fme_feature_ioaddr_by_index(fme, FME_FEATURE_ID_HEADER);
  81         struct feature_header header;
  82
  83         header.csr = readq(&fme_hdr->header);
  84         *revision = header.revision;
  85
  86         return 0;
  87 }
  88
  89 static int fme_hdr_get_ports_num(struct ifpga_fme_hw *fme, u64 *ports_num)
  90 {
  91         struct feature_fme_header *fme_hdr
  92                 = get_fme_feature_ioaddr_by_index(fme, FME_FEATURE_ID_HEADER);
  93         struct feature_fme_capability fme_capability;
  94
  95         fme_capability.csr = readq(&fme_hdr->capability);
  96         *ports_num = fme_capability.num_ports;
  97
  98         return 0;
  99 }
 100
 101 static int fme_hdr_get_cache_size(struct ifpga_fme_hw *fme, u64 *cache_size)
 102 {
 103         struct feature_fme_header *fme_hdr
 104                 = get_fme_feature_ioaddr_by_index(fme, FME_FEATURE_ID_HEADER);
 105         struct feature_fme_capability fme_capability;
 106
 107         fme_capability.csr = readq(&fme_hdr->capability);
 108         *cache_size = fme_capability.cache_size;
 109
 110         return 0;
 111 }
 112
 113 static int fme_hdr_get_version(struct ifpga_fme_hw *fme, u64 *version)
 114 {
 115         struct feature_fme_header *fme_hdr
 116                 = get_fme_feature_ioaddr_by_index(fme, FME_FEATURE_ID_HEADER);
 117         struct feature_fme_capability fme_capability;
 118
 119         fme_capability.csr = readq(&fme_hdr->capability);
 120         *version = fme_capability.fabric_verid;
 121
 122         return 0;
 123 }
 124
 125 static int fme_hdr_get_socket_id(struct ifpga_fme_hw *fme, u64 *socket_id)
 126 {
 127         struct feature_fme_header *fme_hdr
 128                 = get_fme_feature_ioaddr_by_index(fme, FME_FEATURE_ID_HEADER);
 129         struct feature_fme_capability fme_capability;
 130
 131         fme_capability.csr = readq(&fme_hdr->capability);
 132         *socket_id = fme_capability.socket_id;
 133
 134         return 0;
 135 }
 136
 137 static int fme_hdr_get_bitstream_id(struct ifpga_fme_hw *fme,
 138                                     u64 *bitstream_id)
 139 {
 140         struct feature_fme_header *fme_hdr
 141                 = get_fme_feature_ioaddr_by_index(fme, FME_FEATURE_ID_HEADER);
 142
 143         *bitstream_id = readq(&fme_hdr->bitstream_id);
 144
 145         return 0;
 146 }
 147
 148 static int fme_hdr_get_bitstream_metadata(struct ifpga_fme_hw *fme,
 149                                           u64 *bitstream_metadata)
 150 {
 151         struct feature_fme_header *fme_hdr
 152                 = get_fme_feature_ioaddr_by_index(fme, FME_FEATURE_ID_HEADER);
 153
 154         *bitstream_metadata = readq(&fme_hdr->bitstream_md);
 155
 156         return 0;
 157 }
 158
 159 static int
 160 fme_hdr_get_prop(struct feature *feature, struct feature_prop *prop)
 161 {
 162         struct ifpga_fme_hw *fme = feature->parent;
 163
 164         switch (prop->prop_id) {
 165         case FME_HDR_PROP_REVISION:
 166                 return fme_hdr_get_revision(fme, &prop->data);
 167         case FME_HDR_PROP_PORTS_NUM:
 168                 return fme_hdr_get_ports_num(fme, &prop->data);
 169         case FME_HDR_PROP_CACHE_SIZE:
 170                 return fme_hdr_get_cache_size(fme, &prop->data);
 171         case FME_HDR_PROP_VERSION:
 172                 return fme_hdr_get_version(fme, &prop->data);
 173         case FME_HDR_PROP_SOCKET_ID:
 174                 return fme_hdr_get_socket_id(fme, &prop->data);
 175         case FME_HDR_PROP_BITSTREAM_ID:
 176                 return fme_hdr_get_bitstream_id(fme, &prop->data);
 177         case FME_HDR_PROP_BITSTREAM_METADATA:
 178                 return fme_hdr_get_bitstream_metadata(fme, &prop->data);
 179         }
 180
 181         return -ENOENT;
 182 }
 183
 184 struct feature_ops fme_hdr_ops = {
 185         .init = fme_hdr_init,
 186         .uinit = fme_hdr_uinit,
 187         .get_prop = fme_hdr_get_prop,
 188 };
 189
 190 /* thermal management */
 191 static int fme_thermal_get_threshold1(struct ifpga_fme_hw *fme, u64 *thres1)
 192 {
 193         struct feature_fme_thermal *thermal;
 194         struct feature_fme_tmp_threshold temp_threshold;
 195
 196         thermal = get_fme_feature_ioaddr_by_index(fme,
 197                                                   FME_FEATURE_ID_THERMAL_MGMT);
 198
 199         temp_threshold.csr = readq(&thermal->threshold);
 200         *thres1 = temp_threshold.tmp_thshold1;
 201
 202         return 0;
 203 }
 204
 205 static int fme_thermal_set_threshold1(struct ifpga_fme_hw *fme, u64 thres1)
 206 {
 207         struct feature_fme_thermal *thermal;
 208         struct feature_fme_header *fme_hdr;
 209         struct feature_fme_tmp_threshold tmp_threshold;
 210         struct feature_fme_capability fme_capability;
 211
 212         thermal = get_fme_feature_ioaddr_by_index(fme,
 213                                                   FME_FEATURE_ID_THERMAL_MGMT);
 214         fme_hdr = get_fme_feature_ioaddr_by_index(fme, FME_FEATURE_ID_HEADER);
 215
 216         spinlock_lock(&fme->lock);
 217         tmp_threshold.csr = readq(&thermal->threshold);
 218         fme_capability.csr = readq(&fme_hdr->capability);
 219
 220         if (fme_capability.lock_bit == 1) {
 221                 spinlock_unlock(&fme->lock);
 222                 return -EBUSY;
 223         } else if (thres1 > 100) {
 224                 spinlock_unlock(&fme->lock);
 225                 return -EINVAL;
 226         } else if (thres1 == 0) {
 227                 tmp_threshold.tmp_thshold1_enable = 0;
 228                 tmp_threshold.tmp_thshold1 = thres1;
 229         } else {
 230                 tmp_threshold.tmp_thshold1_enable = 1;
 231                 tmp_threshold.tmp_thshold1 = thres1;
 232         }
 233
 234         writeq(tmp_threshold.csr, &thermal->threshold);
 235         spinlock_unlock(&fme->lock);
 236
 237         return 0;
 238 }
 239
 240 static int fme_thermal_get_threshold2(struct ifpga_fme_hw *fme, u64 *thres2)
 241 {
 242         struct feature_fme_thermal *thermal;
 243         struct feature_fme_tmp_threshold temp_threshold;
 244
 245         thermal = get_fme_feature_ioaddr_by_index(fme,
 246                                                   FME_FEATURE_ID_THERMAL_MGMT);
 247
 248         temp_threshold.csr = readq(&thermal->threshold);
 249         *thres2 = temp_threshold.tmp_thshold2;
 250
 251         return 0;
 252 }
 253
 254 static int fme_thermal_set_threshold2(struct ifpga_fme_hw *fme, u64 thres2)
 255 {
 256         struct feature_fme_thermal *thermal;
 257         struct feature_fme_header *fme_hdr;
 258         struct feature_fme_tmp_threshold tmp_threshold;
 259         struct feature_fme_capability fme_capability;
 260
 261         thermal = get_fme_feature_ioaddr_by_index(fme,
 262                                                   FME_FEATURE_ID_THERMAL_MGMT);
 263         fme_hdr = get_fme_feature_ioaddr_by_index(fme, FME_FEATURE_ID_HEADER);
 264
 265         spinlock_lock(&fme->lock);
 266         tmp_threshold.csr = readq(&thermal->threshold);
 267         fme_capability.csr = readq(&fme_hdr->capability);
 268
 269         if (fme_capability.lock_bit == 1) {
 270                 spinlock_unlock(&fme->lock);
 271                 return -EBUSY;
 272         } else if (thres2 > 100) {
 273                 spinlock_unlock(&fme->lock);
 274                 return -EINVAL;
 275         } else if (thres2 == 0) {
 276                 tmp_threshold.tmp_thshold2_enable = 0;
 277                 tmp_threshold.tmp_thshold2 = thres2;
 278         } else {
 279                 tmp_threshold.tmp_thshold2_enable = 1;
 280                 tmp_threshold.tmp_thshold2 = thres2;
 281         }
 282
 283         writeq(tmp_threshold.csr, &thermal->threshold);
 284         spinlock_unlock(&fme->lock);
 285
 286         return 0;
 287 }
 288
 289 static int fme_thermal_get_threshold_trip(struct ifpga_fme_hw *fme,
 290                                           u64 *thres_trip)
 291 {
 292         struct feature_fme_thermal *thermal;
 293         struct feature_fme_tmp_threshold temp_threshold;
 294
 295         thermal = get_fme_feature_ioaddr_by_index(fme,
 296                                                   FME_FEATURE_ID_THERMAL_MGMT);
 297
 298         temp_threshold.csr = readq(&thermal->threshold);
 299         *thres_trip = temp_threshold.therm_trip_thshold;
 300
 301         return 0;
 302 }
 303
 304 static int fme_thermal_get_threshold1_reached(struct ifpga_fme_hw *fme,
 305                                               u64 *thres1_reached)
 306 {
 307         struct feature_fme_thermal *thermal;
 308         struct feature_fme_tmp_threshold temp_threshold;
 309
 310         thermal = get_fme_feature_ioaddr_by_index(fme,
 311                                                   FME_FEATURE_ID_THERMAL_MGMT);
 312
 313         temp_threshold.csr = readq(&thermal->threshold);
 314         *thres1_reached = temp_threshold.thshold1_status;
 315
 316         return 0;
 317 }
 318
 319 static int fme_thermal_get_threshold2_reached(struct ifpga_fme_hw *fme,
 320                                               u64 *thres1_reached)
 321 {
 322         struct feature_fme_thermal *thermal;
 323         struct feature_fme_tmp_threshold temp_threshold;
 324
 325         thermal = get_fme_feature_ioaddr_by_index(fme,
 326                                                   FME_FEATURE_ID_THERMAL_MGMT);
 327
 328         temp_threshold.csr = readq(&thermal->threshold);
 329         *thres1_reached = temp_threshold.thshold2_status;
 330
 331         return 0;
 332 }
 333
 334 static int fme_thermal_get_threshold1_policy(struct ifpga_fme_hw *fme,
 335                                              u64 *thres1_policy)
 336 {
 337         struct feature_fme_thermal *thermal;
 338         struct feature_fme_tmp_threshold temp_threshold;
 339
 340         thermal = get_fme_feature_ioaddr_by_index(fme,
 341                                                   FME_FEATURE_ID_THERMAL_MGMT);
 342
 343         temp_threshold.csr = readq(&thermal->threshold);
 344         *thres1_policy = temp_threshold.thshold_policy;
 345
 346         return 0;
 347 }
 348
 349 static int fme_thermal_set_threshold1_policy(struct ifpga_fme_hw *fme,
 350                                              u64 thres1_policy)
 351 {
 352         struct feature_fme_thermal *thermal;
 353         struct feature_fme_tmp_threshold tmp_threshold;
 354
 355         thermal = get_fme_feature_ioaddr_by_index(fme,
 356                                                   FME_FEATURE_ID_THERMAL_MGMT);
 357
 358         spinlock_lock(&fme->lock);
 359         tmp_threshold.csr = readq(&thermal->threshold);
 360
 361         if (thres1_policy == 0) {
 362                 tmp_threshold.thshold_policy = 0;
 363         } else if (thres1_policy == 1) {
 364                 tmp_threshold.thshold_policy = 1;
 365         } else {
 366                 spinlock_unlock(&fme->lock);
 367                 return -EINVAL;
 368         }
 369
 370         writeq(tmp_threshold.csr, &thermal->threshold);
 371         spinlock_unlock(&fme->lock);
 372
 373         return 0;
 374 }
 375
 376 static int fme_thermal_get_temperature(struct ifpga_fme_hw *fme, u64 *temp)
 377 {
 378         struct feature_fme_thermal *thermal;
 379         struct feature_fme_temp_rdsensor_fmt1 temp_rdsensor_fmt1;
 380
 381         thermal = get_fme_feature_ioaddr_by_index(fme,
 382                                                   FME_FEATURE_ID_THERMAL_MGMT);
 383
 384         temp_rdsensor_fmt1.csr = readq(&thermal->rdsensor_fm1);
 385         *temp = temp_rdsensor_fmt1.fpga_temp;
 386
 387         return 0;
 388 }
 389
 390 static int fme_thermal_get_revision(struct ifpga_fme_hw *fme, u64 *revision)
 391 {
 392         struct feature_fme_thermal *fme_thermal
 393                 = get_fme_feature_ioaddr_by_index(fme,
 394                                                   FME_FEATURE_ID_THERMAL_MGMT);
 395         struct feature_header header;
 396
 397         header.csr = readq(&fme_thermal->header);
 398         *revision = header.revision;
 399
 400         return 0;
 401 }
 402
 403 #define FME_THERMAL_CAP_NO_TMP_THRESHOLD        0x1
 404
 405 static int fme_thermal_mgmt_init(struct feature *feature)
 406 {
 407         struct feature_fme_thermal *fme_thermal;
 408         struct feature_fme_tmp_threshold_cap thermal_cap;
 409
 410         UNUSED(feature);
 411
 412         dev_info(NULL, "FME thermal mgmt Init.\n");
 413
 414         fme_thermal = (struct feature_fme_thermal *)feature->addr;
 415         thermal_cap.csr = readq(&fme_thermal->threshold_cap);
 416
 417         dev_info(NULL, "FME thermal cap %llx.\n",
 418                  (unsigned long long)fme_thermal->threshold_cap.csr);
 419
 420         if (thermal_cap.tmp_thshold_disabled)
 421                 feature->cap |= FME_THERMAL_CAP_NO_TMP_THRESHOLD;
 422
 423         return 0;
 424 }
 425
 426 static void fme_thermal_mgmt_uinit(struct feature *feature)
 427 {
 428         UNUSED(feature);
 429
 430         dev_info(NULL, "FME thermal mgmt UInit.\n");
 431 }
 432
 433 static int
 434 fme_thermal_set_prop(struct feature *feature, struct feature_prop *prop)
 435 {
 436         struct ifpga_fme_hw *fme = feature->parent;
 437
 438         if (feature->cap & FME_THERMAL_CAP_NO_TMP_THRESHOLD)
 439                 return -ENOENT;
 440
 441         switch (prop->prop_id) {
 442         case FME_THERMAL_PROP_THRESHOLD1:
 443                 return fme_thermal_set_threshold1(fme, prop->data);
 444         case FME_THERMAL_PROP_THRESHOLD2:
 445                 return fme_thermal_set_threshold2(fme, prop->data);
 446         case FME_THERMAL_PROP_THRESHOLD1_POLICY:
 447                 return fme_thermal_set_threshold1_policy(fme, prop->data);
 448         }
 449
 450         return -ENOENT;
 451 }
 452
 453 static int
 454 fme_thermal_get_prop(struct feature *feature, struct feature_prop *prop)
 455 {
 456         struct ifpga_fme_hw *fme = feature->parent;
 457
 458         if (feature->cap & FME_THERMAL_CAP_NO_TMP_THRESHOLD &&
 459             prop->prop_id != FME_THERMAL_PROP_TEMPERATURE &&
 460             prop->prop_id != FME_THERMAL_PROP_REVISION)
 461                 return -ENOENT;
 462
 463         switch (prop->prop_id) {
 464         case FME_THERMAL_PROP_THRESHOLD1:
 465                 return fme_thermal_get_threshold1(fme, &prop->data);
 466         case FME_THERMAL_PROP_THRESHOLD2:
 467                 return fme_thermal_get_threshold2(fme, &prop->data);
 468         case FME_THERMAL_PROP_THRESHOLD_TRIP:
 469                 return fme_thermal_get_threshold_trip(fme, &prop->data);
 470         case FME_THERMAL_PROP_THRESHOLD1_REACHED:
 471                 return fme_thermal_get_threshold1_reached(fme, &prop->data);
 472         case FME_THERMAL_PROP_THRESHOLD2_REACHED:
 473                 return fme_thermal_get_threshold2_reached(fme, &prop->data);
 474         case FME_THERMAL_PROP_THRESHOLD1_POLICY:
 475                 return fme_thermal_get_threshold1_policy(fme, &prop->data);
 476         case FME_THERMAL_PROP_TEMPERATURE:
 477                 return fme_thermal_get_temperature(fme, &prop->data);
 478         case FME_THERMAL_PROP_REVISION:
 479                 return fme_thermal_get_revision(fme, &prop->data);
 480         }
 481
 482         return -ENOENT;
 483 }
 484
 485 struct feature_ops fme_thermal_mgmt_ops = {
 486         .init = fme_thermal_mgmt_init,
 487         .uinit = fme_thermal_mgmt_uinit,
 488         .get_prop = fme_thermal_get_prop,
 489         .set_prop = fme_thermal_set_prop,
 490 };
 491
 492 static int fme_pwr_get_consumed(struct ifpga_fme_hw *fme, u64 *consumed)
 493 {
 494         struct feature_fme_power *fme_power
 495                 = get_fme_feature_ioaddr_by_index(fme,
 496                                 FME_FEATURE_ID_POWER_MGMT);
 497         struct feature_fme_pm_status pm_status;
 498
 499         pm_status.csr = readq(&fme_power->status);
 500
 501         *consumed = pm_status.pwr_consumed;
 502
 503         return 0;
 504 }
 505
 506 static int fme_pwr_get_threshold1(struct ifpga_fme_hw *fme, u64 *threshold)
 507 {
 508         struct feature_fme_power *fme_power
 509                 = get_fme_feature_ioaddr_by_index(fme,
 510                                 FME_FEATURE_ID_POWER_MGMT);
 511         struct feature_fme_pm_ap_threshold pm_ap_threshold;
 512
 513         pm_ap_threshold.csr = readq(&fme_power->threshold);
 514
 515         *threshold = pm_ap_threshold.threshold1;
 516
 517         return 0;
 518 }
 519
 520 static int fme_pwr_set_threshold1(struct ifpga_fme_hw *fme, u64 threshold)
 521 {
 522         struct feature_fme_power *fme_power
 523                 = get_fme_feature_ioaddr_by_index(fme,
 524                                 FME_FEATURE_ID_POWER_MGMT);
 525         struct feature_fme_pm_ap_threshold pm_ap_threshold;
 526
 527         spinlock_lock(&fme->lock);
 528         pm_ap_threshold.csr = readq(&fme_power->threshold);
 529
 530         if (threshold <= PWR_THRESHOLD_MAX) {
 531                 pm_ap_threshold.threshold1 = threshold;
 532         } else {
 533                 spinlock_unlock(&fme->lock);
 534                 return -EINVAL;
 535         }
 536
 537         writeq(pm_ap_threshold.csr, &fme_power->threshold);
 538         spinlock_unlock(&fme->lock);
 539
 540         return 0;
 541 }
 542
 543 static int fme_pwr_get_threshold2(struct ifpga_fme_hw *fme, u64 *threshold)
 544 {
 545         struct feature_fme_power *fme_power
 546                 = get_fme_feature_ioaddr_by_index(fme,
 547                                 FME_FEATURE_ID_POWER_MGMT);
 548         struct feature_fme_pm_ap_threshold pm_ap_threshold;
 549
 550         pm_ap_threshold.csr = readq(&fme_power->threshold);
 551
 552         *threshold = pm_ap_threshold.threshold2;
 553
 554         return 0;
 555 }
 556
 557 static int fme_pwr_set_threshold2(struct ifpga_fme_hw *fme, u64 threshold)
 558 {
 559         struct feature_fme_power *fme_power
 560                 = get_fme_feature_ioaddr_by_index(fme,
 561                                 FME_FEATURE_ID_POWER_MGMT);
 562         struct feature_fme_pm_ap_threshold pm_ap_threshold;
 563
 564         spinlock_lock(&fme->lock);
 565         pm_ap_threshold.csr = readq(&fme_power->threshold);
 566
 567         if (threshold <= PWR_THRESHOLD_MAX) {
 568                 pm_ap_threshold.threshold2 = threshold;
 569         } else {
 570                 spinlock_unlock(&fme->lock);
 571                 return -EINVAL;
 572         }
 573
 574         writeq(pm_ap_threshold.csr, &fme_power->threshold);
 575         spinlock_unlock(&fme->lock);
 576
 577         return 0;
 578 }
 579
 580 static int fme_pwr_get_threshold1_status(struct ifpga_fme_hw *fme,
 581                                          u64 *threshold_status)
 582 {
 583         struct feature_fme_power *fme_power
 584                 = get_fme_feature_ioaddr_by_index(fme,
 585                                 FME_FEATURE_ID_POWER_MGMT);
 586         struct feature_fme_pm_ap_threshold pm_ap_threshold;
 587
 588         pm_ap_threshold.csr = readq(&fme_power->threshold);
 589
 590         *threshold_status = pm_ap_threshold.threshold1_status;
 591
 592         return 0;
 593 }
 594
 595 static int fme_pwr_get_threshold2_status(struct ifpga_fme_hw *fme,
 596                                          u64 *threshold_status)
 597 {
 598         struct feature_fme_power *fme_power
 599                 = get_fme_feature_ioaddr_by_index(fme,
 600                                 FME_FEATURE_ID_POWER_MGMT);
 601         struct feature_fme_pm_ap_threshold pm_ap_threshold;
 602
 603         pm_ap_threshold.csr = readq(&fme_power->threshold);
 604
 605         *threshold_status = pm_ap_threshold.threshold2_status;
 606
 607         return 0;
 608 }
 609
 610 static int fme_pwr_get_rtl(struct ifpga_fme_hw *fme, u64 *rtl)
 611 {
 612         struct feature_fme_power *fme_power
 613                 = get_fme_feature_ioaddr_by_index(fme,
 614                                 FME_FEATURE_ID_POWER_MGMT);
 615         struct feature_fme_pm_status pm_status;
 616
 617         pm_status.csr = readq(&fme_power->status);
 618
 619         *rtl = pm_status.fpga_latency_report;
 620
 621         return 0;
 622 }
 623
 624 static int fme_pwr_get_xeon_limit(struct ifpga_fme_hw *fme, u64 *limit)
 625 {
 626         struct feature_fme_power *fme_power
 627                 = get_fme_feature_ioaddr_by_index(fme,
 628                                 FME_FEATURE_ID_POWER_MGMT);
 629         struct feature_fme_pm_xeon_limit xeon_limit;
 630
 631         xeon_limit.csr = readq(&fme_power->xeon_limit);
 632
 633         if (!xeon_limit.enable)
 634                 xeon_limit.pwr_limit = 0;
 635
 636         *limit = xeon_limit.pwr_limit;
 637
 638         return 0;
 639 }
 640
 641 static int fme_pwr_get_fpga_limit(struct ifpga_fme_hw *fme, u64 *limit)
 642 {
 643         struct feature_fme_power *fme_power
 644                 = get_fme_feature_ioaddr_by_index(fme,
 645                                 FME_FEATURE_ID_POWER_MGMT);
 646         struct feature_fme_pm_fpga_limit fpga_limit;
 647
 648         fpga_limit.csr = readq(&fme_power->fpga_limit);
 649
 650         if (!fpga_limit.enable)
 651                 fpga_limit.pwr_limit = 0;
 652
 653         *limit = fpga_limit.pwr_limit;
 654
 655         return 0;
 656 }
 657
 658 static int fme_pwr_get_revision(struct ifpga_fme_hw *fme, u64 *revision)
 659 {
 660         struct feature_fme_power *fme_power
 661                 = get_fme_feature_ioaddr_by_index(fme,
 662                                                   FME_FEATURE_ID_POWER_MGMT);
 663         struct feature_header header;
 664
 665         header.csr = readq(&fme_power->header);
 666         *revision = header.revision;
 667
 668         return 0;
 669 }
 670
 671 static int fme_power_mgmt_init(struct feature *feature)
 672 {
 673         UNUSED(feature);
 674
 675         dev_info(NULL, "FME power mgmt Init.\n");
 676
 677         return 0;
 678 }
 679
 680 static void fme_power_mgmt_uinit(struct feature *feature)
 681 {
 682         UNUSED(feature);
 683
 684         dev_info(NULL, "FME power mgmt UInit.\n");
 685 }
 686
 687 static int fme_power_mgmt_get_prop(struct feature *feature,
 688                                    struct feature_prop *prop)
 689 {
 690         struct ifpga_fme_hw *fme = feature->parent;
 691
 692         switch (prop->prop_id) {
 693         case FME_PWR_PROP_CONSUMED:
 694                 return fme_pwr_get_consumed(fme, &prop->data);
 695         case FME_PWR_PROP_THRESHOLD1:
 696                 return fme_pwr_get_threshold1(fme, &prop->data);
 697         case FME_PWR_PROP_THRESHOLD2:
 698                 return fme_pwr_get_threshold2(fme, &prop->data);
 699         case FME_PWR_PROP_THRESHOLD1_STATUS:
 700                 return fme_pwr_get_threshold1_status(fme, &prop->data);
 701         case FME_PWR_PROP_THRESHOLD2_STATUS:
 702                 return fme_pwr_get_threshold2_status(fme, &prop->data);
 703         case FME_PWR_PROP_RTL:
 704                 return fme_pwr_get_rtl(fme, &prop->data);
 705         case FME_PWR_PROP_XEON_LIMIT:
 706                 return fme_pwr_get_xeon_limit(fme, &prop->data);
 707         case FME_PWR_PROP_FPGA_LIMIT:
 708                 return fme_pwr_get_fpga_limit(fme, &prop->data);
 709         case FME_PWR_PROP_REVISION:
 710                 return fme_pwr_get_revision(fme, &prop->data);
 711         }
 712
 713         return -ENOENT;
 714 }
 715
 716 static int fme_power_mgmt_set_prop(struct feature *feature,
 717                                    struct feature_prop *prop)
 718 {
 719         struct ifpga_fme_hw *fme = feature->parent;
 720
 721         switch (prop->prop_id) {
 722         case FME_PWR_PROP_THRESHOLD1:
 723                 return fme_pwr_set_threshold1(fme, prop->data);
 724         case FME_PWR_PROP_THRESHOLD2:
 725                 return fme_pwr_set_threshold2(fme, prop->data);
 726         }
 727
 728         return -ENOENT;
 729 }
 730
 731 struct feature_ops fme_power_mgmt_ops = {
 732         .init = fme_power_mgmt_init,
 733         .uinit = fme_power_mgmt_uinit,
 734         .get_prop = fme_power_mgmt_get_prop,
 735         .set_prop = fme_power_mgmt_set_prop,
 736 };
 737
 738 static int fme_hssi_eth_init(struct feature *feature)
 739 {
 740         UNUSED(feature);
 741         return 0;
 742 }
 743
 744 static void fme_hssi_eth_uinit(struct feature *feature)
 745 {
 746         UNUSED(feature);
 747 }
 748
 749 struct feature_ops fme_hssi_eth_ops = {
 750         .init = fme_hssi_eth_init,
 751         .uinit = fme_hssi_eth_uinit,
 752 };
 753
 754 static int fme_emif_init(struct feature *feature)
 755 {
 756         UNUSED(feature);
 757         return 0;
 758 }
 759
 760 static void fme_emif_uinit(struct feature *feature)
 761 {
 762         UNUSED(feature);
 763 }
 764
 765 struct feature_ops fme_emif_ops = {
 766         .init = fme_emif_init,
 767         .uinit = fme_emif_uinit,
 768 };
 769
 770 static int spi_self_checking(void)
 771 {
 772         u32 val;
 773         int ret;
 774
 775         ret = max10_reg_read(0x30043c, &val);
 776         if (ret)
 777                 return -EIO;
 778
 779         if (val != 0x87654321) {
 780                 dev_err(NULL, "Read MAX10 test register fail: 0x%x\n", val);
 781                 return -EIO;
 782         }
 783
 784         dev_info(NULL, "Read MAX10 test register success, SPI self-test done\n");
 785
 786         return 0;
 787 }
 788
 789 static int fme_spi_init(struct feature *feature)
 790 {
 791         struct ifpga_fme_hw *fme = (struct ifpga_fme_hw *)feature->parent;
 792         struct altera_spi_device *spi_master;
 793         struct intel_max10_device *max10;
 794         int ret = 0;
 795
 796         dev_info(fme, "FME SPI Master (Max10) Init.\n");
 797         dev_debug(fme, "FME SPI base addr %p.\n",
 798                         feature->addr);
 799         dev_debug(fme, "spi param=0x%llx\n",
 800                         (unsigned long long)opae_readq(feature->addr + 0x8));
 801
 802         spi_master = altera_spi_alloc(feature->addr, TYPE_SPI);
 803         if (!spi_master)
 804                 return -ENODEV;
 805
 806         altera_spi_init(spi_master);
 807
 808         max10 = intel_max10_device_probe(spi_master, 0);
 809         if (!max10) {
 810                 ret = -ENODEV;
 811                 dev_err(fme, "max10 init fail\n");
 812                 goto spi_fail;
 813         }
 814
 815         fme->max10_dev = max10;
 816
 817         /* SPI self test */
 818         if (spi_self_checking()) {
 819                 ret = -EIO;
 820                 goto max10_fail;
 821         }
 822
 823         return ret;
 824
 825 max10_fail:
 826         intel_max10_device_remove(fme->max10_dev);
 827 spi_fail:
 828         altera_spi_release(spi_master);
 829         return ret;
 830 }
 831
 832 static void fme_spi_uinit(struct feature *feature)
 833 {
 834         struct ifpga_fme_hw *fme = (struct ifpga_fme_hw *)feature->parent;
 835
 836         if (fme->max10_dev)
 837                 intel_max10_device_remove(fme->max10_dev);
 838 }
 839
 840 struct feature_ops fme_spi_master_ops = {
 841         .init = fme_spi_init,
 842         .uinit = fme_spi_uinit,
 843 };
 844
 845 static int nios_spi_wait_init_done(struct altera_spi_device *dev)
 846 {
 847         u32 val = 0;
 848         unsigned long timeout = msecs_to_timer_cycles(10000);
 849         unsigned long ticks;
 850
 851         do {
 852                 if (spi_reg_read(dev, NIOS_SPI_INIT_DONE, &val))
 853                         return -EIO;
 854                 if (val)
 855                         break;
 856
 857                 ticks = rte_get_timer_cycles();
 858                 if (time_after(ticks, timeout))
 859                         return -ETIMEDOUT;
 860                 msleep(100);
 861         } while (!val);
 862
 863         return 0;
 864 }
 865
 866 static int nios_spi_check_error(struct altera_spi_device *dev)
 867 {
 868         u32 value = 0;
 869
 870         if (spi_reg_read(dev, NIOS_SPI_INIT_STS0, &value))
 871                 return -EIO;
 872
 873         dev_debug(dev, "SPI init status0 0x%x\n", value);
 874
 875         /* Error code: 0xFFF0 to 0xFFFC */
 876         if (value >= 0xFFF0 && value <= 0xFFFC)
 877                 return -EINVAL;
 878
 879         value = 0;
 880         if (spi_reg_read(dev, NIOS_SPI_INIT_STS1, &value))
 881                 return -EIO;
 882
 883         dev_debug(dev, "SPI init status1 0x%x\n", value);
 884
 885         /* Error code: 0xFFF0 to 0xFFFC */
 886         if (value >= 0xFFF0 && value <= 0xFFFC)
 887                 return -EINVAL;
 888
 889         return 0;
 890 }
 891
 892 static int fme_nios_spi_init(struct feature *feature)
 893 {
 894         struct ifpga_fme_hw *fme = (struct ifpga_fme_hw *)feature->parent;
 895         struct altera_spi_device *spi_master;
 896         struct intel_max10_device *max10;
 897         int ret = 0;
 898
 899         dev_info(fme, "FME SPI Master (NIOS) Init.\n");
 900         dev_debug(fme, "FME SPI base addr %p.\n",
 901                         feature->addr);
 902         dev_debug(fme, "spi param=0x%llx\n",
 903                         (unsigned long long)opae_readq(feature->addr + 0x8));
 904
 905         spi_master = altera_spi_alloc(feature->addr, TYPE_NIOS_SPI);
 906         if (!spi_master)
 907                 return -ENODEV;
 908
 909         /**
 910          * 1. wait A10 NIOS initial finished and
 911          * release the SPI master to Host
 912          */
 913         ret = nios_spi_wait_init_done(spi_master);
 914         if (ret != 0) {
 915                 dev_err(fme, "FME NIOS_SPI init fail\n");
 916                 goto release_dev;
 917         }
 918
 919         dev_info(fme, "FME NIOS_SPI initial done\n");
 920
 921         /* 2. check if error occur? */
 922         if (nios_spi_check_error(spi_master))
 923                 dev_info(fme, "NIOS_SPI INIT done, but found some error\n");
 924
 925         /* 3. init the spi master*/
 926         altera_spi_init(spi_master);
 927
 928         /* init the max10 device */
 929         max10 = intel_max10_device_probe(spi_master, 0);
 930         if (!max10) {
 931                 ret = -ENODEV;
 932                 dev_err(fme, "max10 init fail\n");
 933                 goto release_dev;
 934         }
 935
 936         fme->max10_dev = max10;
 937
 938         /* SPI self test */
 939         if (spi_self_checking())
 940                 goto spi_fail;
 941
 942         return ret;
 943
 944 spi_fail:
 945         intel_max10_device_remove(fme->max10_dev);
 946 release_dev:
 947         altera_spi_release(spi_master);
 948         return -ENODEV;
 949 }
 950
 951 static void fme_nios_spi_uinit(struct feature *feature)
 952 {
 953         struct ifpga_fme_hw *fme = (struct ifpga_fme_hw *)feature->parent;
 954
 955         if (fme->max10_dev)
 956                 intel_max10_device_remove(fme->max10_dev);
 957 }
 958
 959 struct feature_ops fme_nios_spi_master_ops = {
 960         .init = fme_nios_spi_init,
 961         .uinit = fme_nios_spi_uinit,
 962 };