drivers/raw/ioat/idxd_pci.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2020 Intel Corporation
   3  */
   4
   5 #include <rte_bus_pci.h>
   6 #include <rte_memzone.h>
   7
   8 #include "ioat_private.h"
   9 #include "ioat_spec.h"
  10
  11 #define IDXD_VENDOR_ID          0x8086
  12 #define IDXD_DEVICE_ID_SPR      0x0B25
  13
  14 #define IDXD_PMD_RAWDEV_NAME_PCI rawdev_idxd_pci
  15
  16 const struct rte_pci_id pci_id_idxd_map[] = {
  17         { RTE_PCI_DEVICE(IDXD_VENDOR_ID, IDXD_DEVICE_ID_SPR) },
  18         { .vendor_id = 0, /* sentinel */ },
  19 };
  20
  21 static inline int
  22 idxd_pci_dev_command(struct idxd_rawdev *idxd, enum rte_idxd_cmds command)
  23 {
  24         uint8_t err_code;
  25         uint16_t qid = idxd->qid;
  26         int i = 0;
  27
  28         if (command >= idxd_disable_wq && command <= idxd_reset_wq)
  29                 qid = (1 << qid);
  30         rte_spinlock_lock(&idxd->u.pci->lk);
  31         idxd->u.pci->regs->cmd = (command << IDXD_CMD_SHIFT) | qid;
  32
  33         do {
  34                 rte_pause();
  35                 err_code = idxd->u.pci->regs->cmdstatus;
  36                 if (++i >= 1000) {
  37                         IOAT_PMD_ERR("Timeout waiting for command response from HW");
  38                         rte_spinlock_unlock(&idxd->u.pci->lk);
  39                         return err_code;
  40                 }
  41         } while (idxd->u.pci->regs->cmdstatus & CMDSTATUS_ACTIVE_MASK);
  42         rte_spinlock_unlock(&idxd->u.pci->lk);
  43
  44         return err_code & CMDSTATUS_ERR_MASK;
  45 }
  46
  47 static int
  48 idxd_is_wq_enabled(struct idxd_rawdev *idxd)
  49 {
  50         uint32_t state = idxd->u.pci->wq_regs[idxd->qid].wqcfg[WQ_STATE_IDX];
  51         return ((state >> WQ_STATE_SHIFT) & WQ_STATE_MASK) == 0x1;
  52 }
  53
  54 static void
  55 idxd_pci_dev_stop(struct rte_rawdev *dev)
  56 {
  57         struct idxd_rawdev *idxd = dev->dev_private;
  58         uint8_t err_code;
  59
  60         if (!idxd_is_wq_enabled(idxd)) {
  61                 IOAT_PMD_ERR("Work queue %d already disabled", idxd->qid);
  62                 return;
  63         }
  64
  65         err_code = idxd_pci_dev_command(idxd, idxd_disable_wq);
  66         if (err_code || idxd_is_wq_enabled(idxd)) {
  67                 IOAT_PMD_ERR("Failed disabling work queue %d, error code: %#x",
  68                                 idxd->qid, err_code);
  69                 return;
  70         }
  71         IOAT_PMD_DEBUG("Work queue %d disabled OK", idxd->qid);
  72 }
  73
  74 static int
  75 idxd_pci_dev_start(struct rte_rawdev *dev)
  76 {
  77         struct idxd_rawdev *idxd = dev->dev_private;
  78         uint8_t err_code;
  79
  80         if (idxd_is_wq_enabled(idxd)) {
  81                 IOAT_PMD_WARN("WQ %d already enabled", idxd->qid);
  82                 return 0;
  83         }
  84
  85         if (idxd->public.batch_ring == NULL) {
  86                 IOAT_PMD_ERR("WQ %d has not been fully configured", idxd->qid);
  87                 return -EINVAL;
  88         }
  89
  90         err_code = idxd_pci_dev_command(idxd, idxd_enable_wq);
  91         if (err_code || !idxd_is_wq_enabled(idxd)) {
  92                 IOAT_PMD_ERR("Failed enabling work queue %d, error code: %#x",
  93                                 idxd->qid, err_code);
  94                 return err_code == 0 ? -1 : err_code;
  95         }
  96
  97         IOAT_PMD_DEBUG("Work queue %d enabled OK", idxd->qid);
  98
  99         return 0;
 100 }
 101
 102 static const struct rte_rawdev_ops idxd_pci_ops = {
 103                 .dev_close = idxd_rawdev_close,
 104                 .dev_selftest = idxd_rawdev_test,
 105                 .dump = idxd_dev_dump,
 106                 .dev_configure = idxd_dev_configure,
 107                 .dev_start = idxd_pci_dev_start,
 108                 .dev_stop = idxd_pci_dev_stop,
 109 };
 110
 111 /* each portal uses 4 x 4k pages */
 112 #define IDXD_PORTAL_SIZE (4096 * 4)
 113
 114 static int
 115 init_pci_device(struct rte_pci_device *dev, struct idxd_rawdev *idxd)
 116 {
 117         struct idxd_pci_common *pci;
 118         uint8_t nb_groups, nb_engines, nb_wqs;
 119         uint16_t grp_offset, wq_offset; /* how far into bar0 the regs are */
 120         uint16_t wq_size, total_wq_size;
 121         uint8_t lg2_max_batch, lg2_max_copy_size;
 122         unsigned int i, err_code;
 123
 124         pci = malloc(sizeof(*pci));
 125         if (pci == NULL) {
 126                 IOAT_PMD_ERR("%s: Can't allocate memory", __func__);
 127                 goto err;
 128         }
 129         rte_spinlock_init(&pci->lk);
 130
 131         /* assign the bar registers, and then configure device */
 132         pci->regs = dev->mem_resource[0].addr;
 133         grp_offset = (uint16_t)pci->regs->offsets[0];
 134         pci->grp_regs = RTE_PTR_ADD(pci->regs, grp_offset * 0x100);
 135         wq_offset = (uint16_t)(pci->regs->offsets[0] >> 16);
 136         pci->wq_regs = RTE_PTR_ADD(pci->regs, wq_offset * 0x100);
 137         pci->portals = dev->mem_resource[2].addr;
 138
 139         /* sanity check device status */
 140         if (pci->regs->gensts & GENSTS_DEV_STATE_MASK) {
 141                 /* need function-level-reset (FLR) or is enabled */
 142                 IOAT_PMD_ERR("Device status is not disabled, cannot init");
 143                 goto err;
 144         }
 145         if (pci->regs->cmdstatus & CMDSTATUS_ACTIVE_MASK) {
 146                 /* command in progress */
 147                 IOAT_PMD_ERR("Device has a command in progress, cannot init");
 148                 goto err;
 149         }
 150
 151         /* read basic info about the hardware for use when configuring */
 152         nb_groups = (uint8_t)pci->regs->grpcap;
 153         nb_engines = (uint8_t)pci->regs->engcap;
 154         nb_wqs = (uint8_t)(pci->regs->wqcap >> 16);
 155         total_wq_size = (uint16_t)pci->regs->wqcap;
 156         lg2_max_copy_size = (uint8_t)(pci->regs->gencap >> 16) & 0x1F;
 157         lg2_max_batch = (uint8_t)(pci->regs->gencap >> 21) & 0x0F;
 158
 159         IOAT_PMD_DEBUG("nb_groups = %u, nb_engines = %u, nb_wqs = %u",
 160                         nb_groups, nb_engines, nb_wqs);
 161
 162         /* zero out any old config */
 163         for (i = 0; i < nb_groups; i++) {
 164                 pci->grp_regs[i].grpengcfg = 0;
 165                 pci->grp_regs[i].grpwqcfg[0] = 0;
 166         }
 167         for (i = 0; i < nb_wqs; i++)
 168                 pci->wq_regs[i].wqcfg[0] = 0;
 169
 170         /* put each engine into a separate group to avoid reordering */
 171         if (nb_groups > nb_engines)
 172                 nb_groups = nb_engines;
 173         if (nb_groups < nb_engines)
 174                 nb_engines = nb_groups;
 175
 176         /* assign engines to groups, round-robin style */
 177         for (i = 0; i < nb_engines; i++) {
 178                 IOAT_PMD_DEBUG("Assigning engine %u to group %u",
 179                                 i, i % nb_groups);
 180                 pci->grp_regs[i % nb_groups].grpengcfg |= (1ULL << i);
 181         }
 182
 183         /* now do the same for queues and give work slots to each queue */
 184         wq_size = total_wq_size / nb_wqs;
 185         IOAT_PMD_DEBUG("Work queue size = %u, max batch = 2^%u, max copy = 2^%u",
 186                         wq_size, lg2_max_batch, lg2_max_copy_size);
 187         for (i = 0; i < nb_wqs; i++) {
 188                 /* add engine "i" to a group */
 189                 IOAT_PMD_DEBUG("Assigning work queue %u to group %u",
 190                                 i, i % nb_groups);
 191                 pci->grp_regs[i % nb_groups].grpwqcfg[0] |= (1ULL << i);
 192                 /* now configure it, in terms of size, max batch, mode */
 193                 pci->wq_regs[i].wqcfg[WQ_SIZE_IDX] = wq_size;
 194                 pci->wq_regs[i].wqcfg[WQ_MODE_IDX] = (1 << WQ_PRIORITY_SHIFT) |
 195                                 WQ_MODE_DEDICATED;
 196                 pci->wq_regs[i].wqcfg[WQ_SIZES_IDX] = lg2_max_copy_size |
 197                                 (lg2_max_batch << WQ_BATCH_SZ_SHIFT);
 198         }
 199
 200         /* dump the group configuration to output */
 201         for (i = 0; i < nb_groups; i++) {
 202                 IOAT_PMD_DEBUG("## Group %d", i);
 203                 IOAT_PMD_DEBUG("    GRPWQCFG: %"PRIx64, pci->grp_regs[i].grpwqcfg[0]);
 204                 IOAT_PMD_DEBUG("    GRPENGCFG: %"PRIx64, pci->grp_regs[i].grpengcfg);
 205                 IOAT_PMD_DEBUG("    GRPFLAGS: %"PRIx32, pci->grp_regs[i].grpflags);
 206         }
 207
 208         idxd->u.pci = pci;
 209         idxd->max_batches = wq_size;
 210
 211         /* enable the device itself */
 212         err_code = idxd_pci_dev_command(idxd, idxd_enable_dev);
 213         if (err_code) {
 214                 IOAT_PMD_ERR("Error enabling device: code %#x", err_code);
 215                 return err_code;
 216         }
 217         IOAT_PMD_DEBUG("IDXD Device enabled OK");
 218
 219         return nb_wqs;
 220
 221 err:
 222         free(pci);
 223         return -1;
 224 }
 225
 226 static int
 227 idxd_rawdev_probe_pci(struct rte_pci_driver *drv, struct rte_pci_device *dev)
 228 {
 229         struct idxd_rawdev idxd = {{0}}; /* Double {} to avoid error on BSD12 */
 230         uint8_t nb_wqs;
 231         int qid, ret = 0;
 232         char name[PCI_PRI_STR_SIZE];
 233
 234         rte_pci_device_name(&dev->addr, name, sizeof(name));
 235         IOAT_PMD_INFO("Init %s on NUMA node %d", name, dev->device.numa_node);
 236         dev->device.driver = &drv->driver;
 237
 238         ret = init_pci_device(dev, &idxd);
 239         if (ret < 0) {
 240                 IOAT_PMD_ERR("Error initializing PCI hardware");
 241                 return ret;
 242         }
 243         nb_wqs = (uint8_t)ret;
 244
 245         /* set up one device for each queue */
 246         for (qid = 0; qid < nb_wqs; qid++) {
 247                 char qname[32];
 248
 249                 /* add the queue number to each device name */
 250                 snprintf(qname, sizeof(qname), "%s-q%d", name, qid);
 251                 idxd.qid = qid;
 252                 idxd.public.portal = RTE_PTR_ADD(idxd.u.pci->portals,
 253                                 qid * IDXD_PORTAL_SIZE);
 254                 if (idxd_is_wq_enabled(&idxd))
 255                         IOAT_PMD_ERR("Error, WQ %u seems enabled", qid);
 256                 ret = idxd_rawdev_create(qname, &dev->device,
 257                                 &idxd, &idxd_pci_ops);
 258                 if (ret != 0) {
 259                         IOAT_PMD_ERR("Failed to create rawdev %s", name);
 260                         if (qid == 0) /* if no devices using this, free pci */
 261                                 free(idxd.u.pci);
 262                         return ret;
 263                 }
 264         }
 265
 266         return 0;
 267 }
 268
 269 static int
 270 idxd_rawdev_destroy(const char *name)
 271 {
 272         int ret;
 273         uint8_t err_code;
 274         struct rte_rawdev *rdev;
 275         struct idxd_rawdev *idxd;
 276
 277         if (!name) {
 278                 IOAT_PMD_ERR("Invalid device name");
 279                 return -EINVAL;
 280         }
 281
 282         rdev = rte_rawdev_pmd_get_named_dev(name);
 283         if (!rdev) {
 284                 IOAT_PMD_ERR("Invalid device name (%s)", name);
 285                 return -EINVAL;
 286         }
 287
 288         idxd = rdev->dev_private;
 289
 290         /* disable the device */
 291         err_code = idxd_pci_dev_command(idxd, idxd_disable_dev);
 292         if (err_code) {
 293                 IOAT_PMD_ERR("Error disabling device: code %#x", err_code);
 294                 return err_code;
 295         }
 296         IOAT_PMD_DEBUG("IDXD Device disabled OK");
 297
 298         /* free device memory */
 299         if (rdev->dev_private != NULL) {
 300                 IOAT_PMD_DEBUG("Freeing device driver memory");
 301                 rdev->dev_private = NULL;
 302                 rte_free(idxd->public.batch_ring);
 303                 rte_free(idxd->public.hdl_ring);
 304                 rte_memzone_free(idxd->mz);
 305         }
 306
 307         /* rte_rawdev_close is called by pmd_release */
 308         ret = rte_rawdev_pmd_release(rdev);
 309         if (ret)
 310                 IOAT_PMD_DEBUG("Device cleanup failed");
 311
 312         return 0;
 313 }
 314
 315 static int
 316 idxd_rawdev_remove_pci(struct rte_pci_device *dev)
 317 {
 318         char name[PCI_PRI_STR_SIZE];
 319         int ret = 0;
 320
 321         rte_pci_device_name(&dev->addr, name, sizeof(name));
 322
 323         IOAT_PMD_INFO("Closing %s on NUMA node %d",
 324                         name, dev->device.numa_node);
 325
 326         ret = idxd_rawdev_destroy(name);
 327
 328         return ret;
 329 }
 330
 331 struct rte_pci_driver idxd_pmd_drv_pci = {
 332         .id_table = pci_id_idxd_map,
 333         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 334         .probe = idxd_rawdev_probe_pci,
 335         .remove = idxd_rawdev_remove_pci,
 336 };
 337
 338 RTE_PMD_REGISTER_PCI(IDXD_PMD_RAWDEV_NAME_PCI, idxd_pmd_drv_pci);
 339 RTE_PMD_REGISTER_PCI_TABLE(IDXD_PMD_RAWDEV_NAME_PCI, pci_id_idxd_map);
 340 RTE_PMD_REGISTER_KMOD_DEP(IDXD_PMD_RAWDEV_NAME_PCI,
 341                           "* igb_uio | uio_pci_generic | vfio-pci");