drivers/raw/ioat/idxd_pci.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2020 Intel Corporation
   3  */
   4
   5 #include <rte_bus_pci.h>
   6 #include <rte_memzone.h>
   7
   8 #include "ioat_private.h"
   9 #include "ioat_spec.h"
  10
  11 #define IDXD_VENDOR_ID          0x8086
  12 #define IDXD_DEVICE_ID_SPR      0x0B25
  13
  14 #define IDXD_PMD_RAWDEV_NAME_PCI rawdev_idxd_pci
  15
  16 const struct rte_pci_id pci_id_idxd_map[] = {
  17         { RTE_PCI_DEVICE(IDXD_VENDOR_ID, IDXD_DEVICE_ID_SPR) },
  18         { .vendor_id = 0, /* sentinel */ },
  19 };
  20
  21 static inline int
  22 idxd_pci_dev_command(struct idxd_rawdev *idxd, enum rte_idxd_cmds command)
  23 {
  24         uint8_t err_code;
  25         uint16_t qid = idxd->qid;
  26         int i = 0;
  27
  28         if (command >= idxd_disable_wq && command <= idxd_reset_wq)
  29                 qid = (1 << qid);
  30         rte_spinlock_lock(&idxd->u.pci->lk);
  31         idxd->u.pci->regs->cmd = (command << IDXD_CMD_SHIFT) | qid;
  32
  33         do {
  34                 rte_pause();
  35                 err_code = idxd->u.pci->regs->cmdstatus;
  36                 if (++i >= 1000) {
  37                         IOAT_PMD_ERR("Timeout waiting for command response from HW");
  38                         rte_spinlock_unlock(&idxd->u.pci->lk);
  39                         return err_code;
  40                 }
  41         } while (idxd->u.pci->regs->cmdstatus & CMDSTATUS_ACTIVE_MASK);
  42         rte_spinlock_unlock(&idxd->u.pci->lk);
  43
  44         return err_code & CMDSTATUS_ERR_MASK;
  45 }
  46
  47 static int
  48 idxd_is_wq_enabled(struct idxd_rawdev *idxd)
  49 {
  50         uint32_t state = idxd->u.pci->wq_regs[idxd->qid].wqcfg[WQ_STATE_IDX];
  51         return ((state >> WQ_STATE_SHIFT) & WQ_STATE_MASK) == 0x1;
  52 }
  53
  54 static const struct rte_rawdev_ops idxd_pci_ops = {
  55                 .dev_close = idxd_rawdev_close,
  56                 .dev_selftest = idxd_rawdev_test,
  57                 .dump = idxd_dev_dump,
  58 };
  59
  60 /* each portal uses 4 x 4k pages */
  61 #define IDXD_PORTAL_SIZE (4096 * 4)
  62
  63 static int
  64 init_pci_device(struct rte_pci_device *dev, struct idxd_rawdev *idxd)
  65 {
  66         struct idxd_pci_common *pci;
  67         uint8_t nb_groups, nb_engines, nb_wqs;
  68         uint16_t grp_offset, wq_offset; /* how far into bar0 the regs are */
  69         uint16_t wq_size, total_wq_size;
  70         uint8_t lg2_max_batch, lg2_max_copy_size;
  71         unsigned int i, err_code;
  72
  73         pci = malloc(sizeof(*pci));
  74         if (pci == NULL) {
  75                 IOAT_PMD_ERR("%s: Can't allocate memory", __func__);
  76                 goto err;
  77         }
  78         rte_spinlock_init(&pci->lk);
  79
  80         /* assign the bar registers, and then configure device */
  81         pci->regs = dev->mem_resource[0].addr;
  82         grp_offset = (uint16_t)pci->regs->offsets[0];
  83         pci->grp_regs = RTE_PTR_ADD(pci->regs, grp_offset * 0x100);
  84         wq_offset = (uint16_t)(pci->regs->offsets[0] >> 16);
  85         pci->wq_regs = RTE_PTR_ADD(pci->regs, wq_offset * 0x100);
  86         pci->portals = dev->mem_resource[2].addr;
  87
  88         /* sanity check device status */
  89         if (pci->regs->gensts & GENSTS_DEV_STATE_MASK) {
  90                 /* need function-level-reset (FLR) or is enabled */
  91                 IOAT_PMD_ERR("Device status is not disabled, cannot init");
  92                 goto err;
  93         }
  94         if (pci->regs->cmdstatus & CMDSTATUS_ACTIVE_MASK) {
  95                 /* command in progress */
  96                 IOAT_PMD_ERR("Device has a command in progress, cannot init");
  97                 goto err;
  98         }
  99
 100         /* read basic info about the hardware for use when configuring */
 101         nb_groups = (uint8_t)pci->regs->grpcap;
 102         nb_engines = (uint8_t)pci->regs->engcap;
 103         nb_wqs = (uint8_t)(pci->regs->wqcap >> 16);
 104         total_wq_size = (uint16_t)pci->regs->wqcap;
 105         lg2_max_copy_size = (uint8_t)(pci->regs->gencap >> 16) & 0x1F;
 106         lg2_max_batch = (uint8_t)(pci->regs->gencap >> 21) & 0x0F;
 107
 108         IOAT_PMD_DEBUG("nb_groups = %u, nb_engines = %u, nb_wqs = %u",
 109                         nb_groups, nb_engines, nb_wqs);
 110
 111         /* zero out any old config */
 112         for (i = 0; i < nb_groups; i++) {
 113                 pci->grp_regs[i].grpengcfg = 0;
 114                 pci->grp_regs[i].grpwqcfg[0] = 0;
 115         }
 116         for (i = 0; i < nb_wqs; i++)
 117                 pci->wq_regs[i].wqcfg[0] = 0;
 118
 119         /* put each engine into a separate group to avoid reordering */
 120         if (nb_groups > nb_engines)
 121                 nb_groups = nb_engines;
 122         if (nb_groups < nb_engines)
 123                 nb_engines = nb_groups;
 124
 125         /* assign engines to groups, round-robin style */
 126         for (i = 0; i < nb_engines; i++) {
 127                 IOAT_PMD_DEBUG("Assigning engine %u to group %u",
 128                                 i, i % nb_groups);
 129                 pci->grp_regs[i % nb_groups].grpengcfg |= (1ULL << i);
 130         }
 131
 132         /* now do the same for queues and give work slots to each queue */
 133         wq_size = total_wq_size / nb_wqs;
 134         IOAT_PMD_DEBUG("Work queue size = %u, max batch = 2^%u, max copy = 2^%u",
 135                         wq_size, lg2_max_batch, lg2_max_copy_size);
 136         for (i = 0; i < nb_wqs; i++) {
 137                 /* add engine "i" to a group */
 138                 IOAT_PMD_DEBUG("Assigning work queue %u to group %u",
 139                                 i, i % nb_groups);
 140                 pci->grp_regs[i % nb_groups].grpwqcfg[0] |= (1ULL << i);
 141                 /* now configure it, in terms of size, max batch, mode */
 142                 pci->wq_regs[i].wqcfg[WQ_SIZE_IDX] = wq_size;
 143                 pci->wq_regs[i].wqcfg[WQ_MODE_IDX] = (1 << WQ_PRIORITY_SHIFT) |
 144                                 WQ_MODE_DEDICATED;
 145                 pci->wq_regs[i].wqcfg[WQ_SIZES_IDX] = lg2_max_copy_size |
 146                                 (lg2_max_batch << WQ_BATCH_SZ_SHIFT);
 147         }
 148
 149         /* dump the group configuration to output */
 150         for (i = 0; i < nb_groups; i++) {
 151                 IOAT_PMD_DEBUG("## Group %d", i);
 152                 IOAT_PMD_DEBUG("    GRPWQCFG: %"PRIx64, pci->grp_regs[i].grpwqcfg[0]);
 153                 IOAT_PMD_DEBUG("    GRPENGCFG: %"PRIx64, pci->grp_regs[i].grpengcfg);
 154                 IOAT_PMD_DEBUG("    GRPFLAGS: %"PRIx32, pci->grp_regs[i].grpflags);
 155         }
 156
 157         idxd->u.pci = pci;
 158         idxd->max_batches = wq_size;
 159
 160         /* enable the device itself */
 161         err_code = idxd_pci_dev_command(idxd, idxd_enable_dev);
 162         if (err_code) {
 163                 IOAT_PMD_ERR("Error enabling device: code %#x", err_code);
 164                 return err_code;
 165         }
 166         IOAT_PMD_DEBUG("IDXD Device enabled OK");
 167
 168         return nb_wqs;
 169
 170 err:
 171         free(pci);
 172         return -1;
 173 }
 174
 175 static int
 176 idxd_rawdev_probe_pci(struct rte_pci_driver *drv, struct rte_pci_device *dev)
 177 {
 178         struct idxd_rawdev idxd = {{0}}; /* Double {} to avoid error on BSD12 */
 179         uint8_t nb_wqs;
 180         int qid, ret = 0;
 181         char name[PCI_PRI_STR_SIZE];
 182
 183         rte_pci_device_name(&dev->addr, name, sizeof(name));
 184         IOAT_PMD_INFO("Init %s on NUMA node %d", name, dev->device.numa_node);
 185         dev->device.driver = &drv->driver;
 186
 187         ret = init_pci_device(dev, &idxd);
 188         if (ret < 0) {
 189                 IOAT_PMD_ERR("Error initializing PCI hardware");
 190                 return ret;
 191         }
 192         nb_wqs = (uint8_t)ret;
 193
 194         /* set up one device for each queue */
 195         for (qid = 0; qid < nb_wqs; qid++) {
 196                 char qname[32];
 197
 198                 /* add the queue number to each device name */
 199                 snprintf(qname, sizeof(qname), "%s-q%d", name, qid);
 200                 idxd.qid = qid;
 201                 idxd.public.portal = RTE_PTR_ADD(idxd.u.pci->portals,
 202                                 qid * IDXD_PORTAL_SIZE);
 203                 if (idxd_is_wq_enabled(&idxd))
 204                         IOAT_PMD_ERR("Error, WQ %u seems enabled", qid);
 205                 ret = idxd_rawdev_create(qname, &dev->device,
 206                                 &idxd, &idxd_pci_ops);
 207                 if (ret != 0) {
 208                         IOAT_PMD_ERR("Failed to create rawdev %s", name);
 209                         if (qid == 0) /* if no devices using this, free pci */
 210                                 free(idxd.u.pci);
 211                         return ret;
 212                 }
 213         }
 214
 215         return 0;
 216 }
 217
 218 static int
 219 idxd_rawdev_destroy(const char *name)
 220 {
 221         int ret;
 222         uint8_t err_code;
 223         struct rte_rawdev *rdev;
 224         struct idxd_rawdev *idxd;
 225
 226         if (!name) {
 227                 IOAT_PMD_ERR("Invalid device name");
 228                 return -EINVAL;
 229         }
 230
 231         rdev = rte_rawdev_pmd_get_named_dev(name);
 232         if (!rdev) {
 233                 IOAT_PMD_ERR("Invalid device name (%s)", name);
 234                 return -EINVAL;
 235         }
 236
 237         idxd = rdev->dev_private;
 238
 239         /* disable the device */
 240         err_code = idxd_pci_dev_command(idxd, idxd_disable_dev);
 241         if (err_code) {
 242                 IOAT_PMD_ERR("Error disabling device: code %#x", err_code);
 243                 return err_code;
 244         }
 245         IOAT_PMD_DEBUG("IDXD Device disabled OK");
 246
 247         /* free device memory */
 248         if (rdev->dev_private != NULL) {
 249                 IOAT_PMD_DEBUG("Freeing device driver memory");
 250                 rdev->dev_private = NULL;
 251                 rte_free(idxd->public.batch_ring);
 252                 rte_free(idxd->public.hdl_ring);
 253                 rte_memzone_free(idxd->mz);
 254         }
 255
 256         /* rte_rawdev_close is called by pmd_release */
 257         ret = rte_rawdev_pmd_release(rdev);
 258         if (ret)
 259                 IOAT_PMD_DEBUG("Device cleanup failed");
 260
 261         return 0;
 262 }
 263
 264 static int
 265 idxd_rawdev_remove_pci(struct rte_pci_device *dev)
 266 {
 267         char name[PCI_PRI_STR_SIZE];
 268         int ret = 0;
 269
 270         rte_pci_device_name(&dev->addr, name, sizeof(name));
 271
 272         IOAT_PMD_INFO("Closing %s on NUMA node %d",
 273                         name, dev->device.numa_node);
 274
 275         ret = idxd_rawdev_destroy(name);
 276
 277         return ret;
 278 }
 279
 280 struct rte_pci_driver idxd_pmd_drv_pci = {
 281         .id_table = pci_id_idxd_map,
 282         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 283         .probe = idxd_rawdev_probe_pci,
 284         .remove = idxd_rawdev_remove_pci,
 285 };
 286
 287 RTE_PMD_REGISTER_PCI(IDXD_PMD_RAWDEV_NAME_PCI, idxd_pmd_drv_pci);
 288 RTE_PMD_REGISTER_PCI_TABLE(IDXD_PMD_RAWDEV_NAME_PCI, pci_id_idxd_map);
 289 RTE_PMD_REGISTER_KMOD_DEP(IDXD_PMD_RAWDEV_NAME_PCI,
 290                           "* igb_uio | uio_pci_generic | vfio-pci");